JP5407335B2 - Netlist generator for simulation - Google Patents

Description

  The present invention relates to a design technique for a printed circuit board (PCB).

  In the design of printed circuit boards, after creating a circuit diagram using a tool such as CAD (Computer Aided Design), perform visual confirmation, and if a defective part is found, correct the circuit diagram. After that, it was common to go through the process of submitting (drawing out) circuit diagrams to the production department.

  However, due to the increase in the number of terminals such as ASIC (Application Specific Integrated Circuit) mounted on the printed circuit board and the increase in the number of power supplies, simple mistakes cannot be prevented by just visual confirmation after entering the circuit diagram. It has become. For example, in the case of a printed circuit board used for an MFP (Multi Function Printer), the number of objects to be visually checked is 10,000 or more, such as signal connection mistakes, logical mistakes such as reversal leakage, and mounting instruction mistakes. It is difficult to prevent mistakes.

  Mistakes included in the circuit diagram are directly connected to defects in the printed circuit board, and additional work such as wiring changes is required. In the worst case, the printed circuit board must be re-produced, and the delivery date Lead to delays and increased production costs.

  In order to cope with such a situation, a mechanism for automatically verifying logical connection using information of a design specification (functional block diagram, connector specification, etc.) before a circuit diagram is drawn is being sought. That is, since the design specification contains information equivalent to the circuit diagram, the expected value of each signal line is generated from this information and compared with the simulation result of the circuit diagram described above. It is expected that such simple mistakes can be checked before drawing.

By the way, in order to simulate a circuit diagram, it is necessary to generate a simulation netlist according to a format such as Verilog HDL (Hardware Description Language) from the circuit diagram. Since various parts including ASIC are mounted in the circuit diagram and simulation cannot be performed only with simple connection information, the simulation netlist includes a library showing the input / output behavior of each part. It is.
Japanese Patent No. 2669316

  Conventionally, the above-mentioned library is manually created by the person in charge, and even if the parts have the same function, the pin names are different or the model numbers are different, so it is necessary to create them individually. In addition, even with the same parts, there are some which have different operations depending on the circuit configuration, and it is difficult to create an appropriate library.

  On the other hand, Patent Document 1 discloses a technique of extracting connection information from an apparatus circuit diagram, outputting a netlist, and outputting a simulation netlist by performing circuit conversion (conversion of connection information). However, since circuit conversion is performed, a simulation netlist is output for a circuit diagram different from the original circuit diagram, and there is a disadvantage that simulation of all nets (wiring or signal lines) cannot be performed. is there. In addition, the assignment of simulation models (libraries) corresponding to parts is based on the operator's specifications, and even if the parts have the same function, they cannot easily cope with pin names or model numbers being different. It is not possible to easily cope with parts that operate differently depending on the configuration.

  The present invention has been proposed in view of the above-described conventional problems, and an object of the present invention is to provide a simulation netlist generation device capable of easily creating a simulation library. .

In order to solve the above problems, according to the present invention, as described in claim 1, at least a part including an address and a symbol shape of a part on the circuit diagram stored in the circuit diagram file storage unit A circuit diagram reading unit for reading a circuit diagram file including information and connection information indicating a connection relation between components, and a component-model correspondence table for reading a component-model correspondence table stored in the component-model correspondence table storage unit A model template reading unit that identifies an appropriate model template from the component-model correspondence table according to the component information and connection information included in the circuit diagram file, and reads the model template stored in the model template storage unit; A simulation network that generates a simulation netlist based on the circuit diagram file and the model template. And a Trst generator, wherein the model template reading unit determines the circuit pattern of the components included in the circuit diagram based on the component information and the connection information of the schematic file, the part on the basis of the circuit pattern - The gist of the simulation netlist generation device is to identify an appropriate model template from the model correspondence table .

Further, as described in claim 2, described in the simulation net list generating apparatus according to claim 1, model template stored in the model template storage unit a signal line on the schematic in pin number Then, after the model template is read from the model template storage unit, it can be replaced with the corresponding function name.

According to a third aspect of the present invention, there is provided a method executed by the simulation netlist generation apparatus, including at least the addresses and symbol shapes of parts on the circuit diagram stored in the circuit diagram file storage unit. A circuit diagram reading process for reading a circuit diagram file including component information and connection information indicating a connection relationship between components, and a component-model correspondence table for reading a component-model correspondence table stored in the component-model correspondence table storage unit. A model template reading step of identifying an appropriate model template from the component-model correspondence table according to the component information and connection information included in the circuit diagram file, and reading the model template stored in the model template storage unit; , A simulation netlist based on the circuit diagram file and the model template And a simulation netlist generating step of generating to the model template reading step determines the circuit pattern of the components included in the circuit diagram based on the component information and the connection information of the schematic file, to the circuit pattern Based on the part-model correspondence table, a simulation netlist generation method for specifying an appropriate model template can be configured.

  In the simulation netlist generation device of the present invention, a library model template in which parts are organized by function and package unit is prepared in advance, an appropriate model template is selected based on circuit diagram information, and predetermined processing is performed. By doing this, it is possible to easily create a library for simulation.

  Hereinafter, preferred embodiments of the present invention will be described.

<Configuration>
FIG. 1 is a diagram showing a configuration example of a simulation net list generation apparatus according to an embodiment of the present invention.

  In FIG. 1, a simulation netlist generation apparatus 1 includes, as function units, a circuit diagram reading unit 101, a part-model correspondence table reading unit 102, a model template reading unit 103, a simulation netlist generation unit 104, and a simulation netlist. And an output unit 105. These functional units are computer programs that are executed on hardware resources such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory) of a computer constituting the simulation netlist generation apparatus 1. Is realized. Note that these functional units do not have to be arranged on a single computer, and may be distributed as necessary.

  The simulation netlist generation apparatus 1 includes a circuit diagram file storage unit 111, a part-model correspondence table storage unit 112, a model model storage unit 113, and a simulation netlist storage unit 114 as data holding units. . These data holding units hold data systematically on a storage medium such as an HDD (Hard Disk Drive) in the simulation netlist generation apparatus 1.

  The circuit diagram reading unit 101 has a function of reading a circuit diagram file stored in the circuit diagram file storage unit 111 and giving the read circuit diagram file to the component-model correspondence table reading unit 102 of the next stage. The circuit diagram file is created in advance by a tool such as CAD.

  The part-model correspondence table reading unit 102 reads the part-model correspondence table stored in the part-model correspondence table storage unit 112, and the circuit diagram given from the circuit diagram reading unit 101 by the read part-model correspondence table. It has a function to be given to the next model model reading unit 103 together with the file.

  The model template reading unit 103 identifies an appropriate model template from the part-model correspondence table according to the information contained in the circuit diagram file, reads the model template stored in the model template storage unit 113, and loads the read model template into the circuit. It has a function to be given to the simulation netlist generation unit 104 in the next stage together with the figure file.

  The simulation netlist generation unit 104 has a function of generating a simulation netlist based on the circuit diagram file and the model model and supplying the simulation netlist to the simulation netlist output unit 105 in the next stage.

  The simulation netlist output unit 105 has a function of outputting (storing) the simulation netlist to the simulation netlist storage unit 114.

  FIG. 2 is a diagram showing an example of the data structure of the circuit diagram file F stored in the circuit diagram file storage unit 111. The circuit diagram file F includes component information and connection information. The component information includes items of “address”, “manufacturer model number”, “product type”, “function name”, “symbol shape”, “number of pins”, and “pin definition”. “Address” is information for specifying a component on the circuit diagram, and a value such as “IC1” is entered, for example. The “manufacturer model number” is information indicating the model number of the part determined by the manufacturer, and a value such as “TC74VHC00FT (K)” is entered, for example. “Product type” is information indicating the type of component, and for example, a value such as “logic” is entered. “Function name” is information indicating the functional name of a component, and a value such as “00” is entered, for example. “Symbol shape” is information for identifying a symbol of a component, and a value such as “2NAND-P” is entered, for example. “Number of pins” is information indicating the number of pins of a component, and a value such as “14” is entered. When the component is a resistor, the number of pins of the single resistor is “2”, but when using a component in which four elements are included in one package, the number of pins is “8”. “Pin definition” is information for associating a pin number of a component with a function name, and a value such as “1: 1A, 2: 1B,.

  The connection information includes “connection source” and “connection destination”. “Connection source” is information indicating the starting point of the connection. For example, in the case of the third pin of the component IC1, a value such as “IC1.3” is entered. “Destination” is information indicating the end point of the connection.

  FIG. 3 is a diagram showing an example of the data structure of the part-model correspondence table T stored in the part-model correspondence table storage unit 112. The part-model correspondence table T includes items of “product type”, “number of pins”, “symbol shape”, “function name”, “circuit pattern”, “model template”, and “output model name”. “Product type” is information indicating the type of component, and for example, a value such as “logic” is entered. “Number of pins” is information indicating the number of pins of a component, and a value such as “14” is entered. “Symbol shape” is information for identifying a symbol of a component, and a value such as “2NAND-P” is entered, for example. “Function name” is information indicating the functional name of a component, and a value such as “00” is entered, for example.

  “Circuit pattern” is information indicating how the part is used. For example, “Pull-up / Pull-down” “Other (Damping resistor)” for resistors, “Voltage follower” “Other” for operational amplifiers, and Comparator “Divided” or “Other”, “Forward connection” or “Reverse connection” for diodes, “Emitter follower”, “Others”, etc. for transistors.

  The “model template” is information indicating the file name of the corresponding model template, and a value such as “logic_00_14.v” is entered, for example. The “output model name” is information indicating the naming rule of the module name of the library generated from the model template, and includes a value such as “use model number”, for example.

  FIG. 4 is a diagram illustrating an example of the model template M stored in the model template storage unit 113. The illustrated example corresponds to a two-element NAND gate such as a manufacturer model number “TC74VHC00FT (K)”, a model template (file name) “logic — 00 — 14.v” having a product type “logic”, a pin number “14”, and a function name “00”. The module name shown in the description d1 is “logic_00_14”.

  In addition, the port name following the module name is described with “n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14” with the pin number. Has been. The reason why the pin number is used for the port name is that it is not necessary to use a function name unique to the manufacturer or part series of the part. The reason why “n_” is added to the beginning of the port name is that a number cannot be used at the beginning according to the description rule of Verilog HDL.

  In the module, the declaration of the input port starting with “input” shown in the description d2, the declaration of the output port starting with “output” shown in the description d3, “nand (n_3, n_1, n_2)” shown in the description d4, etc. A description of the element is included. “Nand” is a description (embedded primitive) indicating a NAND gate prepared in advance (Build-in) in Verilog HDL.

<Operation example 1>
FIG. 5 is a flowchart showing a processing example of the above embodiment.

  In FIG. 5, when the process is started by a process start instruction or the like by the operator (step S <b> 11), the circuit diagram reading unit 101 reads the target circuit diagram file F from the circuit diagram file storage unit 111 and reads the read circuit diagram file. F is given to the next-stage part-model correspondence table reading unit 102 (step S12).

  FIG. 6A shows an example of a circuit diagram corresponding to the read circuit diagram file F. FIG. This circuit diagram is visually shown for convenience of explanation, and the entity of the circuit diagram file F is electronic data based on the component information and connection information shown in FIG. Although an example of connection information is omitted, connection information is obtained by associating a starting point and an ending point of each signal line in the circuit diagram of FIG. FIG. 6B shows an example of component information. Address “IC1”, manufacturer model number “TC74VHC00FT (K)”, product type “logic”, function name “00”, symbol shape “2NAND-P”, Values such as the number of pins “14” and pin definitions “1: 1A, 2: 1B,...” Are set.

  Returning to FIG. 5, the part-model correspondence table reading unit 102 reads the part-model correspondence table T stored in the part-model correspondence table storage unit 112, and the read part-model correspondence table T is a circuit diagram reading unit. It is given to the next model template reading unit 103 together with the circuit diagram file F given from 101 (step S13).

  FIG. 6C shows an example of the part-model correspondence table T. The product type “logic”, the number of pins “14”, the symbol shape “2 NAND-P”, the function name “00”, and the circuit pattern “-”. The model template “logic — 00 — 14.v”, the output model name “model number use”, and the like are set.

  Returning to FIG. 5, the model template reading unit 103 identifies an appropriate model template M from the component-model correspondence table T based on the type and / or the number of pins included in the component information of the circuit diagram file F, and stores the model template. The model template M stored in the unit 113 is read, and the read model template M is given to the next simulation netlist generation unit 104 together with the circuit diagram file F (step S14).

  The component (logic) of the address “IC1” in FIG. 6A is based on the component “logic” and / or the number of pins “14” in the component information in FIG. A model template “logic — 00 — 14.v” is specified from the model correspondence table, and based on this, the model template M is read from the model template storage unit 113.

  Returning to FIG. 5, the model template reading unit 103 replaces the pin number of the read model template M with the function name based on the pin definition included in the component information of the circuit diagram file F, and the component-model correspondence table. If there is an instruction such as “use model number” in the output model name of T (FIG. 6C), the model name (module name) is changed in accordance with the instruction (step S15). Note that both or one of pin number replacement and model name (module name) change may be performed in the simulation netlist generation unit 104 in the next stage.

  The signal name is replaced with the pin number so that it is not necessary to use a unique function name depending on the manufacturer or part series in the state of the model model M, whereas the simulation netlist is followed visually. It is sometimes difficult to associate the function of each pin, and the visibility of the simulation netlist is improved by replacing the description of the pin number with the function name. In the example of the model template M shown in FIG. , N_2B, n_2Y, GND, n_3Y, n_3A, n_3B, n_4Y, n_4A, n_4B, Vcc, etc. Function names such as 1A, 1B, and 1Y have “n_” at the beginning so that the first character is a number, so that it conforms to the description rule of VerilogHDL. The module name is changed to “TC74VHC00FT_K_” if the manufacturer model number is “TC74VHC00FT (K)” in the case of “use model number”. Since “(” “)” is prohibited from the description rule of Verilog HDL, “(” “)” is replaced with “_” (underbar character).

  Returning to FIG. 5, the simulation netlist generation unit 104 generates a simulation netlist based on the circuit diagram file F and the model template M, and supplies the simulation netlist to the next simulation netlist output unit 105 (step S <b> 16).

  7A and 7B are diagrams illustrating examples of simulation netlists. 7A and 7B may be separate files for each module or one file.

  FIG. 7A is an overall netlist corresponding to the circuit diagram of FIG. 6A, the module name is “Sample1” in the description d11, and the port name following the module name is the pin “CN1_1” of the connector CN1. , CN1_2, CN1_3, CN1_4, CN1_5, CN1_6, CN1_7, CN1_8 ".

  In the module, an input port declaration starting with “input” shown in description d12, an output port declaration starting with “output” shown in description d13, a net declaration starting with “wire” shown in description d14, and shown in description d15 Net assignment starting with “assign”, description of bidirectional switch starting with “tran” shown in description d16, and declaration of two-element NAND gate with manufacturer model number “TC74VHC00FT (K)” shown in description d17 Contains a description.

  FIG. 7B is a library generated from the model template M shown in FIG. 4 and added to the simulation netlist. Compared to FIG. 4, the module name is “TC74VHC00FT_K_” corresponding to the manufacturer model number “TC74VHC00FT (K)” according to the output model name “use model number” (FIG. 6C) of the part-model correspondence table T. Yes.

  Also, the port name is replaced with the function name from the pin number, and the port names “n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14" in FIG. Are replaced with “n_1A, n_1B, n_1Y, n_2A, n_2B, n_2Y, GND, n_3Y, n_3A, n_3B, n_4Y, n_4A, n_4B, Vcc”.

  Returning to FIG. 5, the simulation netlist output unit 105 outputs (stores) the simulation netlist to the simulation netlist storage unit 114 (step S17), and ends the process (step S18).

<Operation example 2>
FIG. 8 is a flowchart showing another processing example of the above-described embodiment, and the model template is specified more strictly.

  In FIG. 8, when the process is started by a process activation instruction or the like by the operator (step S <b> 21), the circuit diagram reading unit 101 reads the target circuit diagram file F from the circuit diagram file storage unit 111 and reads the read circuit diagram file. F is given to the next-stage part-model correspondence table reading unit 102 (step S22).

  FIG. 9A shows an example of a circuit diagram corresponding to the read circuit diagram file F. FIG. This circuit diagram is visually shown for convenience of explanation, and the entity of the circuit diagram file F is electronic data based on the component information and connection information shown in FIG. FIG. 9B shows an example of the component information. The address “IC1”, the type “logic”, the address “RN1”, the type “resistance”, the address “RN2”, and the type “resistance”. Contains information on parts. FIG. 9C shows an example of connection information. The connection between the third pin of IC1 and the first pin of RN1, the connection between the eighth pin of RN1 and the first pin of RN2, and the eighth pin of RN1 and CN1 A connection with the first pin and a connection between the eighth pin of RN2 and VCC (power supply) are included.

  Returning to FIG. 8, the part-model correspondence table reading unit 102 reads the part-model correspondence table T stored in the part-model correspondence table storage unit 112, and the read part-model correspondence table T is a circuit diagram reading unit. It is given to the next model template reading unit 103 together with the circuit diagram file F given from 101 (step S23).

  FIG. 9D shows an example of the part-model correspondence table T. The parts of the type “logic” are the same as those in FIG. 6C, but the circuit pattern “pull-up / Two records, “pull-down” and “other”, are provided, the model template corresponding to the circuit pattern “pull-up / pull-down” is “allrtran.v”, and the model template corresponding to the circuit pattern “other” is “alltran.v”. It has become. Although other components are not shown in this example, two records are provided in the same manner as in the case of resistors, and the model templates to be associated with are different depending on the circuit pattern. It is as follows if it shows collectively including the case of resistance.

In the case of product type “resistor” Circuit pattern “pull-up / pull-down” Model template “allrtran.v”
Circuit pattern “Others” Model template “alltran.v”
In the case of product type “op-amp” Circuit pattern “Voltage follower” Model template “op_vf.v”
Circuit pattern “Others” Model template “op_other.v”
In case of product type “Comparator” Circuit pattern “With partial pressure” Model template “cmp_b.v”
Circuit pattern “Others” Model template “cmp_other.v”
In case of product type “Diode” Circuit pattern “Sequential connection” Model template “jun.v”
Circuit pattern “reverse connection” model template “gyaku.v”
In the case of product type “transistor” circuit pattern “emitter follower” model template “tr_ef.v”
Circuit pattern “Others” Model template “tr_other.v”
Returning to FIG. 8, the model template reading unit 103 identifies an appropriate model template M from the component-model correspondence table T according to a predetermined rule based on the component information and connection information of the circuit diagram file F, and the model template storage unit 113. The model model M stored in is read, and the read model model M is given to the simulation netlist generation unit 104 in the next stage together with the circuit diagram file F (step S24). The predetermined rule is based on the type and / or the number of pins included in the component information of the circuit diagram file F as in the above-described operation example (FIG. 5) when there is no option based on the circuit pattern in the component-model correspondence table T. Thus, an appropriate model template M is specified from the part-model correspondence table T. When there is an option based on the circuit pattern, the circuit pattern is determined and the model model M is specified according to the following rules, for example.

In the case of product type “resistor” Focusing on each net connected to the power supply and ground, the resistor connected to the net via the net and through-determinable parts (described later) is recognized as “pull-up / pull-down”, and the others are “others” (Damping resistance) ”. However, in the case of series, only the first resistor is “pull-up / pull-down” and there is no further point.

  0Ω resistor such as chip jumper is “other (damping resistor)”, and if one of the resistors is connected to the power supply or ground when looking at the resistor connected to the net as a part that can be judged through, “pull up / pull down” "

  When it is determined that “pull-up / pull-down” is used, the model template “allrtran.v” is used. Otherwise, “alltran.v” is used.

For product type “op amp” For each pin of the product symbol of the product type op amp, follow the net connected to the minus pin (the pin function name includes “-”), and the net through the net that can be judged through If the input / output type of the pin in the same symbol is “output”, this symbol is determined as “voltage follower” and the model template “op_vf.v” is used. Otherwise, “op_other.v” is used.

For the type “Comparator” For each pin of the component symbol whose type is the comparator, follow the net connected to the minus pin (the pin whose function name includes “-”), and the net through the net that can be judged through Is connected to both the power supply symbol and the ground symbol, this symbol is determined as “with partial pressure”, and the model template “cmp_b.v” is used. Otherwise, use “cmp_other.v”.

For the type “diode” If the net connected to the pin with the function name of the component symbol “Cathode” of the type is “Cathode” and the net through the net or a part that can be judged through is connected to the ground symbol, Judgment is made. In addition to this, if a net connected to a pin whose function name is “Anode” is traced and a net through a part that can be judged through the net or through is connected to a power supply symbol, it is determined as “forward connection”. Then, the model template “jun.v” is used. Otherwise, it is determined as “reverse connection” and the model template “gyaku.v” is used.

In the case of product type “transistor” If the function name of the component symbol of the product type is “collector”, the net connected to the pin is connected to the power supply symbol. And the model template “tr_ef.v” is used. Otherwise, it is determined as “others” and the model template “tr_other.v” is used.

  In the above description, parts that can be determined to be through are parts that are not logically meaningful, such as switches and jumpers. If such a through-determinable part is connected, the correct connection cannot be confirmed unless the net is followed. Therefore, the types of parts that can be judged through each of the above five determinations are defined in advance. In the case of the part of, through and follow the net to the beyond.

  The component (logic) at the address “IC1” in FIG. 9A is based on the component information type “logic” and / or the number of pins “14” in FIG. The model template “logic — 00 — 14.v” is specified from the model correspondence table, and the model template is read from the model template storage unit 113 based on this.

  Further, the component (resistor) at the address “RN1” in FIG. 9A is determined as “other (damping resistor)” because it is not connected to either the power source or the ground from the connection information in FIG. 9C. Then, the model template “alltran.v” corresponding to the circuit pattern “others” is specified from the component-model correspondence table of FIG.

  The component (resistor) at address “RN2” in FIG. 9A is determined as “pull-up / pull-down” because one end is connected to the power supply from the connection information in FIG. 9C, and FIG. The model template “allrtran.v” corresponding to the circuit pattern “pull-up / pull-down” is specified from the component-model correspondence table of FIG.

  Returning to FIG. 8, the model template reading unit 103 replaces the pin number of the read model template with the function name based on the pin definition included in the component information of the circuit diagram file F, and the component-model correspondence table T If there is an instruction such as “use model number” in the output model name (FIG. 6C), the model name (module name) is changed in accordance with the instruction (step S25). Note that both or one of pin number replacement and model name (module name) change may be performed in the simulation netlist generation unit 104 in the next stage.

  Next, the simulation netlist generation unit 104 generates a simulation netlist based on the circuit diagram file F and the model template, and supplies the simulation netlist to the simulation netlist output unit 105 in the next stage (step S26).

  10A and 10B are diagrams showing examples of simulation netlists. 10A and 10B may be separate files for each module or one file.

  The description d21 in FIG. 10A is an overall netlist corresponding to the circuit diagram of FIG. 9A, the description d22 includes a description of the resistance declaration of the manufacturer model number “MNR14E0APJ104”, and the description d23 includes the manufacturer model number “TC74VHC00FT”. (K) ”includes a description of the declaration of the two-element NAND gate, and the description d24 includes a description of the declaration of the resistance of the manufacturer model number“ CN1J4TBK330J ”.

  The description d25 is a library corresponding to the resistance of the manufacturer model number “MNR14E0APJ104” generated from the model template and added to the simulation netlist. A description d26 in FIG. 10B is a library corresponding to the two-element NAND gate of the manufacturer model number “TC74VHC00FT (K)” generated from the model template and added to the simulation netlist. The description d27 is a library corresponding to the resistance of the manufacturer model number “CN1J4TBK330J” generated from the model template and added to the simulation netlist. Note that, for example, the part of RN1 in the circuit diagram of FIG. 9A may be the same part as RN2 (manufacturer model number “MNR14E0APJ104”). In this case, the contents of the library are different between RN1 and RN2. It is necessary to distinguish the title of the library. Therefore, as model names (locations d22, d24, d25, and d27 in FIGS. 10A and 10B), “_P” and “_D” are appended to the model number to obtain “MNR14E0APJ104_P” and “CN1J4TBK330J_D”. Whether or not “_P” and “_D” are to be added is determined based on whether the description in the “output model name” column of the part-model correspondence table in FIG. Use “_D”.

  Returning to FIG. 8, the simulation netlist output unit 105 outputs (stores) the simulation netlist to the simulation netlist storage unit 114 (step S27), and ends the process (step S28).

<Example of application to logical connection verification>
FIG. 11 is a diagram illustrating a configuration example of a logical connection verification system using a simulation netlist.

  In FIG. 11, a functional block diagram F1 and a connector specification table F2 are created by the design specification creation unit 2 using MS-Visio (trade name, trademark) or the like. The functional block diagram F1 includes component information and connection information. The connector specification table F2 includes connector connection information.

  The functional block diagram F1 and the connector specification table F2 are reviewed by the parties concerned, and after the contents are corrected through corrections to the items to be pointed out, a drawing is input by CAD or the like, and a circuit diagram F3 is created.

  The logical connection verification unit 3 creates an expected value list F6 by the expected value generation unit 33 from the functional block diagram F1 and the connector specification table F2. The expected value list F6 shows combinations of logical values of nets in the circuit diagram.

  On the other hand, the logical connection verification unit 3 causes the simulation netlist generation unit 31 to generate a simulation netlist F4 from the circuit diagram F3. The simulation net list generation unit 31 corresponds to the simulation net list generation apparatus 1 shown in FIG.

  Subsequently, the logical connection verification unit 3 performs a simulation based on the simulation netlist F4 by the simulation unit 32 and outputs a simulation result F5. A simulation result F5 indicates a combination of logical values of each net in the circuit diagram.

  Then, the logical connection verification unit 3 compares the expected value list F6 with the simulation result F5 by the comparison unit 34, and outputs a verification result F7 indicating a match / mismatch situation.

  By referring to the verification result F7, it is possible to know whether the circuit diagram F3 is created as described in the functional block diagram F1 and the connector specification table F2, or if it is not created, what is wrong. The circuit diagram F3 can be corrected before the drawing.

<Summary>
As described above, the present embodiment has the following advantages.
(1) Prepare a library model template in which parts are organized by function and package unit in advance, select an appropriate model template based on circuit diagram information, and perform predetermined processing to create a library for simulation Can be easily performed.
(2) When a new part is added or when it is necessary to change the model description, the desired netlist result can be obtained simply by adding or changing the model template. Is no longer necessary.
(3) Although the logical result (0/1 value) varies depending on the circuit (how to connect signal lines and power / ground) even with the same component, the connection state of the net connected to each component symbol in the circuit diagram By determining the circuit pattern and specifying different model templates even for the same part, a more appropriate model template can be specified, and an accurate result can be obtained without correcting the circuit diagram.
(4) By describing a model model with a pin number, it is possible to prepare a model model in a collective manner because it is not necessary to use a unique function name depending on the manufacturer or part series of the part.
(5) By replacing the description of the pin number of the model template with the function name, it becomes easy to associate the function of each pin when following the net list, and the visibility of the net list can be improved.

  The present invention has been described above by the preferred embodiments of the present invention. While the invention has been described with reference to specific embodiments, various modifications and changes may be made to the embodiments without departing from the broad spirit and scope of the invention as defined in the claims. Obviously you can. In other words, the present invention should not be construed as being limited by the details of the specific examples and the accompanying drawings.

It is a figure which shows the structural example of the net list production | generation apparatus for simulation concerning one Embodiment of this invention. It is a figure which shows the example of a data structure of a circuit diagram file. It is a figure which shows the example of a data structure of a component-model corresponding table. It is a figure which shows the example of a model model. It is a flowchart which shows the process example of embodiment. It is a figure which shows examples, such as a circuit diagram. FIG. 10 is a first diagram illustrating an example of a simulation netlist; FIG. 10 is a second diagram illustrating an example of a simulation netlist; It is a flowchart which shows the other process example of embodiment. It is a figure which shows examples, such as a circuit diagram. It is FIG. (1) which shows the other example of the net list | wrist for simulation. It is FIG. (2) which shows the other example of the net list | wrist for simulation. It is a figure which shows the structural example of the logical connection verification system using the net list for simulation.

DESCRIPTION OF SYMBOLS 1 Simulation net list production | generation apparatus 101 Circuit diagram reading part 102 Component-model corresponding | compatible table reading part 103 Model model reading part 104 Simulation net list production | generation part 105 Simulation net list output part 111 Circuit diagram file storage part 112 Component-model correspondence Table storage unit 113 Model template storage unit 114 Simulation netlist storage unit 2 Design specification creation unit 3 Logical connection verification unit 31 Simulation netlist generation unit 32 Simulation unit 33 Expected value generation unit 34 Comparison unit F Circuit diagram file T part -Model correspondence table M Model template F1 Functional block diagram F2 Connector specification table F3 Circuit diagram F4 Simulation netlist F5 Simulation result F6 Expected value list F7 Verification result

Claims (3)

A circuit diagram reading unit for reading a circuit diagram file including at least part information including the address and symbol shape of the component on the circuit diagram and connection information indicating a connection relationship between the components, which is stored in the circuit diagram file storage unit;
A component-model correspondence table reading unit for reading a component-model correspondence table stored in the component-model correspondence table storage unit;
A model template reading unit that identifies an appropriate model template from the component-model correspondence table according to the component information and connection information included in the circuit diagram file, and reads the model template stored in the model template storage unit;
A simulation netlist generation unit that generates a simulation netlist based on the circuit diagram file and the model template ;
The model template reading unit determines a circuit pattern of each component included in the circuit diagram based on the component information and connection information of the circuit diagram file, and based on the circuit pattern, an appropriate model is determined from the component-model correspondence table. A simulation netlist generation device characterized by specifying a template . The simulation netlist generation device according to claim 1 ,
The model model stored in the model model storage unit describes a signal line on a circuit diagram with a pin number, and after the model model is read from the model model storage unit, the model model is replaced with a corresponding function name Netlist generator. A method executed by a simulation netlist generator,
A circuit diagram reading step for reading a circuit diagram file including at least part information including the address and symbol shape of the component on the circuit diagram and connection information indicating a connection relationship between the components, which is stored in the circuit diagram file storage unit;
A component-model correspondence table reading process for reading a component-model correspondence table stored in the component-model correspondence table storage unit;
A model template reading step of identifying an appropriate model template from the component-model correspondence table according to the component information and connection information included in the circuit diagram file, and reading the model template stored in the model template storage unit;
A simulation netlist generating step for generating a simulation netlist based on the circuit diagram file and the model template ;
The model template reading step determines a circuit pattern of each component included in the circuit diagram based on the component information and connection information of the circuit diagram file, and based on the circuit pattern, an appropriate model is determined from the component-model correspondence table. A simulation netlist generation method characterized by specifying a template .

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