JP5404709B2 - Semiconductor device, LED device, LED head, and image forming apparatus - Google Patents

Description

    The present invention relates to a semiconductor device such as an LED device, and an LED head and an image forming apparatus using the semiconductor device.

FIG. 33 is a perspective view schematically showing a part of a conventional LED print head 500, and FIG. 34 shows an LED array chip 502 as an example of an LED array chip that can be included in the LED print head of FIG. It is a top view which shows a part. The illustrated LED print head 500 has a structure in which the electrode pads 503 of the LED array chip 502 provided on the substrate 501 and the electrode pads 505 of the driving IC chip 504 provided on the substrate 501 are connected by bonding wires 506. have. Patent Document 1 below discloses a card-type information control device in which a thinned light emitting diode is attached to a card substrate.
(For example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 10-063807 (FIGS. 3 to 6, FIG. 8, paragraph 0021)

  However, in the LED print head 500 shown in FIGS. 33 and 34, since the LED array chip 502 and the driving IC chip 504 are connected by the bonding wires 506, the LED array chip 502 and the driving IC chip 504 are respectively connected. It was necessary to provide large (for example, 100 μm × 100 μm) electrode pads 503 and 505 for wire bonding. For this reason, it is difficult to reduce the area of the LED array chip 502 and the drive IC chip 504, and as a result, it is difficult to reduce the material cost.

  In the LED array chip 502, a region functioning as the light emitting unit 507 is a region having a depth of about 5 μm from the surface. However, in the LED print head 500 shown in FIGS. 33 and 34, in order to secure a stable yield of wire bonds, the wires may come into contact with the end of the IC chip or the end of the LED array chip. The thickness of the LED array chip 502 needs to be approximately the same as the thickness of the driving IC chip 504 (for example, 250 μm to 300 μm). Further, since the impact during wire bonding is large, it has been difficult to reduce the thickness of the LED chip provided with the wire bonding pads. For this reason, in the LED print head 500 described above, it has been difficult to reduce the material cost of the LED array chip 502.

  Therefore, in order to avoid connection by wire bonding, a pad on the light emitting element and a pad on the substrate are connected to each other by using a flip paste bonding method on a substrate provided with wiring as in Patent Document 1 described above. A connected form is conceivable. However, even in this case, it is necessary to provide a bonding pad on the light-emitting element, and a certain amount of bonding area is necessary to obtain a low resistance contact resistance (that is, a certain large bonding pad). Therefore, even when the flip chip bonding method using paste is applied, there is a limit in reducing the material cost.

  On the other hand, a form in which a thin semiconductor film such as a light-emitting element is directly attached to a substrate without performing connection between connection pads / connection pads by a flip chip bonding method or the like can be considered. In this embodiment, it is not always necessary to provide a connection pad that requires a certain large area. However, when the thinned semiconductor thin film is directly attached to the substrate, if no adhesive such as paste is used, the bonding strength between the thinned semiconductor thin film and the bonding region on the substrate is It was strongly dependent on the flatness of the attachment area.

  An object of the present invention is to solve these problems and attach a thin semiconductor thin film to a substrate, and between the semiconductor thin film and a predetermined wiring on the substrate or another element group provided on the substrate. In a form in which a wiring structure is provided, a form in which a necessary adhesion strength can be obtained between a thin semiconductor thin film and a substrate, and a semiconductor device and an LED device capable of forming a conductive contact with a necessary adhesion strength on the adhesion surface of the thin semiconductor thin film An LED head and an image forming apparatus are provided. In addition, in this invention, LED means a light emitting diode (Light Emitting Diode).

The semiconductor device of the present invention is
A substrate provided on the substrate, a multi-layered reflection film dielectric films having different refractive indices are stacked, is provided in the multi-layered reflection film, made of an organic conductive material, the opposing surface of the substrate and The opposite surface has a planarization layer that has been planarized, and a semiconductor thin film that includes a light-emitting element and is attached to the planarization layer.
Wherein the planarization layer, the flatness of the surface of the opposite surface of the substrate is characterized by a 5nm less der Turkey.

The LED device of the present invention is
A substrate provided on the substrate, a multi-layered reflection film dielectric films having different refractive indices are stacked, is provided in the multi-layered reflection film, made of an organic conductive material, the opposing surface of the substrate and The opposite surface has a flattened layer that has been flattened, and an LED thin film that includes a light emitting element and is affixed on the flattened layer,
Wherein the planarization layer, the flatness of the surface of the opposite surface of the substrate is characterized by a 5nm less der Turkey.

The LED head according to the present invention is
The above LED device;
And an optical system for guiding light emitted from the LED thin film.

Furthermore, an image forming apparatus according to the present invention includes:
An image forming apparatus having an image forming unit for forming an image of a recording material on a recording medium conveyed by a conveying unit,
The image forming unit includes: an image carrier; a charging unit that charges the surface of the image carrier; an exposure unit that selectively irradiates light to the charged surface to form an electrostatic latent image; Developing means for developing the electrostatic latent image,
The LED head is used as the exposure means.

  According to the semiconductor device of the present invention, when the semiconductor device is formed by bonding the semiconductor thin film layer on the substrate, the semiconductor devices can be firmly bonded to each other. According to another aspect of the present invention, the bonding strength between the substrate and the semiconductor thin film can be strengthened, and the reflected light reflected by the reflective thin film can be emitted from the light emitting surface.

It is a principal part block diagram which shows typically the laminated structure of the semiconductor composite device of Embodiment 1 by this invention. It is a principal part block diagram which shows typically the example of 1 structure at the time of comprising a compound semiconductor epitaxial by the semiconductor layer containing LED. It is a top view which shows notionally another formation example of the semiconductor compound apparatus formed by affixing a semiconductor thin film layer on the planarization layer. It is a top view which shows roughly the principal part structure of the semiconductor compound apparatus of Embodiment 2 by this invention. It is principal part sectional drawing which shows roughly the cross section which cuts the semiconductor compound apparatus shown in FIG. 4 by an AA line. (A) is a figure which shows the modification of Embodiment 2, (b), (c), (d), (e) is the part which shows another example of a connection of a light emission part area | region and a connection pad, respectively. It is a top view. It is a principal part block diagram which shows typically the laminated structure of the semiconductor composite apparatus of Embodiment 3 by this invention. (A) is the figure which showed the planarization effect of the planarization layer at the time of using a coating film as a planarization layer, (b) is a figure which shows the modification of the semiconductor compound apparatus of Embodiment 3. is there. It is a top view which shows notionally another formation example of the semiconductor compound apparatus formed by affixing a semiconductor thin film layer on the planarization layer. It is a top view which shows roughly the principal part structure of the semiconductor composite device of Embodiment 4 by this invention. It is principal part sectional drawing which shows roughly the cross section which cuts the semiconductor compound apparatus shown in FIG. 10 by an AA line. It is sectional drawing which shows roughly the principal part structure of the semiconductor composite device of Embodiment 5 by this invention. It is a top view which shows roughly the principal part structure of the semiconductor composite device of Embodiment 6 by this invention. It is principal part sectional drawing which shows roughly the cross section which cuts the semiconductor compound apparatus shown in FIG. 13 by an AA line. It is sectional drawing which shows schematically the principal part structure of the 1st modification of the semiconductor composite device of Embodiment 6. It is sectional drawing which shows roughly the principal part structure of the 2nd modification of the semiconductor composite device of Embodiment 6. It is sectional drawing which shows schematically the principal part structure of the 3rd modification of the semiconductor composite device of Embodiment 6. It is sectional drawing which shows schematically the principal part structure of the 4th modification of the semiconductor composite device of Embodiment 6. (A) is a top view which shows roughly the principal part structure of the semiconductor composite device of Embodiment 7 by this invention, (b) cuts the semiconductor composite device shown to (a) by the BB line. It is principal part sectional drawing which shows a surface schematically. It is a top view which shows roughly the principal part structure of the semiconductor composite device of Embodiment 8 by this invention. FIG. 21 is a main part sectional view schematically showing a section taken along line CC of the semiconductor composite device shown in FIG. 20; FIG. 28 is a cross sectional view schematically showing a main configuration of a first modification of the semiconductor composite device in Embodiment 8. It is sectional drawing which shows schematically the principal part structure of the 2nd modification of the semiconductor composite device of Embodiment 8. FIG. 21 is a main part sectional view schematically showing a section taken along line DD of the semiconductor composite device shown in FIG. 20; It is a top view which shows roughly the principal part structure of the semiconductor composite device of Embodiment 9 by this invention. It is principal part sectional drawing which shows roughly the cross section which cuts the semiconductor compound apparatus shown in FIG. 25 by EE line. It is principal part sectional drawing which shows roughly the cross section which cuts the semiconductor compound apparatus shown in FIG. 25 by FF line. It is sectional drawing which shows roughly the principal part structure of the semiconductor composite device of Embodiment 10 by this invention. It is sectional drawing which shows roughly the principal part structure of the semiconductor composite device of Embodiment 11 by this invention. It is a figure which shows the LED print head of Embodiment 12 based on the LED head of this invention. It is a plane arrangement | positioning figure which shows one structural example of an LED unit. It is a principal part block diagram which shows typically the principal part structure of the image forming apparatus of Embodiment 13 based on the image forming apparatus of this invention. It is a perspective view which shows a part of conventional LED print head roughly. It is a top view which shows a part of LED array chip as an example of the LED array chip which can be provided in the LED print head of FIG.

Embodiment 1 FIG.
FIG. 1 is a main part configuration diagram schematically showing a stacked structure of the semiconductor composite device according to the first embodiment of the present invention.

  As shown in the figure, the semiconductor composite device 1 has, for example, a Si substrate 2 which is a semiconductor substrate disposed as a first substrate in the lowermost layer, and has a function of planarizing the surface of the Si substrate 2 thereon. A planarizing layer 3 is formed. A semiconductor thin film layer 4, for example, a compound semiconductor epitaxial layer, is directly attached on the planarizing layer 3 whose surface has predetermined flat characteristics. The compound semiconductor epitaxial layer can be an LED thin film layer including a light emitting element such as a light emitting diode (hereinafter referred to as LED). In this case, the semiconductor composite device 1 corresponds to an LED device.

  FIG. 2 is a main part configuration diagram schematically showing a configuration example when the compound semiconductor epitaxial (semiconductor thin film layer 4) is configured by a semiconductor layer including an LED.

As shown in the figure, the semiconductor thin film layer 4 includes, in order from the lowest layer, a first conductivity type contact layer, for example, an n-GaAs layer 4a, and a first conductivity type cladding layer, for example, n-Al _x Ga _1-x. The As layer 4b, the first conductivity type active layer, for example, the n-Al _y Ga _1-y As layer 4c, the second conductivity type cladding layer, for example, the p-Al _z Ga _1-z As layer 4d, and the second layer For example, the contact layer has an epitaxial layer structure in which a p-GaAs layer 4e is stacked. In this example, for example, by setting y <x, z, an LED with high luminous efficiency can be formed.

In FIG. 1, an interlayer insulating film 7 is formed so as to cover the planarizing layer 3 and the semiconductor thin film layer 4. For example, an Si _x N _y film, an Al _x O _y film, an Si _x O _y film, a PSG film (P A silicon oxide film), a BSG film (silicon oxide film containing B), and a single-layer thin film such as a Si _x O _y N _z film, or a stacked film. The connection wirings 5 and 6 are respectively formed on the interlayer insulating film 7, and the first conductive type region and the second conductive type region of the semiconductor thin film layer 4 through the openings 7 a and 7 b formed in the interlayer insulating film 7. Has contact with each junction. That is, for example, when the semiconductor thin film layer 4 has the structure shown in FIG. 2, the connection wires 5 and 6 are respectively formed on the first conductive type layer 4a of the semiconductor thin film and on the second conductive type layer 4e of the semiconductor thin film. Has ohmic contact.

In the process of forming the semiconductor composite device 1, the semiconductor thin film layer 4 is formed on a second substrate (not shown) different from the Si substrate 2 as the first substrate. For example, the second substrate and GaAs substrate, the semiconductor thin film layer including an LED for example, _{thereon, n-GaAs / n-Al} x Ga 1-x As / n-Al y Ga 1-y As / p-Al z Ga _1-z As / p-GaAs is provided. At this time, for example, an AlAs layer is provided as a peeling layer between the GaAs substrate and the generated semiconductor thin film layer 4. After the semiconductor thin film layer 4 is formed on the second substrate through the peeling layer in this way, the peeling layer is selectively removed by etching with, for example, diluted hydrofluoric acid, hydrochloric acid, etc. The layer 4 is peeled off from the second substrate (GaAs substrate).

  In the semiconductor composite device 1 of the present embodiment, the semiconductor thin film layer 4 separately formed in this way is directly planarized without using an adhesive or a bonding material such as solder that forms a eutectic. 3 is attached to the structure.

The planarization layer 3 can be formed of a thin film such as a coating film layer, an oxide, a nitride, or a PSG film (silicon oxide film containing P), for example. Specific examples of coating film layers include SOG films (spin-on-glass films), polyimide films, and other stable films by volatilizing solvents by heat treatment and by causing crosslinking reaction by heating or light irradiation. There are organic films that form layers or thick film layers. For example, when the upper layer is an ion-bonding material such as a compound semiconductor material, an organic material having more polarity, the same material as the material included in the compound semiconductor material as its constituent material, or a chemically equivalent ( For example, a material containing an oxide having the same activation energy for the oxidation reaction is considered to be more suitable. On the other hand, when the upper layer is a material having a covalent bond such as Si, Ge, SiGe, or SiC, the semiconductor material is the same material as the material included as a constituent material, and is chemically equivalent (for example, the activation energy of the oxidation reaction is equivalent). ) (Including Si _x O _y and Si _x N _y (eg, x = 3, y = 4)) or organic materials having covalent chemical properties are suitable. It is done.

  Moreover, the organic material used as the planarization layer 3 may be, for example, a polymer imparted with photosensitivity. For example, in these organic materials, a polymer having a carbonyl group adjacent to a hetero atom may be used. For example, a material in which photosensitivity is imparted to a polymer including polyimide, polycarbonate, polyetherimide, polyarylate, polyurethane, polyamide, and polyamideimide may be used.

  The planarization layer 3 desirably has a surface flatness E of 5 nm or less. For the flatness of the surface, for example, means such as AFM (Atomic Force Microscope) or SPM (Scanning Probe Microscope) can be used to evaluate and measure the surface roughness on the order of nanometers. Obtained. The surface flatness is the flatness before the semiconductor thin film layer 4 is attached to the flattening layer 3, and shows the maximum difference in average peak / valley of the measurement region. Here, the average maximum peak / valley level difference means, for example, the maximum level difference between the top / valley of the surface excluding specific peaks such as particles on the surface.

  The following method is also effective for measuring the flatness. That is, in the state after the semiconductor thin film layer 4 is pasted, the region where the semiconductor thin film layer 4 is pasted, and the region where the semiconductor thin film layer 4 is pasted are pasted by pasting the semiconductor thin film layer 4 and subsequent processing. In a situation where the state of the attachment interface changes, the region where the surface state of the planarization layer 3 is considered to be maintained before the semiconductor thin film layer 4 is attached, for example, the region under the interlayer insulating film 7 It may be determined by a TEM (transmission electron microscope) image of each cross section.

According to the inventors' systematic experiment, the flatness E of the flattening layer 3 is
When 20 nm <E, it is difficult to attach the semiconductor thin film layer 4 to the planarization layer 3.
When 10 nm <E ≦ 20 nm, the semiconductor thin film layer 4 can be partially attached to the planarizing layer 3.
In the case of 5 nm <E ≦ 10 nm, the semiconductor thin film layer 4 can be attached to the planarization layer 3, but the attachment strength is weak,
In the case of 2 nm <E ≦ 5 nm, the semiconductor thin film layer 4 can be attached to the planarizing layer 3, and the result is that the attachment strength is high, and in the case of E ≦ 2 nm, the semiconductor thin film layer 4 is The result that the pasting strength when pasting on the flattening layer 3 was stably high was obtained.

  A suitable example regarding the thickness of the planarizing layer 3 based on the results of systematic experiments by the inventors is as follows.

  When the planarizing layer 3 cannot be provided thick, for example, when the planarizing layer 3 has a thickness of 3 μm or less, the flatness of the surface of the Si substrate 2 (the definition of planarity is the same as described above) should be 50 nm or less. Is desirable. In addition, when the flatness of the surface of the Si substrate 2 exceeds 10 nm, it is desirable that the thickness of the planarizing layer 3 is greater than 10 nm. Here, the flatness of the surface of the Si substrate 2 means that the surface with which the lower surface of the planarizing layer 3 is in direct contact, including the structure of the thin film, when a thin film is provided on the Si substrate 2. means.

  In addition, although it is desirable that the planarizing layer 3 has sufficient flatness so that the surface of the planarizing layer 3 is attached with a semiconductor thin film, chemical surface treatment (for example, etching) or mechanical surface treatment (for example, Polishing) or mechanochemical surface treatment (treatment with both chemical surface treatment and mechanical surface treatment) to form a material layer that constitutes a planarization layer, and then apply a semiconductor thin film to the surface Sufficient flatness may be imparted.

  FIG. 3 is a plan view conceptually showing another example of the semiconductor composite device formed by attaching the semiconductor thin film layer 4 on the planarizing layer 3 as shown in FIG. In the figure, for the sake of simplicity, an interlayer insulating film and the like are omitted.

  In the figure, a plurality of planarization layers 13a, 13b, and 13c are provided on the Si substrate 12, and formed on each planarization layer by a second substrate different from the Si substrate 12 as the first substrate. The semiconductor thin film layers 14a, 14b, and 14c are pasted. For this reason, these semiconductor thin film layers can be comprised by a separate semiconductor thin film layer according to an element form, for example, contains several elements, such as a light emitting element, a light receiving element, a transmitting element, or a receiving element. In the semiconductor composite device 11 of FIG. 3, for example, the light emitting element group is provided separately on the semiconductor thin film layer 14a, the light receiving element group is provided on the semiconductor thin film layer 14b, and the receiving / transmitting element group is provided separately on the semiconductor thin film layer 14c. . As described above, since the semiconductor thin film layers 14a, 14b, and 14c attached to the planarization layers 13a, 13b, and 13c are formed on different substrates, for example, the semiconductor thin film layer 14a for a light emitting element is 2 and the other semiconductor thin film layers 14b and 14c can have a different laminated structure.

  The Si substrate 12 further includes an integrated circuit 15 for controlling each element, a power supply pad for each element region, a pad 16 for signal input and signal output, and a wiring 17 for connecting each element. Is formed. Such functional integrated element chips can be formed on a wafer, for example.

  As for the semiconductor thin film layer, as described above, the semiconductor layer grown on another substrate may be chemically peeled off and then attached to a predetermined substrate. The substrate may be peeled off or the substrate may be removed by chemical or mechanical polishing after being applied, and the formation method is not limited.

  In the present embodiment, an example in which a Si substrate is employed as the first substrate has been described. However, the present invention is not limited to this example. For example, various materials such as ceramic, metal, glass, quartz, sapphire, and organic materials can be used. A material can be employed as the substrate.

  In the above-described embodiments, the example in which the semiconductor thin film layer is pasted on the planarizing layer is shown. However, the present invention is not limited to this, and another material or a structure material layer may be pasted. Good.

  Furthermore, in the description with reference to FIG. 3, an example is shown in which the planarization layers 13 a, 13 b, and 13 c are divided and formed, and the semiconductor thin film layers 14 a, 14 b, and 14 c are attached to predetermined regions of the respective planarization layers. However, the present invention is not limited to this. For example, the flattened layers 13a, 13b, and 13c formed separately may be formed as one continuous flattened layer. is there.

  As described above, according to the semiconductor composite device of the present embodiment, the planarization layer is provided on the substrate, and the semiconductor thin film layer is pasted on the planarization layer. Therefore, the semiconductor composite device with high quality and reliability can be provided.

Embodiment 2. FIG.
FIG. 4 is a plan view schematically showing a main configuration of the semiconductor composite device 21 according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line AA of the semiconductor composite device 21 shown in FIG. It is principal part sectional drawing which shows this roughly. In FIG. 4, for the sake of simplicity, the interlayer insulating film 35 (FIG. 5) for preventing short-circuits between the wirings and between the wirings and the conductive layers is omitted. Shown in a state lacking a part.

  As shown in the cross-sectional view of FIG. 5, the semiconductor composite device 21 includes, for example, a Si substrate 22, which is a semiconductor substrate, as a first substrate in the lowermost layer, and a multilayer insulating film region 23 on the Si substrate 22. Is formed. Unit elements including FETs, resistors, and the like using Si for driving a light emitting element described later are connected to predetermined regions of the Si substrate 22 and the multilayer insulating film region 23 using multilayer wiring. A drive integrated circuit region 24 in which a drive integrated circuit is formed is provided. The multilayer insulating film region 23 is a region having an interlayer insulating film laminated structure equivalent to the drive integrated circuit region 24, for example. A planarization layer 25 made of, for example, an organic thin film layer is formed on the multilayer insulating film region 23, and a semiconductor thin film layer 28 is formed on the planarization layer 25.

In the process of forming the semiconductor composite device 21, the semiconductor thin film layer 28 is formed by growing an epitaxial stack on a second substrate (not shown) different from the Si substrate 22 as the first substrate. For example, the second substrate and GaAs substrate, on _{which, n-GaAs / n-Al} x Ga 1-x As / n-Al y Ga 1-y As / p-Al z Ga 1-z As / p -Provide GaAs. At this time, for example, an AlAs layer is provided as a peeling layer between the GaAs substrate and the generated semiconductor thin film layer 28. In this way, the second substrate, via the peeling layer semiconductor thin film layer _{28 (n-GaAs / n-} Al x Ga 1-x As / n-Al y Ga 1-y As / p-Al z Ga _1-z As / p-GaAs), the release layer is selectively removed by etching with, for example, diluted hydrofluoric acid or hydrochloric acid, and the resulting semiconductor thin film layer 28 is formed into a second substrate (GaAs substrate). And then affixed on the planarization layer 25 as shown in FIG.

Further, at least a part of the semiconductor thin film layer 28 is removed by etching so that the pn junction is isolated, and as will be described later, the individual element region formed by isolating the lower region 26 and the upper region thereon. A plurality of superstructures 27. Here, the lower region 26 is a first conductivity type contact layer, for example, an n-GaAs layer, and the upper structure 27 is a first conductivity type cladding layer 27a, for example, an n-Al _x Ga _1-x As layer, For example, the n-Al _y Ga _1-y As layer is formed in the active layer 27b of one conductivity type, and the p-Al _z Ga _1-z As layer is formed in the clad layer 27c of the second conductivity type, and the contact layer 27d of the second conductivity type. For example, it is composed of a p-GaAs layer. For example, by setting y <x, z, it is possible to obtain an LED with high light emission efficiency using the upper structure 27 as a light emitting portion. As described above, in the process of forming the semiconductor composite device 21, the semiconductor thin film layer 28 is formed with a plurality of upper structures 27 in which elements are separated by etching in the upper region.

  The individual electrode contact 30 is formed on the interlayer insulating film 35 so as to cover the upper structure 27, and contacts the second conductivity type contact layer 27 d through the opening 35 a of the interlayer insulating film 35 formed on the upper structure 27. Electrically connected. Further, the individual electrode contact 30 is a transparent conductive film, for example, an inorganic material oxide thin film such as an indium / tin oxide (ITO) film or a zinc oxide film (ZnO) or an organic conductive film. The metal wiring 31 is formed on the interlayer insulating film 35, and the individual electrode contact 30 and the output terminal 32 of the driving integrated circuit for driving the LED are connected to the interlayer insulating film 35 formed on the output terminal 32. It is electrically connected through the opening 35b.

  The common electrode contact 33 is formed on the interlayer insulating film 35 at a position facing the lower region 26 of the semiconductor thin film layer 28 (on the contact layer of the lower region 26), and an opening 35c formed in the interlayer insulating film 35 is formed. And a metal contact connected to the lower region 26.

  On the other hand, as shown in FIG. 4, the planarization layer 25, the lower region 26 of the semiconductor thin film layer 28, and the common electrode contact 33 each extend in the longitudinal direction of the semiconductor composite device 21 and correspond to the light emitting portion of the LED. A plurality of element-separated upper structures 27 are arranged in substantially one row in the longitudinal direction of the semiconductor composite device 21. The output terminals 32 of the drive integrated circuit described above are also formed in the vicinity of the corresponding light emitting portions, and these are electrically connected by transparent individual electrode contacts 30 and metal wirings 31.

  The connection pads 34 are arranged at predetermined intervals along the common electrode contact 33 on the interlayer insulating film 35 (FIG. 5), and apply a common potential to the lower region 26 of the semiconductor thin film layer 28 from the outside. Therefore, each is electrically connected to the common electrode contact 33. Here, the connection pads 34 are not necessarily arranged at a predetermined interval, and a plurality of connection pads are not necessarily provided. The input pad 36 is an external connection portion for supplying power and drive signals to the integrated circuit formed in the drive integrated circuit region 24 (FIG. 5), and is electrically connected to a predetermined portion of the integrated circuit.

Specifically, the planarization layer 25 in the present embodiment may be a polyimide layer or another organic material layer. In addition to an organic material, an oxide layer, for example, a coating film such as a SiO ₂ film may be used. Further, it may be a film of SiO _x , SiN, SiON, ITO, ZnO, or the like. Here, SiO _x can be formed by, for example, sputtering, CVD, p-CVD, or coating. SiN and SiON films can be formed by, for example, p-CVD. ITO can be formed by, for example, sputtering. ZnO can be formed by sputtering or ion plating, for example, and the Al ₂ O ₃ film can be formed by sputtering, for example.

  Furthermore, the planarization layer 25 may be formed of an organic material layer, for example. The organic material layer may be formed by a vapor deposition method, a printing method, or a coating method. As the organic material, for example, polyacetylene, polypyrrole, polythiophene, polyparaphenylene, poly p-phenylene vinylene, polynaphthylene vinylene, polyaniline, polyethylene terephthalate, or the like can be used. In addition, transparent organic materials such as polymethyl methacrylate, polypropylene, polycarbonate, methyl methacrylate styrene, polyvinyl carbonate, polymethyl pentene, polystyrene, and alicyclic polyolefin resin may be used. For example, side chains may be introduced into these organic materials to make them soluble in a solvent, and the organic material layer may be formed by a method such as coating in a form melted in the solvent.

  Further, in the present embodiment, the bonding strength when the semiconductor thin film layer 28 is bonded to the flat lower layer 25 is at least a necessary manufacturing process such as formation of an interlayer insulating film, formation of an opening in the interlayer insulating film, and wiring formation. However, it is necessary that the semiconductor thin film has a strength that does not cause defects that affect device characteristics, yield, and reliability, such as peeling. The bonding strength of the semiconductor thin film can be easily evaluated by, for example, an etching test or a tape test. The flatness E of the flattening layer 25 for obtaining the required bonding strength is desirably 5 nm or less, and by further setting it to 2 nm or less, a high bonding strength can be stably obtained. Note that the definition of the flatness E is as described in the first embodiment, and a description thereof is omitted here.

  In this embodiment, mesa etching is performed to at least the active layer of the semiconductor thin film layer 28 to form the individual upper structure 27 (light emitting portion) separated from the element. For example, in the first conductivity type semiconductor epitaxial layer, Alternatively, a structure in which the second conductivity type impurity is selectively doped may be used. Further, the method of dividing each upper structure 27 that is a light emitting portion, and further, the method of dividing the common electrode can be modified as appropriate. Further, the driving method of the light emitting element group may be a wiring form that can be used in a matrix driving method.

  FIG. 6 is a diagram illustrating a modification of the second embodiment. As shown in FIG. 5A, the transparent individual electrode contact 30 (FIG. 5) is omitted, and the connection pad 36 covers the light emitting portion (corresponding to the upper structure 27) part of the region of the upper structure 27. It may be configured to be electrically connected to the contact layer 27d. FIGS. 6B, 6C, 6D, and 6E are portions showing another connection example of the light emitting portion (corresponding to the upper structure 27) region and the connection pad, respectively. It is a top view. FIG. 5B shows a configuration example in which the connection pad 36 is formed up to the middle of the light emitting portion region, and FIG. 5C shows the connection pad 36 formed so as to cover the end region adjacent to the light emitting portion region. An example configuration is shown. FIG. 6D shows a configuration example in which, for example, a conductive layer region 27g extending from the light emitting region 27f is provided in the upper structure 27, and a connection pad 36 is connected to the conductive layer region 27g. Shows a configuration example in which the connection pad 36 is formed so as to penetrate the light emitting portion region. Furthermore, it is not limited to the example shown here, The shape of the connection pad 36 can be variously modified. For example, a form surrounding the light emitting unit may be used, or a form extending in the horizontal direction (the vertical direction of the wiring 36) may be used. In this way, it is also possible to form an electrical wiring without using the transparent individual electrode contact 30 without much or no hindrance to the light output from the light emitting region.

  As described above, according to the semiconductor composite device of the second embodiment, the semiconductor thin film layer is pasted on the flat planarization layer to form the light emitting element array having the light emitting portion. A light-emitting element array with high strength, high reliability, and little variation in characteristics can be obtained.

Embodiment 3 FIG.
FIG. 7 is a main part configuration diagram schematically showing a stacked structure of the semiconductor composite device according to the third embodiment of the present invention.

  The semiconductor composite device 41 is mainly different from the semiconductor composite device 1 of the first embodiment shown in FIG. 1 in that a reflective layer 43 is provided under the planarizing layer 42. Accordingly, parts common to the semiconductor composite device 1 of the first embodiment described above are denoted by the same reference numerals in the semiconductor composite device 41, description thereof will be omitted, and different points will be mainly described.

  The reflective layer 43 provided under the planarization layer 42 is, for example, a metal layer, and is made of a single layer, stacked layer, composite or alloy, Ti, Pt, or Au of any element of Ti, Au, and Ge. Or a layer containing Cr, Ni, Pd, or Al. In particular, when the planarizing layer 42 is an organic layer, the uppermost layer of the reflective layer 43 is preferably Ti, Au, Cr, Ni, or Al. In addition, when the Si substrate includes an integrated circuit and a metal reflective layer is formed in a manufacturing process for manufacturing the integrated circuit, it is desirable to use a metal material that does not include an Au-based material.

Further, the reflective layer 43 may not be a metal layer, and may be a laminated material layer such as a semiconductor / insulating film or a semiconductor / semiconductor layer. As the semiconductor / insulating film, for example, a Si / SiO ₂ laminated film or a SiO ₂ / TiO ₂ laminated film can be used. In addition, a laminated film of a low refractive index material / a high refractive index material may be used. The low refractive index material can be a material such as SiO ₂ , CaF ₂ , LiF, or MgF _2, and the high refractive material can be TiO ₂ , CeO ₂ , CdS, ZnS, or the like. In addition, it may be a metal / semiconductor laminated film.

  The flatness of the surface of the reflective layer 43 is preferably 50 nm or less, and more preferably 15 nm or less. When the flatness of the surface of the reflective layer 43 is set as described above, the desired flattening can be performed with the flattening layer 42 provided thereon. FIG. 8A is a diagram showing the planarization effect of the planarization layer when a coating film is used as the planarization layer, for example. As shown in the figure, the flatness of the underlying layer (reflecting layer 43 in FIG. 7) located under the flattening layer is 50 nm, whereas the flatness on the flattening layer is 5 nm, which is about an order of magnitude higher. doing. Note that the definition of flatness is the same as that described in the first embodiment, and a description thereof is omitted here.

The reflective layer 43 may not be formed over the entire surface of the substrate, but may be formed in a pattern on the substrate. By forming the pattern in this way, the planarizing layer 42 formed of, for example, an organic material thin film can be provided on the reflective layer 43 with better adhesion. Furthermore, the reflective layer 43 is, for example, a metal layer, so that it functions as a conductive layer and a wiring layer provided below the back side of the material to be pasted on the planarizing layer 42 in addition to the function as a reflective layer. It can also be fulfilled. As a modification of the semiconductor composite device 41, as shown in FIG. 8B, another layer, for example, a dielectric film 48 such as a SiN film or a SiO ₂ film is provided between the substrate 2 and the reflective layer 43. May be.

  FIG. 9 is a plan view conceptually showing another formation example of the semiconductor composite device formed by attaching the semiconductor thin film layer 4 on the planarizing layer 42 as shown in FIG. In the drawing, for the sake of simplicity, the interlayer insulating film and the like are omitted, and for further explanation, the planarization layer 13a and the semiconductor thin film layer 14a are partially omitted.

  Further, the semiconductor composite device 45 shown in FIG. 9 is different from the semiconductor composite device 11 shown in FIG. 3 described in Embodiment 1 in that a reflective layer 46 is provided below the planarization layer 13a. Therefore, parts common to the semiconductor composite device 11 shown in FIG. 3 described above are denoted by the same reference numerals in this semiconductor composite device 45, description thereof will be omitted, and different points will be mainly described.

  In the figure, the semiconductor thin film layer 14a includes a light emitting element (for example, an LED, an LED array in which LEDs are arranged in one or two dimensions, a laser diode, a laser diode array in which laser diodes are arranged in one or two dimensions), A planarizing layer 13a is formed below the semiconductor thin film layer 14a, and a reflective layer 46 is formed below the planarizing layer 13a. For example, the semiconductor thin film layer 14a can have the same configuration as the semiconductor thin film layer 28 described in the second embodiment.

  With this configuration, light emitted from the light emitting element provided on the semiconductor thin film layer 14a in the back surface direction (lower layer direction than the semiconductor thin film layer 14a) is reflected by the reflective layer 46 and extracted from the upper surface of the semiconductor thin film layer 14a. Therefore, substantial luminous efficiency can be improved.

  As described above, when the light emitted toward the back surface of the semiconductor thin film layer 14a is reflected from the reflective layer 46 and extracted from the upper surface, the light absorption by the planarization layer 13a provided on the reflective layer 46 is minimized. Therefore, the thickness (film thickness) of the planarization layer 13a is reduced. In particular, when an organic material film is used as the planarizing layer 13a, the thickness is desirably 1 μm or less. For example, when an organic material film material such as polyimide is used for the planarizing layer 13a, the inventors have reflected the light from the back surface obtained by setting the film thickness to 1 μm or less, and thereby the upper surface of the semiconductor thin film layer 14a. It has been experimentally confirmed that the amount of light extracted from the liquid is substantially doubled.

  The reflective layer 46 may be formed by applying or printing a conductive liquid material. For example, when a coating material containing a metal material is applied, the coating material is cured by annealing after coating, and can be substantially made into a metal layer or a conductive material layer.

  As described above, according to the semiconductor composite device of the present embodiment, since the reflective layer is provided under the planarization layer, the semiconductor thin film layer is firmly fixed to the substrate via the planarization layer, and the light emitting unit Since the light emitted from the semiconductor thin film layer having the surface in the back surface direction (lower layer direction) can be reflected and taken out from the front surface, substantial light emission efficiency can be improved. If the reflective layer is formed of a metal layer, it can be used as a conductive layer on the lower layer side of the semiconductor thin film layer.

Embodiment 4 FIG.
FIG. 10 is a plan view schematically showing a main configuration of a semiconductor composite device 51 according to the fourth embodiment of the present invention. FIG. 11 is a cross-sectional view taken along line AA of the semiconductor composite device 21 shown in FIG. It is principal part sectional drawing which shows this roughly. In FIG. 10, for the sake of simplicity, the interlayer insulating film 35 (FIG. 5) for preventing short-circuit between each wiring and between the wiring and the conductive layer is omitted. For further explanation, individual electrode contacts 30 and A state in which a part of the planarizing layer 25 is omitted is shown.

  The semiconductor composite device 51 is mainly different from the semiconductor composite device 21 shown in FIG. 5 in that a reflective layer 52 is provided under the planarization layer 25. Therefore, parts common to the semiconductor composite device 21 of the first embodiment described above are denoted by the same reference numerals in the semiconductor composite device 51, and the description thereof is omitted here, and different points are mainly described. In FIG. 11, the reflective layer 52 is provided on the multilayer insulating film region 23. However, the reflective layer may be provided in contact with the substrate 22 if necessary, or on the substrate 22 instead of the multilayer film. You may provide on the provided single layer film.

  The reflective layer 52 provided under the planarizing layer 25 is, for example, a metal layer, and is made of a single layer, a laminate, a composite or an alloy, Ti, Pt, or Au of any element of Ti, Au, and Ge. Or a layer containing Cr, Ni, Pd, or Al. In particular, when the planarizing layer 25 is an organic material layer, the uppermost layer of the reflective layer 52 is desirably Ti, Au, Cr, Ni, or Al. In the case where the Si substrate includes an integrated circuit and a metal reflective layer is formed in a manufacturing process for manufacturing the integrated circuit, a metal material that does not include an Au-based material (for example, Ni, Pt, Ti, Al, etc.) It is desirable to use a material containing

Further, the reflective layer 52 may not be a metal layer, but may be a laminated material layer such as a semiconductor / insulating film or a semiconductor / semiconductor layer. As the semiconductor / insulating film, for example, a Si / SiO ₂ laminated film or a SiO ₂ / TiO ₂ laminated film can be used. In addition, a laminated film of a low refractive index material / a high refractive index material may be used. Examples of the low refractive index material include SiO ₂ , CaF ₂ , LiF, and MgF _2, and examples of the high refractive material include TiO, CeO ₂ , CdS, and ZnS. In addition, it may be a metal / semiconductor laminated film.

  The flatness of the surface of the reflective layer 52 is preferably 50 nm or less, and more preferably 15 nm or less. When the flatness of the surface of the reflective layer 52 is set as described above, the desired flattening can be performed by the flattening layer 25 provided thereon. Note that the definition of flatness is the same as that described in the first embodiment, and a description thereof is omitted here.

  Further, the reflective layer 52 may be a pattern formed on a substrate. By forming the pattern in this way, the planarizing layer 25 formed of, for example, an organic material thin film can be provided on the reflective layer 52 with good adhesion. Further, the reflective layer 52 may be a metal layer, for example, and may function as a conductive layer provided below the back side of the material to be pasted on the planarizing layer 25 in addition to the function as a reflective layer. it can.

  As described above, according to the semiconductor composite device of the fourth embodiment, the semiconductor thin film layer is pasted on the flat planarizing layer to form the light emitting element array having the light emitting portion. A light-emitting element array with high strength, high reliability, and little variation in characteristics can be obtained. In addition, since a reflective layer such as a metal layer is provided under the planarization layer, a light emitting element array with high light emission efficiency can be obtained.

Embodiment 5 FIG.
FIG. 12 is a cross sectional view schematically showing a main configuration of a semiconductor composite device 55 according to the fifth embodiment of the present invention.

  The semiconductor composite device 55 is mainly different from the semiconductor composite device 51 of the fourth embodiment shown in FIG. 11 described above in that an inorganic material layer (intermediate layer) is provided between the reflective layer 52 and the planarizing layer 25. Is a point. Therefore, parts common to the semiconductor composite device 51 of the fourth embodiment described above are denoted by the same reference numerals or the drawings are omitted and the description thereof is omitted here, and different points are emphasized. Explained. The cross section shown in FIG. 12 is a cross section taken along the line AA shown in the plan view of FIG. 10 in the semiconductor composite device 51 of the fourth embodiment, that is, the upper region 27 of the semiconductor composite device 55 is formed. It corresponds to the cross section at the part.

  As shown in FIG. 12, an inorganic material layer 56 as an intermediate layer is formed between the reflective layer 52 and the planarizing layer 25. The material suitable for the reflective layer 52 is as described in the third and fourth embodiments, and the material suitable for the planarizing layer 25 is as described in the first to fourth embodiments. Explanation here is omitted.

The intermediate layer 56 may be an oxide film or a nitride film, for example, SiO _x (for example, x = 2), Si _x O _y N _z , Si _x N _y , or Al ₂ O ₃ .

  As described above, according to the semiconductor composite device of the fifth embodiment, by providing the inorganic material layer 56 as the intermediate layer, the planarizing layer 25, for example, an organic material layer provided on the reflective layer 52, It can be provided with better adhesion. Also in the fifth embodiment, the electrode configuration as described in the second embodiment (FIG. 6) can be modified.

Embodiment 6 FIG.
FIG. 13 is a plan view schematically showing a configuration of a main part of the semiconductor composite device 101 according to the sixth embodiment of the present invention. FIG. 14 is a cross section of the semiconductor composite device 101 shown in FIG. It is principal part sectional drawing which shows this roughly.

  As shown in the cross-sectional view of FIG. 14, in the semiconductor composite device 101, for example, a Si substrate 110, which is a semiconductor substrate, is disposed as a first substrate in the lowermost layer, and a semiconductor element formation region 111 is formed thereon. Yes. In the semiconductor element formation region 111, an insulating region, an impurity doped region, or a junction region is formed, and each element such as a diode, a transistor, or a resistor or a capacitor is formed. For example, a digital or analog integrated circuit is formed. Is done.

  The wiring region 112 thereabove is a circuit having a wiring region for connecting the component region of the semiconductor element forming region 111 by two-dimensional or three-dimensional wiring, and a wiring pad region for connection to an external circuit. A wiring region 112a is included. The second wiring region 112b is a region that is formed at the same time as the wiring region 112, for example, and has a film structure or the like that is the same as the wiring region 112.

  The conductive layer 114 is, for example, a metal layer provided on the second wiring region 112b, and includes any element of Au, Ni, Ge, Pt, Ti, In, and Al. It is made of an alloy material. The conductive layer 114 is connected to an element or an element group constituting a semiconductor composite device such as a drive integrated circuit by a wiring connection pad provided in the second wiring region 112b. Alternatively, the conductive layer 114 is connected to a pad for connection to the outside of the semiconductor device by a wiring (not shown). On the conductive layer 114, a planarized conductive layer 115 having a sufficiently flat surface for attaching a semiconductor thin film is formed. The planarization conductive layer 115 is an organic conductive material layer formed by, for example, a coating method, a vapor deposition method, a printing method, or the like.

As the organic conductive material, for example, polyacetylene, polypyrrole, polythiophene, polyparaphenylene, poly p-phenylene vinylene, polynaphthylene vinylene, polyaniline, polyethylene terephthalate, or the like can be used. These materials can be used after appropriate doping. Examples of the dopant include halogens such as iodine and bromine, Lewis acids such as FeCl ₃ and AsF ₅ , proton acids such as HNO ₃ , H ₂ SO ₄ and HClO ₄ , transition metal halides such as FeCl ₃ and MoCl ₅ , LI Alkali metals such as Na and K, and alkylammonium ins such as tetraethylammonium can be used. An organic material layer, particularly a polymer material layer, can be expected to have good surface flatness when formed.

  In another example of the planarization conductive layer 115, a transparent conductive material layer or a metal layer may be used. The transparent conductive material layer is, for example, a conductive metal containing elements such as indium tin oxide (ITO), zinc oxide (ZnO), or Cu, Sr, Bi, Ca, Y, Rb, etc. It may be an oxide. The metal layer is formed of, for example, Ti, Ni, Cr, Ge, Pd. Note that the planarization conductive layer 115 is a material through which an electric current can flow, and it is desirable that the surface has sufficient planarity to form a semiconductor thin film when formed, but a chemical surface treatment ( For example, etching), mechanical surface treatment (for example, polishing), or mechanochemical surface treatment to form a material layer constituting the planarization layer and then provide sufficient flatness to attach a semiconductor thin film to the surface. May be.

A semiconductor thin film layer 116 is disposed on the planarized conductive layer 115. The semiconductor thin film layer 116 has, for example, a single layer of GaAs, AlGaAs, AlGaInP, InP, GaP, GaInP, GaN, AlGaN, InGaN, and AlGaInAs, or a laminated structure composed of various mixed crystal ratios of these materials. . In our example, having a pn _junction, is _{n-GaAs / n-Al x} Ga 1-x As / n-Al y Ga 1-y As / p-Al z Ga 1-z As / p-GaAs . However, 0 ≦ x, y, z ≦ 1, and for example, y <x, z.

Here, the semiconductor thin film layer 116 has a structure in which at least a part is removed by etching so as to isolate the pn junction, and as will be described later, the lower region 116a and the upper region 116b are formed by element isolation. A plurality of upper structures 116c which are individual element regions. Lower region 116a is, for example, _{n-GaAs / n-Al x} Ga 1-x As, the superstructure 116 b, includes at least pn connection regions, for example _{n-Al y Ga 1-y} As layer / p-Al _z It is a Ga _1-z As / p-GaAs layer. The lower region 116a, construction of the upper region 116b is capable of various modifications, for example, a lower region 116a n-GaAs, the upper region _{116b n-Al x Ga 1-} x As / n-Al y Ga 1-y As layer _{/ p-Al z Ga 1-} z may be used as the as / p-GaAs layer, the lower region _{116a n-GaAs / n-Al} x Ga 1-x as, an upper region _{116b n-Al x Ga 1-} x _{as / n-Al y Ga 1} -y as layer _{/ p-Al} z Ga may be 1-z as / p-GaAs layer.

  The semiconductor material may be an AlGaAs-based material, an AlGaInP-based material, an AlGaAsP-based material, a nitride-based material including AlGaN, GaN, AlInN, or InGaN. In addition, the nitride-based semiconductor may be a III-VN type semiconductor material such as GaAsN, GaPN, InAsN, InPN, InGaAsN, InPAsN, and GaPAsN. Further, it may be a group I-VI compound semiconductor material such as ZnSe.

  The individual electrode 117 is formed on the interlayer insulating film 113, and connects the upper structure 116c of the semiconductor thin film layer 116 which is a pn junction element region and the output pad 122 which is a predetermined output terminal region of the circuit wiring region 112a to the interlayer insulating film. Metal wiring (wiring formed with a thin film of metal material) individually connected through openings 113a and 113b formed in 113. The material of the individual electrode 117 is, for example, Ti / Pt / Au, AuGe / Ni / Au, Ti / Pt / Al, Ni / Al, AlSiCu, TiN, or the like. In the semiconductor thin film layer 116, the combination of the lower region 116a and the upper structure 116c formed by separating the upper region 116b into the element forms a semiconductor element in the sixth embodiment.

  For example, the conductive layer 114 applies a common potential, for example, a ground potential, to each semiconductor element formed in the semiconductor thin film layer 116. Therefore, a ground potential is supplied to the conductive layer 114 via an electrode pad (not shown) on the substrate or a ground potential line of the integrated circuit.

  On the other hand, as shown in FIG. 13, the circuit wiring region 112 a and the second wiring region 112 b each extend in the longitudinal direction of the semiconductor composite device 101. The conductive layer 114 is formed on the second wiring region 112b, the planarized conductive layer 115 is formed on the conductive layer 114, and the semiconductor thin film layer 116 is formed on the planarized conductive layer 15, respectively. It extends in the longitudinal direction. The lower region 116a of the semiconductor thin film layer 116 is, for example, at least a region below the pn junction surface, and the upper region 116b is located on the lower region 116a and includes at least the pn junction surface in the region, and is etched away. Elements are separated into a plurality of upper structures 116c which are individual element regions.

  In FIG. 13, the lower region 116a is drawn as a region common to the plurality of individual element regions 116c. However, the lower region 116a may be separated into individual regions by etching. Further, as shown in FIG. 13, a common electrode is provided for all the individual elements, and in addition to a mode of driving by a static method, the common electrode is divided into a plurality of parts and the common electrode and the individual electrodes are driven by a matrix method. Form may be sufficient. Further, the individual electrode 117 may be formed of a transparent conductive thin film in addition to the metal thin film. Further, as shown in FIG. 12, the individual electrode 117 may be formed by combining a transparent conductive thin film and a metal thin film.

  Further, in the present embodiment, the semiconductor element is an LED, and a plurality of upper structures 116 c corresponding to the light emitting portions are arranged in a line in the longitudinal direction of the semiconductor composite device 101. An integrated circuit output pad 122 for driving the LED is formed at each position of the circuit wiring region 112a facing the plurality of upper structures 116c. Similarly, an input pad 121 for inputting an external signal, power supply, etc. is formed at a predetermined position in the circuit wiring region 112a. Between the plurality of upper structures 116c and the output pads 122 formed opposite thereto, individual electrodes 117 are individually connected to each other. In FIG. 13, for the sake of simplicity, the interlayer insulating film 113 (FIG. 14) for preventing short-circuit between each wiring and between the wiring and the conductive layer is omitted.

  Next, the operation of the semiconductor composite device 101 configured as described above will be described.

  The semiconductor composite device 101 inputs a power source and a signal for driving and controlling the LED formed on the semiconductor thin film layer 116 from the input pad 121 (FIG. 13), and thereby the semiconductor thin film layer from the output pad 122 of the integrated circuit. In 116, individual currents are supplied to the plurality of upper structures 116c forming the light emitting portions of the LEDs, and lighting of each LED is controlled. Further, the common potential of each LED is supplied to the lower region 116 a of the semiconductor thin film layer 116 via the conductive layer 114 and the planarized conductive layer 115.

  Next, a method for manufacturing the semiconductor composite device 101 configured as described above will be described.

The semiconductor thin film layer 116 is formed by growing an epitaxial stack on a second substrate (not shown). For example, the second substrate and GaAs substrate, for example on _{its, n-GaAs / n-Al} x Ga 1-x As / n-Al y Ga 1-y As / p-Al z Ga 1-z As / p-GaAs is provided. In this case, the semiconductor thin film layer ₁₁₆ that generated the GaAs substrate _{(n-GaAs / n-Al} x Ga 1-x As / n-Al y Ga 1-y As / p-Al z Ga 1-z As / p-GaAs ), For example, an AlAs layer is provided as a release layer.

  After the semiconductor thin film layer 116 is formed on the second substrate through the release layer in this manner, the release layer is selectively removed by etching with, for example, diluted hydrofluoric acid or hydrochloric acid. 116 is peeled from the second substrate (GaAs substrate). Under the present circumstances, the support body for protecting the produced | generated semiconductor thin film layer 116 can be provided suitably.

  On the other hand, an integrated circuit for driving and controlling the light emitting elements is formed on the Si substrate 110 (FIG. 13) (semiconductor element formation region 111 and wiring region 112). A circuit wiring region 112a and a second wiring region 112b, which are multilayer wiring regions constituting the integrated circuit, are formed on the integrated circuit. A conductive layer 114 is formed on the second wiring region 112b, and a planarized conductive layer 115 is formed. When the planarizing layer 115 is formed of an organic conductor material, a vapor deposition method is used in the case of a low molecular organic material, and a coating method (spin coating method) or a printing method (screen printing method or Ink jet method), doctor blade method and the like.

When the planarizing conductive layer 115 is formed of a metal oxide such as ITO or ZnO, it can be formed by, for example, a sputtering method or an ion plating method. In the case where the planarization conductive layer 115 is formed using a conductive metal oxide containing an element such as Cu, Sr, Bi, Ca, Y, or Rb, it can be formed by a sputtering method or the like. When the planarizing conductive layer 115 is formed using a metal layer, it can be formed by, for example, a resistance heating method, a sputtering method, or an electron beam evaporation method. The thickness of the planarized conductive layer 115 can be set to, for example, 50 nm-5 μm. As for the resistance of the planarized conductive layer 115, for example, the specific resistance is desirably 5 × 10 ⁻³ Ωcm or less.

  In the planarized conductive layer 115, for example, when a current = 1 mA flows in a thickness = 1 μm, a width = 50 μm, a length = 50 μm, a voltage drop is 0.05 V, and a voltage when driving an LED (drive voltage: Vf) is not greatly affected. Regarding the merit / demerit of the flattened conductive layer 115 when it is thin or thick, the resistance increases and the forward direction Vf increases when the film thickness is thin, and the resistance can be reduced when the film thickness is thick. , Stress increases.

  The electrode pattern of the individual electrode 117 is formed by a standard lift-off method or a photolithography / etching method. In the case of forming a pattern by etching, for example, in the case of ITO, a hydrochloric acid-based etching solution can be used, and in the case of ZnO, for example, a hydrofluoric acid-based etching solution can be used. In the case of forming a conductive metal oxide containing elements such as Cu, Sr, Bi, Ca, Y, and Rb, it can be formed by photolithography / etching using a hydrofluoric acid-based or hydrochloric acid-based etching solution or a lift-off method. . Note that it is preferable that the planarization conductive layer 115 be optimized for thin film formation conditions so that desired flatness can be obtained when the thin film is formed.

  After the planarized conductive layer 115 is formed in this manner, sintering is performed to reduce electrical contact resistance. In the case where the planarization conductive layer 115 is formed using a metal oxide, low-efficiency reduction of the planarization conductive layer 115 is achieved by sintering. At this time, the sintering is performed at a sintering temperature in a temperature range that does not damage the conductive layer 114, the elements in the semiconductor element formation region 111, and the planarization layer electrode layer 115, for example. In the case where the planarized thin film is an organic conductive material, the temperature is set according to the material characteristics, for example, 300 ° C. or lower. In the case of a metal oxide material, the temperature is set to 500 ° C. or lower.

  Thus, the semiconductor thin film layer formed on the planarized conductive layer 115 made of the transparent conductive film shown as an example on the second substrate (GaAs substrate) (not shown) and peeled off from the second substrate as described above. 116 is bonded and, for example, sintered at a temperature of 100 to 400 ° C. for about 1 to 3 hours to obtain necessary bonding strength and electrical contact between the semiconductor thin film layer 116 and the planarized conductive layer 115. After that, as described above, the upper region 116b is separated by etching to form a plurality of upper structures 116c that are individual device regions. In the present embodiment, the upper structure 116c corresponds to the light emitting portion of the LED that is a semiconductor element as described above.

  As shown in FIG. 15, the semiconductor composite device 101 according to the sixth embodiment has a connection opening 118a between the conductive layer 114 and the wiring region 112, as shown in FIG. Another planarization layer 118 may be provided, such as an oxide or nitride dielectric thin film. In this case, the conductive layer 114 is electrically connected to the second wiring region 112b through the connection opening 118a.

  Further, as shown in FIG. 16, the semiconductor composite device 101 according to the sixth embodiment omits the conductive layer 114 and extends the planarized conductive layer 115 to the connection region of the wiring region 112b. You may connect.

  Further, as shown in FIG. 17 as a third modification, the semiconductor composite device 101 of the sixth embodiment is an organic material such as polyimide having a connection opening 118a between the conductive layer 114 and the planarized conductive layer 115. Another planarization layer 118, such as a material or a dielectric thin film of oxide or nitride, may be provided. In this case, the planarization conductive layer 115 is electrically connected to the conductive layer 114 through the connection opening 118a.

  Further, in the semiconductor composite device 101 of the sixth embodiment, a metal layer 119 can be provided between the semiconductor thin film layer 116 and the planarized conductive layer 115 as shown in FIG. In this case, for example, a metal thin film, such as AuGe / Ni / Au or Ti / Pt / Au, is provided on the back surface (GaAs layer functioning as a contact layer) of an AlGaAs-based semiconductor thin film layer, and is pasted on the planarizing conductive layer 115. Alternatively, a metal layer can be provided over the planarization conductive layer 115 and a semiconductor thin film layer can be attached thereover. When a GaN-based semiconductor thin film is used as the semiconductor thin film layer 116, when a p-type layer is in contact with the metal thin film layer 119, a metal layer such as aluminum or titanium / aluminum, or an n-type layer is in contact, A metal layer such as gold, platinum, or nickel can be provided. These metal layers may be formed to be thin and translucent.

  Further, for example, in FIG. 18, wiring connection is made by the planarized conductive layer 115 instead of the conductive layer 114, the semiconductor element formation region 111 and the second wiring region 112 b are omitted, and the conductive layer 114 is provided on the substrate 110. The thin film structure below the semiconductor thin film layer 116 shown in FIG. 18 can be formed by appropriately selecting.

  According to the semiconductor composite device of the sixth embodiment as described above, the following effects can be obtained.

  Since the semiconductor thin film is affixed on the conductive thin film layer with excellent flatness, the semiconductor thin film can be firmly attached and the ohmic contact can be formed on the back surface of the semiconductor thin film, thus simplifying the wiring structure of the device And the size of the semiconductor thin film can be reduced.

  Further, the following effects can be further obtained by making the planarizing conductive layer particularly an organic conductive layer. Organic thin film materials, particularly polymer materials, have the effect of following the surface structure of the substrate well and reducing the surface roughness, and the effect of increasing the bonding strength is obtained. In addition, for example, a material used as a planarization layer with a large forbidden band width (HOMO (highest occupied level) −LUMO (lowest empty level)) with respect to the energy of light emitted from the LED is used. The transmittance of light emitted from the light emitting element can be increased by selecting a material that does not absorb light or has low absorption. Therefore, the conductive layer provided under the planarized conductive layer is reflected by a layer having a high reflectance such as metal, and a semiconductor composite device with high light emission efficiency is obtained.

  Further, the following effects can be further obtained by making the planarizing conductive layer particularly a transparent oxide layer. First, since the planarized conductive layer surface is an oxide layer, hydrophilicity is obtained on the surface, and high strength adhesive force is obtained by interposing moisture. In addition, since the planarized conductive layer is transparent, light emitted from the semiconductor thin film layer and radiated to the opposite side of the light emitting surface is transmitted through the planarized conductive layer and reflected from the surface of the conductive layer made of metal to be reflected by the light emitting surface. Therefore, the adhesive strength can be increased without reducing the light emission intensity, and a semiconductor composite device having a high light emission intensity can be obtained.

  When the planarizing conductive layer is made of metal, reflection is performed with high reflectivity on the mirror-like metal layer surface with less light scattering, so that a semiconductor composite device with high emission intensity can be obtained.

  In this embodiment mode, a conductive layer 114 is provided under the planarization conductive layer 115, and a common potential is connected to the conductive layer 114 via an electrode pad (not shown) or a ground potential line of an integrated circuit. However, the present invention is not limited to this, and the common potential may be directly supplied to the planarized conductive layer 115 without providing the conductive layer 114. In this case, the conductive layer 114 can be omitted. In this case, if the planarization conductive layer 115 is a transparent layer, a high emission intensity can be maintained by providing a direct reflection layer below the planarization conductive layer 115.

Embodiment 7 FIG.
FIG. 19A is a plan view schematically showing a main part configuration of the semiconductor composite device 131 according to the seventh embodiment of the present invention. FIG. 19B is a semiconductor composite device shown in FIG. It is principal part sectional drawing which shows roughly the cross section which cuts 131 by a BB line.

  The semiconductor composite device 131 of the present embodiment is mainly different from the semiconductor composite device 101 of the sixth embodiment shown in FIG. 13 described above to drive a semiconductor element (for example, LED) formed in the semiconductor thin film layer 135. The semiconductor element forming region 111 (FIG. 14) in which the integrated circuit for forming the circuit is formed and the wiring region 112 (FIG. 14) in which the wiring of the integrated circuit is formed are removed. An electrode contact 136 and the like are provided. The configuration of the semiconductor composite device 131 of the present embodiment will be described below.

  As shown in the cross-sectional view of FIG. 19B, in the semiconductor composite device 131, a conductive layer 133 is formed on a Si substrate 132 which is a semiconductor substrate, for example, as a first substrate. The conductive layer 133 is a metal layer, for example, and is formed of a single layer, a multilayer, a composite, or an alloy material containing any element of Au, Ni, Ge, Pt, Ti, In, and Al. A planarized conductive layer 134 is formed on the conductive layer 133. The planarization conductive layer 134 is an organic conductive material layer formed by, for example, a coating method, a vapor deposition method, a printing method, or the like. The organic conductive material is formed of, for example, the material described in the description of the sixth embodiment. An organic material layer, particularly a polymer material layer, can be expected to have good surface flatness when formed.

  In another example of the planarization conductive layer 134, a transparent conductive material layer or a metal layer may be used. The transparent conductive material layer is a conductive metal oxide containing elements such as indium / tin oxide (ITO), zinc oxide (ZnO), or Cu, Sr, Bi, Ca, Y, Rb. May be. The metal layer is made of, for example, Ti, Ni, Cr, Ge. Note that the planarization conductive layer 134 is a material through which an electric current can flow, and it is desirable that the surface has sufficient planarity to form a semiconductor thin film when formed, but a chemical surface treatment ( For example, etching), mechanical surface treatment (for example, polishing), or mechanochemical surface treatment to form a material layer constituting the planarization layer and then provide sufficient flatness to attach a semiconductor thin film to the surface. May be. A semiconductor thin film layer 135 is disposed on the planarization conductive layer 134.

  The semiconductor thin film layer 135 has, for example, the same configuration as that of the semiconductor thin film layer 116 of the sixth embodiment described above, and has at least a structure in which a part of the pn junction is removed by etching so as to isolate the element. As described above, it is an individual element region formed by separating the lower region 135a (equivalent to the lower region 116a in the sixth embodiment) and the upper region 135b (equivalent to the lower region 116b in the sixth embodiment) into elements. It has a plurality of upper structures 135c (equivalent to the upper structure 116c in Embodiment 6).

  Further, a method for manufacturing the semiconductor thin film layer 135, a method for bonding the semiconductor thin film layer 135 on the planarization conductive layer 134, a method for planarizing the planarization conductive layer 134, and the like will be described in Embodiment 6 described above. The description is omitted here.

  A common electrode 137 is formed on the lower surface of the Si substrate 132. The common electrode 137 and the conductive layer 133 desirably have an ohmic contact on the substrate surface of the first substrate 132.

  An interlayer insulating film 138 (FIG. 19B) is formed on the upper surface of each of these layers (not shown in FIG. 19A), and the upper surface of the first substrate 132 is interposed with an interlayer insulating film 138 interposed therebetween. Thus, a plurality of electrode pads 139 are formed as shown in FIG. The plurality of upper structures 135c separated from each other have openings 138a in the interlayer insulating film 138 formed thereon, and corresponding electrode pads 139 are formed by electrode contacts 136 that are electrically connected through the openings 138a. Is electrically connected. The electrode pad 139 is a connection pad (wire bonding pad) for connection to an external drive circuit.

  In this embodiment, the conductive layer 133 is formed on the conductive Si substrate 132 and the planarized conductive layer 134 is provided thereon. However, the conductive layer 133 may be provided directly on the Si substrate 132. Further, the planarization conductive layer 134 may be at least under the semiconductor thin film layer 135 or a semiconductor element included in the semiconductor thin film layer 135, for example, an LED, and the formation area can be variously modified. Further, the conductive layer and the planarizing conductive layer may be formed on the integrated circuit through an interlayer insulating film or another planarizing layer, for example. An opening for wiring can be appropriately provided in the interlayer insulating film or the planarization layer. Further, a conductive layer such as a metal thin film layer may be provided between the semiconductor thin film layer 135 and the planarized conductive layer 134. Further, the conductive Si substrate 132 may be a substrate such as a compound semiconductor substrate, a metal substrate, a conductive organic substrate, or conductive glass in addition to the Si substrate.

  As described above, according to the semiconductor composite device of the seventh embodiment, in addition to obtaining the same effects as those of the sixth embodiment described above, an electrode pad for external connection is provided to integrate the semiconductor integrated device in the device. Even when a circuit is not provided, it is possible to cope with it.

Embodiment 8 FIG.
20 is a plan view schematically showing a configuration of a main part of the semiconductor composite device 141 according to the eighth embodiment of the present invention. FIG. 21 is a cross section of the semiconductor composite device 141 shown in FIG. FIG. 24 is a fragmentary cross-sectional view schematically showing a surface of the semiconductor composite device 141 shown in FIG. 20 taken along the line DD. In FIG. 20, for the sake of simplicity, the interlayer insulating film 113 (FIG. 21) for preventing short-circuit between each wiring and between the wiring and the conductive layer is omitted.

  The semiconductor composite device 141 is mainly different from the semiconductor composite device 101 of the sixth embodiment shown in FIG. 13 described above in that an electrode pad 142 electrically connected to the conductive layer 114 through the conductive wiring layer 143 is provided. It is a point provided in a plurality of places. Accordingly, parts common to the semiconductor composite device 101 of the sixth embodiment described above are denoted by the same reference numerals in the semiconductor composite device 141, and the description thereof is omitted here, and different points are mainly described.

  The cross section (the surface cut along the DD line of the semiconductor composite device 141 shown in FIG. 20) at the portion where the upper structure 116c of the semiconductor composite device 141 is formed is as shown in FIG. The semiconductor multilayer device 101 has the same laminated structure as the cross section at the same position.

  On the other hand, the cross-sectional view of FIG. 21 is a cross-section (a section taken along the line CC of the semiconductor composite device 141 shown in FIG. 20) at a portion where the conductive wiring layer 143 of the semiconductor composite device 141 is formed. As shown in the figure, an electrode pad 142 is formed on the wiring region 112 on the side opposite to the side where the upper structure 116c is arranged in the width direction orthogonal to the longitudinal direction of the conductor composite device 141. . A conductive wiring layer 143 extending from the electrode pad 142 toward the side where the upper structure 116 c is arranged along the width direction of the semiconductor composite device 141 is formed. The leading end of the conductive wiring layer 143 is electrically connected to a wiring layer 144 (FIG. 21) extending from the conductive layer 114 formed under the semiconductor thin film layer 116. The conductive wiring layer 143 and the wiring layer 144 are formed of, for example, a metal layer.

  The conductive wiring layer 143 formed as described above is paired with the electrode pad 142, and a plurality of conductive wiring layers 143 are arranged in the longitudinal direction of the semiconductor composite device 141 at a predetermined interval as shown in FIG. Each of these electrode pads 142 is supplied with a predetermined potential, for example, a ground potential from the outside.

  In the semiconductor composite device 141 configured as described above, for example, the method of supplying current to the plurality of upper structures 116c in the semiconductor thin film layer 116 formed as the light emitting portion of the LED is the same as the method of the sixth embodiment described above. Therefore, the description here is omitted. In addition, a predetermined common potential, for example, a ground potential, is supplied to the conductive layer 114 from the outside through the electrode pads 142 and the conductive wiring layer 143 that are connected at a plurality of positions with a predetermined interval. For this reason, it is possible to suppress the occurrence of a potential difference distribution due to a voltage drop in the conductive layer 114 on the bonding surface of the semiconductor thin film layer 116.

  Next, a method for manufacturing the semiconductor composite device 141 configured as described above will be described. Note that the manufacturing method of the semiconductor thin film layer 116 can be equivalent to the method described in the sixth embodiment, and thus the description thereof is omitted here.

  The planarization conductive layer 115 is an organic conductive material layer formed by, for example, a coating method, a vapor deposition method, a printing method, or the like. The organic conductive material is formed of, for example, the material described in the description of the sixth embodiment. An organic material layer, particularly a polymer material layer, can be expected to have good surface flatness when formed.

  In another example of the planarized conductive layer, a transparent conductive material layer or a metal layer may be used. The transparent conductive material layer is a conductive metal oxide containing elements such as indium / tin oxide (ITO), zinc oxide (ZnO), or Cu, Sr, Bi, Ca, Y, Rb. May be. The metal layer is made of, for example, Ti, Ni, Cr, Ge. Note that the planarization conductive layer 115 is a material through which an electric current can flow, and it is desirable that the surface has sufficient planarity to form a semiconductor thin film when formed, but a chemical surface treatment ( For example, etching), mechanical surface treatment (for example, polishing), or mechanochemical surface treatment provides a flatness sufficient to apply a semiconductor thin film on the surface after forming a material layer constituting the planarization layer. May be.

  In the case where the planarization conductive layer 115 is made of zinc oxide (ZnO), the ZnO film can be formed by an ion plating method. The planarization conductive layer 115 can be a zinc oxide (ZnO) film that is a metal oxide, for example, as a transparent conductive film. In this case, the ZnO film can be formed by an ion plating method. When forming the ZnO film, it is desirable to form it at as low a temperature as possible, for example, at room temperature. By forming the film at room temperature, it is possible to remove the image of the conductive layer 114 and the element of the semiconductor element formation region 111 on the element. The ZnO film layer can be formed by a standard photolithography / etching process after forming the ZnO film. For example, buffered hydrofluoric acid can be used as the etching solution. As in the sixth embodiment, a ZnO film pattern can be formed by a lift-off method.

  A semiconductor thin film layer 116 separately formed is bonded onto the ZnO film, which is the planarization conductive layer 115, in the same manner as in Embodiment 6 described above, and then sintered at, for example, 500 ° C. or lower. More specifically, for example, sintering is performed for about 1 to 3 hours at a temperature of 100 to 400 ° C., and a necessary bonding strength and electrical contact are obtained between the semiconductor thin film layer 116 and the planarized conductive layer 115. obtain. Thereafter, the upper region 116b is separated by etching to form a plurality of upper structures 116c which are individual device regions. In the present embodiment, the upper structure 116c corresponds to the light emitting portion of the LED that is a semiconductor element as described above.

  In this embodiment, the example in which the upper structure 116c and the output pad 122 of the integrated circuit are connected by the individual electrode 117 is shown. However, when the semiconductor composite device 141 does not include the integrated circuit, the above-described embodiment is used. As shown in FIG. 7, a connection pad for connection to an external drive circuit may be provided, and the upper structure 116c and the connection pad may be connected.

Further, in the semiconductor composite device 141 of the eighth embodiment, another flattening layer 145 may be provided under the conductive layer 114 as shown in FIG. The other planarization layer 145 can be formed of an organic material such as polyimide, or a dielectric film such as an oxide such as Al ₂ O ₃ or SiO ₂ or a nitride such as Si _x N _y .

  Further, as shown in FIG. 23, the semiconductor composite device 141 of the eighth embodiment may be provided with a conductive layer 146 such as a metal thin film between the semiconductor thin film 116 and the planarized conductive layer 115 as a second modification. . Further, the planarized conductive layer 115 may be directly connected to the wiring 143 instead of the conductive layer 114.

  According to the semiconductor composite device of the eighth embodiment as described above, since the predetermined common potential, for example, the ground potential, can be supplied to the conductive layer 114 at a plurality of locations, the thickness of the planarized conductive layer 115 is reduced. In addition, even when the planarization conductive layer 115 has a relatively high sheet resistance, the occurrence of a potential difference distribution in the lower region 116a (common potential region) of the semiconductor thin film layer 116 can be suppressed. . For this reason, it is possible to obtain a good light emission operation with small variation in the amount of light in each light emitting unit.

  Further, in the case where the planarization conductive layer 115 is formed using a ZnO film, ZnO can be formed at room temperature, so that damage to the conductive layer 114 and the elements in the semiconductor element formation region 111 due to heating can be prevented.

Embodiment 9 FIG.
FIG. 25 is a plan view schematically showing a configuration of a main part of the semiconductor composite device 151 according to the ninth embodiment of the present invention. FIG. 26 is a cross section of the semiconductor composite device 151 shown in FIG. FIG. 27 is a principal part sectional view schematically showing a section of the semiconductor composite device 151 shown in FIG. 25 taken along the line FF.

  In FIG. 25, for the sake of simplicity, the interlayer insulating film 155 (FIG. 26) for preventing a short circuit between each wiring and between the wiring and the conductive layer is omitted, and a transparent conductive film layer 156, which will be described later, is described for the sake of explanation. Is shown in a state lacking a part. Further, in FIGS. 26 and 27, reference numerals 116, 116a, and 116b indicate the semiconductor thin film layer before the semiconductor elements 154 are separated and the lower and upper areas thereof, as will be described later.

  The semiconductor composite device 151 is mainly different from the semiconductor composite device 101 of the sixth embodiment shown in FIG. 13 in that not only the upper region 116b of the semiconductor thin film layer 116 but also the lower region 116a and the first planarization. Element isolation up to a conductive layer (in the sixth embodiment shown in FIG. 13 corresponds to the planarized conductive layer 115) 153 and an individual conductive layer (in the sixth embodiment shown in FIG. 13 corresponds to the conductive layer 114) 152. Along with this, the feeding path to each individual area is different. Accordingly, parts common to the semiconductor composite device 101 of the sixth embodiment described above are denoted by the same reference numerals in the semiconductor composite device 151, description thereof will be omitted, and different points will be described mainly.

  The cross-sectional view of FIG. 26 shows a cross section (a plane cut along the line EE of the semiconductor composite device 151 shown in FIG. 25) at a portion where the individual semiconductor region 159 of the semiconductor composite device 151 is formed. As shown in the figure, the individual semiconductor region 159 has the individual conductive layer 152 of the metal layer formed above the wiring region 112 as the lowest layer, and the first planarized conductive film layer 153 is formed thereon, A semiconductor element 154 is formed thereon.

  The individual conductive layer 152 has a connection convex portion that is electrically connected to the output pad 157 formed in the circuit wiring region 112 a in order to drive the semiconductor element 154 in the individual semiconductor region 159. The first planarizing conductive layer 153 is an organic conductive material layer formed by, for example, a coating method, a vapor deposition method, a printing method, or the like. The organic conductive material is formed of, for example, the material described in the description of the sixth embodiment. An organic material layer, particularly a polymer material layer, can be expected to have good surface flatness when formed.

  In another example of the planarization conductive layer 153, a transparent conductive material layer or a metal layer may be used. The transparent conductive material layer is, for example, a conductive metal containing elements such as indium tin oxide (ITO), zinc oxide (ZnO), or Cu, Sr, Bi, Ca, Y, Rb, etc. It may be an oxide. The metal layer is formed of, for example, Ti, Ni, Cr, Ge, Pd. Note that the planarization conductive layer 153 is a material through which a current can flow, and it is desirable that the surface of the planarization conductive layer 153 has sufficient planarity to attach a semiconductor thin film when formed, but a chemical surface treatment ( For example, etching), mechanical surface treatment (for example, polishing), or mechanochemical surface treatment provides a flatness sufficient to apply a semiconductor thin film on the surface after forming a material layer constituting the planarization layer. May be.

  The semiconductor element 154 is formed by separating the lower region 116a and the upper region 116b of the semiconductor thin film layer 116 into a plurality of lower structures 154a and upper structures 154b by etching away. The semiconductor element 54 in the present embodiment is constituted by a pair of lower structure 154a and upper structure 154b which are separated from each other as described above. In the present embodiment, it is assumed that the semiconductor element 154 is configured as an LED, for example.

  As shown in FIG. 25, a plurality of individual semiconductor regions 159 configured as described above are formed at predetermined intervals along the longitudinal direction of the semiconductor composite device 151, and together with other regions except for predetermined portions described later. Covered with an interlayer insulating film 155 (FIG. 27). In FIG. 25, for the sake of simplicity, an interlayer insulating film 155 (FIG. 27) for preventing a short circuit between each wiring and between the wiring and the conductive layer is omitted, but only through holes 155a and 155b described later are provided. Shown with dotted lines.

  As shown in FIGS. 26 and 27, a through hole 155a is formed in a portion of the interlayer insulating film 155 corresponding to the contact region on the semiconductor element 154 in each individual semiconductor region 159. As shown in FIG. 25, in the circuit wiring region 112a, a reference potential of the driving integrated circuit formed in this region, for example, a common potential pad 158 for ground potential, corresponds to the vicinity of each individual semiconductor region 159. Are arranged. The interlayer insulating film 155 also has a through hole 155 b in a predetermined region on each common potential pad 158.

  On the interlayer insulating film 155, a transparent conductive film layer 156 made of, for example, a film of indium tin oxide (ITO), zinc oxide (ZnO) or the like is formed. As shown in FIG. 25, the transparent conductive film layer 156 is formed so as to cover all the individual semiconductor regions 159 and the common potential pad 158, and further to the contact region of each individual semiconductor region 159 through the through hole 155a. Each of the common potential pads 158 is electrically connected to a predetermined region via a through hole 155b.

  By being configured as described above, the transparent conductive film layer 156 corresponds to a common electrode of the semiconductor element 154 (LED here) formed in each individual semiconductor region 159, and the individual conductive layer 152 described above includes This corresponds to an individual electrode for individually driving the LEDs. Further, the transparent conductive film layer 156 is connected to the common potential pad 158 of the driving integrated circuit at a plurality of positions so that the potential of the common electrode does not fluctuate due to a voltage drop in the transparent conductive film layer 156 during the operation of each LED. doing.

  In the semiconductor composite device 151 of the present embodiment described above, the transparent conductive film layer 156 is a continuous thin film, but can be appropriately divided. In this case, the transparent conductive film layer 156 is connected to the output pad 157 of the integrated circuit as an individual electrode by dividing each region into the region including the individual semiconductor region 159, and the individual conductive layer 152 of each individual region is integrated as a common electrode. It can also be configured to be connected to the common potential pad 158 of the circuit.

  Further, in the present embodiment, an example in which the individual conductive layer 152 and the output pad 157 of the integrated circuit are connected is shown. However, when the semiconductor composite device 151 does not include an integrated circuit, as in the seventh embodiment described above. In addition, a connection pad for connection to an external drive circuit may be provided, and the connection pad and the individual conductive layer 152 may be connected.

  According to the semiconductor composite device 151 of the ninth embodiment configured as described above, the semiconductor element 154 formed in each individual semiconductor region 159, for example, covers part or all of the LED provided on the light extraction surface of the LED. Since the electrode is a transparent electrode (transparent conductive film layer 156), light extraction efficiency is improved. Further, by setting the individual electrode to the individual conductive layer 152 side which is a metal layer, the current spreads more efficiently over the entire surface of the LED, and the light emission efficiency can be improved.

  In addition, since the individual conductive layer 152 (metal layer), which is a wiring layer for individual electrodes, is disposed below the semiconductor thin film layer 116, the lower layer of the individual conductive layer 152 has a configuration with few steps. Therefore, even if the width of the individual conductive layer 152 is narrowed, it is difficult for the wiring to be cut off, and the yield as an integrated circuit is improved.

Embodiment 10 FIG.
FIG. 28 is a cross sectional view schematically showing a main configuration of a semiconductor composite device 161 according to the tenth embodiment of the present invention.

  This semiconductor composite device 161 is mainly different from the semiconductor composite device 151 of the ninth embodiment shown in FIG. 26 in that the configuration of the metal layer that connects the first planarizing conductive film layer 153 and the output pad 157 is different. It is a different point. Accordingly, parts common to the semiconductor composite device 151 of the ninth embodiment described above are denoted by the same reference numerals or the drawings are omitted and the description thereof is omitted here, and different points are emphasized. Explained. The cross section shown in FIG. 28 is a cross section taken along line EE shown in the plan view of FIG. 25 in the semiconductor composite device 151 of the ninth embodiment, that is, the individual semiconductor region 159 of the semiconductor composite device 161 is formed. This corresponds to the cross section at the portion where the current is applied.

  As shown in FIG. 28, the individual conductive layer 162 in the semiconductor composite device 161 covers and is electrically connected to the upper surface end portion of the first planarized conductive film layer 153, and from the side portion of the integrated circuit. The metal layer extends toward the output pad 157 and is configured to be electrically connected to the output pad 157.

  According to the semiconductor composite device 161 of the tenth embodiment configured as described above, an upper surface of the first planarizing conductive film layer 153 is provided without providing a metal layer immediately below the first planarizing conductive film layer 153. Since the metal layer extending from the end portion to another region is provided, even if the sintering temperature of the first planarizing conductive film layer 153 is increased, the metal layer is not damaged, and the resistance is lower. A transparent conductive film layer with better quality can be prepared.

Embodiment 11 FIG.
FIG. 29 is a cross sectional view schematically showing a main configuration of a semiconductor composite device 171 according to the eleventh embodiment of the present invention.

  This semiconductor composite device 171 is mainly different from the semiconductor composite device 161 of the tenth embodiment shown in FIG. 28 described above in that a dielectric film is multiplexed between the first planarizing conductive film layer 153 and the wiring region 112. This is the point that a laminated reflective film layer 172 is provided. Accordingly, parts common to the semiconductor composite device 161 of the tenth embodiment described above are denoted by the same reference numerals, or the drawings are omitted and the description thereof is omitted here, and different points are emphasized. Explained. The cross section shown in FIG. 28 is a cross section taken along line EE shown in the plan view of FIG. 25 in the semiconductor composite device 151 of the ninth embodiment, that is, the individual semiconductor region 159 of the semiconductor composite device 171 is formed. This corresponds to the cross section at the portion where the current is applied.

The multi-layered reflective film layer 172 shown in FIG. 29 is a multi-layered reflective film of a dielectric film in which a reflective layer is formed by laminating materials having different refractive indexes, for example. This multiple laminated reflective film can be, for example, a Si / SiO ₂ laminated film or a SiO ₂ / TiO ₂ laminated film. In addition, a laminated film of a low refractive index material / a high refractive index material may be used. The low refractive index material can be a material such as SiO ₂ , CaF ₂ , LiF, or MgF _2, and the high refractive material can be TiO ₂ , CeO ₂ , CdS, ZnS, or the like. In addition, it may be a metal / semiconductor laminated film. The multi-layered reflective film layer 172 can be formed, for example, by sputtering. A first planarized conductive film layer 153 is formed thereon, and a semiconductor thin film 116 is bonded thereon. .

  In place of the multi-layered reflective film layer 172 made of only a dielectric, a multi-layered reflective film layer of a dielectric film and a metal thin film may be provided. Also in the semiconductor composite device 101 of the sixth embodiment, the conductive layer 114 is formed of a transparent conductive film layer by forming the conductive layer 114 so as to extend from the upper end portion of the planarization conductive layer 115 to another region. A multi-layered reflective film layer 172 can be provided immediately below the planarized conductive layer 115.

  According to the semiconductor composite device 171 of the eleventh embodiment configured as described above, since the dielectric multi-layered reflective film layer 172 is provided below the first planarized conductive film layer 153, the multi-layered reflective film The reflected light of the LED reflected by the layer 172 is also obtained from the light emitting surface, and a conductive contact is obtained on the back surface of the semiconductor thin film.

  Further, since the dielectric multilayer laminated film is provided without providing the metal layer immediately below the first planarizing conductive film layer 153, the first planarizing conductive film is provided as in the ninth embodiment (see FIG. 26). Compared with the case where a metal layer is provided immediately below the film layer 153, there is no possibility of a change in reflectance due to heat treatment such as sintering, and a favorable reflectance can be obtained.

Embodiment 12 FIG.
FIG. 30 is a diagram showing an LED print head 200 according to a twelfth embodiment based on the LED head of the present invention.

  As shown in the figure, an LED unit 202 is mounted on the base member 201. This LED unit 202 is obtained by mounting the semiconductor composite device according to any one of Embodiments 1 to 11 on a mounting substrate. FIG. 31 is a plan layout view showing an example of the configuration of the LED unit 202. On the mounting board 202e, the semiconductor composite device that combines the light emitting unit and the driving unit described in the above embodiments emits light. A plurality of unit units 202a are arranged along the longitudinal direction. On the mounting substrate 202e, electronic component mounting areas 202b and 202c in which electronic components are arranged and wirings are formed, and a connector 202d for supplying control signals and power from the outside are provided. Yes.

  Above the light emitting part of the light emitting part unit 202a, a rod lens array 203 is disposed as an optical element for condensing the light emitted from the light emitting part. The rod lens array 203 includes a large number of columnar optical lenses arranged along a linear arrangement of light emitting unit units 202a (for example, an array of individual element regions 116c in FIG. 13). Is held at a predetermined position by a lens holder 204 corresponding to.

  The lens holder 204 is formed so as to cover the base member 201 and the LED unit 202 as shown in FIG. The base member 201, the LED unit 202, and the lens holder 204 are sandwiched integrally by a clamper 205 disposed through openings 201 a and 204 a formed in the base member 201 and the lens holder 204. Therefore, the light generated by the LED unit 202 is irradiated to a predetermined external member through the rod lens array 203. The LED print head 200 is used as an exposure device such as an electrophotographic printer or an electrophotographic copier.

  As described above, according to the LED head of the present embodiment, any one of the semiconductor composite devices described in the first to eleventh embodiments is used as the LED unit 202. Thus, a highly reliable LED head can be provided.

Embodiment 13 FIG.
FIG. 32 is a main part configuration diagram schematically showing a main part configuration of an image forming apparatus 300 according to Embodiment 13 based on the image forming apparatus of the present invention.

  As shown in the figure, in the image forming apparatus 300, four process units 301 to 304 that respectively form yellow, magenta, cyan, and black images are provided along the conveyance path 320 of the recording medium 305. They are arranged in order from the upstream side. Since the internal configurations of these process units 301 to 304 are common, the internal configuration will be described by taking, for example, a cyan process unit 303 as an example.

  In the process unit 303, a photosensitive drum 303a as an image carrier is rotatably arranged in the direction of the arrow. Electricity is supplied to the surface of the photosensitive drum 303a around the photosensitive drum 303a sequentially from the upstream side in the rotation direction. A charging device 303b for charging and an exposure device 303c for forming an electrostatic latent image by selectively irradiating light onto the surface of the charged photosensitive drum 303a are provided. Further, a developing device 303d that generates a visible image by attaching toner of a predetermined color (cyan) to the surface of the photosensitive drum 303a on which the electrostatic latent image is formed, and toner remaining on the surface of the photosensitive drum 303a. A cleaning device 303e to be removed is provided. The drums or rollers used in these devices are rotated by a drive source and gears (not shown).

  In addition, the image forming apparatus 300 has a paper cassette 306 for storing a recording medium 305 such as paper stacked in a lower portion of the image forming apparatus 300, and the recording medium 305 is separated and conveyed one by one above the paper cassette 306. A hopping roller 307 is provided. Further, the recording medium 305 is sandwiched together with the pinch rollers 308 and 309 on the downstream side of the hopping roller 307 in the conveyance direction of the recording medium 305, thereby correcting the skew of the recording medium 305, and the process units 301 to 304. Registration rollers 310 and 311 are disposed. These hopping roller 307 and registration rollers 310 and 311 rotate in conjunction with a driving source and gears (not shown).

  Transfer rollers 312 made of semiconductive rubber or the like are disposed at positions facing the respective photosensitive drums of the process units 301 to 304. In order to adhere the toner on the photosensitive drums 301a to 304a to the recording medium 305, a predetermined potential difference is generated between the surfaces of the photosensitive drums 301a to 304a and the surfaces of the transfer rollers 312. Has been.

  The fixing device 313 includes a heating roller and a backup roller, and fixes the toner transferred onto the recording medium 305 by pressurizing and heating. The discharge rollers 314 and 315 sandwich the recording medium 305 discharged from the fixing device 313 together with the pinch rollers 316 and 317 of the discharge unit, and convey the recording medium 305 to the recording medium stacker unit 318. The discharge rollers 314 and 315 rotate in conjunction with a drive source and a gear (not shown). As the exposure apparatus 303c used here, the LED print head 200 described in the twelfth embodiment is used.

Next, the operation of the image forming apparatus having the above configuration will be described.
First, the recording medium 305 stored in a stacked state in the paper cassette 306 is separated and transported one by one from the top by the hopping roller 307. Subsequently, the recording medium 305 is sandwiched between the registration rollers 310 and 311 and the pinch rollers 308 and 309 and conveyed to the photosensitive drum 301 a and the transfer roller 312 of the process unit 301. Thereafter, the recording medium 305 is sandwiched between the photosensitive drum 301a and the transfer roller 212, and the toner image is transferred to the recording screen and simultaneously conveyed by the rotation of the photosensitive drum 301a.

  Similarly, the recording medium 305 sequentially passes through the process units 302 to 304, and the electrostatic latent images formed by the exposure devices 301c to 304c are developed by the developing devices 301d to 304d in the passing process. The toner images are sequentially transferred and superimposed on the recording screen. Then, after the toner images of the respective colors are superimposed on the recording surface, the recording medium 305 on which the toner image is fixed by the fixing device 313 is sandwiched between the discharge rollers 314 and 315 and the pinch rollers 316 and 317 so that the image The recording medium stacker 318 outside the forming apparatus 300 is discharged. A color image is formed on the recording medium 305 through the above process.

  As described above, according to the image forming apparatus of the present embodiment, since the LED print head described in the above-described Embodiment 12 is employed, it is possible to provide a high-quality and highly reliable image forming apparatus. it can.

  In the above sixth to eleventh embodiments, examples in which a light emitting element (LED) is formed as a semiconductor element formed in a semiconductor thin film layer of a semiconductor composite device have been described. However, the present invention is not limited to this. Instead of this light emitting element, a light receiving element may be formed, or other semiconductor elements may be formed in addition to these optical elements.

  In the claims and the description of the embodiments, the words “upper” and “lower” are used for the sake of convenience, and the absolute positional relationship in the state in which each device is arranged. It is not intended to limit.

  DESCRIPTION OF SYMBOLS 1 Semiconductor composite device, 2 Si substrate, 3 Planarization layer, 4 Semiconductor thin film layer, 5, 6 Connection wiring, 7 Interlayer insulation film, 11 Semiconductor composite device, 12 Si substrate, 13a, 13b, 13c Planarization layer, 14a, 14b, 14c Semiconductor thin film layer, 15 integrated circuit, 16 pad, 17 wiring, 21 semiconductor composite device, 22 Si substrate, 23 multilayer insulating film region, 24 driving integrated circuit region, 25 planarization layer, 26 lower region, 27 upper structure 27a First conductivity type cladding layer, 27b First conductivity type active layer, 27c Second conductivity type cladding layer, 27d Second conductivity type contact layer, 28 Semiconductor thin film layer, 30 Individual electrode contact, 31 Metal wiring 32 output terminals, 33 common electrode contacts, 34 connection pads, 35 layers Edge film, 36 connection pad, 41 semiconductor composite device, 42 flat lower layer, 43 reflective layer, 45 semiconductor composite device, 46 reflective layer, 48 dielectric film, 51 semiconductor composite device, 52 reflective layer, 55 semiconductor composite device, 56 Inorganic material layer, 101 semiconductor composite device, 110 Si substrate, 111 semiconductor element formation region, 112 wiring region, 112a circuit wiring region, 112b second wiring region, 113 interlayer insulating film, 114 conductive layer, 115 planarizing conductive layer, 116 Semiconductor thin film layer, 116a lower region, 116b upper region, 116c (upper structure) individual element region, 117 individual electrode, 118 planarization layer, 118a connection opening, 119 metal layer, 121 input pad, 122 output pad, 131 semiconductor Compound equipment, 13 2 Si substrate, 133 conductive layer, 134 planarization conductive layer, 135 semiconductor thin film layer, 135a lower region, 135b upper region, 135c upper structure, 136 electrode contact, 138 interlayer insulating film, 138a opening, 139 electrode pad, 141 semiconductor Composite device, 142 electrode pad, 143 conductive wiring layer, 144 wiring layer, 145 planarization layer, 151 semiconductor composite device, 152 individual conductive layer, 153 first planarization conductive film layer, 154 semiconductor element, 154a lower individual region, 154b Upper individual region, 155 interlayer insulating film, 155a, 155b through-hole, 156 transparent conductive film layer, 157 output pad, 158 common potential pad, 159 individual semiconductor region, 161 semiconductor composite device, 162 individual conductive layer, 171 Conductor composite device, 172 multi-layer reflection film layer, 200 LED print head, 201 base member, 202 LED unit, 202a light emitting unit, 203 rod lens array, 204 lens holder, 205 clamper, 300 image forming device, 301, 302, 303,304 Process unit, 301a to 304a Photosensitive drum, 303b Charging device, 303c Exposure device, 303d Developing device, 303e Cleaning device, 305 Recording medium, 306 Paper cassette, 307 Hopping roller, 308,309 Pinch roller, 310,311 Registration roller, 312 transfer roller, 313 fixing device, 314, 315 discharge roller, 316, 317 pinch roller, 318 recording medium stack Part.

Claims (9)

A substrate,
A multi-layered reflection film provided on the substrate and laminated with dielectric films having different refractive indexes;
Said provided multiple layered reflective film made of an organic conductive material, the planarizing layer facing surface opposite to the surface of the substrate is planarized,
A semiconductor thin film including a light emitting element and attached on the planarization layer,
Of the planarization layer, the flatness of the surface of the opposite surface of the substrate Ru Der below 5nm
Semiconductor device comprising a call. _2. The semiconductor device according to claim 1, wherein the multi-layered reflective film is a Si / SiO2 laminated film. The semiconductor device according to claim 1, wherein the multi-layered reflective film is a SiO ₂ / TiO ₂ laminated film.   2. The semiconductor device according to claim 1, wherein the multiple laminated reflective film is a laminated film of a low refractive index material / a high refractive index material. The semiconductor device according to claim 4, wherein the low refractive index material is any one of SiO ₂ , CaF ₂ , LiF, and MgF ₂ . 5. The semiconductor device according to claim 4, wherein the high refractive index material is any one of TiO ₂ , CeO ₂ , CdS, and ZnS. A substrate,
A multi-layered reflection film provided on the substrate and laminated with dielectric films having different refractive indexes;
Said provided multiple layered reflective film made of an organic conductive material, the planarizing layer facing surface opposite to the surface of the substrate is planarized,
An LED thin film including a light emitting element, and affixed on the planarization layer,
Of the planarization layer, the flatness of the surface of the opposite surface of the substrate Ru Der below 5nm
LED device comprising a call. LED device according to claim 7 ,
An LED head comprising: an optical system that guides light emitted from the LED thin film. In an image forming apparatus having an image forming unit for forming an image of a recording material on a recording medium conveyed by a conveying unit,
The image forming unit includes: an image carrier; a charging unit that charges the surface of the image carrier; an exposure unit that selectively irradiates light to the charged surface to form an electrostatic latent image; Developing means for developing the electrostatic latent image,
An image forming apparatus using the LED head according to claim 8 as the exposure means.

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