JP4663357B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as an LED device, a semiconductor unit using the semiconductor device, an LED head, and an image forming apparatus.

  Conventionally, for example, as disclosed in Patent Document 1, the electrode pad surface of a semiconductor element formed on a Si substrate is easily oxidized, and when probing is performed, the oxide film is broken to have a low contact resistance. It was necessary to increase the needle pressure of the probe needle.

Japanese Patent Laying-Open No. 2004-179641 (pages 19-20, FIG. 39)

  Therefore, even if the electrode pad is provided on the semiconductor element formation region, there is a risk of damaging the semiconductor element formation region below the electrode pad region during probing, and the electrode pad can be provided on the semiconductor element formation region. There wasn't. Further, when the probe pressure of the probing needle is increased, the amount of movement on the pad at the tip of the needle increases accordingly, and it is necessary to increase the pad area accordingly. For this reason, it is necessary to provide an electrode pad having a large area outside the semiconductor element formation region, and the chip width of the semiconductor element chip is increased accordingly, and there is a problem that it is difficult to reduce the chip width (chip shrink).

  An object of the present invention is to solve the above problems and provide a semiconductor device capable of reducing the chip width (chip shrink) of a semiconductor device including, for example, a semiconductor element formed on a Si substrate.

The semiconductor device of the present invention is
A semiconductor substrate in which an element region constituting a driving integrated circuit is formed on a surface layer, a multilayer wiring layer formed on a surface of the semiconductor substrate, and a planarizing layer having an insulating property formed on the surface of the multilayer wiring layer And a semiconductor thin film on which a light emitting element that is directly or indirectly bonded to the planarizing layer and driven by the driving integrated circuit is formed, and an output pad portion extending on the surface of the planarizing layer. All of the semiconductor thin film except for an output electrode pad electrically connected to a predetermined portion of the element region via a wiring member formed in the multilayer wiring layer and a contact layer provided on the semiconductor thin film Alternatively, the insulating layer covering a part, the covering portion covering at least the output pad portion extending on the surface of the planarizing layer, and the insulating portion from the covering portion to the contact layer provided on the semiconductor thin film And a separate wiring portion extending above and having a thin film wiring and electrically connecting the contact layer and the output electrode pad.

  According to the semiconductor device of the present invention, it is possible to form the electrode pad surface with a coating layer that is difficult to be oxidized, so that the needle pressure can be reduced during probing. For this reason, since the deviation | shift amount of a needle | hook becomes small, the area of an electrode pad can be made small.

Embodiment 1 FIG.
FIG. 1 is a plan view schematically showing a main configuration of a semiconductor device 10 according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device 10 shown in FIG. It is principal part sectional drawing shown roughly. For the sake of explanation, FIG. 1 shows a state in which a coating layer 17 described later is partially omitted.

  As shown in FIG. 1, the semiconductor device 10 includes a Si substrate 11, multilayer wiring layers 12 and 13, input electrode pads 14 and 15, an output electrode pad 16, and a covering layer 17.

  The semiconductor device 10 is a driving integrated circuit chip that drives and controls an optical element or an optical element array such as a light emitting diode or a light receiving sensor. The multilayer wiring layer 12 and the multilayer wiring layer 13 are formed in different regions, that is, the multilayer wiring layer 12 is formed in the semiconductor element forming region 21 and the multilayer wiring layer 13 is formed in the output pad forming region 22, respectively. As will be described later, the input electrode pads 14 and 15 formed in the multilayer wiring layer 12 and the output electrode pad 16 formed in the multilayer wiring layer 13 are, for example, electrode pads containing Al. The coating layer 17 is a coating layer that is difficult to oxidize such as a noble metal that covers the output electrode pad 16 and the input electrode pads 14 and 15, and is different from the electrode pad, for example, Ti, Pt, Au, Ge, Ni, Cr, W It is constituted by a single layer or a laminated metal film containing one or a plurality of elements. Further, a composite layer such as Ti—Pt—Au may be used. Further, the coating layer 17 is formed with a layer thickness of, for example, about 0.1 μm to 1 μm.

  As shown in the sectional view of FIG. 2, in the semiconductor device 10, the multilayer wiring layer 12 is formed in the semiconductor element forming region 21 and the multilayer wiring layer 13 is formed in the output pad forming region 22 on the Si substrate 11. . In the Si substrate 11, an element region 25 including a semiconductor element such as an optical element such as a light emitting diode or a light receiving sensor or a driving integrated circuit for driving and controlling the optical element array is formed in a predetermined region including the upper side surface thereof. ing. The semiconductor element formation region 21 shown in FIG. 1 corresponds to the region seen in the plan view of the element region 25.

  A wiring member 23 is formed on the multilayer wiring layers 12 and 13. The wiring member 23 is connected to a predetermined terminal (not shown) connected to a semiconductor element (not shown) formed in the element region 25 and is connected to a vertical wiring portion 23a that is planted substantially vertically on the upper surface of the element region 25; An output electrode pad extending from the upper end portion of the vertical wiring portion 23 a and formed substantially parallel to the upper surface of the element region 25 from the semiconductor element formation region 21 to the output pad formation region 22 and disposed in the output pad formation region 22 16 and a horizontal wiring portion 23 b connected to 16. Moreover, the wiring member 23 is comprised from the material equivalent to a multilayer wiring material, for example, for example, is a metal material containing Al.

  The output electrode pad 16 is formed in the multilayer wiring layer 13, and an opening 13 a is formed in the multilayer wiring layer 13 at a position facing the output electrode pad 16. On the output electrode pad 16, a covering layer 17 that covers the output electrode pad 16 is formed over a predetermined region including the opening 13a. On the other hand, the input electrode pads 14 and 15 are formed in the multilayer wiring layer 12. Similarly, an opening 12 a (see FIG. 5) is formed at a position of the multilayer wiring layer 12 facing the input electrode pads 14 and 15. 1) is formed, and a covering layer 17 covering each input electrode pad is formed over a predetermined region including the opening 12a.

  In the case of including the input electrode forming portion 26 having the input electrode pads 14 and 15 and the covering layer 17 and the output electrode forming portion 27 having the output electrode pad 16 and the covering layer 17 configured as described above, for example, FIG. As shown, the output electrode forming portions 27 are preferably arranged in a line along the longitudinal direction of the semiconductor device 10 so that the chip width of the semiconductor 10 is not increased as much as possible. At this time, the output electrode forming portions 27 are arranged with an arrangement pitch of, for example, 50 μm or less.

  Next, a method for manufacturing the semiconductor device 10 configured as described above will be described.

  First, processes such as thermal oxide film formation, impurity implantation and impurity activation, interlayer insulating film formation and etching, wiring formation and etching, etc. on the element region 25 and the multilayer wiring layers 12 and 13 of the Si substrate 11 shown in FIG. Then, the driving integrated circuit and the input / output electrode pads 14, 15 and 16 are formed. Next, a lift-off resist pattern is formed so as to expose the input electrode pads 14 and 15 and the output electrode pad 16 of the driving integrated circuit. Next, the surface of each electrode pad is cleaned with oxygen plasma or the like, and then the oxide film on the pad surface with, for example, buffered hydrofluoric acid is removed. In removing the oxide film on the pad surface with buffered hydrofluoric acid, for example, it is immersed in buffered hydrofluoric acid for several seconds to 10 seconds.

  Next, a layered film made of Ti / Pt / Au or the like that is hardly oxidized such as a noble metal is formed by, for example, electron beam evaporation. Here, the outermost surface of the coating layer is an Au layer that is not easily oxidized. Next, a lift-off resist stripping process and a cleaning process are performed. Finally, a sinter in the range of 200 ° C. to 400 ° C., for example, to reduce the contact resistance between the electrode pads 14, 15, 16 and the coating layer 17 as much as possible. Process.

  As described above, according to the semiconductor device 10 of the present embodiment, since the pad surface of the semiconductor integrated circuit chip is covered with the coating layer 17 that is not easily oxidized, the needle pressure can be reduced during probing. For this reason, the deviation | shift amount of a needle | hook can also be made small and the area of the pitch pad arranged by the predetermined pattern can be reduced. For example, the electrode pads can be arranged in a line such that the arrangement pitch of the electrode pads is 50 μm or less.

  FIG. 3 is a diagram illustrating a modification of the first embodiment. In the semiconductor device 10 (FIG. 1) of the first embodiment described above, the electrode pads 14, 15, and 16 are covered with a metal layer that is difficult to oxidize, and the output electrode pads 16 are arranged in a row at a narrow pitch (for example, 50 μm or less). However, as shown in FIG. 3, a staggered arrangement in which the adjacent electrodes of the plurality of output electrode pads 16 are alternately displaced may be employed. In the case where the number of output electrode pads is small and it is not necessary to arrange them at a high density, the output electrode pads 16 need not be made narrow (for example, 50 μm or less).

  FIG. 4 is a diagram showing still another modification of the first embodiment. In the semiconductor device 10 (FIG. 1) of the first embodiment described above, an example in which the area of the input electrode pads 14 and 15 as well as the output electrode pad 16 is reduced is shown. If there is a margin, only the area of the input electrode pads 14 and 15 may be increased (FIG. 3).

Although not shown, for example, when the pad on the input side is connected to an external circuit with a wire, even if the surface area of the wire bond is somewhat oxidized, it is possible to select conditions that can break through the oxide layer. In some cases, only the output-side pad may be covered with a metal layer that is difficult to oxidize. Here, the metal that is difficult to oxidize means the following. That is,
[Metal] + [Oxygen] ← → [Oxygen metal]
In the phase diagram of the reaction, from room temperature to the maximum processing temperature in a semiconductor process such as a thin film formation process, a photolithography / etching process and an electrode sintering process, for example, in a temperature region of 450 ° C. or lower and an oxygen partial pressure region of atmospheric pressure, [Metal] It means the metal in the phase. Alternatively, it means a metal in which a metal oxide layer covering a surface of 3 nm or more is not formed on the metal surface when exposed to air at atmospheric pressure at room temperature.

Embodiment 2. FIG.
FIG. 5 is a plan view schematically showing a main configuration of the semiconductor device 30 according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view of the semiconductor device 30 shown in FIG. It is principal part sectional drawing shown roughly. For the sake of explanation, the coating layer 37 described later is partially omitted.

  The main difference between the semiconductor device 30 and the semiconductor device 10 of the first embodiment shown in FIG. 1 is that the output electrode pad 36 is formed in the semiconductor formation region 41, and for this reason, The planarizing layer 38 is newly provided in the output pad forming region 42 where the output electrode pad 36 is formed. Therefore, in this semiconductor device 30, the same reference numerals are given to the parts common to the semiconductor device 10 (FIG. 1) of the first embodiment described above, and the description here is omitted, and different points will be described mainly. .

  As shown in the cross-sectional view of FIG. 6, in the Si substrate 31 of the semiconductor device 30, for example, a drive for driving and controlling an optical element or an optical element array such as a light emitting diode or a light receiving sensor over substantially the entire region including the upper side surface. An element region 45 including a semiconductor element such as an integrated circuit is formed. The semiconductor element formation region 41 shown in FIG. 5 corresponds to the region seen in the plan view of the element region 45. A multilayer wiring layer 32 is formed on the element region 45, and a planarization layer 38 is formed on the multilayer wiring layer 32 in the output pad formation region 42 where the output electrode pad 36 is formed. Here, the planarization layer means that when the layer B in the region R is formed on the surface A having certain unevenness or roughness, the unevenness or roughness on the surface of the layer B formed in the region R is the surface of the region R. It means a layer B that is at least smaller than the unevenness or roughness of A.

  As shown in FIG. 5, the planarization layer 38 is formed so as to extend along the longitudinal direction of the semiconductor device 30. As the planarizing layer 38, for example, a coating film such as an SOG film (spin-on-glass film), a polyimide film, or an organic insulating film can be used. Further, the planarization layer 38 may be provided only in the vicinity of the output pad formation region 42 as shown in FIG.

  A wiring member 43 is formed on the multilayer wiring layer 32. The wiring member 43 is connected to a predetermined terminal (not shown) connected to a semiconductor element (not shown) formed in the element region 45 and is connected to a vertical wiring portion 43a which is planted substantially vertically on the upper surface of the element region 45; A horizontal pad portion 43b is formed extending from the upper end portion of the vertical wiring portion 43b and connected to an output electrode pad 36, which will be described later, disposed in the output pad forming region 42. Moreover, the wiring member 43 is comprised from the material equivalent to a multilayer wiring material, for example, for example, is a metal material containing Al.

  The output electrode pad 36 is formed on the planarizing layer 38 with an electrode pad containing Al, for example, and extends from the output pad portion 36a on the planarizing layer 38 and formed in a square shape. The wiring member 43 includes a terminal portion 36b connected to the horizontal pad portion 43b through an opening 38a (FIG. 6) formed in the multilayer wiring layer 32 and the planarizing layer 38 corresponding to the horizontal pad portion 43b. . A coating layer 37 is formed on the output electrode pad 36 so as to cover the output pad portion 36a. The coating layer 37 is composed of a single layer or a laminated metal film containing one or a plurality of elements among, for example, Ti, Pt, Au, Ge, Ni, Cr, and W.

  The output electrode forming portions 47 configured as described above are desirably arranged in a line along the longitudinal direction of the semiconductor device 30 as shown in FIG. 5, for example, so that the chip width of the semiconductor 40 is not increased as much as possible. At this time, the output electrode forming portions 27 are arranged with an arrangement pitch of, for example, 50 μm or less.

  In the above configuration, the surface of the multilayer wiring layer 32 in the semiconductor element formation region 41 does not always have a wide flat area due to the multilayer wiring structure of the multilayer wiring layer 32, for example, unevenness of about 1 μm to several μm, for example. Exists. The flattening layer 38 is formed in the output pad forming region 42 where the output electrode pad 36 is formed, thereby flattening such an uneven surface as much as possible. For example, when the output electrode pad 36 is provided on a layer having a large unevenness on the surface, the contact state varies due to the unevenness of the surface that the probe needle contacts when probing, and a good contact can always be obtained. Not exclusively. However, such a problem can be solved by providing the output electrode pad 36 on the planarized flattening layer 38.

  Next, a method for manufacturing the semiconductor device 30 configured as described above will be described.

  After the driving integrated circuit and the input / output electrode pads 14, 15, 16 are formed in the element region 45 and the multilayer wiring layer 32 by the same method as described in the first embodiment, the planarizing film 38, for example, A photosensitive polyimide film is applied to the entire region on the multilayer wiring layer 32 by, for example, spin coating. Thereafter, exposure and development are performed so that the polyimide layer remains on the predetermined region, for example, the output pad formation region 42, and then curing is performed at 400 ° C., for example.

  Next, the output electrode pad 36 including the terminal portion 36b and the output pad portion 36a connected to the horizontal pad portion 43b of the wiring portion member 43 is formed. In this step, for example, an AlSiCu layer is formed by sputtering, and a pattern is formed by photolithography / etching. Next, the pattern of the coating layer 37 is formed by the same processing steps as described in the first embodiment, for example, the lift-off step. Here, for example, a Ti / Pt / Au laminated film is formed as the coating layer material.

  As described above, according to the semiconductor device 30 of the present embodiment, the input / output pad surface is covered with the metal layer that is difficult to oxidize, and the planarization layer 38 is provided in the semiconductor element formation region 41 to form the output pad. Since the region 42 is arranged, in addition to the effects obtained in the first embodiment, the chip width of the semiconductor device 30 can be further reduced.

Embodiment 3 FIG.
FIG. 7 is a plan view schematically showing a main configuration of the semiconductor device 50 according to the third embodiment of the present invention. FIG. 8 is a cross-sectional view of the semiconductor device 50 shown in FIG. FIG. 9 is a schematic cross-sectional view of a relevant part, and FIG. 9 is a schematic cross-sectional view of the relevant part of the semiconductor device 50 shown in FIG. 7 taken along the line DD. In FIG. 7, for the sake of explanation, the coating layers 17 and 57, which will be described later, are partially omitted, and for the sake of simplicity, the interlayer insulating film 59 (FIG. 8) is shown only by its outer shape and opening 59a by dotted lines. Yes.

  The semiconductor device 50 is mainly different from the semiconductor device 10 (FIG. 1) of the first embodiment described above in a semiconductor thin film formation region 52 (corresponding to the output pad formation region 22 of the semiconductor device 10 of the first embodiment). A semiconductor thin film 62 to be described later is formed, and a component connected to the semiconductor thin film 62 is added. Therefore, in this semiconductor device 50, parts common to those of the semiconductor device 10 (FIG. 1) of the first embodiment described above are denoted by the same reference numerals, description thereof is omitted, and different points are mainly described. .

  As shown in FIGS. 7 and 8, in the semiconductor device 50, the multilayer wiring layer 12 is formed in the semiconductor element formation region 21 on the element region 25 on the Si substrate 51, and is different from the semiconductor element formation region 21. A multilayer wiring layer 53 is formed in the semiconductor thin film formation region 52 in the region. A conductive layer 61 extending in the longitudinal direction of the semiconductor device 50 is formed on the multilayer wiring layer 53 in the semiconductor thin film formation region 52 as shown in FIG. The conductive layer 61 is a metal layer, for example, and is a single layer or a laminated film containing one or more elements of, for example, Ti, Pt, Au, Ni, Ge, Cr, and In.

  A semiconductor thin film 62 is formed on the conductive layer 61. As will be described later, the semiconductor thin film 62 is, for example, a semiconductor thin film formed on another substrate, and the semiconductor thin film peeled off from the substrate can be bonded to the conductive layer 61.

  The semiconductor thin film 62 is made of, for example, GaAs, AlGaAs, InP. It has a single layer or a plurality of semiconductor laminated structures of compound semiconductors such as InGaAsP, AlGaInP, GaN, AlGaN, and AlInN, and one or more semiconductor elements. The semiconductor element is, for example, an optical element such as a light emitting diode, a semiconductor laser, or a light receiving element. In the present embodiment, the semiconductor thin film 62 includes a plurality of light emitting diodes 63 as an example, for example, 42.4 μm (600 dpi) or more. It is assumed that the light emitting diode array is arranged in a line at a high density. As shown in FIG. 7, the light emitting diode 63 and the plurality of output electrode pads 16 are formed to correspond to each other, for example, on a one-to-one basis.

  FIG. 8 is a cross-sectional view showing a cross section taken along the line C-C including the region where the light emitting diode 63 of the semiconductor device 50 is formed as shown in FIG. 7, and FIG. 10 is a semiconductor thin film shown in FIG. It is the elements on larger scale which expanded 62 and its lower layer part.

As shown in FIG. 10, the semiconductor thin film 62 formed on the conductive layer 61, n-GaAs lower contact layer 62a in this order from the _{bottom, n-Al x Ga 1-} x As lower cladding layer 62b, n-Al _y Ga _1-y As active layer 62c, p-Al _z Ga _1-z As upper cladding layer 62d, p-GaAs upper contact layer 62e, and 0 ≦ x, y, z ≦ 1, for example, y <x, z. In order to form an individual light emitting diode, the semiconductor thin film 62 has at least the active layer 62c individually separated. Of these, a portion corresponding to a region where the individual light emitting diodes 63 are separated is referred to as an upper region 62f, and a lower region is referred to as a lower region 62g. 7 and 8 show the upper region 62f, the uppermost upper contact layer 62e of the upper region 62f, and the lower region 62g.

  As shown in FIGS. 7 and 8, an interlayer insulating film 59 is formed on the semiconductor thin film 62 having the above-described configuration. This interlayer insulating film 59 has an opening 59a in a portion corresponding to each upper region 62f of the semiconductor thin film 62, and is formed so as to extend to a position over the end of the output electrode pad 16 as shown in FIG. ing. Each output electrode pad 16 is formed with a coating layer 57 covering the electrode pad in the same manner as the coating layer 17 in the first embodiment. From this coating layer 57, an individual wiring reaching the semiconductor thin film 62 is described later. 58 is formed continuously. The covering film 57 is, for example, a single layer or a laminated metal containing one or a plurality of elements among Ti, Pt, Au, Ge, Ni, Cr, and W, similarly to the covering layer 17 in the first embodiment. It can be a membrane.

  The individual wiring 58 extending from the covering layer 57 is formed on the interlayer insulating film 59, and through the opening 59a formed in the interlayer insulating film 59, the contact layer 62e in the corresponding upper region 62f of the semiconductor thin film 62 (FIG. 10) and electrically connected.

  In the above configuration, for example, the layer thickness of the individual wiring 58 is 0.5 μm to 1 μm, and the semiconductor thin film layer 62 is formed to a total of 10 μm or less, preferably 3 μm or less. As will be described later, the coating layer 57 is formed of the same wiring layer when the individual wiring 58 is formed.

  FIG. 9 is a cross-sectional view showing a cross section taken along a line DD including a region where the light emitting diode 63 of the semiconductor device 50 is not formed, as shown in FIG.

  As shown in the figure, since this region corresponds to a portion where the upper region 62f of the semiconductor thin film 62 is removed by element isolation of the semiconductor thin film 62, only the lower region 62g of the semiconductor thin film 62 is formed on the conductive layer 61. Exists. On the other hand, a wiring layer 65 for electrically connecting the conductive layer 61 and the input electrode pad 14 of the predetermined input electrode forming portion 26 is formed at this position, as shown in FIG. The wiring layer 65 is formed, for example, continuously from the input electrode pad 14 and extends in the multilayer wiring layers 12 and 53 to the lower part of the conductive layer 61. In the conductive layer 61, connection terminals 61 a that are electrically connected to the wiring layer 65 through openings 53 a formed in the multilayer wiring layer 53 corresponding to the end portions of the wiring layer 65 are formed.

  Next, a method for manufacturing the semiconductor device 50 configured as described above will be described.

  After the drive integrated circuit and the input / output electrode pads 14, 15 and 16 are formed in the element region 25 and the multilayer wiring layer 12 by the same method as described in the first embodiment, the lift-off method is used, for example. A conductive layer (metal layer) 61 is formed. On the other hand, as shown in FIG. 11, a semiconductor thin film layer 62 'is formed on the second substrate 67 different from the Si substrate 11 by, for example, the MOCVD method. At this time, the buffer layer 68 and the release layer 69 are provided between the semiconductor thin film layer 62 ′ and the second substrate 67.

  The semiconductor thin film until it is formed on the conductive layer 61 shown in FIG. 7 is denoted by reference numeral 62 ′, and the semiconductor thin film at the stage where the element is separated into individual regions is denoted by reference numeral 62.

The second substrate 67 is, for example, a GaAs layer, the buffer layer 68 is, for example, a GaAs buffer layer, and the release layer 69 is, for example, an AlAs layer. The semiconductor thin film 62 ′ is formed in order from the side in contact with the buffer layer 68, for example, an n-GaAs lower contact layer 62 a, an n-Al _x Ga _1-x As lower cladding layer 62 b, and an n-Al _y Ga _1-y As activity. layer _{62c, p-Al z Ga 1} -z as upper cladding layer 62d, a p-GaAs on the contact layer 62e, a 0 ≦ x, y, z ≦ 1.

  The semiconductor thin film layer 62 ′ formed on the second substrate 67 is separated by mesa etching into the size of the semiconductor thin film 62 shown in FIG. 7, and a first support (not shown) is provided on each semiconductor thin film 62 ′. A second support (not shown) for connecting the supports is further provided, and the semiconductor thin film 62 ′ is immersed in an etching solution that selectively etches only the peeling layer 69, for example, diluted hydrofluoric acid, to form the second substrate. The semiconductor thin film 62 ′ peeled off from 67 is bonded onto the conductive layer 61 shown in FIG. 7.

  Bonding is performed using, for example, intermolecular force. After bonding, for example, sintering is performed at 200 ° C. to increase the bonding force between the conductive layer 61 and the semiconductor thin film 62 ′. Next, the semiconductor layer of the semiconductor thin film 62 ′ is mesa-etched to separate the elements into predetermined individual element regions, and an interlayer insulating film 59 is provided. Openings 59a for contacts are formed in the interlayer insulating film 59, and individual wirings 58 are formed. At this time, for example, the pad coating layer 57 is formed simultaneously with the individual wiring 58.

  The output electrode pad 16 formed here is for testing an integrated circuit such as a driving integrated circuit formed on the Si substrate 51 alone or a semiconductor thin film 62 which is a driven semiconductor device alone. This is a test pad to be used.

FIG. 12 is a diagram illustrating a modification of the semiconductor device 50 according to the third embodiment. In the semiconductor device 50 of the third embodiment described above, as shown in FIG. 10, the individual light emitting diodes 63 are formed by element isolation. However, as shown in FIG. 12, the light emitting diodes are formed by selective diffusion type. Also good. That is, in FIG. 12, 70 is a semiconductor thin film region, 61 is a conductive layer, 53 is a multilayer wiring layer, and 51 is a Si substrate. The semiconductor thin film 70 in turn for example, the first conductivity type from below, wherein n-type n-GaAs layer 70a _{is, n-Al x Ga 1-} x As layer _{70b, n-Al y Ga 1} -y As layer 70c, n -Al _z Ga _1-z as layer 70d, an n-GaAs layer 70e, a 0 ≦ x, y, z ≦ 1 in, for example, y <x, z. An impurity diffusion region 72 is formed in a predetermined region of the semiconductor thin film 70 by, for example, impurity selective diffusion that selectively diffuses a second conductivity type, here, p-type impurity. The diffusion front of the impurity diffusion region 72 is in the active layer 70c, and light is emitted in this region. The second conductivity type impurity is, for example, Zn.

  As described above, according to the semiconductor device 50 of the present embodiment, the semiconductor thin film on which the semiconductor element is formed is provided near the driving integrated circuit, and the output electrode pad of the driving integrated circuit and the individual element formed on the semiconductor thin film are thin film Since the connection is made by wiring, in addition to the effect obtained in the first embodiment, the chip width in which the drive element and the semiconductor element are combined can be reduced. Further, although the probe needle also contacts this pad, the needle pressure can be reduced as described above, so that this pad can be reduced. In particular, when the semiconductor thin film is an LED array for a printer, a large number of pads are required in accordance with the number of LEDs. Therefore, it is very important to keep the pads small.

  In the case where a coating layer is previously formed on the output pad as in the semiconductor device of the first embodiment (FIG. 1), an integrated circuit such as a driving integrated circuit alone is bonded before the semiconductor thin film is bonded. Since the probe test using the pad 104 (107) can be performed with a small probe needle pressure, the pad 104 can be made small. On the other hand, when the coating layer is formed after adhering the semiconductor thin film as in the present embodiment, since the coating layer by the wiring layer can be formed simultaneously with the wiring layer on the semiconductor thin film such as individual wiring, The photolithography process is reduced, which can contribute to reduction of man-hours and improvement of yield.

Embodiment 4 FIG.
FIG. 13 is a plan view schematically showing a main configuration of a semiconductor device 80 according to the fourth embodiment of the present invention, and FIG. 14 is a schematic cross-sectional view of the semiconductor device 80 shown in FIG. FIG. In FIG. 13, for the sake of explanation, a part of coating layers 17 and 87, which will be described later, is omitted, and for the sake of simplicity, the interlayer insulating film 89 (FIG. 14) is shown only by its outline and opening 89a by dotted lines. Yes.

  The semiconductor device 80 is mainly different from the semiconductor device 50 (FIG. 7) of the third embodiment described above in that the semiconductor thin film formation region 93 including the semiconductor thin film and the output electrode pad overlaps the semiconductor element formation region 92. For this reason, a planarizing layer 94 is newly provided in the semiconductor thin film formation region 93, and the layout in the semiconductor thin film formation region 93 is changed. Therefore, in this semiconductor device 80, parts common to the semiconductor device 50 (FIG. 7) of the above-described third embodiment are denoted by the same reference numerals, description thereof is omitted, and different points are mainly described. . Here, the planarization layer 94 is a semiconductor thin film 62 bonded to the semiconductor thin film formation region 93 and provides a surface flatness necessary and sufficient to obtain a bonding strength that ensures the reliability of the formed device. It means that.

  As shown in the cross-sectional view of FIG. 14, in the Si substrate 81 of the semiconductor device 80, drive integration for driving and controlling an optical element or an optical element array such as a light-emitting diode or a light-receiving sensor is performed over substantially the entire area including the upper side surface thereof. An element region 85 including a semiconductor element such as a circuit is formed. The semiconductor element formation region 92 shown in FIG. 13 corresponds to the region seen in the plan view of the element region 85. A multilayer wiring layer 82 is formed on the element region 85, and a planarization layer 94 is formed on the multilayer wiring layer 82 in the semiconductor thin film formation region 93 including the semiconductor thin film 62 and the output electrode pad 36. . As shown in FIG. 13, the planarizing layer 94 is formed so as to extend along the longitudinal direction of the semiconductor device 80. As the planarizing layer 94, for example, a coating film such as an SOG film (spin-on-glass film), a polyimide film, or an organic insulating film can be used.

  A conductive layer 91 extending in the longitudinal direction of the semiconductor device 80 is formed on the planarization layer 94 in the semiconductor thin film formation region 93 as shown in FIG. The conductive layer 91 is a metal layer, for example, and is a single layer or a laminated film containing one or more elements of, for example, Ti, Pt, Au, Ni, Ge, Cr, and In. A semiconductor thin film 62 is formed on the conductive layer 91. Since the semiconductor thin film 62 has been described in the third embodiment with reference to the enlarged view of FIG. 10, description thereof is omitted here, for example, a semiconductor thin film formed on another substrate, The semiconductor thin film peeled from the substrate is bonded onto the conductive layer 91.

A wiring member 43 is formed on the multilayer wiring layer 82. The wiring member 43 is connected to a predetermined terminal (not shown) connected to a semiconductor element (not shown) formed in the element region 85 and is connected to a vertical wiring portion 43a that is planted substantially vertically on the upper surface of the element region 85; The vertical wiring portion 43 a is formed to extend from the upper end portion, and includes a horizontal pad portion 43 b connected to the output electrode pad 86. Moreover, the wiring member 43 is comprised from the material equivalent to a multilayer wiring material, for example, for example, is a metal material containing Al.

  The output electrode pad 86 is formed on the planarizing layer 94 with an electrode pad containing Al, for example, and extends from the output pad portion 86a on the planarizing layer 94 and formed in a square shape. The wiring member 43 includes a terminal portion 86b connected to the horizontal pad portion 43b through an opening 94a (FIG. 14) formed in the multilayer wiring layer 32 and the planarizing layer 94 corresponding to the horizontal pad portion 43b. . As shown in FIG. 13, the plurality of light emitting diodes 63 formed on the semiconductor thin film 62 and the output electrode pad portion 86 are formed to correspond to each other, for example, one to one.

  An interlayer insulating film 89 is formed on the semiconductor thin film 62 described above. The interlayer insulating film 89 has an opening 89 a in a portion corresponding to each upper region 62 f of the semiconductor thin film 62 and is formed so as to cover substantially the entire area of the semiconductor thin film 62 and the conductive layer 91. A coating layer 87 is formed on each output electrode pad 86 so as to cover the output pad portion 86a, and individual wirings 88 extending from the coating layer 87 to the semiconductor thin film 62 are continuously formed as will be described later. Yes. The covering film 87 is, for example, a single layer or a laminated metal containing one or a plurality of elements among Ti, Pt, Au, Ge, Ni, Cr, and W, similarly to the covering layer 57 in the third embodiment. It can be a membrane.

  The individual wiring 88 extending from the covering layer 87 is formed on the interlayer insulating film 89, and through the opening 89a formed in the interlayer insulating film 89, the contact layer 62e (see FIG. 10) and electrically connected.

  On the other hand, a wiring layer 65 for electrically connecting the conductive layer 91 and the input electrode pad 14 of the predetermined input electrode forming portion 26 is formed at the cross-sectional position shown in FIG. Yes. The wiring layer 65 is formed, for example, continuously from the input electrode pad 14 and extends in the multilayer wiring layer 82 to the lower part of the conductive layer 91. In the conductive layer 91, connection terminals 91 a that are electrically connected to the wiring layer 65 are formed through openings 82 a formed in the multilayer wiring layer 82 corresponding to the ends of the wiring layer 65.

  Next, the manufacturing method of the semiconductor device 80 configured as described above can be formed in substantially the same manner as the manufacturing method described in the second embodiment until the planarizing layer 94 is formed, and thereafter. Since the semiconductor thin film 62, the light emitting diode 63, the interlayer insulating film 89, the individual wiring 88, and the pad covering layer 87 can be formed by the method described in the third embodiment, detailed description thereof is omitted here.

  As described above, according to the semiconductor device 80 of the present embodiment, the planarization layer 94 is provided in the semiconductor element formation region 92 and the semiconductor thin film formation region 93 including the semiconductor thin film and the output electrode pad is disposed. In addition to the effects obtained in the third embodiment, the chip width of the semiconductor device 80 can be further reduced.

Embodiment 5. FIG.
FIG. 15 is a plan view schematically showing a main configuration of the semiconductor device 100 according to the fifth embodiment of the present invention, and FIG. 16 is a schematic cross-sectional view of the semiconductor device 100 shown in FIG. FIG. In FIG. 15, for the sake of explanation, a part of coating layers 17 and 107, which will be described later, is partially omitted, and for the sake of simplicity, the interlayer insulating film 89 (FIG. 16) is shown only by its outline and opening 89a by dotted lines. Yes.

  The semiconductor device 100 is mainly different from the semiconductor device 80 (FIG. 13) of the fourth embodiment described above in that the output electrode forming portion 27 having the output electrode pad 16 and the covering layer 107 is not the semiconductor element forming region 112. The other points are formed in the output pad formation region 113. Therefore, in this semiconductor device 100, parts common to those of the semiconductor device 80 (FIG. 13) of the above-described fourth embodiment are denoted by the same reference numerals, description thereof is omitted, and different points are mainly described. .

  As shown in FIGS. 15 and 16, the semiconductor device 100 includes, on the Si substrate 101, an element including a semiconductor element such as an optical element such as a light emitting diode or a light receiving sensor or a driving integrated circuit that drives and controls an optical element array. A multilayer wiring layer 102 is formed in the semiconductor element formation region 112 on the region 105, and a multilayer wiring layer 103 is formed in the output pad formation region 113, which is a region different from the semiconductor element formation region 112. In the semiconductor element formation region 112, a planarization layer 114, a conductive layer 91, a semiconductor thin film 62, an interlayer insulating film 89, a wiring layer 65, and an input electrode formation portion 26 are formed. Since the configuration is the same as that of the semiconductor device 80 described in the fourth embodiment except that the formation region 114 does not cover the output electrode forming portion 27, the description thereof is omitted here.

  For the planarizing layer 114, for example, a coating film such as an SOG film (spin-on-glass film), a polyimide film, or an organic insulating film can be used. Further, since the semiconductor thin film 62 has been described in the third embodiment with reference to the enlarged view of FIG. 10, the description thereof is omitted here. For example, the semiconductor thin film 62 is a semiconductor thin film formed on another substrate. The semiconductor thin film peeled from the substrate is bonded onto the conductive layer 91.

  A wiring member 23 is formed on the multilayer wiring layers 102 and 103. The wiring member 23 is connected to a predetermined terminal (not shown) connected to a semiconductor element (not shown) formed in the element region 105 and is connected to a vertical wiring portion 23a that is planted substantially vertically on the upper surface of the element region 105; An output electrode pad that extends from the upper end portion of the vertical wiring portion 23 a and is formed substantially parallel to the upper surface of the element region 105 from the semiconductor element formation region 112 to the output pad formation region 113, and is disposed in the output pad formation region 113. 16 and a horizontal wiring portion 23 b connected to 16.

  The output electrode pad 16 is formed in the multilayer wiring layer 103, and an opening 103a (FIG. 16) is formed in the multilayer wiring layer 103 at a position facing the output electrode pad 16. A coating layer 107 covering the output electrode pad 16 is formed on the output electrode pad 16 over a predetermined region including the opening 103a. The coating layer 107 reaches the semiconductor thin film 62 as described later. The individual wiring 108 is continuously formed. As shown in FIG. 15, the light emitting diode 63 and the output electrode pad 16 of the semiconductor thin film 62 are formed so as to correspond to each other on a one-to-one basis, for example. Further, the coating film 107 includes one or a plurality of elements among, for example, Ti, Pt, Au, Ge, Ni, Cr, and W, similarly to the coating layer 17 (FIG. 1) in the first embodiment. It can be a single layer or a laminated metal film.

  The individual wiring 108 extending from the covering layer 107 is formed on the interlayer insulating film 89, and through the opening 89a formed in the interlayer insulating film 89, the contact layer 62e (see FIG. 10) and electrically connected.

  According to the semiconductor device 100 of the present embodiment configured as described above, a planarization film is provided on the semiconductor element formation region 112 where the drive integrated circuit is formed, and the semiconductor thin film layer is formed on the planarization film layer. The output electrode pad 16 for connecting or probing with the individual wiring 108 connected to the semiconductor element (light emitting diode 63) provided in the semiconductor thin film is formed as an output pad other than the semiconductor element formation region 112. Since it is formed in the region 113, the chip width of the semiconductor device can be reduced by the width of the region where the semiconductor thin film 62 is bonded, and at the same time, the needle pressure of the probe needle brought into contact with the output electrode pad 16 can be increased. it can.

  The reason why the needle pressure of the probe needle can be increased is as follows. That is, if the output electrode pad 16 is formed on the semiconductor element formation region 112, when a probe needle is applied to the output electrode pad 16, for example, there is a wiring layer under the output electrode pad 16, Stress from the tip of the probe needle is applied to the unevenness due to the presence / absence of the wiring layer, which may cause a problem such as a short circuit due to the breakdown of the interlayer insulating film, but the output electrode pad 16 is formed outside the semiconductor element formation region 112. Such a problem can be eliminated even if the pressure of the probe needle is slightly increased.

Embodiment 6 FIG.
FIG. 17 is a plan view schematically showing a main configuration of the semiconductor device 120 according to the sixth embodiment of the present invention. FIG. 18 is a schematic view of the semiconductor device 120 shown in FIG. FIG. In FIG. 17, for the sake of explanation, a part of coating layers 17 and 57, which will be described later, is shown in a partially omitted state, and for the sake of simplicity, the interlayer insulating film 59 (FIG. 8) is shown only by its outline and opening 59a by dotted lines. Yes.

  The semiconductor device 120 is mainly different from the semiconductor device 50 (FIG. 7) of the third embodiment described above in that the conductive layer 122 that electrically connects the upper surface of the lower region 62g of the semiconductor thin film layer 62 and the conductive layer 61. Is a new point. Therefore, in this semiconductor device 120, parts common to those of the semiconductor device 50 (FIG. 7) of the third embodiment described above are denoted by the same reference numerals, or the description thereof is omitted by omitting the drawings. Will be explained with emphasis.

  The conductive layer 122 electrically connects the upper surface of the lower region 62g serving as a common potential region and the conductive layer 61 of the plurality of light emitting diodes 63 formed by separating the elements from the semiconductor thin film layer 62. The upper surface of the lower region 62g with which the conductive layer 122 contacts is a semiconductor layer made of a material in which a metal layer and a low resistance contact are formed. For example, as shown in FIG. For this reason, as shown in FIG. 17, the semiconductor thin film layer 62 is formed over substantially the entire region in the longitudinal direction so as to cover a predetermined region of the upper surface of the lower region 62 g and the upper surface of the conductive layer 61. The conductive layer 122 is, for example, a metal layer, and is a laminated film or alloy including one or more elements of Au, Ge, Ni, Pt, Ti, Pd, In, Al, Cu, Cr, and Si. It is the material which consists of.

  As described above, according to the semiconductor device of the sixth embodiment, since the contact with the conductive layer connected to the electrode is formed on a surface different from the bonding surface of the semiconductor thin film, for example, the effect obtained in the third example can be obtained. In addition, the electrical characteristics of the semiconductor element included in the semiconductor thin film can be controlled without depending on the bonding form or state on the back surface of the semiconductor thin film. For example, characteristic variations such as drive voltages of a large number of semiconductor elements can be reduced.

  FIG. 19 is a cross-sectional view of a semiconductor device 130 that is a modification of the semiconductor device 120 of the sixth embodiment. Here, with respect to the semiconductor device 120 described above, an insulating layer 131 such as a dielectric thin film is provided between the semiconductor thin film 62 (FIG. 17) and the conductive layer 61. The insulating layer 131 may be a single layer thin film, a laminated film, or may include an insulating adhesive layer.

  Although not shown, a plurality of wiring layers that can be directly connected to the input electrode pad 14 such as the wiring layer 65 in the conductive layer 61 may be provided in the conductive layer 122 without using the conductive layer 61 shown in FIG. Good. Note that the form in which the common potential region in contact with the conductive layer 122 is formed on the upper surface of the semiconductor thin film as in the sixth embodiment can be applied to the other third to fifth embodiments.

Embodiment 7 FIG.
FIG. 20 is a plan view schematically showing the configuration of the light-emitting diode unit according to the seventh embodiment of the present invention.

  As shown in the figure, the light-emitting diode unit 150 includes, for example, a light-emitting diode array in which the semiconductor device 100 described in the fifth embodiment is mounted on a mounting substrate 151 and the light-emitting diodes 63 are arranged in a row. A light emitting diode unit serving as a writing light source. In addition to the semiconductor device 100, a wiring / connection pad region 152 is provided on the mounting substrate 151. In this wiring / connection pad region 152, for example, a wiring region (not shown) provided on the surface of the mounting substrate 151 and a semiconductor thin film 62 are bonded to the semiconductor device 100 in the form of a semiconductor composite chip. A connection pad region (not shown) for inputting power is provided.

  Furthermore, on the mounting substrate 151, for example, connector terminals for inputting external signals and power, capacitors and resistors for reducing signal noise and reflection, voltage dividing resistors for determining a current for driving, Components necessary for driving such as a regulator IC and a memory for storing data for current correction are mounted, but the description thereof is omitted here. A bonding wire 153 for electrical connection is provided between each connection pad (not shown) in the wiring / connection pad region 152 and each input electrode pad 14, 15 of the input electrode forming portion 26 of the semiconductor device 100 in a predetermined correspondence relationship. It is built and electrically connected.

  In the above example, the example in which the semiconductor device 100 described in the fifth embodiment is mounted on the mounting substrate 151 has been described. However, the present invention is not limited to this, and the configuration described in the third and fourth embodiments is described. The composite semiconductor device 50 or the semiconductor device 80 may be used instead. Further, a semiconductor element group to be driven, for example, a light emitting diode array chip, is separately provided on the mounting substrate 151 by using the semiconductor device 10 or the semiconductor device 30 having the driving integrated circuit as described in the first and second embodiments. The driving terminals of these integrated circuits and the input terminals of the light-emitting diode array chip may be replaced with a form in which, for example, wine bonding or flip chip connection is used.

  As described above, according to the light emitting diode unit of the present embodiment, the semiconductor device including the composite type with a reduced chip width is mounted to constitute the semiconductor composite element unit, and therefore the unit substrate width can also be reduced. .

Embodiment 8 FIG.
FIG. 21 is a cross-sectional view of an LED head for explaining an LED head on which a light emitting diode unit including the semiconductor device of the present invention is mounted.

  In the figure, an LED head 200 has a base member 201 and an LED unit 202 fixed thereon. The LED unit 202 is, for example, the light emitting diode unit 150 described in the seventh embodiment. For example, any one of the semiconductor devices described in the first to sixth embodiments is mounted on the mounting substrate 151. It is mounted on.

  A rod lens array 203 as an optical element for condensing light emitted from the light emitting unit is disposed above the light emitting unit of the light emitting unit 202a. The rod lens array 203 includes a large number of columnar optical lenses arranged along light emitting diodes (for example, refer to the arrangement of the light emitting diodes 63 shown in FIG. 15) arranged in a linear shape in the light emitting unit 202a. The lens holder 204 corresponding to the element holder is held at a predetermined position.

  The lens holder 204 is formed so as to cover the base member 201 and the LED unit 202 as shown in FIG. The base member 201, the LED unit 202, and the lens holder 204 are integrally held by a clamper 205 disposed through openings 201a and 204a formed in the base member 201 and the lens holder 204.

  Accordingly, the light generated by the LED unit 202 is applied to a predetermined external member through the rod lens array 203. The LED head 200 is used as an exposure apparatus such as an electrophotographic printer or an electrophotographic copying apparatus.

  As described above, according to the LED head of the present embodiment, as the LED unit 202, a composite chip in which the LED / driving integrated circuit described in each of the third to sixth embodiments is integrated. Since a semiconductor device having a small width is used, a compact and high-quality LED head can be provided. Even if the semiconductor device is not a composite type semiconductor device, a compact LED head with a reduced drive integrated circuit width can be provided by using the semiconductor devices of the first and second embodiments.

Embodiment 9 FIG.
FIG. 22 is a main part configuration diagram illustrating an image forming apparatus using an LED head on which the semiconductor device of the present invention is mounted.

  In the figure, an image forming apparatus 300 has four process units 301 to 304 that respectively form yellow, magenta, cyan, and black images, and these are arranged in order from the upstream side of the conveyance path of the recording medium 305. Has been. Since the internal configurations of these process units 301 to 304 are common, the internal configuration will be described by taking, for example, a cyan process unit 303 as an example.

  In the process unit 303, a photosensitive drum 303a as an image carrier is rotatably arranged in the direction of the arrow. Around the photosensitive drum 303a, the surface of the photosensitive drum 303a is sequentially arranged from the upstream side in the rotation direction. A charging device 303b that supplies and charges electric charges and an exposure device 303c that forms an electrostatic latent image by selectively irradiating light onto the surface of the charged photosensitive drum 303a are provided. Furthermore, a developing device 303d that generates a visible image by attaching toner of a predetermined color (cyan) to the surface of the photosensitive drum 303a on which the electrostatic latent image is formed, and a visible image of the toner on the photosensitive drum 303a. A cleaning device 303e that removes toner remaining after the transfer is provided. The drums or rollers used in each of these devices rotate by receiving power from a drive source (not shown) via a gear or the like.

  The image forming apparatus 300 also has a paper cassette 306 for storing a recording medium 305 such as paper in a stacked state below the image forming apparatus 300, and the recording medium 305 is separated and conveyed one by one above it. A hopping roller 307 is provided. Further, by sandwiching the recording medium 305 together with the pinch rollers 308 and 309 in the downstream direction of the hopping roller 307 in the conveyance direction of the recording medium 305, the skew of the recording medium 305 is corrected and the resist conveyed to the process unit 301 is corrected. Rollers 310 and 311 are provided. The hopping roller 307 and the registration rollers 310 and 311 are rotated by power transmitted from a driving source (not shown) via a gear or the like.

  Transfer rollers 312 made of semiconductive rubber or the like are disposed at positions facing the respective photosensitive drums of the process units 301 to 304. These transfer rollers 312 have a potential difference between the surface potentials of the photosensitive drums 301a to 304a and the surface potentials of the respective transfer rollers 312 when transferring the visible image of the toner attached on the photosensitive drum 303a to the recording medium 305. A potential for applying the voltage is applied.

  The fixing device 313 includes a heating roller and a backup roller, and fixes the toner transferred onto the recording medium 305 by pressurizing and heating. The downstream discharge rollers 314 and 315 sandwich the recording medium 305 discharged from the fixing device 313 together with the pinch rollers 316 and 317 of the discharge unit and convey the recording medium 305 to the recording medium stacker unit 318. The fixing device 313, the discharge roller 314, and the like are rotated by driving power transmitted from a driving source (not shown) via gears.

  As the exposure apparatus 303c used here, the LED head 200 described in the eighth embodiment is used.

The operation of the image recording apparatus having the above configuration will be described.
First, the recording medium 305 stored in a stacked state in the paper cassette 305 is separated and conveyed one by one from the top by the hopping roller 307. Subsequently, the recording medium 305 is sandwiched between the registration rollers 310 and 311 and the pinch rollers 308 and 309 and is conveyed to the photosensitive drum 301 a and the transfer roller 312 of the process unit 301. Thereafter, the recording medium 305 is sandwiched between the photosensitive drum 301a and the transfer roller 312, and the toner image is transferred to the recording surface thereof and is simultaneously conveyed by the rotation of the photosensitive drum 301a.

  Similarly, the recording medium 305 sequentially passes through the process units 302 to 204, and in the passing process, the electrostatic latent images formed by the exposure devices 301 c to 304 c are developed for the respective colors developed by the developing devices 301 d to 304 d. The toner images are sequentially transferred onto the recording surface and superimposed.

  Then, after the toner images of the respective colors are superimposed on the recording surface, the recording medium 305 on which the toner image is fixed by the fixing device 313 is sandwiched between the discharge rollers 314 and 315 and the pinch rollers 316 and 317 so that the image The recording medium is discharged to a recording medium stacker unit 318 outside the recording apparatus 300. A color image is formed on the recording medium 305 through the above process.

  As described above, according to the image forming apparatus of the present embodiment, since the LED head of the eighth embodiment described above is employed, an image forming apparatus that is excellent in space efficiency, high quality, and can be expected to reduce manufacturing costs. Can be provided.

  In addition, in the above-described claims and the description of the embodiments, the words “upper” and “lower” are used for the sake of convenience, and the absolute positional relationship in the state where the semiconductor device is arranged. It is not intended to limit.

1 is a plan view schematically showing a main configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is an essential part cross-sectional view schematically showing a cross section of the semiconductor device shown in FIG. 1 taken along line AA. FIG. 6 is a diagram showing a modification of the semiconductor device of First Embodiment. FIG. 10 is a diagram showing still another modification of the semiconductor device of First Embodiment. It is a top view which shows roughly the principal part structure of the semiconductor device of Embodiment 2 by this invention. FIG. 6 is a cross-sectional view of an essential part schematically showing a cross section of the semiconductor device shown in FIG. 5 taken along line BB. It is a top view which shows roughly the principal part structure of the semiconductor device of Embodiment 3 by this invention. FIG. 8 is a fragmentary cross-sectional view schematically showing a cross section of the semiconductor device shown in FIG. FIG. 8 is an essential part cross-sectional view schematically showing a cross section of the semiconductor device shown in FIG. 7 taken along line DD. It is the elements on larger scale which expanded the semiconductor thin film shown in FIG. 8, and its lower layer part. It is a figure where it uses for description of the manufacturing method of the semiconductor device of Embodiment 3 by this invention. FIG. 10 is a diagram showing a modification of the semiconductor device of the third embodiment. It is a top view which shows roughly the principal part structure of the semiconductor device of Embodiment 4 by this invention. It is principal part sectional drawing which shows roughly the cross section which cuts the semiconductor device shown in FIG. 13 by EE line. It is a top view which shows roughly the principal part structure of the semiconductor device of Embodiment 5 by this invention. FIG. 16 is a main part cross-sectional view schematically showing a cross section of the semiconductor device shown in FIG. 15 taken along line FF; It is a top view which shows roughly the principal part structure of the semiconductor device of Embodiment 6 by this invention. It is principal part sectional drawing which shows roughly the surface which cuts the semiconductor device shown in FIG. 17 by a GG line. It is sectional drawing of the modification of the semiconductor device of this Embodiment 6. It is a top view which shows roughly the structure of the light emitting diode unit of Embodiment 7 by this invention. It is a cross-sectional view of the LED head for demonstrating the LED head which mounts the light emitting diode unit provided with the semiconductor device of this invention. It is a principal part block diagram explaining the image forming apparatus using the LED head carrying the semiconductor device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device, 11 Si substrate, 12 Multilayer wiring layer, 13 Multilayer wiring layer, 13a Opening, 14 Input electrode pad, 15 Input electrode pad, 16 Output electrode pad, 17 Covering layer, 21 Semiconductor element formation area, 22 Output pad Forming region, 23 wiring member, 23a vertical wiring portion, 23b horizontal wiring portion, 25 element region, 26 input electrode forming portion, 27 output electrode forming portion, 30 semiconductor device, 31 Si substrate, 32 multilayer wiring layer, 36 output electrode pad 36a, output pad section, 36b terminal section, 37 coating layer, 38 planarization layer, 38a opening, 41 semiconductor element formation area, 42 output pad formation area, 43 wiring member, 43a vertical wiring section, 43b horizontal pad section, 45 element Region, 47 output electrode forming portion, 50 semiconductor device, 51 Si substrate, 52 semiconductor thin film type Region, 53 multilayer wiring layer, 57 covering layer, 58 individual wiring, 59 interlayer insulating film, 59a opening, 61 conductive layer, 61a connection terminal, 62, 62 'semiconductor thin film, 62e upper contact layer, 62f upper region, 62g lower region , 63 Light emitting diode, 65 wiring layer, 67 second substrate, 70 semiconductor thin film, 80 semiconductor device, 81 Si substrate, 82 multilayer wiring layer, 85 element formation region, 86 output electrode pad, 86a output pad portion, 86b terminal portion , 87 coating layer, 88 individual wiring, 89 interlayer insulating film, 89a opening, 91 conductive layer, 91a connection terminal, 92 semiconductor element formation region, 93 semiconductor thin film formation region, 94 planarization layer, 100 semiconductor device, 101 Si substrate, 102,103 multilayer wiring layer, 105 element region, 107 coating layer, 108 individual wiring, 1 2 Semiconductor element formation region, 113 Output pad formation region, 114 Planarization layer, 120 Semiconductor device, 122 Conductive layer, 130 Semiconductor device, 131 Insulating layer, 150 Light emitting diode unit, 151 Mounting substrate, 152 Wiring / connection pad region, 153 Bonding wire, 200 LED head, 201 base member, 202 LED unit, 202a light emitting unit, 203 rod lens array, 204 lens holder, 205 clamp, 300 printer, 301, 302, 303, 304 process unit, 303a photosensitive drum, 303b Charging device, 303c Exposure device, 303d Development device, 303e Cleaning device, 305 Recording medium, 306 Paper cassette, 307 Hopping roller, 308,309 Pinch roller 310 and 311 a registration roller, 312 a transfer roller, 313 a fixing device, 314 and 315 discharge rollers, 316 and 317 pinch roller, 318 a recording medium stacker unit.

Claims (11)

A semiconductor substrate in which an element region constituting a driving integrated circuit is formed on a surface layer;
  A multilayer wiring layer formed on the surface of the semiconductor substrate;
  A planarizing layer formed on the surface of the multilayer wiring layer and having an insulating property;
  A semiconductor thin film formed with a light emitting element that is directly or indirectly bonded on the planarization layer and driven by the driving integrated circuit;
  An output electrode pad having an output pad portion extending on a surface of the planarizing layer, and electrically connected to a predetermined portion of the element region via a wiring member formed in the multilayer wiring layer;
  An insulating layer covering all or part of the semiconductor thin film except for a contact layer provided on the semiconductor thin film;
  A covering portion covering at least the output pad portion extending on the surface of the planarizing layer, and an individual wiring portion extending on the insulating layer from the covering portion to the contact layer provided on the semiconductor thin film; A thin film wiring for electrically connecting the output electrode pad and the contact layer;
  A semiconductor device comprising: The semiconductor device according to claim 1, wherein a conductive layer is formed on a surface of the planarizing layer, and the semiconductor thin film is bonded to the surface of the conductive layer. The substrate is a semiconductor device according to claim 1 or 2, wherein it is a Si substrate. The metal material of the covering portion is a single layer or a laminated metal film containing one or a plurality of elements among Ti, Pt, Au, Ge, Ni, Cr, and W. The semiconductor device according to any one of 1 to 3 . The semiconductor device according to any one of claims 1 to 4, wherein the planarization layer is a coating film. 6. The semiconductor device according to claim 5, wherein the coating film is an SOG film. 6. The semiconductor device according to claim 5 , wherein the coating film is polyimide. 6. The semiconductor device according to claim 5, wherein the coating film is an organic film. 3. The semiconductor device according to claim 2 , further comprising an input electrode pad , wherein the conductive layer and the input electrode pad are electrically connected. Claims wherein the light emitting element, the light emitting diode array der in which a plurality of light emitting diodes in a row is, the output electrode pad and the thin film wiring is characterized, characterized in that provided in correspondence with the respective light emitting diodes The semiconductor device according to any one of 1 to 9 . Metallic material of the covering portion, the semiconductor device according to any one of claims 1 to 3, characterized in that the noble metals.

Images