JP5404182B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a data transfer circuit having a prefetch memory that simultaneously reads a plurality of bits from a memory cell and serially outputs them.

  This type of prefetch memory data transfer method is generally advantageous in improving the operating frequency in a clock synchronous semiconductor memory device. In practice, a DDR (Double Data rate) -1 SDRAM (Synchronous Dynamic Random Access) is used. Memory) 2N (N = 1; number of I / Os per address) prefetch, and DDR-2 SDRAM, 4N prefetch, and increasing the prefetch number, the data transfer rate is improved. However, it is difficult to increase the access time of the chip itself.

  Therefore, as the operating frequency increases, only the data transfer rate is improved without improving the access time by increasing the latency.

  Actually, the data transfer rate of DDR-1 SDRAM is 266 Mbps (Mega bit / second), while using the same performance device, DDR-2 SDRAM has a data transfer rate that is twice that of 533 Mbps. realizable.

  However, the latency is 2 clocks in the DDR-1 SDRAM and 15 ns in terms of access time, whereas it is 4 clocks in the DDR-2 SDRAM, and the access time is equal to 15 ns.

  Further, in the DDR-2 SDRAM, increasing the latency from 2 to 4 clocks complicates the data path circuit, and the access time is further delayed due to an increase in the number of output registers (FIFO (First In First OUT)). There are also problems.

  Furthermore, in recent years, it has been required not only to improve the data transfer rate but also to improve the access time (latency) as well.

  For a data transfer circuit that performs a 2N prefetch operation in a DDR SDRAM read system circuit, for example, refer to Patent Document 1 below. In Patent Document 1, 32-bit data read to a main input / output line (MIO line) is simultaneously sensed by a main amplifier circuit and transferred to an output register in parallel through a global input / output line (GIO line). In order to reduce the peak current, a configuration is disclosed in which data is output with the timing shifted between the 1st output data and the 2nd output data.

  FIG. 11 shows a typical example of a 2N prefetch data transfer circuit at the time of reading of a conventional DDR-1 SDRAM. FIG. 12 is a timing chart showing an example of the read operation of the configuration shown in FIG. The configuration shown in FIG. 11 does not have a configuration for holding data for one clock cycle period on the GIO line, as is clear from comparison with FIG. 1 (configuration of the embodiment of the present invention) described later. . As shown in FIG. 12, the specification of the DDR-1 SDRAM allows a read command (READ) to be input at every rising edge of the external clock signal CK, and holds data for one clock period on the GIO line. This causes a collision with the next read data, resulting in a malfunction. For this reason, data transfer is performed using a signal generated by a one-shot pulse (MAE0, MOE0) from a clock cycle (for example, CK “0” in FIG. 12) in which a read command is input, and the next clock cycle. It is necessary to transfer data within one clock cycle period (for example, CK “1” in FIG. 12).

  As shown in FIGS. 11 and 12, the MA control circuit 110A that inputs the read clock RCLK0 generated from the external clock signal CK and outputs the output control signals MAE0 and MOE0 of the main amplifier is the rising edge of the read clock RCLK0. One-shot pulses (output control signals MAE0 and MOE0) are generated based on the rising edge of the signal obtained by delaying the read clock RCLK0. In FIG. 11, the selection circuit 102 outputs the data to be output first to the F-GIO line and the data to be output later to the S-GIO line according to the start address among the read data of the even address and the odd address. In this way, the connection between the two inputs and the two outputs is switched. Then, the latch circuit 103 delays data to be output later according to the start address among the read data of the even address and the odd address, and outputs the delayed data to the S-GIO line. The selection circuit 108A selects two outputs of the output register (FIFO) based on the rising edge and the falling edge of the clock signal CK20 (same frequency as the external clock CK) and outputs it as serial data. The output of the final stage of the four-stage latch circuit 106 (output at the rising edge of the clock CK15) is selected at the rising edge of the clock CK20, and the output of the final stage of the four-stage latch circuit 107 (output at the rising edge of the clock CK20). Is selected at the falling edge of the clock CK20. The output buffer 109 receives the output from the selection circuit 108A and outputs it to the external data terminal DQ.

JP 2002-25265 A (7th and 9th pages, FIGS. 4 and 9)

  In the conventional data transfer circuit shown in FIG. 11, data transfer is performed using a signal generated by a one-shot pulse from a clock in which a read command is input, and within a period until the next clock, It is necessary to transfer data, and for this reason, data cannot be held on the GIO line for a plurality of clock cycles.

  Therefore, the pipeline stage “0” (Stage_0) in the prefetch data transfer is up to the first stage of the output register circuit (FIFO), and the output register latch circuits (106, 107) require four stages. Become. As a result, it is difficult to increase the access time, and there is a problem that the latency increases as the operating frequency improves.

  Further, as the output register circuit becomes more complicated, there are problems that the chip area increases and the current consumption increases.

  Accordingly, it is a primary object of the present invention to provide a semiconductor integrated circuit device that can reduce latency by simplifying the configuration of a data transfer circuit having a prefetch memory configuration.

  Another object of the present invention is to provide a semiconductor integrated circuit device which can reduce the number of stages of latch circuits of an output register, thereby simplifying the control of the output circuit and realizing area saving, and reducing current consumption. It is in.

  To briefly explain the outline of typical inventions disclosed in the present application, a data transfer circuit between a memory cell and a data pad in a prefetch memory for simultaneously reading and writing a plurality of data is provided on a data bus. And a circuit for holding data for a plurality of clock cycle periods.

A semiconductor integrated circuit device according to an aspect of the present invention includes a plurality of amplification circuit units that respectively receive a plurality of data signals, and a plurality of data signals that are respectively amplified by the plurality of amplification circuit units. A signal transmission path, a plurality of registers that respectively receive the plurality of data signals transmitted through the first signal transmission path, a first control signal that activates the plurality of amplifier circuits, and the plurality of registers And a control circuit that generates a second control signal that controls the timing for determining the data to be input, wherein the first control signal is generated from the first edge of the external clock signal and maintained for a predetermined period of time, The second control signal is generated from a second edge input after the first edge, and the plurality of register circuits input the plurality of register circuits during the predetermined period. Is the time to confirm the over data.
A semiconductor integrated circuit device according to the present invention includes a plurality of amplifier circuit units each receiving a plurality of data signals, and a first signal transmission path through which the plurality of data signals amplified by the plurality of amplifier circuit units are transferred A latch circuit for holding the negative data signal output from the plurality of amplification circuit units through the first signal transmission path, and the plurality of the plurality of signals held in the first signal transmission path by the latch circuit. A plurality of registers each receiving a data signal, a first control signal for activating the plurality of amplifier circuits, a second control signal for controlling the latch circuit, and data input by the plurality of registers are determined. And a control circuit for generating a third control signal for controlling timing, wherein the first control signal is generated from a first edge of an external clock signal, and the second control signal is generated. The signal is generated from the first edge and maintained for a predetermined period, the third control signal is generated from the second edge input after the first edge, and the predetermined period includes the plurality of This is the time until the plurality of data inputted by the register circuit is determined.

Alternatively, in the present invention, a first signal transmission path for transferring a plurality of data in parallel, a plurality of amplifier circuit units receiving the plurality of data, and the plurality of amplifiers amplified by the plurality of amplifier circuit units, respectively. A second signal transmission path for transferring the data, a plurality of output registers for receiving the plurality of data transmitted through the second signal transmission path, and the plurality of output registers respectively held in the plurality of output registers An output unit that serially outputs data based on a clock signal for synchronization, wherein the plurality of amplifier circuit units are output later with respect to data to be output first among the plurality of data Delaying the output timing of at least one other data to the second signaling path to reduce data on the second signaling path Both one clock cycle, and is configured to hold.
A semiconductor integrated circuit device according to another aspect of the present invention is activated based on a signal obtained by dividing a clock signal (referred to as an “external clock signal”) input to the semiconductor integrated circuit device from the outside of the semiconductor integrated circuit device. A control circuit for generating first and second control signals having different timing phases, and a read data signal from a memory cell array corresponding to four addresses, respectively, and receiving the first control signal in common, Four amplifier circuits for amplifying and outputting data signals corresponding to the four addresses in response to the first control signal, first and second selection circuits, and first and second latch circuits, respectively And the first selection circuit that receives data signals of two even addresses out of the four addresses includes a read start address. Accordingly, the signal transmission path of the output destination is switched depending on whether it is output first or later, and the first latch circuit that receives the data signal to be output later of the data signals of the two even addresses is the second latch circuit. In response to the control signal, the second selection circuit outputs the latch output to the corresponding signal transmission path and receives the data signals of two odd addresses out of the four addresses. Accordingly, the signal transmission path of the output destination is switched depending on whether it is output first or later, and the second latch circuit that receives the data signal to be output later among the data signals of the two odd addresses is the second latch circuit. In response to the control signal, the latch output is output to the corresponding signal transmission path, and is transmitted to the signal transmission path from the amplifier circuit stage, and is output to the even-numbered address first. From the amplifier circuit stage, a third selection circuit that inputs a data signal and a data signal of an odd address that is output first, and supplies the data signal to the two inputs of the first output register in correspondence with the reading order The data signal of the even address output later and the data signal of the odd address output later are input to the signal transmission path, and the two inputs of the second output register correspond to the reading order. And a fourth selection circuit for supplying each of the first and second outputs of the first output register and the two outputs of the second output register. And a fifth selection circuit that outputs a serial data output signal in the order of read addresses in accordance with the rising and falling edges of the clock signal.

  According to the present invention, data can be held on a signal transmission path for data transfer for a period corresponding to a plurality of clock cycles. Therefore, the number of latency latch circuits can be reduced. Data transfer time can be increased.

  According to the present invention, by reducing the number of latch circuits of the output register, it is possible to simplify the control of the output circuit and to reduce the area. Furthermore, according to the present invention, current consumption can be reduced.

It is a figure which shows the structure of the data transfer circuit of one Example of this invention. It is a figure which shows the structure of the memory device of one Example of this invention. 1 is a diagram showing a layout configuration of an entire chip of an embodiment of a DDR SDRAM according to the present invention. FIG. It is a figure which shows the structure of MA control circuit of one Example of this invention. It is a figure which shows the structure of MA circuit of one Example of this invention. FIG. 6 is a timing diagram for explaining a read operation according to an embodiment of the present invention. FIG. 4 is a timing diagram for explaining a write operation according to an embodiment of the present invention. It is a figure which shows the structure of the data transfer circuit of the other Example of this invention. It is a figure which shows the structure of the GIO data holding circuit of FIG. It is a timing diagram for explaining a read operation of another embodiment of the present invention. It is a figure which shows the structure of the conventional 2N prefetch data transfer circuit. FIG. 10 is a timing diagram for explaining the operation of a conventional 2N prefetch / data transfer circuit.

  In order to describe the present invention in detail, the configuration principle of the present invention will be described with reference to the drawings, and then examples will be described.

FIG. 1 shows a prefetch data transfer circuit according to the present invention. The data transfer circuit of the present embodiment inputs first and second read clock signals (RCLK0, RCLK1) having different phases from each other by dividing a clock signal input to the semiconductor memory device by two, An amplifier circuit control circuit (110) for generating first and second control signals (MAE0, MOE0) having different phases, and read data from the memory cell array corresponding to the four addresses are respectively sent from the main input / output line (MIO). First to first input a first control signal (MAE0), and amplify and output read data corresponding to the four addresses in response to the first control signal (MAE0). fourth and amplifying circuit (main amplifier ₁₀₁ 1 to 101 _4), the first to fourth amplifying unit output circuit ₍₁₀₄ 1 to 104 _4), four address The first and second output data from the two amplifier circuits respectively corresponding to the two even addresses are input, and the output destination is switched to which of the two outputs according to the read start address. Third and fourth output data from the first selection circuit (102 ₁ ) and two amplification circuits respectively corresponding to two odd addresses of the four addresses are input, and according to the read start address And a second selection circuit (102 ₂ ) that switches an output destination to which of the two outputs is output.

The first output terminal of the first selection circuit (102 ₁ ) and the first output terminal of the second selection circuit (102 ₂ ) are the first and third amplifier output circuits (101 ₁ , 101 ₃ ). Is connected to the input terminal. In response to the output data output from the second output of the _first selection circuit (102 ₁ ), and in response to the second control signal (MOE0), the latch output is output to the second amplifier output circuit (104). ₂ ) receives the output data output from the second output of the first latch circuit (103 ₁ ) and the second selection circuit (102 ₂ ) supplied to the input terminal of the second control signal (MOE0) In response to the second latch circuit (103 ₂ ) for supplying the latch output to the input terminal of the fourth amplifier output circuit (104 ₄ ), and the first and third amplifier output circuits (104 _1). 104 ₃ ), input the output data transmitted to the first and third signal transmission paths, respectively, and switch the output destination of the input output data to the first and second output terminals in the order of reading. 3 selection circuits (105 ₁ ), second and fourth Output data transmitted from the amplifier output circuit (104 ₂ , 104 ₄ ) to the second and fourth signal transmission paths is input, and the output destinations of the input output data are first, second in order of reading. The output data from the first and second output terminals of the fourth selection circuit (105 ₂ ) and the third selection circuit (105 ₁ ) to be switched to the output terminals of the first and second output terminals are input and output in parallel. First-in first-out first output registers (106 _{1 to} 106 ₃ , 106 _{4 to} 106 ₆ ) and output data from the first and second output terminals of the fourth selection circuit (105 ₂ ) are input in parallel. 2 series first-in first-out type second output registers (107 _{1 to} 107 ₄ , 107 _{5 to} 107 ₈ ), two series of outputs of the first output register, and 2 of the second output register Total of 4 series output A fifth selection circuit (108) for inputting an output and outputting it as a serial data signal corresponding to a read address in synchronization with the rising and falling edges of the input clock signal, and a fifth selection circuit ( 108) and an output buffer (109) for driving and outputting data to the data pad (terminal DQ).

For a configuration in which 32-bit data is transferred from a main amplifier circuit (101 _{1 to} 101 ₄ ) to a FIFO (First In First Out) using an F-GIO (global input / output) line and an S-GIO line, As shown in FIG. 1, according to the present invention, a control signal (MAE0) for controlling the data output circuit to the F-GIO line and a control signal (MOE0) for controlling the data output circuit to the S-GIO line are provided. Two types of control signals are provided.

  The main amplifier control circuit (110) receives two read clock signals (RCLK0, RCLK1) having different phases and outputs first and second output control signals (MAE0, MOE0). The rising edge of the first output control signal (MAE0) is generated from the rising edge of the first read clock signal (RCLK0), and the falling edge of the first output control signal (MAE0) is the second read clock signal (RCLK1). ) Made from the rise. Since the two read clock signals (RCLK0, RCLK1) are generated from different edges of the external clock signal (CK), the period of the first output control signal (MAE0) is a length corresponding to a plurality of clock cycle periods. On the other hand, the rise of the second output control signal (MOE0) is similarly generated from the rise of the first read clock signal (RCLK0), but is controlled at a timing different from that of the first output control signal (MAE0). (Delayed). The falling edge of the second output control signal (MOE0) is also generated from the rising edge of the second read clock signal (RCLK1), and the cycle of the second output control signal (MOE0) has a length corresponding to a plurality of clock cycle periods. Become.

  With this configuration, according to the embodiment of the present invention, data can be held on the data bus for a plurality of clock cycle periods, the number of stages of the latch circuit for latency in the FIFO portion is reduced, and the data transfer time is increased. be able to.

  In order to explain the present invention in more detail, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 2 shows an overall block diagram of an embodiment of a DDR SDRAM (Double Data Rate synchronous DRAM) according to the present invention. Referring to FIG. 2, the control input signals are a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and a chip selection signal / CS. Here, / corresponds to an overbar of a logical symbol where the low level represents the active level. The X address signal and the Y address signal are input in time series from the common address terminal Add in synchronization with the clock signals CK and / CK. The control input signals / RAS, / CAS, / WE, / CS are input to the input circuit 207 and supplied to the command decoder 208. The command decoder 208 decodes a read / write command or the like based on the input signal. Then, the control circuit 216 and 217 for the read system and the write system are controlled and a control signal is output to the X system control circuit and the Y system control circuits 213 and 211.

  The X address signal and the Y address signal input through the address buffer 209 are taken into the latch circuit 210, respectively. The X address signal taken into the latch circuit 210 is supplied by a predecoder (X system control circuit) 213, and its output signal is supplied to the X decoder 202 to form a selection signal for the word line WL. By the word line selection operation, a minute read signal appears on the complementary bit line BL of the memory array 201, and the amplification operation is performed by the sense amplifier 203. The Y address signal fetched by the latch circuit 210 is supplied to a predecoder (Y system control circuit) 211, and its output signal is supplied to a Y decoder 204 to form a selection signal for the bit line BL. The X relief circuit 215 and the Y relief circuit 212 compare the storage operation of the defective address with the stored defective address and the fetched address signal, and if they match, select the spare word line or bit line and select the spare word line or bit line. While instructing the Y decoder 204, the selection operation of the normal word line or the normal bit line is prohibited.

  The storage information amplified by the sense amplifier 203 is selected by a column switch circuit (not shown) and connected to the common input / output line MIO and transmitted to the main amplifier 225. The main amplifier 225 is not particularly limited, but a write circuit write amplifier 222 is also provided. That is, during the read operation, the read signal read through the Y switch circuit is amplified and output from the external terminal DQ through the output buffer (output circuit) 227. In the write operation, the write signal input from the external terminal DQ is taken in via the input buffer (input circuit) 224 and transmitted to the common input / output line and the selected bit line via the write circuit, and the selected bit line is sensed. The write signal is transmitted by the amplification operation of the amplifier 203, and the charge corresponding to the write signal is held in the capacitor of the memory cell.

  The timing generation circuit 206 selects a memory cell such as an address signal fetch control timing signal input corresponding to the clock signals CK, / CK and the signals / RAS and / CAS, an operation timing signal of the sense amplifier, and the like. Various timing signals necessary for operation are generated.

  The internal power generation circuit 218 receives the operating voltage of the high-side power supply voltage VCC and the low-side power supply voltage VSS supplied from the power supply terminal, and receives a plate voltage, a precharge voltage such as VCC / 2, an internal boost voltage VPP, and an internal voltage drop. Various internal voltages such as a voltage VDL and a substrate back bias voltage VBB are generated.

  The refresh counter 214 generates a refresh address signal when the refresh mode is set, and is used for an X-system selection operation.

  A read transfer circuit including the MIO, main amplifier unit 225, GIO line, FIFO 226, and output circuit (output buffer) 227 in FIG. 2 corresponds to the data transfer circuit shown in FIG. The read system control circuit 216 generates a signal for controlling the main amplifier unit 225, and has a function corresponding to the main amplifier control circuit 110 in FIG. Furthermore, the input circuit (input buffer) 224, the FIFO 223, the GIO line, the write amplifier 222, and the MIO line constitute a write data transfer circuit. DQS is an I / O terminal for the data strobe signal.

  FIG. 3 shows the layout of the entire chip of an embodiment of the DDR SDRAM according to the present invention. Referring to FIG. 3, in the SDRAM of this embodiment, the chip is divided into eight as a whole so as to form a plurality of memory blocks or banks. Each block divided into eight has the same configuration. An X decoder XDC is provided along one end of the memory array, and a Y decoder YDC and a main amplifier MA are arranged near the center of the chip in a direction orthogonal thereto. The eight memory blocks are arranged symmetrically in the vertical direction in the drawing so that two are made into one set and the X decoder XDC is adjacent to each other, thereby forming one memory bank as described above. The two memory banks each consisting of two sets of memory blocks are also symmetrically arranged in the figure. The Y decoder YDC and the main amplifier MA are arranged symmetrically so as to be adjacent to each other around a peripheral circuit provided at the horizontal center of the chip.

  The memory array portion of one memory block includes an array divided into a plurality of word lines extending in the horizontal direction from the X decoder XDC in the same figure, and a plurality of sub word lines provided in each array. A hierarchical word line system is adopted in which the main word line is arranged so as to penetrate through the sub word line and the sub word line selection line. Thereby, the number of memory cells connected to the sub word line is reduced, and the sub word line selection operation is speeded up.

  The memory block has an array divided into a plurality along the Y selection line extending from the Y decoder YDC, and the bit line is divided for each array. As a result, the number of memory cells connected to the bit line is reduced, and a signal voltage read from the memory cell to the bit line is ensured. The memory cell is composed of a dynamic memory cell, and corresponds to information 1 and 0 indicating whether or not the storage capacitor has a charge. By the charge coupling between the charge of the storage capacitor and the precharge charge of the bit line. Since a read operation is performed, a necessary signal amount can be ensured by reducing the number of memory cells connected to the bit line.

  Sub-word driver columns are arranged on the left and right sides of the divided array, and sense amplifier columns are arranged above and below the array (in the bit line direction). The sense amplifier column is provided with a column selection circuit, a bit line precharge circuit, and the like, and a minute potential difference that appears on each bit line by reading data from a memory cell by selecting a word line (sub word line) is detected by the sense amplifier. Detect and amplify.

  A main input / output line MIO, which will be described later, is not particularly limited, but extends in the vertical direction in FIG. A local input / output line LIO is arranged along the sense amplifier row, and the local input / output line LIO and the main input / output line MIO are connected by a row selection signal. In the peripheral circuit, the global input / output line GIO is arranged and connected to the main input / output line MIO corresponding to the selected memory bank. The global input / output line MIO is connected to a pad DQPAD connected to an external terminal through the output buffer and the input buffer through an input / output FIFO.

  Although not shown, peripheral circuits as will be described next are appropriately provided in the center of the chip. The address signal supplied from the address input terminal is taken into the row address buffer circuit and the column address buffer in the address multiplex format. Each address buffer holds the supplied address signal. For example, the row address buffer and the column address buffer each hold an address signal captured over one memory cycle period. At the center of the chip, a relief circuit made up of a fuse and a MOSFET for address comparison is also provided.

  In the refresh operation mode, the row address buffer takes in the refresh address signal output from the refresh control circuit as a row address signal. In this embodiment, the refresh address signal is fetched as a row address signal through a clock generation circuit, although not particularly limited. The address signal taken into the column address buffer is supplied as preset data to a column address counter included in the control circuit. The column address counter outputs a column address signal as preset data or a value obtained by sequentially incrementing the column address signal to the Y decoder YDC in accordance with an operation mode specified by a command described later.

  The control circuit is not particularly limited, but external control signals such as a clock signal, a clock enable signal, a chip select signal, a column address strobe signal, a row address strobe signal, a write enable signal, a data input / output mask control signal, and a memory bank Corresponding address signals are supplied, and various control signals such as an operation mode of the DDR SDRAM and various timing signals corresponding thereto are formed on the basis of the level change and timing of these signals, A mode register is provided.

In the DDR SDRAM of this embodiment, in the two memory arrays of one memory bank, the main input / output line MIO includes:
Depending on the Y0 and Y1 addresses,
0 address (Y0 = 0, Y1 = 0),
1 address (Y0 = 1, Y1 = 0),
2 addresses (Y0 = 0, Y1 = 1),
3 addresses (Y0 = 1, Y1 = 1),
(Refer to the correspondence between the main input / output line MIO and the main amplifier in FIG. 1), in the read operation, 8 bits from each memory array corresponding to the column address signal, 32 bits in total. 4N (where N is 8: N = number of I / Os per one address) prefetch operation is performed to select and output 32-bit data using the global input / output line GIO.

  In the output circuit, 8 bits of “0 address” are synchronized with the rising edge of the first clock signal CK, and 8 bits of “1 address” are synchronized with the falling edge of the first clock signal. In synchronization with the next rising edge of the clock, 8 bits of “2 addresses” are synchronized with the falling edge of the second clock, and the remaining 8 bits of data of “3 addresses” are transferred. Output.

  Although not particularly limited, the present invention is directed to a DDR SDRAM having a large storage capacity such as about 256 Mbits. The chip is divided into eight memory blocks, and two blocks form one bank. One memory block is divided into an 8 × 16 array (submat), and one submat is 512 × 512 bits. That is, 512 memory cells are connected to one sub-word line, and 512 memory cells are connected to the bit line. In the following description, the main input / output line MIO is abbreviated as “MIO line” using the circuit symbol MIO, and the global input / output line GIO is abbreviated as “GIO line” using the circuit symbol GIO.

  In this embodiment, a main amplifier circuit, a main amplifier output circuit, a GIO line, and an output register circuit are allocated for 0/1/2/3 addresses, respectively. As described above, data transfer from the main amplifier to the output register is performed simultaneously with 0/1/2/3 addresses. That is, the 32-bit data read to the MIO line is simultaneously sensed by the main amplifier circuit and transferred in parallel to the output register. In response to the start addresses Y0 and Y1, the data in the output register is output in synchronization with the rising and falling edges of the clock. Therefore, in this embodiment, 32 main amplifier circuits and GIO lines operate simultaneously.

FIG. 1 shows the configuration of an embodiment of a read system circuit of a DDR SDRAM according to the present invention. Referring to FIG. 1, this embodiment is directed to the 4N prefetch operation as described above. That is, in accordance with the read address, 32-bit data read from the memory cell array to the MIO line is simultaneously sensed by the main amplifier circuits (MA circuits) 101 _{1 to} 101 ₄ , and in parallel through the GIO line. In order to reduce the peak current when transferring to the output register, the data transferred by the GIO line is divided into the first 16 (2N) bit output data (F-GIO) and the second 16 (2N) bit output data (S- GIO) and output at different timings.

  Further, in this embodiment, in order to reduce the number of circuit stages of the access path (the number of latch circuits of the output register), data is held for a plurality of clock periods on the F-GIO and S-GIO lines. This is one of the features of the present invention. As the configuration, for the address 0 data, the address 1 data, the address 2 data, and the address 3 data, the main amplifier, its amplifier output circuit, the GIO line, and the output register correspond to the input / output terminals DQ0 to DQ7. 8 pieces are provided. The amplifier output circuit is provided with an MA (main amplifier) control circuit 110 that generates output control signals MAE0 and MOE0 for adjusting the output timing.

Corresponding to the start address information, the 16 (2N) bit data to be output first is directly transmitted to the output register (FIFO) through the F-GIO line, and the 16 (2N) bit data to be output later is The latch circuits 103 ₁ and 103 ₂ are latched and delayed by the output control signal MOE0 from the MA control circuit 110, and are transmitted to the output register (FIFO) through the S-GIO line.

  Further, the first and second read clock signals RCLK0 and RCLK1 forming the basic clock input to the MA control circuit 110 are generated from the rising edge of the clock pulse following the external clock signal CK. The read clock signals RCLK0 and RCLK1 have a cycle that is twice the clock cycle of the external clock signal CK.

In the MA control circuit 110, the rise of the output control signal MAE0 of the F-GIO line is generated from the first read clock signal RCLK0, and the fall is generated from RCLK1. That is, the data output period of the F-GIO line is from the read clock signal RCLK0 to RCLK1. For this reason, the pipeline stage 0 (Stage_0) of the data transfer is set up to the MA circuit, and the stage 1 is set to the MA circuit output unit (104 ₁ , 104 ₃ ) to the first stage of the FIFO (106 ₁ , 106 ₄ ). Is possible. Similarly, the data output period of the S-GIO line is from RCLK0 to RCLK1. Therefore, the stage 1 (Stage_1) can be the MA circuit output units (104 ₂ , 104 ₄ ) to the first FIFO stage (107 ₁ , 107 ₅ ).

The configuration of the output register is for the F-GIO line and has three stages of latch circuits (106 _{1 to} 106 ₃ ; 106 _{4 to} 106 ₆ ), and for the S-GIO line, four stages of latch circuits (107 _{1 to} 107 ₄ ; 107 _{5 to} 107 ₈ ).

This is the case of the read latency “4”, but similarly, when the read latency is “5” or “3”, the stage 1 (Stage_1) can be the MA circuit output part to the first FIFO stage. It is. Incidentally, for example, the clock signal CK1 is input to the latch circuit ₁₀₆ 1 to 106 ₃ of three stages of the output register, CK25, CK35 corresponds to latency 1,2.5,3.5, respectively, one shot eyes the CK1 The rising timing of the clock pulse corresponds to the falling timing of the second clock pulse. Selection circuit (multiplexer) 108, at the rising edge of the clock signal CK4, selects and outputs the output of the latch circuit 106 _3, at the falling edge of the clock signal CK4, selects and outputs the output of the latch circuit 106 _6, following in the rise of the clock signal CK4 cycle, selects and outputs the output of the latch circuit 107 _4, at the fall of the subsequent clock signal CK4, selects and outputs the output of the latch circuit 107 _8.

  In this embodiment, in the 4N prefetch DDR SDRAM as described above, the number of GIO lines that are charged and discharged simultaneously can be reduced from 32 to 16.

  Further, according to this embodiment, the number of output registers for the F-GIO line can be reduced from four (see FIG. 11) to three.

  Here, since the latter half 16 (2N) bit output data has a time margin for one clock cycle, the performance of the data output operation does not deteriorate even if the transfer timing on the S-GIO line is delayed.

  Furthermore, in 4N prefetch, the read command (READ) is input only once every two clocks. Therefore, even if data is held for one clock period on the GIO line, the data read time of the next read command is affected. do not do.

  FIG. 4 shows a circuit configuration of an embodiment of a main amplifier (MA) control circuit 110 used in the DDR SDRAM according to the present invention. Referring to FIG. 4, the main amplifier (MA) control circuit 110 generates a one-shot pulse (low level) based on a signal obtained by inverting RCLK0 by the inverter 401 (delay circuit 404, inverter 405, NAND circuit 406). The SR flip-flops (407, 408) are set based on the rising edge of the first read clock signal RCLK0, the outputs of the SR flip-flops (407, 408) are set to the high level, and the inverter 411 and the inverter (inverting driver) ) The output control signal MAE0 rises to a high level via 413.

  The circuits (delay circuit 409, inverter 410, NAND circuit 417A) that generate a one-shot pulse from the rising edge of the second read clock signal RCLK1 are SR flip-flops (407, 408) based on the rising edge of the second read clock signal RCLK1. ) To reset the output to low level and the output control signal MAE0 to low level. A circuit (delay circuit 415, inverter 416, NAND circuit 417B) that generates a one-shot pulse (low level) based on a signal obtained by delaying the signal obtained by inverting the first read clock signal RCLK0 by the inverter 401 by the delay circuit 414, The SR flip-flop (418, 419) is set based on the rising edge of the first read clock signal RCLK0, the output of the SR flip-flop (418, 419) is set to the high level, the inverter 424, and the inverter (inverting driver) The output control signal MOE0 rises through 425. MIOEQ0 output from the inverter 402, MAPG0 output from the inverter 403, and MAEQ0 output from the NAND circuit 412 are control signals for controlling the operation of the main amplifier (MA) 101 described later.

  FIG. 5 shows a configuration of an embodiment of a main amplifier circuit suitable for use in the present invention. Referring to FIG. 5, in this embodiment, a control circuit for F-GIO line output control signal MAE0 and S-GIO line output control signal MOE0 corresponding to 4N prefetch is exemplarily shown as a representative. As shown in FIG. 4, the MIO precharge control signal MIOEQ0 and the MA control signals MAPG0 and MAEQ0 are also generated at the same time. These control signals are generated by the circuit shown in FIG.

  Referring to FIG. 5, in main amplifier circuit 101, signals of a pair of main input / output lines MIOT and MIOB are taken in through P-channel type MOSFETs Q1 and Q2 which are turned on by the low level of MA control signal MAPG0. The captured signals are the P-channel MOSFETs Q3 and Q4 whose gates and drains are cross-connected, the N-channel MOSFETs Q5 and Q6, and the commonly connected sources of the N-channel MOSFETs Q5 and Q6 and the circuit ground. Amplified by a CMOS latch circuit comprising an N-channel type MOSFET Q7 provided between the potential and serving as a current source.

  That is, when the timing signal MAPG0 is low level and the input signal is taken in and a desired signal amount is secured, the timing signal MAPG0 becomes high level, and the main input / output lines MIOT and MIOB and the CMOS latch circuit The input / output terminal is separated, and the CMOS latch circuit starts an amplifying operation in response to the high level of the timing signal MAE0. At this time, since the MIO line having a large parasitic capacitance is separated from the input / output terminal of the CMOS latch circuit, the CMOS latch circuit amplifies the signal transmitted through the MIO line to the CMOS level at high speed. It is transferred to the amplifier output circuit. The MOSFETs Q12, Q13, and Q14 are circuits that precharge and equalize MIO line pairs (MIOB, MIOT) based on the signal MIOEQ0. The MOSFETs Q15, Q16, and Q17 precharge and equalize the signal line pair on the main amplifier output circuit side.

The output of the main amplifier MA00 (e.g. corresponding to 101 ₁ of FIG. 1) (the output of inverter 501 and 502) is, Y0, Y1 CMOS pass gate circuit controlled by the address (provided in parallel two CMOS transfer gates 503, Through the two tri-state inverters 504 provided in parallel (which constitutes the MUX 102 in FIG. 1), the output signal of the main amplifier circuit is an output circuit (for example, an N-channel output MOSFET Q9 and an N-channel output MOSFET Q9). transmitted to the corresponding) to 104 ₁ of FIG. 1, it transmits the output signal taken to the main amplifier circuit to F-GIO line.

  At this time, the output circuit (Q8, Q9) of the F-GIO line continues to output the data of the main amplifier while the output control signal MAE0 is at the high level.

  Accordingly, since the output control signal MAE0 is at a high level during the rise of the second read clock signal RCLK1 from the rise of the first read clock signal RCLK0 that forms the basic clock, the output circuit of the F-GIO line is 1 The clock period is activated.

  On the other hand, the output circuit (Q10, Q11) of the S-GIO line continues to output the data of the main amplifier while the output control signal MOE0 is at the high level. Here, the output control signal MOE0 delays the rising edge of the first read clock signal RCLK0, which is the basic clock, by a delay circuit (414 in FIG. 4) for a predetermined time, and then the rising edge of the second read clock signal RCLK1. Since the delay circuit (420 in FIG. 4) is high for a period delayed by a certain period, the output circuits (MOSFETs Q10 and Q11) of the S-GIO line are activated for one clock period.

  With the configuration of this embodiment, it is possible to hold data for a plurality of clock cycle periods regarding the clock signal CK for synchronization on the F-GIO and S-GIO lines. When the output of the main amplifier MA01 is the first output and the output of the main amplifier MA00 is the rear output based on the read start address, the output of the main amplifier MA00 is a CMOS pass gate circuit controlled in parallel by the Y0 and Y1 addresses (in parallel). The two CMOS transfer gates 507 provided and two tri-state inverters 508 provided in parallel are switched to the SR latch circuit (510, 511) side, and the output circuit (Q10, Q11) of the S-GIO line On the other hand, the output of the main amplifier MA01 is transmitted to the output circuit (Q8, Q9) of the F-GIO line via the CMOS pass gate circuit (503, 504). The output of the SR latch circuit (510, 511) is transmitted to the gate of the PMOSFET Q10 via the NAND circuit 512 and to the gate of the NMOSFET Q11 via the NOR circuit 513 when the output control signal MOE0 is at the high level. Is done. When the output control signal MOE0 is at a low level, the output circuits (Q10, Q11) of the S-GIO line are turned off (the output is in a high impedance state).

  The operation of the present embodiment will be described below with reference to the timing chart of FIG.

  The read command (READ) is input in synchronization with the rising edge of the external clock signal CK. Here, in the 4N prefetch memory, the interval between the read command and the next read command is defined in the specification as 2 clocks or more. This is because the internal read operation of the chip is performed over a period of two clocks. By using this technique, the operation frequency of the 4N prefetch memory can be improved by about twice that of the 2N prefetch memory.

  Therefore, when a read command is input at the rising edge “0” of the external clock signal CK, the next read command is input after the rising edge “2” of the external clock signal CK.

  Here, the first read clock signal RCLK0 is generated from the rising “0” of the external clock signal CK and the rising “2” of the external clock signal CK. On the other hand, the second read clock signal RCLK1 is generated from the rising “1” of the external clock signal CK and the rising “3” of the external clock signal CK.

  In the present embodiment, the control circuit 110 generates output control signals MAE0 and MOE0 that are input to the main amplifier 101 using the first and second read clock signals RCLK0 and RCLK1.

On the other hand, first-stage latch circuit ₁₀₆ 1, 106 ₄ of the latch signal CK1 of the output register and, first-stage latch circuit ₁₀₇ 1, 107 ₅ of the latch signal CK1D is generated from the rising "1" of the clock signal CK. This is because data can be held on the F-GIO and S-GIO lines for one clock period. Note that the clock cycle of the latch signals CK1 and CK1D of the output register is twice the clock cycle of the external clock CK.

  The write operation of this embodiment is performed according to the timing operation shown in FIG.

  That is, as shown in FIG. 7, the S-GIO line is used for transferring the first half of the 2-bit data from the DQ pad to the main amplifier (MA), and the F-GIO line is used for the second half of the 2-bit data transfer. Used. At this time, the output control signal (S-GIO output in FIG. 7) of the S-GIO line becomes high level at the rising edge “3” of the external clock signal CK, and becomes low level at the rising edge “4” of the external clock signal CK. The output circuit of the S-GIO line operates during the period “3” to “4” of the rising edge of the external clock signal CK. On the other hand, the output control signal (F-GIO output in FIG. 7) of the F-GIO line becomes a high level at the rising edge “4” of the external clock signal CK and becomes a low level at one shot (the pulse width of the clock signal CK).

  According to this embodiment having such a configuration, the data of the S-GIO line can be held on the S-GIO line for one clock period. For this reason, the main amplifier unit for writing (the write amplifier unit of FIG. It is unnecessary to provide a circuit for latching data on the S-GIO line.

  The effects obtained from the above-described embodiments are as follows.

  (1) At the time of reading, by holding data on the F-GIO line and S-GIO line for one clock period, the pipeline stage 0 of the 4N prefetch memory is made up to the main amplifier (MA) circuit, and the pipeline The stage 1 can be the first stage of the FIFO from the main amplifier (MA) output unit, and the effect that the number of latch circuit stages of the output register can be reduced and high-speed operation can be realized is obtained.

  (2) In addition to the above, by reducing the number of latch circuits of the output register, it is possible to simplify the control of the output circuit and to realize area saving.

  (3) In addition to the above (1) and (2), an effect that low current consumption can be realized by reducing the number of latch circuits of the output register can be obtained.

  (4) At the time of writing, by holding data for one clock period on the S-GIO line, the data latch circuit of the S-GIO line in the main amplifier portion is eliminated, and the effect of reducing area and current consumption can be obtained.

Next, a second embodiment of the present invention will be described. The basic configuration of the second embodiment of the present invention is the same as that of the above-described embodiment, but further contrivance is provided for data retention on the GIO line. FIG. 8 is a diagram showing the configuration of the second exemplary embodiment of the present invention. In FIG. 8, the same elements as those in FIG. 1 are denoted by the same reference numerals. Referring to FIG. 8, the second embodiment of the present invention includes a data holding circuit 111 for the GIO line in the output register portion. That is, a data holding circuit 111 for latching the output of the selection circuit 105 _1, output of the data holding circuit 111 is connected to the F-GIO line via the output buffer 112. The data holding circuit 111 holds GIO line data while the data holding circuit control signal GIOL is at a high level.

  FIG. 9 is a diagram illustrating an example of the configuration of the GIO data holding circuit 111 of the present embodiment. Referring to FIG. 9, tri-state inverters 901 and 902 whose outputs are connected in common constitute a selector, and output (DinBuff) of a buffer (corresponding to 221 in FIG. 2) for inputting data at the time of writing, F -GIO is input, F-GIO is selected at the time of reading, and DinBuff is output at the time of writing. The outputs of the selectors (901, 902) are input to a tri-state inverter 903, and the output of the tri-state inverter 903 is input to a flip-flop composed of an inverter 905 and a tri-state inverter 904 whose inputs and outputs are connected to each other. Connected. The tri-state inverters 903 and 904 and the inverter 905 constitute a latch circuit. The output of the latch circuit is input to one input terminal of each of the NAND circuit 909 and the NOR circuit 910. The outputs of the NAND circuit 909 and the NOR circuit 910 are connected to the power sources VDD and VSS, respectively, and the drains are common. The signals are input to the gates of the PMOSFET 911 and the NMOSFET 912 that are connected to the F-GIO. The other input terminal of the NAND circuit 909 is connected to the output of the inverter 907 that inputs and outputs the output of the NOR circuit 906, and the other input terminal of the NOR circuit 910 is connected to the output of the inverter 908. The operation of the circuit shown in FIG. 9 is outlined. During the period when the data holding circuit control signal GIOL is high level, the output of the NOR circuit 906 is low level, the output of the inverter 907 is high level, and the NAND circuit 909 is tristate. The inverted signal of the output of the inverter 903 is transmitted to the gate of the PMOSFET 911, the output of the inverter 908 is set to the low level, and the NOR circuit 910 transmits the inverted signal of the output of the inverter 903 to the gate of the NMOSFET 912. On the other hand, while the data holding circuit control signal GIOL is at the low level, the output of the NOR circuit 906 is at the high level, the outputs of the inverters 907 and 908 are at the low level and the high level, the output of the NAND circuit 909 is at the high level, and the NOR circuit 910 Is set to a low level, the MOSFETs 911 and 912 are both turned off, and the output is set to a high impedance state.

  In the configuration shown in FIG. 9, a write F-GIO output circuit is used to hold data when reading F-GIO. That is, by using the data output circuit to the F-GIO line at the time of writing as the F-GIO line data holding circuit at the time of reading, the area penalty is eliminated and the load (diffusion layer capacitance) of the F-GIO line is reduced. It is possible to prevent the increase and eliminate the speed penalty.

  In order to reduce the area, the GIO line is generally used as a read / write common line, and the data holding circuit can be realized with a small area.

  FIG. 10 is a diagram showing an example of the timing of the read operation of the second embodiment of the present invention using the data holding circuit. As shown in FIG. 10, the output signal MAE0 of F-GIO is generated in one shot from the rising “0” of the external clock signal CK. Therefore, the F-GIO line output period of the main amplifier is one shot, but the data holding circuit control signal GIOL in the output register portion becomes high level during the period from the rising “0” to the rising “1” of the external clock signal CK. 1-clock period data is held.

  Therefore, also in this embodiment, as shown in FIG. 8, pipeline stage 0 (Stage_0) of 4N prefetch data transfer is set up to MA, and pipeline stage 1 (Stage_1) is changed from MA output part to FIFO 1 stage. It can be an eye. Further, it is possible to reduce the number of latch circuits of the output register and to realize a high speed operation.

  In addition, according to the present embodiment, the data holding circuit 111 is shared with the F-GIO output circuit for writing, and an effect that the area increase can be realized with almost zero is obtained.

  The present invention has been described with reference to the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the principle of the present invention. Of course, it includes deformation and correction.

100 MIO
101 MA (main amplifier)
102 Selector (Multiplexer)
103 Latch 104 MA Output Circuit 105 Selector (Multiplexer)
106 Latch 107 Latch 108, 108A Selector (Multiplexer)
109 Output Circuit 110 MA Control Circuit 111 Data Holding Circuit 112 Output Buffer Circuit 201 Memory Cell Array 202 X Decoder 203 Sense Amplifier 204 Y Decoder 205 Input Circuit 206 Timing Generation Circuit 207 Input Circuit 208 Command Decoder 209 Input Circuit 210 Latch Circuit 211 Y System Control Circuit 212 relief circuit 213 X system control circuit 214 refresh counter 215 relief circuit 216 read system control circuit 217 write system control circuit 218 internal voltage generation circuit 219 input circuit 220 data storage circuit 221 output circuit 222 write amplifier 223 input register (FIFO)
224 Input circuit 225 Main amplifier (MA)
226 Output register (FIFO)
227 Output circuit 401, 402, 403, 405, 410, 411, 413, 416, 422, 424, 425 Inverter 406, 407, 408, 412, 417A, 417B, 418, 419, 423 NAND circuit 404, 409, 414, 415, 420, 421 Delay circuit 501, 502, 505, 506, 514 Inverter 503, 507 CMOS transfer gate 504, 508 Tristate inverter 510, 511, 513 NOR circuit 512 NAND circuit 901, 902 903, 904 Tristate inverter 905, 907, 908 Inverter 906, 910 NOR circuit 909 NAND circuit 911 PchMOSFET
912 Nch MOSFET

Claims (5)

Four amplifying circuit units each receiving four data signals;
4 and the signal transmitting path of the four said four data signals are amplified by the amplifier circuit portion of is transferred,
Four registers for receiving said four data signals transmitted through the four signal transmission path, respectively,
A control circuit for generating a first control signal for activating the four amplifier circuit units , and a second control signal for controlling timing for determining data input by the four registers;
With
The first control signal is generated from a first edge of an external clock signal and is maintained in an activated state for one clock cycle;
It said second control signal is generated from a second edge that is input after the first one clock cycle from the edge of the external clock signal,
Wherein 1 during clock cycle, the a time until four register circuits is determined the four data signals input, it semiconductor integrated circuit device according to claim. Four amplifying circuit units each receiving four data signals;
4 and the signal transmitting path of the four said four data signals are amplified by the amplifier circuit portion of is transferred,
A data holding circuit for holding the four in the signal transduction pathway the four output from the amplifier circuit unit is said four output to out destination of the data signals the two data signals, respectively,
A latch circuit that holds two data signals that are output later among the four data signals that are output from the four amplifier circuit units and outputs them to the corresponding two signal transmission paths;
Four registers for receiving said four data signals transmitted through the first signal transmission path of said four respectively,
It said first control signal for activating the four amplifier circuit and a second control signal for controlling the data holding circuit, the timing for determining the data to be input in succession by two the four registers a third, fourth control signals for controlling each of the control circuit for generating a fifth control signal for controlling the latch circuit,
With
The first control signal is generated from a first edge of an external clock signal;
It said second control signal, the external clock signal the first delayed than the first control signal based on the edge of being activated, the external clock signal the first input from one clock cycle after the edge of the Based on the second edge to be deactivated,
The third control signal is generated from the second edge of the external clock signal ;
The fourth control signal is generated later than the third control signal from the second edge of the external clock signal ;
The fifth control signal is generated later than the first control signal based on the first edge of the external clock signal, and is maintained in an activated state for one clock cycle.
During the one clock cycle, the a time until four register circuits is determined the four data input, that semiconductor integrated circuit device according to claim. Of the four data signals output from the four amplifier circuit units, two data signals to be transferred to the two signal transmission paths in parallel later in time are respectively held, and the two signal transmission paths are Each has a latch circuit to output,
Of the four data signals, two data signals transferred in parallel to the two signal transmission paths earlier in time are transferred from the two amplification circuit units of the four amplification circuit units to the two data signals. The remaining two data signals that are output to the signal transmission paths and transferred in parallel to the remaining two signal transmission paths after time are transferred from the remaining two amplification circuit units to the latch circuit. Through the remaining two signal transmission paths,
The second control signal determines two data signals transferred in parallel first to two signal transmission paths of the four signal transmission paths in two of the four registers. A third control signal for controlling the timing to be transmitted and the remaining two registers of the four registers are transferred in parallel to the remaining two signal transmission paths of the four signal transmission paths in time later A fourth control signal for controlling the timing of determining the two data signals generated,
The control circuit generates a fifth control signal for controlling the latch circuit;
The third control signal is generated from the second edge of the external clock signal, and has a cycle that is twice the clock cycle of the external clock signal.
The fourth control signal is generated later than the third control signal from the second edge of the external clock signal, and has a cycle twice the clock cycle of the external clock signal,
The fifth control signal is generated later than the first control signal from the first edge of the external clock signal, and is maintained in an activated state for one clock cycle. The semiconductor integrated circuit device according to claim 1. The four of the four data signal held respectively in the register on the basis of a clock signal for synchronization further comprising an output unit for outputting serially, that in any one of claims 1 to 3, wherein The semiconductor integrated circuit device described. It said four data signals, each was read from the memory cell array corresponding to the lower 2 bits of the column address, including data information of each 8-bit, any one of claims 1 to 4, characterized in that 2. A semiconductor integrated circuit device according to item 1.

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