JP5401715B2 - Delay circuit and delay circuit system - Google Patents

Description

  The present invention relates to a delay circuit and a delay circuit system in which a plurality of impedance circuits each having one end connected to the input signal path and the other connected to the ground are provided in the input signal path, and a fine delay can be generated. The present invention also relates to a delay circuit and a delay circuit system that are easy to design.

  In general, a delay circuit has a number of delay elements connected in series, and obtains a delay signal from a tap provided between the elements. The detection circuit integrates the input of the rectangular wave, and generates a delay signal when the capacitor voltage constituting the integration circuit reaches a set threshold value.

FIG. 11 shows the method. In FIG. 11, the delay circuit 8 is composed of a plurality of delay forming elements 81 (1) to 81 (N).
The line of the signal S0 on the input signal path,
A line on the output side (signal S1) of the delay forming element 81 (1),
A line on the output side (signal S2) of the delay forming element 81 (2),
...
A line on the output side (signal SN) of the delay forming element 81 (N),
(These are indicated by a line group 83)
(See Patent Document 1).

The selection circuit 82 can take out signals having different delay times (any one of the original signal S0, the delay signals S1, S2,..., SN) by selecting one of these line groups 83.
Japanese Patent Laid-Open No. 2-141029

  In the delay circuit of FIG. 11, in order to increase the resolution, for example, 1000 or more delay forming elements must be connected (that is, N is 10,000 or more). In this case, an accurate delay cannot be generated unless the distances between the delay forming elements 81 (1) to 81 (N) are equal. Further, even when the line lengths from the delay forming elements 81 (1) to 81 (N) to the selection circuit 82 are different, an accurate delay cannot be generated. Actually, it is not easy to make the distances between the delay forming elements 81 (1) to 81 (N) equal, and the line lengths from the delay forming elements 81 (1) to 81 (N) to the selection circuit 82 are set to be different. It cannot be equal.

For this reason, it is not easy to actually set the fine time fine (for example, to set a large number of delays at intervals of several nanoseconds).
Moreover, in the integrated circuit manufacturing process, as described above, 1000 or more delay forming elements 81 (1) to 81 (N) are selected from the delay forming elements with the same distance between the delay forming elements. Since there is a request to keep the line length to the circuit 82 constant, it is extremely difficult to design a pattern.

  An object of the present invention is to provide a delay circuit and a delay circuit system that can generate a delay with a fine resolution and that can be easily designed.

(1)
A delay circuit having an impedance circuit having one end connected to the input signal path of the detection circuit and the other end connected to the ground;
The impedance circuit includes a plurality of switches that change the overall impedance of the impedance circuit when an on control signal or an off control signal is input, respectively.
A delay circuit, wherein a delay time generated by the detection circuit is changed by changing an impedance of the impedance circuit according to a combination of an on state or an off state of the plurality of switches.

(2)
The delay circuit according to (2), wherein the impedance circuit includes at least impedance (resistance component, capacitance component, inductance component) of the plurality of switches and / or impedance caused by wiring.

(3)
The delay circuit according to (1) or (2), wherein the impedance circuit includes one or a combination of a resistance element, a capacitance element, and an inductance element.

(4)
The delay circuit according to any one of (2) to (3), wherein the switch is a gate switch (buffer with a control terminal).

(5)
The delay circuit according to any one of (1) to (4);
A delay control circuit for sending an on / off control signal to each of the switches;
A delay circuit system comprising:

(6)
A delay circuit having a plurality of impedance circuit elements having one end connected to the input signal path of the detection circuit and the other end connected to the ground;
Each impedance circuit element forms an open state between the input signal path and the ground when an ON control signal is input, and the input signal path and the ground when an OFF control signal is input. Each includes a switch that forms an impedance between
A delay circuit, wherein a delay time generated by the detection circuit is changed by changing an impedance of the impedance circuit according to a combination of an on state or an off state of each switch.

(7)
The delay circuit according to (6), wherein the impedance circuit element includes at least impedance (resistance component, capacitance component, inductance component) of the switch and / or impedance caused by wiring.

(8)
The delay circuit according to (6) or (7), wherein the impedance circuit element includes one or a combination of a resistance element, a capacitance element, and an inductance element.

(9)
A delay circuit having P impedance circuit elements each having an impedance of Z (1), Z (2), ..., Z (N),
The delay time Τ _k by each impedance circuit element (k = 1, 2,..., N) is unit delay time τ ₀ ,
Τ _k (Z (k)) = (P + 1) ^k−1 τ ₀
The delay circuit according to any one of (6) to (8), characterized in that:

(10)
The delay circuit according to any one of (6) to (9), wherein the switch is a gate switch (buffer with a control terminal).

(11)
The delay circuit according to any one of (6) to (10), wherein the impedance circuit element includes a buffer, and the buffer is provided closer to a ground side than the switch.

(12)
The delay circuit according to any one of (6) to (11), wherein the detection circuit includes a CR integration circuit including a capacitor element and a resistance element, and a capacitor element and a resistance element.

(13)
The delay circuit according to any one of (6) to (12);
A delay control circuit for sending an on / off control signal to each of the switches;
A delay circuit system comprising:
In an AC / DC converter, DC / DC converter, step-up chopper, step-down chopper, etc., the voltage and current of each part are detected by frequency conversion, and the output and input are controlled (output current, output voltage, output power, input current, When controlling output voltage, input power, etc.), the delay circuit system of the present invention is particularly effective.

According to the present invention, the delay time can be set with high accuracy.
Since the delay circuit of the present invention does not require a selection circuit (multiplexer) for selecting a signal that is appropriately delayed from among a large number (1000 or more) of delay signals, the line from each delay forming element to the selection circuit 82 is not necessary. There is no need to keep the length constant. In addition, a large number of delay circuit elements are not connected in series, and the design restriction is eased. In addition, the circuit can be simplified.

  In the present invention, it is easy to determine the delay time in consideration of the values of stray resistance, stray capacitance, and stray inductance such as circuit wiring (that is, circuit design is facilitated).

A three-state buffer having the same specification is suitable for the present invention because it can be easily manufactured in a semiconductor process and has little variation in input impedance.
One or a combination of a resistance element, a capacitance element, and an inductance element can be connected to these three-state buffers.

It is explanatory drawing which shows embodiment of the delay circuit and delay circuit system of this invention. It is a graph which shows the time change of the voltage which arises in a detection circuit. It is explanatory drawing which shows other embodiment of the delay circuit and delay circuit system of this invention. It is an embodiment showing a delay circuit for equalizing discrete intervals of delay time and a delay circuit system using the delay circuit. It is explanatory drawing of the delay circuit which replaced the impedance circuit element of FIG. 3 with the buffer, and a delay circuit system using the same. It is explanatory drawing of the delay circuit whose impedance circuit element is a three-state buffer, and a delay circuit system using the same. FIG. 5 is an explanatory diagram showing a wiring configuration of the delay circuit shown in FIG. 4. It is explanatory drawing which shows the example of an application of a delay circuit, and is a figure which shows the example which increases an input clock 4 times by three delay circuit units. It is explanatory drawing which shows embodiment which applied the delay circuit and delay circuit system of this invention to the power converter device. It is explanatory drawing which shows other embodiment which applied the delay circuit and delay circuit system of this invention to the power converter device. It is explanatory drawing of the conventional delay circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Delay circuit 11 Detection circuit 12 Impedance circuit 13 Control circuit 14 Input buffer 15 Input signal path SW _k switch Z (k) Impedance B _k buffer r Resistance TB _k Three state buffer

  FIG. 1 is an explanatory diagram showing an embodiment of a delay circuit and a delay circuit system according to the present invention. In FIG. 1, the delay circuit 1 includes a detection circuit 11, an impedance circuit 11, a control circuit 13, and an input buffer 14.

The impedance circuit 12 has one end connected to the input signal path 15 and the other end connected to the ground G. The impedance circuit 12 includes a plurality of switches (SW _{1 to} SW _M ) that change the overall impedance of the impedance circuit when an on control signal or an off control signal is input. In general, the impedance circuit 12 includes impedance elements (at least one of a resistance element, a capacitance element, and a reactance element, or a combination thereof) in addition to the switches SW _{1 to} SW _M. The total impedance of the impedance circuit 12, impedance of the switch SW ₁ to SW _M, but those including the impedance of the wiring can be formed impedance of the switch SW ₁ to SW _M, the delay to be described later only impedance of the wiring In some cases, the impedance circuit 12 may not have an impedance element.

  The detection circuit 11 only needs to have a configuration capable of detecting a threshold value. The detection circuit 11 compares the voltage at the end of the input signal path 15 with the threshold value, and the threshold voltage of the resistance element formed on the input signal path 15. Can be compared with the value. In addition, a voltage drop caused by a resistance component included in the input signal path 15 itself can be compared with a threshold value.

In FIG. 1, an input buffer 14 is connected to the starting end of the input signal path 15. When the output impedance of the input buffer 14 (indicated by Z ₀ in FIG. 1) cannot be ignored, the impedance value is set substantially in the impedance circuit 12 in consideration of Z ₀ . The power source included in the input buffer 14 is indicated by ge.

FIG. 2 is a graph showing a time change of the voltage V _D generated in the detection circuit 11. The detection circuit 11 outputs a delay signal SD when the voltage V _D reaches the threshold value V _SH .
A threshold value V _SH is appropriately set in the detection circuit 11. In FIG. 1, the threshold value V _SH is set by the control device 13. This control device 13 can be used, for example, as a control device for a power converter (see FIGS. 9 and 10 described later).

The control circuit 13 can change the impedance of the detection circuit 11 by a combination of the ON state or the OFF state of the switches SW _{1 to} S _M , so that the detection circuit 11 can generate a delay time (delay time) generated by the detection circuit 11. The time signal DS) can be varied. In Figure 1, there is shown a control signal of the switch SW ₁ to SW _M in S ₁ to S _M.

FIG. 3 is an explanatory diagram showing another embodiment of the delay circuit and the delay circuit system of the present invention.
In FIG. 3, the delay circuit 1 includes an impedance circuit 12, a detection circuit 11, a control circuit 13, and an input buffer 14. The impedance circuit 12 includes a plurality of impedance elements 12 (1) to 12 (N).
A detection circuit 11 is connected to the end of the input signal path 15, and a set S of impedance circuit elements 12 (k) (k = 1, 2, 3,..., N) is connected to the input signal path 15. Is connected. Each impedance circuit element 12 (k) has one end connected to the input signal path 15 and the other end connected to the ground G.

In the present embodiment, each impedance circuit element 12 (k) includes a switch SW (k). The switch SW (k) forms an open state between the input signal path 15 and the ground G when the _ON control signal S _ON is input, and the input signal when the OFF control signal S _OFF is input. An impedance Z (k) (or admittance Y (k) = 1 / Z (k)) is formed between the path 15 and the ground G.

  In FIG. 3, the switch SW (k) is a transistor, and the impedance Z (k) is the element resistance r (k), the element capacitance C (k), and the floating impedance Zf (floating resistance Rf, floating capacitance Cf, and floating), respectively. Inductance Lf).

In the present embodiment, the impedance when all the switches of the detection circuit 11 are ON is expressed as Z _allON by the combination of ON / OFF of the switch SW (k).
1 / Z _allON t = Σ (a (k) / (Z (k))
However, a (k) is a coefficient that is “0” when the switch is on and “1” when the switch is off. Σ is the total from 1 to N. In terms of admittance, the total admittance YZ _allON is represented by YZ _allON = Σa (k) Y (k).

FIG. 4 is an embodiment showing a delay circuit for equalizing discrete intervals of delay time and a delay circuit system using the delay circuit. In this embodiment, the delay circuit 1 includes one impedance circuit element having impedances Z (1), Z (2),..., Z (N) (when the number of circuit elements is P, P = N), the delay time Τ _k (k = 1, 2,..., N) due to the respective impedance circuit elements, where the unit delay time is τ ₀ ,
Τ ₁ (Z (1)) = τ ₀
Τ ₂ (Z (2)) = 2τ ₀
Τ ₃ (Z (3)) = 2 ² τ ₀
...
Τ _k (Z (k)) = 2 ^k−1 τ ₀
...
Τ _N (Z (N)) = 2 ^N-1 τ ₀
It is represented by
Thereby, the detection circuit 13 can make the intervals of the outputs (delay time) equal intervals (equalize the discrete intervals of the delay times).

FIG. 5 shows the impedance circuit element 12 (k) (k = 1, 2, 3,..., N) of FIG. 3 and the buffer B (k) (k = 1, 2, 3,..., N). It is explanatory drawing of the delay circuit 1 replaced by and the delay circuit system using the same. In FIG. 5, the input impedance Z (k) = 2 ⁰ r of the buffer B _k is the same as in FIG.

FIG. 6 is an explanatory diagram of a delay circuit 1 in which the impedance circuit element 12 (k) (k = 1, 2, 3,..., N) is a three-state buffer TB _k and a delay circuit system using the same. . In FIG. 6, the input terminal of the three-state buffer TB _k is connected to the input signal path 15, and the control signal S (on control signal or off control signal) is input to the control terminal of the three-state buffer TB _k . The three-state buffer TB _k has a high impedance output regardless of the input when the control signal S is OFF (S = 0), and when the control signal S is ON (S = 1). The input appears as it is in the output.

6, the resistance elements shown in impedance and 4 shown in FIG. 3 is not connected, it is possible to connect such impedance or resistance element in front of the three-state buffer TB _k.

FIG. 7 is an explanatory diagram showing a wiring configuration of the delay circuit 1 shown in FIG. In FIG. 7, the three-state buffers TB _k (k = 1, 2, 3,..., N) are arranged in the diameter direction of concentric circles. As a result, the wirings other than the control signal lines are equal in each impedance circuit element 12, and the circuit design is facilitated.

FIG. 8 is an explanatory diagram showing an application example of the delay circuit 1 described above. In FIG. 8, the input clock is increased four times by three delay circuit units UA, UB, and UC.
In the present embodiment, the impedance circuit element 12A of the unit UA, the impedance circuit element 12B of the unit UA, and the impedance circuit element 12C of the unit UA have the same configuration. Although the control circuit 13 is provided in the unit A, the control circuit 13 is not provided in the unit B and the unit C, and the impedance circuit element 12B and the impedance circuit element 12C are controlled by the control circuit 13 of the unit UA. Is done.
In the delay circuit 1 of FIG. 8, the control circuit 13 causes the unit UA, unit UB, and unit UC to generate a delay that is delayed by 1/4 of one cycle of the input signal S0. Operate.

FIG. 9 is an explanatory diagram showing an embodiment in which the delay circuit and the delay circuit system of the present invention are applied to the power conversion device 2. FIG. 9 uses the clock quadruple circuit of FIG. 8 as the control signal clock.
In FIG. 9, the power conversion device 2 includes a power converter 21 that inputs power from a DC power supply 31 and supplies power to a load 32, and a control device 22.
The control device 22 includes a control circuit 221, a frequency signal generation circuit 222, a reference clock generation circuit 223, a pulse synthesis circuit 224, and the delay circuit 1 in FIG. The control circuit 221 can convert a voltage corresponding to the output voltage eo from the frequency signal generation circuit 222 into a frequency signal, and perform PWM control by a known method.

  In the power conversion device 2 of FIG. 9, the reference pulse S0 generated by the reference clock generation circuit 223 is divided into three pulses SDA, SDB, Converted to SDC. These pulses are sent out by the pulse synthesis circuit 224 to the control circuit 221 and the frequency signal generation circuit (VF conversion circuit) 222. Therefore, the operation clocks of the control circuit 221 and the frequency signal generation circuit 222 can be four times the pulse generated by the reference clock generation circuit 223.

FIG. 10 is an explanatory diagram showing an embodiment in which the delay circuit and the delay circuit system of FIG.
In FIG. 10, the power conversion device 4 includes a power converter 41 that inputs power from a DC power supply 31 and supplies power to a load 32, and a control device 42.
The control device 42 includes a control circuit 421 and a frequency signal generation circuit 422, and the control device 42 includes a drive signal generation circuit 423 and a frequency detection circuit 424. The frequency detection circuit 424 includes a determination circuit 425 and the delay circuit 1 described with reference to FIGS. 1 and 3 to 7.
The frequency signal generation circuit 422 detects the output voltage e _O of the power converter 41 and a current (circuit current equivalent voltage V _i ) flowing through a reactor or a control switch (not shown), and uses the detected value as the first frequency signal F ₁ . Convert.

The frequency detection circuit 424 includes a delay circuit 1 and a determination circuit 425. The frequency signal generation circuit 423 detects the output voltage e _O and the circuit current equivalent voltage V _i as a voltage signal F ₁ and outputs it to the determination circuit 425. The delay control circuit 13 (the control circuit in FIGS. 1, 2 to 7) 13 of the delay circuit 1 sets a delay time Δτ in the impedance circuit 12, and the delay circuit 1 is delayed by Δτ with respect to the first voltage signal F ₁ . The second frequency signal F ₂ is output to the determination circuit 425. Judging circuit 425, a first frequency signal F ₁ and inputs the second frequency signal F _2, whether the period of the first frequency signal F ₁ is included in the second period of the frequency signal F _1, and / or Then, it detects whether or not the cycle of the second frequency signal F ₂ is included in the cycle of the first frequency signal F ₁ and outputs a determination signal. The drive signal generation circuit 423 generates a control signal V _Gs from the determination circuit signal and sends it to a switch (not shown) included in the power conversion circuit 21.

In FIG. 10, the control circuit detects the output voltage of the power converter 21 and the circuit current equivalent voltage V _i and generates a delay control signal.

Claims (5)

A delay circuit having an impedance circuit having one end connected to the input signal path of the detection circuit and the other end connected to the ground, wherein the impedance circuit receives the impedance when an ON control signal or an OFF control signal is input. Consists of buffers with multiple control terminals that change the overall impedance of the circuit,
A delay circuit, wherein a delay time generated by the detection circuit is changed by changing an impedance of the impedance circuit according to a combination of an ON state or an OFF state of the plurality of buffers with control terminals. A delay circuit according to claim 1;
A delay control circuit for sending an on / off control signal to each of the switches;
A delay circuit system comprising: A delay circuit having a plurality of impedance circuit elements having one end connected to the input signal path of the detection circuit and the other end connected to the ground;
Each impedance circuit element forms an open state between the input signal path and the ground when an on control signal is input, and the input signal path and the ground when an off control signal is input. It consists of a buffer with multiple control terminals that form impedance between
A delay circuit that changes a delay time generated by the detection circuit by changing an impedance of the impedance circuit according to a combination of an ON state or an OFF state of the plurality of buffers with control terminals in each impedance circuit element. . A delay circuit having P impedance circuit elements each having an impedance of Z (1), Z (2), ..., Z (N),
The delay time T _k due to each impedance circuit element (k = 1, 2,..., N) is unit delay time τ ₀ ,
T _k (Z (k)) = (P + 1) ^k−1 τ ₀
The delay circuit according to claim 6, represented by: A delay circuit according to claim 6 or 9,
A delay control circuit for sending an on / off control signal to each of the switches;
A delay circuit system comprising:

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