JP5397393B2 - Physical quantity sensor - Google Patents

Description

  The present invention relates to a physical quantity sensor.

  Conventionally, in a physical quantity sensor, the output of one acceleration sensor element is passed through each of a first filter and a second filter that pass signal components in different frequency bands, and the output of the first filter is sent to an airbag system. In some cases, the output of the second filter is output to an ABS control system (see, for example, Patent Document 1).

  The sensor device includes a detection element and a sensor circuit unit that processes an output signal of the detection element, and a request input from the outside in order to match the filter characteristics of the sensor circuit unit with the installation location and application of the sensor device itself There is one in which the filter characteristic of the sensor circuit unit is adjusted in accordance with a signal (see, for example, Patent Document 2).

  Further, there is a sensor system in which the power source of the sensor and the control microcomputer is intermittently turned on to reduce power consumption (see, for example, Patent Document 3).

JP-A-10-282136 JP 2009-63471 A JP 2009-184368 A

  The inventors examined a system for converting the output of the sensor element into a digital signal and performing a digital filter operation on the converted digital signal with reference to the above-mentioned three Patent Documents 1, 2, and 3. For example, in order to repeatedly perform a digital filter operation at short time intervals, it is necessary to perform a high-speed operation when performing the digital filter operation, which requires a great amount of power.

  In view of the above points, an object of the present invention is to reduce power consumption in a physical quantity sensor that performs a digital filter operation on the output of a sensor element.

  In order to achieve the above object, according to the first aspect of the present invention, when the determining means determines that the sampling value is less than the specified value, the calculating means repeatedly performs the filter operation with a long period, and the sampling value is the specified value. When the determination means determines that the above is true, the calculation means repeatedly performs the filter calculation in a short cycle.

  According to the first aspect of the present invention, when the determination unit determines that the sampling value is less than the specified value, the calculation unit repeatedly performs the filter calculation with a long cycle, so that the calculation amount of the calculation unit can be reduced. it can. For this reason, it is possible to reduce the power consumption required when the calculation means calculates. Therefore, power consumption can be reduced in a physical quantity sensor that performs digital filter operation on the output of the sensor element.

In the invention according to claim 2, when the falling period determining means determines that the current sampling timing is in the falling period, the calculating means repeatedly performs the filter calculation in a short cycle,
When the falling period determining unit determines that the current sampling timing has finished the falling period, the calculating unit repeatedly performs the filter calculation with a long cycle.

  For example, if the calculation means performs a filter operation with a long period when the current sampling timing is within the falling period, the change in the period greatly affects the filter characteristics in the filter operation and the calculation result fluctuates. .

  On the other hand, in the invention according to claim 2, when the timing of the current sampling is in the falling period, the calculation means performs the filter calculation with a short cycle. Will not be affected. For this reason, the calculation result equivalent to the past can be calculated | required as a calculation result in a descent | fall period.

  In the invention according to claim 3, when the rising period determining means determines that the current sampling timing is in the rising period, the calculating means calculates Yn by setting Yn-S to the same value as Yn-1. It is characterized by doing.

  For example, when the current sampling timing is within the rising period, when the calculation means performs the filter calculation, Yn-S greatly affects the filter characteristics in the filter calculation, and the calculation result fluctuates.

  On the other hand, in the invention according to claim 4, when the timing of the current sampling is in the rising period, Yn is calculated by setting Yn-S to the same value as Yn-1, so that Yn-S is It does not affect the filter characteristics in the filter operation. For this reason, the calculation result equivalent to the past can be calculated | required as a calculation result in a raise period.

In the invention according to claim 5, the rising period determining means (S310) determines that the determining means determines that the sampling value is less than the specified value before the determining means determines that the current sampling value is equal to or greater than the specified value. If it is determined that the sampling timing is within the rising period,
The rising period determination unit (S310) determines that the current sampling value is determined when the determination unit determines that the sampling value is equal to or greater than the specified value prior to the determination unit determining that the current sampling value is equal to or greater than the specified value. It is characterized by the fact that the timing of has finished the descent period.

  Furthermore, in the invention according to claim 6, when the determining means determines that the difference is less than the specified value, the calculating means repeatedly performs the filter operation with a long period, and the determining means determines that the difference is greater than or equal to the specified value. When the determination is made, the calculation means repeatedly performs the filter calculation with a short cycle.

  According to the sixth aspect of the present invention, when the determination unit determines that the difference between the current sampling value and the previous sampling value is less than the specified value, the calculation unit repeatedly performs the filter operation with a long period. The amount of calculation of the calculation means can be reduced. For this reason, it is possible to reduce the power consumption required when the calculation means calculates. Therefore, similarly to the first aspect of the invention, power consumption can be reduced in the physical quantity sensor that performs the digital filter operation on the output of the sensor element.

In the invention according to claim 7, when the falling period determining means determines that the current sampling timing is in the falling period, the calculating means repeatedly performs the filter calculation in a short cycle,
When the falling period determining unit determines that the current sampling timing has finished the falling period, the calculating unit repeatedly performs the filter calculation with a long cycle.

  Thus, the same effect as that of the above-described invention can be obtained.

  In the invention described in claim 8, the descent period determining means (S230) is less than the predetermined number of times that the determining means determines that the difference is less than the specified value after the determining means determines that the difference is greater than or equal to the specified value. In this case, it is determined whether or not the current sampling timing is within the falling period.

  According to the ninth aspect of the present invention, when the rising period determining means determines that the current sampling timing is in the rising period, the calculating means calculates Yn by setting Yn−S to the same value as Yn−1. It is characterized by doing.

  Thereby, the same effect as that of the above-mentioned invention can be obtained.

In the invention according to claim 10, the rising period determination means (S310), when the determination means determines that the difference is less than the specified value prior to the determination means determining that the difference is equal to or greater than the specified value. Suppose that the timing of this sampling is within the rising period,
The rising period determination means (S310) determines the timing of the current sampling if the determination means determines that the difference is greater than or equal to the specified value prior to the determination means determining that the current difference is greater than or equal to the specified value. Is characterized by the end of the descent period.

  In the invention according to claim 11, each time the AD converter (32) performs sampling a plurality of times, the calculation means performs the filter calculation once, so that the calculation means performs the filter calculation with a long cycle. It is characterized by that.

  In the invention according to claim 12, when the calculation means performs the filter calculation with a long cycle and when the calculation means performs the filter calculation with a short cycle, the filter characteristics of the filter calculation are calculated to be the same. The means is characterized in that A0 and B as coefficients used in the filter operation are switched.

  According to the twelfth aspect of the present invention, when the calculation means performs the filter calculation with a short cycle, the calculation having the filter characteristics equivalent to the conventional one is performed as in the case where the calculation means performs the filter calculation with a long cycle. The result can be determined.

In the invention according to claim 13, when the comparison means (33a) determines that the sampling value is not less than the specified value, the comparison means sets the frequency of the clock supplied from the clock generation means to the CPU as the frequency of the first clock. Is set to
When the comparison unit (33a) determines that the sampling value is less than the specified value, the comparison unit outputs a determination result signal indicating that the sampling value is determined to be less than the specified value to the CPU, and the CPU clocks. The frequency of the clock given from the generating means to the CPU itself is set to the frequency of the second clock.

  According to the thirteenth aspect of the present invention, when the comparison unit determines that the sampling value is equal to or higher than the specified value, the frequency of the operation clock of the CPU is set to the frequency of the first clock. On the other hand, when the comparison means determines that the sampling value is less than the specified value, the frequency of the CPU operation clock is set to the frequency of the second clock (<the frequency of the first clock). For this reason, the power consumed by the CPU is reduced as compared with the case where the frequency of the operation clock of the CPU is set to the frequency of the first clock regardless of whether or not the sampling value is equal to or higher than the specified value. be able to. For this reason, the same effect as that of claim 1 can be obtained.

According to the fourteenth aspect of the present invention, when the CPU determines that the current sampling timing is in the falling period, the clock frequency supplied from the clock generation means to the CPU is maintained at the frequency of the first clock. And
When the CPU determines that the current sampling timing has finished the falling period, the frequency of the clock that the CPU gives to the CPU itself from the clock generating means is set to the frequency of the second clock. And

  For example, if the CPU operating clock frequency is set to the second clock frequency when the current sampling timing is within the falling period, the change in the operating clock frequency is the filter in the filter operation. The calculation result fluctuates with a great influence on the characteristics.

  On the other hand, in the invention according to the fourteenth aspect, when the current sampling timing is in the falling period, the frequency of the operation clock of the CPU is maintained at the frequency of the first clock. Does not affect the filter characteristics in the filter operation. For this reason, the calculation result equivalent to the past can be calculated | required as a calculation result in a descent | fall period.

In the invention described in claim 15, each time the AD converter performs sampling, the comparison means determines whether or not the sampling value is equal to or greater than a specified value.
The CPU determines whether or not the number of times the comparison unit has determined that the sampling value is smaller than the predetermined value after the comparison unit has determined that the sampling value is greater than or equal to the predetermined value is less than a predetermined number of times. It is characterized in that it is determined whether or not the sampling timing is within the falling period.

  In the sixteenth aspect of the present invention, when the CPU determines that the current sampling timing is in the rising period, the CPU calculates Yn by setting Yn−S to the same value as Yn−1. And

  For example, when the sampling timing of this time is within the rising period, when the CPU performs a filter operation, Yn-S greatly affects the filter characteristics in the filter operation, and the calculation result fluctuates.

  On the other hand, in the invention of the sixteenth aspect, when the timing of the current sampling is in the rising period, Yn is calculated by setting Yn-S to the same value as Yn-1, so that Yn-S is It does not affect the filter characteristics in the filter operation. For this reason, the calculation result equivalent to the past can be calculated | required as a calculation result in a raise period.

In the invention according to claim 17, when the CPU determines that the sampling value is less than the specified value prior to determining that the current sampling value is equal to or greater than the specified value, the timing of the current sampling is determined. Suppose you are in the rising period,
If the CPU determines that the sampling value is greater than or equal to the specified value prior to determining that the current sampling value is greater than or equal to the specified value, the CPU determines that the current sampling timing has ended the rising period. It is characterized by.

In the invention according to claim 18, when the comparison means determines that the difference is equal to or greater than the specified value, the comparison means sets the frequency of the clock supplied from the clock generation means to the CPU to the frequency of the first clock. And
When the comparison unit determines that the difference is less than the specified value, the comparison unit outputs a determination result signal indicating that the difference is determined to be less than the specified value to the CPU, and the CPU generates a CPU itself from the clock generation unit. The frequency of the clock applied to is set to the frequency of the second clock.

  According to the eighteenth aspect of the present invention, when the comparison means determines that the difference is greater than or equal to the specified value, the frequency of the operation clock of the CPU is set to the frequency of the first clock. On the other hand, when the comparison means determines that the difference is less than the specified value, the frequency of the CPU operating clock is set to the frequency of the second clock (<the frequency of the first clock). For this reason, the power consumed by the CPU is reduced as compared with the case where the frequency of the operation clock of the CPU is set to the frequency of the first clock regardless of whether or not the difference is equal to or greater than the specified value. Can do. For this reason, the same effect as in the thirteenth aspect is obtained.

  In the nineteenth aspect of the present invention, when the falling period determining means determines that the current sampling timing has finished the falling period, the frequency of the clock that the CPU gives to the CPU itself from the clock generating means is set to the second clock. The frequency is set. Thus, the same effect as that attained by the 14th aspect described above can be attained.

  In the invention according to claim 20, the CPU determines whether or not the number of times the comparison means has determined that the difference is less than the specified value after the comparison means has determined that the difference is greater than or equal to the specified value. By determining, it is characterized in that it is determined whether or not the current sampling timing is within a falling period in which the difference shifts from a state larger than a specified value to a smaller state.

  In a twenty-first aspect of the present invention, when the CPU determines that the current sampling timing is in the rising period, the CPU calculates Yn by setting Yn−S to the same value as Yn−1. And

  Thus, the same effect as that attained by the 16th aspect described above can be attained.

In the invention according to claim 22, when the CPU determines that the difference is less than the specified value prior to determining that the difference is greater than or equal to the specified value, the current sampling timing is within the rising period. Suppose that
If the CPU determines that the difference is greater than or equal to the specified value prior to determining that the current difference is greater than or equal to the specified value, the timing of the current sampling ends the rising period. And

  In the invention described in claim 23, when the frequency of the clock supplied from the clock generating means to the CPU is set to the frequency of the first clock, the frequency of the clock supplied from the clock generating means to the CPU is the second frequency. The CPU is configured to switch between A0 and B as coefficients used in the filter operation so that the filter characteristics of the filter operation are the same when the clock frequency is set.

  In the invention described in claim 23, when the CPU operates using the first clock as the operation clock, the calculation showing the filter characteristics equivalent to the conventional case is performed as in the case where the CPU operates using the second clock as the operation clock. The result can be determined.

  In a twenty-fourth aspect of the present invention, when the frequency of the operation clock of the CPU is set to the frequency of the second clock by the clock generation means, the CPU performs a single filter operation in a distributed manner. Features.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is a figure which shows the circuit structure of the acceleration sensor for motor vehicles in 1st Embodiment of this invention. It is a figure for demonstrating the action | operation of the acceleration sensor for motor vehicles of FIG. It is a flowchart which shows the main arithmetic processing of CPU of FIG. It is a flowchart which shows AD interrupt processing of CPU of FIG. It is a flowchart which shows the communication interruption process of CPU of FIG. It is a figure which shows the relationship between the sampling timing of the conventional AD converter, and the execution timing of the digital filter calculation by CPU. It is a figure which shows the relationship between the sampling timing of AD converter of FIG. 1, and the execution timing of the digital filter calculation by CPU. It is a figure which shows the processing state of the calculator of FIG. It is a figure which shows the processing state of the conventional arithmetic unit. It is a figure which shows the circuit structure of the acceleration sensor for motor vehicles in 2nd Embodiment of this invention. It is a flowchart which shows the main arithmetic processing of CPU of FIG. 10 is a flowchart showing the AD interrupt processing of the CPU. It is a figure which shows the processing state of the calculator of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(First embodiment)
FIG. 1 shows an electric circuit configuration of an automotive acceleration sensor 1 according to the present invention. The automobile acceleration sensor 1 includes a sensor element 10, an amplifier circuit 20, a control device 30, and an oscillation circuit 40.

  The sensor element 10 is a sensor element that detects the acceleration (physical quantity) of an automobile as a detection target. The amplifier circuit 20 is an amplifier that amplifies the voltage of the output signal of the sensor element 10. The control device 30 is a circuit that converts the output signal of the amplifier circuit 20 into a digital signal and performs a digital filter operation (hereinafter simply referred to as a filter operation) for filtering the converted digital signal. The filtering process is a process for obtaining a filtered signal by filtering (that is, filtering) a digital signal.

  Specifically, the control device 30 includes a low power consumption circuit 31, an AD converter 32, a calculator 33, and a communication circuit 34.

  The low power consumption circuit 31 divides the clock from the oscillation circuit 40 by the first division ratio and outputs the divided clock to the AD converter 31 as the first clock. The low power consumption circuit 31 divides the clock from the oscillation circuit 40 by the second division ratio and outputs the divided clock to the CPU 36 of the computing unit 33 as the second clock.

  Here, the clock is a signal having a certain frequency. The first clock is used as an operation clock for the AD converter 31. The second clock is used as an operation clock for the computing unit 33. The first and second clocks are set to different frequencies.

  The AD converter 32 operates based on the clock from the low power consumption circuit 31, and repeatedly samples the output signal of the amplifier circuit 20 and outputs a sampling value. The computing unit 33 is a digital filter circuit that operates based on the clock from the low power consumption circuit 31 and performs a filter computation for performing a filtering process on the sampling value from the AD converter 32. Specifically, the computing unit 33 includes a memory 35, a CPU 36, and a product-sum computing unit 37.

  As will be described later, the CPU 36 performs a filtering process on the sampling value (AD conversion data) from the AD converter 32. The CPU 36 of this embodiment has a sleep function (or a stop function) that stops execution of the CPU 36 itself when there is no need to execute an instruction, and an external interrupt (AD conversion from an AD converter 32 described later). A wakeup function for resuming the operation upon reception of a completion signal or a calculation result request signal from the electronic control unit.

  The product-sum operation unit 37 performs various operations such as integration, addition, and subtraction for filter processing in accordance with instructions from the CPU 36 as the CPU 36 executes the computer program.

  The memory 35 includes a ROM and a RAM, and stores a computer program of the CPU 36 and a buffer (hereinafter referred to as an operation result buffer) for storing an operation result required when the product-sum operation unit 36 performs an operation. . Details of the operation result buffer will be described later.

  The communication circuit 34 communicates with an electronic control device (not shown) as a host. Reference numeral 38 in the figure is a bus that connects any two of the low power consumption circuit 31, the AD converter 32, the arithmetic unit 33, and the communication circuit 34.

  Next, the calculation result buffer of the memory 35 will be described prior to the description of the operation of the automobile acceleration sensor 1 of the present embodiment.

  In the memory 35 of this embodiment, first, second, and third calculation result buffers are prepared as calculation result buffers. The first calculation result buffer is a buffer for storing the value of Yn-1. Yn−1 is a calculation result calculated by Equation 1 described later in the (n−1) th filter operation, as will be described later. The second calculation result buffer is a buffer for storing the value of Yn−2. Yn-2 is a calculation result calculated by Formula 1 in the (n-2) th filter calculation, as will be described later. The third operation result buffer is a buffer for storing the value of Yn-3. Yn-3 is a calculation result calculated by Expression 1 in the (n-3) th filter calculation, as will be described later.

  Hereinafter, in order to clearly distinguish the first to third calculation result buffers, for convenience, the first calculation result buffer will be referred to as a Yn-1 calculation result buffer, and the second calculation result buffer will be referred to as Yn-2. The operation result buffer is used, and the third operation result buffer is used as a Yn-3 operation result buffer.

  Next, the operation of the automobile acceleration sensor 1 of the present embodiment will be described with reference to FIGS. FIG. 2 is a diagram showing an outline of the operation of the automobile acceleration sensor 1.

  The sensor element 10 outputs an output signal indicating the acceleration (ie, analog physical quantity) of the automobile. The amplifier circuit 20 amplifies the voltage of the output signal of the sensor element 10. Next, the AD converter (denoted by AD in the figure) 32 samples the output signal (that is, an analog signal) of the amplifier circuit 20 at regular intervals and outputs a sampling value for each sampling. The AD converter 32 outputs an AD completion signal to the CPU 36 of the computing unit 33 every time sampling is completed. As a result, the AD converter 32 notifies the CPU 36 of completion of the analog / digital conversion.

  The CPU 36, together with the product-sum calculator 37, repeatedly performs a filter operation for filtering processing on the sampling value from the AD converter 32, as will be described later. Thereafter, the communication circuit 34 outputs a calculation result (digital signal) to the electronic control unit in response to a calculation result request signal from an electronic control unit (not shown) as a host.

  Hereinafter, the details of the main calculation process by the CPU 36 of the calculator 33 will be described with reference to FIG. FIG. 3 is a flowchart showing the entire main calculation process. The execution of the main calculation process is started, for example, when the calculator 33 is powered on.

  First, in step S100, the AD converter 32 is initialized, and in the next step S110, the communication circuit 34 is initialized. In the next step S120, the calculation result buffer for Yn-1, the calculation result buffer for Yn-2, and the calculation result buffer for Yn-3 are each initialized.

  In the next step S130, -2 is set as the count value K of the operation counter. The count value K of the arithmetic counter is a parameter used for determination processing of an ascending period and a descending period (steps 310 and S230 in FIG. 4) described later.

  In the next step S140, an interrupt from the AD converter 32 is permitted. In the next step S150, the interruption from the communication circuit 34 is permitted.

  Thereafter, sleep (step S160) and wakeup (step S170) are alternately performed. Sleep is a state in which the CPU 36 stops operating. Sleep is performed when there is no more instruction to be executed by the CPU 36.

  Here, the CPU 36 outputs a clock stop signal to the low power consumption circuit 31 when shifting to sleep. Accordingly, when the low power consumption circuit 31 receives a clock stop signal from the CPU 36, the low power consumption circuit 31 stops outputting the CPU clock to the CPU 36. This causes the CPU 36 to go to sleep.

  On the other hand, the wake-up is performed when an interrupt from either the AD converter 32 or the communication circuit 34 is performed. Specifically, the CPU 36 wakes up assuming that an interrupt from the AD converter 32 is received when receiving an AD completion signal from the AD converter 32. When the communication circuit 34 receives the calculation result request signal from the electronic control unit, the communication circuit 34 transmits the received calculation result request signal to the CPU 36. The CPU 36 wakes up assuming that it receives an interrupt from the communication circuit 34 when it receives an operation result request signal from the communication circuit 34.

  Here, the AD completion signal from the AD converter 32 and the calculation result request signal from the communication circuit 34 are also transmitted to the low power consumption circuit 31. For this reason, when the low power consumption circuit 31 receives either the AD completion signal or the calculation result request signal, the low power consumption circuit 31 starts outputting the clock to the CPU 36.

  When receiving either one of the AD completion signal and the calculation result request signal, the CPU 36 wakes up and starts AD interrupt processing and communication interrupt processing.

  In the AD interrupt processing of this embodiment, the calculation result of the filter operation is obtained by either the normal operation or the thinning operation. The normal calculation is to perform the filter calculation every time an interrupt is received from the AD converter 32, and the thinning calculation is to perform the filter calculation with a period longer than the period of performing the normal calculation. In this embodiment, the thinning-out calculation period is set to four times the normal calculation period.

  Hereinafter, an outline of the AD interrupt process will be described. FIG. 4 is a flowchart showing AD interrupt processing. The execution of the AD interrupt process is started every time an interrupt is received from the AD converter 32 as described above.

  First, in step S200, the sampling value X output from the AD converter 32 (that is, the output value of the sensor element 10) is acquired, and in the next step S210 (determination means), is the sampling value X equal to or greater than a specified value? Determine whether or not. In the present embodiment, the specified value is an acceleration that is set to determine whether the vehicle is traveling or a collision.

  If the sampling value X is less than the specified value, it is determined as NO in step S210, and the process proceeds to the next step S220 to increment the count value K of the operation counter by one.

  Here, in the present embodiment, when the sampling value X is less than the specified value, in principle, although the calculation result is obtained by the thinning calculation that performs the filter operation in a long cycle, the sampling value X is larger than the specified value. In the descending period in which the state changes from the small state to the small state, when the filter operation is performed by the thinning-out operation, the change of the filter operation cycle affects the filter characteristics of the filter operation too much. For this reason, the calculation result of the filter calculation fluctuates and deviates from the calculation result to be originally obtained (that is, the calculation result equivalent to the conventional one).

  Therefore, in the next step S230 (falling period determining means), whether or not the count value K of the calculation counter is equal to or less than zero in order to determine whether or not the current sampling timing is within the above-described falling period. Determine whether.

  For example, after determining YES in step S210 of the (m-3) th AD interrupt process, the (m-2) th AD interrupt process, the (m-1) th AD interrupt process, and the mth AD interrupt When NO is determined in each step S210 of the process, the count value K> 0 of the operation counter is obtained. m is an integer indicating the number of AD interrupt processing executions.

  In other words, when the number of determinations for determining NO in step S210 is three or more after determining YES in step S210, the count value K> 0 of the operation counter is satisfied. For this reason, the above-described descent period is ended, and YES is determined in step S230.

On the other hand, when the number of determinations for determining NO in step S210 is less than 3 after determining YES in step S210, the count value K ≦ 0 of the operation counter is satisfied, and the m-th sampling timing falls within the above-described falling period It is determined that YES is entered in step S230. This waits for a stabilization period during which the calculation result of the filter calculation is stable.

  In this determination step S230, assuming that the count value K of the calculation counter is less than or equal to zero (K ≦ 0) and determining YES, the current sampling timing is within the above-described falling period. And In this case, in the next step S240, the coefficients (A, B0, B1, B2) used in the following formula 1 are set as coefficients for normal calculation.

Yn = A0 · X + B0 · Yn-1
+ B1 · Yn-2 + B2 · Yn-3 (Equation 1)
Here, n is and indicates the number of executions of the filter calculation process. A is a coefficient for multiplying X, B0 is a coefficient for multiplying by Yn-1, B1 is a coefficient for multiplying by Yn-2, and B2 is a coefficient for multiplying by Yn-3. B0, B1, and B2 correspond to B described in the claims. B1 and B2 correspond to the BS described in the claims, and Yn-2 and Yn-3 correspond to Yn-S described in the claims.

  Next, in step S250 (calculation means), the product-sum calculator 37 performs filter calculation processing using Formula 1.

  That is, every time sampling of the AD converter 32 is performed, the sampling value acquired in step 200 is substituted into X in Equation 1. As the sampling value, a value newly acquired every time AD interrupt processing is executed is used. Then, the storage value of the calculation result buffer for Yn-1 is assigned to Yn-1 in Equation 1, the storage value of the calculation result buffer for Yn-2 is assigned to Yn-2 in Equation 1, and Yn-3 is used. Yn is obtained by substituting the stored value of the calculation result buffer into Yn-3 in Equation 1. Yn is a calculation result in the n-th filter calculation process.

  Here, the above-described Equation 1 is used to configure, for example, a band-pass filter, and filters signal components in a predetermined frequency band from the output signal of the amplifier circuit 20 (that is, the output signal of the sensor element 10). Used to extract as a signal.

  In the next step S260, the storage value of the calculation result buffer for Yn-1, the storage value of the calculation result buffer for Yn-2, and the storage value of the calculation result buffer for Yn-3 are updated.

Specifically, the calculation result buffer Yn-1 stores the calculation result Yn of the nth filter calculation instead of the calculation result Yn of the (n-1) th filter calculation.
The calculation result buffer for Yn-2 stores the calculation result Yn-1 used in the nth filter calculation instead of the calculation result Yn-1 used in the (n-1) th filter calculation. Instead of Yn-2 used in the (n-1) th filter operation, Yn-2 used in the nth filter operation is stored in the Yn-3 operation result buffer.

  Here, the number of bits of the calculation result Yn calculated in step S250 is larger than the number of bits of communication data used in communication between the electronic control unit and the communication circuit 34. Therefore, in step S270, Y is obtained by converting the calculation result Yn calculated in step S250 into data of a predetermined number of bits. The number of data constituting Y is smaller than the number of data constituting Yn. Thereafter, the AD interrupt process is terminated.

  In step S230 described above, when the count value K of the operation counter is greater than zero (the count value of the operation counter K> 0), it is determined that the current sampling timing has finished the above-described falling period, NO. Along with this, a thinning calculation is performed as follows.

  In the next step S280, it is determined whether or not the count value K of the operation counter is 4 or more. Thus, it is determined whether or not a filter operation (calculation of the operation result yn) should be performed in the thinning operation.

  Here, when the count value K of the operation counter is less than 4 (count value K <4 of the operation counter), it is determined that the filter operation should not be performed, and NO is determined in step S280, and the AD interrupt processing is terminated. To do. As a result, even if an interrupt signal is received from the AD converter 32, the AD interrupt process is terminated without executing the filter operation of step S250, and the computer immediately goes to sleep.

  If the count value K of the calculation counter is 4 or more (count value K of the calculation counter K ≧ 4), it is determined that the filter calculation should be performed, and YES is determined in step S280. Along with this, the count value K of the operation counter is set to zero in step S290, the process proceeds to the next step S300, and the coefficient used in Equation 1 is set as a coefficient for thinning calculation.

  Here, the coefficient for thinning calculation and the coefficient for normal calculation are set so that a filter having the same characteristic is formed by Equation 1. For example, when a band-pass filter is configured according to Equation 1, the thinning calculation and the normal calculation are different from each other in the period of the filter calculation, but the thinning calculation coefficient and the normal calculation so as to extract the filtered signals in the same frequency band. The coefficient for is set.

  Next, in step S250, as described above, the sampling value X acquired in step S200, the stored value in the Yn-1 calculation result buffer, the stored value in the Yn-2 calculation result buffer, and the calculation result for Yn-3. Yn is calculated by substituting the stored value of the buffer into Equation 1.

  As described above, every time the count value K of the operation counter becomes 4 or more, the filter operation is performed using the coefficient for thinning operation in steps S300 and S250.

  Next, in step S260, as described above, the storage value of the calculation result buffer for Yn-1, the storage value of the calculation result buffer for Yn-2, and the storage value of the calculation result buffer for Yn-3 are updated. Thereafter, after converting Yn to Y in step S270, the AD interrupt process is terminated.

  In step S210, when the sampling value X is equal to or greater than the specified value (sampling value X ≧ specified value), the determination is YES.

  Next, in the next step S310 (rising period determination means), in order to determine whether or not the current sampling timing is within the rising period in which the sampling value X changes from a state smaller than the specified value to a larger state. Then, it is determined whether or not the count value K of the operation counter is greater than or equal to zero.

  For example, when it is determined NO in step S210 in the m−1th AD interrupt processing before determining YES in step S210 in the mth AD interrupt processing, the count value K ≧ 0 of the operation counter is obtained, and in step S310. It determines with YES.

  That is, it is determined that the current sampling timing (that is, the m-th sampling timing) is within the rising period.

  Prior to the determination of YES in step S210 in the m-th AD interrupt process, if YES is determined in step S210 in the m-1th AD interrupt process, the count value K <0 of the operation counter is obtained, and in step S310. Determine NO.

  That is, it is determined that the current sampling timing (that is, the m-th sampling timing) ends the rising period.

  If YES is determined in step S310, the Yn-1 calculation result buffer is stored in the next step S320 for each of the Yn-2 calculation result buffer and the Yn-3 calculation result buffer. Stores a value.

  Thereafter, in step S330, zero is set to the count value K of the calculation counter, and in the next step S240, the coefficient used in Equation 1 is set as a coefficient for normal calculation.

  In the next step S250, as described above, the sampling value acquired in step 200 is substituted for X in Equation 1, the stored value in the calculation result buffer for Yn-1 is substituted for Yn-1 in Equation 1, and Yn The stored value in the −2 calculation result buffer is substituted for Yn−2 in Formula 1, and the stored value in the Yn−3 calculation result buffer is substituted for Yn−3 in Formula 1 to obtain Yn.

  Here, the stored value of the calculation result buffer for Yn-1 is stored in each of the calculation result buffer for Yn-2 and the calculation result buffer for Yn-3. Therefore, in this step S250, Yn-2 and Yn-3 are respectively set to the same value as Yn-1, and Yn is obtained.

  Thereafter, in the next step S260, the storage value of the calculation result buffer for Yn-3, the storage value of the calculation result buffer for Yn-2, and the storage value of the calculation result buffer for Yn-1 are updated. In step S270, Convert Yn to Y.

  Next, details of the communication interrupt processing will be described with reference to FIG. FIG. 5 is a flowchart showing details of the communication interrupt process. The execution of the communication interrupt process is started every time an interrupt is received from the communication circuit 34, as described above.

  First, in step S500, the communication circuit 34 is controlled to transmit Y to the electronic control unit. As Y to be transmitted, Y calculated at the timing closest to the reception timing of the interrupt signal from the communication circuit 34 is used.

  Next, a specific example of AD interrupt processing according to the present embodiment will be described with reference to FIGS. FIG. 6 is a diagram showing the relationship between the sampling timing of the conventional AD converter 32 and the execution timing of the filter operation by the CPU 36. FIG. 7 is a diagram showing the relationship between the sampling timing of the AD converter 32 and the execution timing of the filter operation by the CPU 36 according to this embodiment.

  In the conventional automotive acceleration sensor 1, as shown in FIG. 6, every time the AD converter 32 samples the output signal of the amplifier circuit 20, the CPU 36 performs a filter operation on the sampling value X (this is performed in step S 250 of FIG. 4). Equivalent).

  On the other hand, in the automobile acceleration sensor 1 of the present embodiment, the cycle in which the CPU 36 performs the filter calculation is changed as shown in FIG. Hereinafter, the output signal of the amplifier circuit 20 (solid line in FIG. 7) becomes larger from a state where the output signal is smaller than the prescribed value (chain line in FIG. 7), and then the magnitude of the output signal of the amplifier circuit 20 becomes smaller than the prescribed value. An example will be described.

  First, the AD converter 32 performs sampling of m (≧ 3: m is an integer), determines NO in step S210, and increments the count value K of the operation counter by 1 in step S220. Accordingly, if the count value K ≧ 4 of the operation counter is satisfied, NO is determined in step S230. Thereafter, the filter calculation is executed using the thinning calculation coefficients in steps S300 and S250.

  Thereafter, when the AD converter 32 performs the (m + 1) th to (m + 3) th sampling, it is determined NO in step S210, and the count value K of the operation counter is incremented by 1 in step S220. Then, NO is determined in step S280 with the count value K <4 of the operation counter, and the process ends without executing the filter operation.

  Next, when the AD converter 32 performs the (m + 4) th sampling and determines NO in step S210, the count value K of the calculation counter is incremented by one in step S220 and the count value K of the calculation counter is increased. ≧ 4. For this reason, it determines with YES by step S280, and performs filter calculation using the coefficient for a thinning calculation by step S300, S250 after that.

  Thus, when the sampling value of the AD converter 32 is less than the prescribed value and the count value K> 0 of the operation counter, every time the count value K of the operation counter becomes 4 or more, steps S300 and S250 are performed. The filter operation is executed using the coefficient for the thinning operation.

  Next, when the AD converter 32 performs the (m + 5) -th sampling and determines NO in step S210, the processing ends without performing the filter operation as in the case of the m-th sampling.

  Thereafter, when the magnitude of the output signal of the amplifier circuit 20 becomes larger than the specified value and the AD converter 32 performs the (m + 6) th sampling, it is determined as YES in Step S210. In this case, assuming that the count value K of the calculation counter becomes zero or more in step S310 and the timing of the (m + 6) th sampling is within the above-described rising period, the calculation result for Yn-2 is set in the next step S320. The stored value of the calculation result buffer for Yn-1 is stored in each of the buffer and the calculation result buffer for Yn-3. In this case, in steps S240 and S250, Yn-2 and Yn-3 in Equation 1 are set to the same value as Yn-1, respectively, and the filter operation using the coefficient for normal operation is executed.

  Next, when the AD converter 32 performs (m + 7) -th sampling and determines YES in step S210, it determines NO in step S310 because the count value K of the operation counter is less than zero. That is, it is determined that the timing of the (m + 6) th sampling is out of the above rising period. Next, the filter calculation is executed using the normal calculation coefficients in steps S240 and S250. At this time, the filter operation is executed using Yn-2 and Yn-3 as they are in Equation 1.

  Thereafter, when the (m + 8) -th sampling and the (m + 9) -th sampling are performed by the AD converter 32, “YES” is determined in the step S210. In this case, the filter calculation is executed using the normal calculation coefficients in steps S240 and S250.

  Thereafter, when the magnitude of the output signal of the amplifier circuit 20 becomes smaller than the specified value and the AD converter 32 performs the (m + 10) th sampling, it is determined as NO in step S210. Thereafter, the count value K of the calculation counter is incremented by 1 in step S220, the count value K ≦ 0 of the calculation counter is set, and YES is determined in step S230. In this case, it is determined that the (m + 10) -th sampling timing is in the above-described falling period. Next, the filter calculation is executed using the normal calculation coefficients in steps S240 and S250.

  Next, even when the AD converter 32 performs the (m + 11) -th sampling, the count value K ≦ K of the operation counter is equal even when the increment processing of step S220 is performed as in the case of the (m + 10) -th sampling. 0. For this reason, it is determined YES in step S230, assuming that the timing of the (m + 11) th sampling is in the above-described falling period. Next, the filter calculation is executed using the normal calculation coefficients in steps S240 and S250.

  Next, when the AD converter 32 performs the (m + 12) -th sampling and determines NO in step S210, the count value K> 0 of the operation counter is obtained through the increment process in step S220. For this reason, assuming that the timing of the (m + 12) th sampling ends the above-described falling period, YES is determined in step S230. Then, it determines with NO by step S280, and complete | finishes, without performing a filter calculation.

  In this way, every time the CPU 36 receives an AD interrupt from the AD converter 32, the AD interrupt process is performed to perform a filter calculation process. At this time, when the CPU 36 receives a communication interrupt from the communication circuit 34 during the execution of the AD interrupt process (see Ta in the figure), the communication interrupt process is performed after the end of the AD interrupt process (see Tb in the figure). Here, in a period excluding the AD interrupt process and the communication interrupt process, the CPU 36 goes to sleep.

  When the sampling value X is less than the specified value and the counter value of the operation counter is less than zero, the CPU 36 performs a thinning operation as shown in FIG.

  In other words, AD interrupt processing is performed every time an AD interrupt is received from the AD converter 32, but the number of filter operations is thinned out, and one filter operation is performed every time AD interrupt processing is performed four times. The example shown in FIG. 8B shows an example in which the communication interrupt is performed at the timing when the AD interrupt is offset with respect to the processing. In the period excluding the AD interrupt processing and the communication interrupt processing, the CPU 36 goes to sleep. Yes.

  On the other hand, in the case of the conventional automobile acceleration sensor 1, as shown in FIG. 9, every time the CPU 36 receives an AD interrupt from the AD converter 32, an AD interrupt process is performed to perform a filter calculation process. At this time, during the period excluding the AD interrupt processing and the communication interrupt processing, the wait mode is set.

  According to the embodiment described above, the sensor element 10 that detects the acceleration of the automobile, the amplifier circuit 20 that amplifies the output signal of the sensor element 10, and the AD that samples the output signal of the amplifier circuit 20 at regular intervals. And an arithmetic unit 33 that repeatedly performs a filter operation for performing filter processing on the sampling value output from the AD converter 32, and the sampling value output from the AD converter 32 is defined. When it is determined that the value is greater than or equal to the value, the filter operation is repeatedly performed in a short cycle, and when the sampling value is less than the specified value, the filter operation is repeatedly performed in a long cycle.

  For this reason, according to the present embodiment, each time the AD converter 32 performs sampling, the filter calculation is performed more than when the sampling is performed, regardless of whether the sampling value is less than the specified value. The number of times can be reduced. For this reason, the calculation amount of the CPU 36 can be reduced. Therefore, it is possible to reduce the power consumption of the CPU 36 and thus the computing unit 33.

  In this embodiment, when normal calculation is performed, filter calculation is performed using Formula 1 using the normal calculation coefficient. When performing the decimation operation, the filter operation is performed using Equation 1 using the decimation coefficient.

  Here, the normal calculation coefficient and the thinning calculation coefficient are set so that the filter characteristic of the thinning calculation and the filter characteristic of the normal calculation are the same. For this reason, although the thinning calculation and the normal calculation have different periods for performing the filter calculation, it is possible to obtain the calculation result Yn of the filter calculation equivalent to the conventional one.

  In the present embodiment, when the count value K ≦ 0 of the operation counter, the current sampling timing is lowered so that the magnitude of the output signal of the amplifier circuit 20 changes from a state larger than the prescribed value to a state smaller than the prescribed value. Assuming that the period falls within the period, the normal calculation is performed as the filter calculation even though the sampling value X ≦ the specified value.

  Here, if the thinning calculation is performed as the filter calculation when the current sampling timing is within the falling period, the cycle for performing the filter calculation is increased (that is, the filter calculation is thinned out). As a result, the calculation result Yn fluctuates and deviates from the calculation result equivalent to the conventional one that should be obtained.

  Therefore, in the present embodiment, as described above, when it is determined YES in step S230 that the current sampling timing is within the falling period, the normal calculation as the filter calculation is performed and the filter calculation is performed. Since the fluctuation of the calculation result Yn can be suppressed as the cycle is lengthened, the calculation result Yn equivalent to the conventional one can be obtained.

That is, when YES is determined in step S230, a stabilization period is provided until the calculation result Yn is stabilized . During this period, normal calculation is performed, and when the stabilization period ends, the process proceeds to thinning calculation. As a result, while the magnitude of the output signal from the sensor element 10 is a value that is not monitored as control, the amount of calculation is reduced, and the calculator 33 is stopped for the remaining time, thereby reducing power consumption. can do.

  In the present embodiment, in step S310, it is determined that the current sampling timing is within the rising period, YES. Accordingly, Yn-3 and Yn-2 are respectively set to the same value as Yn-1, and the calculation result Yn of Equation 1 is obtained.

  Therefore, when the current sampling timing is within the rising period, the calculation result (Yn-3, Yn-2) when the magnitude of the output signal of the amplifier circuit 20 is smaller than the specified value. Can suppress the influence on the filter characteristics, so that a calculation result Yn equivalent to the conventional one can be obtained.

  However, at the time of a vehicle collision, the acceleration changes rapidly after the end of the ascending period. And Yn-3 and Yn-2 do not affect the filter characteristics during the period in which the acceleration changes rapidly after the end of the rising period. For this reason, you may implement this embodiment, without using the process of step S320.

  Next, specific numerical examples of the automobile acceleration sensor 1 of the present embodiment will be described.

For example, no acceleration occurs when the automobile is stopped, and the acceleration changes slowly at several G or less when the automobile is running. At the time of a vehicle collision, an acceleration of 20G or more occurs and the acceleration changes rapidly. For this reason, the AD converter 32 performs sampling at a cycle of about 20 KHz. A value equivalent to several G is used as a specified value for determining the magnitude of the change in the output signal of the amplifier circuit 20 (that is, the output of the sensor element 10) (that is, whether it changes slowly or suddenly). Is used. This means that when the vehicle is traveling at a low speed, the calculator 33 repeatedly performs the filter calculation with a long period as described above. For this reason, the amount of calculation can be reduced. For example, when the vehicle is traveling at a low speed, the calculation amount can be reduced to 1/10 without performing a high-speed calculation such as a vehicle collision, so the power consumption of the CPU 36 is reduced to about 1/10. I can do it.
(Second Embodiment)
In the first embodiment, the example in which the filter operation is performed with a long period when the sampling value X is less than the specified value has been described. Instead, in the second embodiment, the sampling value X is specified. An example in which the frequency of the operation clock of the CPU 36 is lowered when the value is less than the value will be described.

  FIG. 10 shows an electric circuit configuration of the automobile acceleration sensor 1 of the present embodiment. The automobile acceleration sensor 1 of this embodiment includes a sensor element 10, an amplifier circuit 20, a control device 30A, and an oscillation circuit 40.

  The configuration (10, 20, 40) other than the control device 30A in the automotive acceleration sensor 1 of the present embodiment is the same as the circuit configuration of the automotive acceleration sensor 1 of FIG. Therefore, description of other configurations (10, 20, 40) is omitted, and the control device 30A will be described below.

  The control device 30A according to the present embodiment includes a frequency divider 31a, a clock switch 31b, an AD converter 32, a calculator 33, a comparator 33a, and a communication circuit 34.

  In FIG. 1, the control device 30A includes a frequency divider 31a, a clock switch 31b, and a comparator 33a instead of the low power consumption circuit. Therefore, the description of the AD converter 32, the arithmetic unit 33, and the communication circuit 34 is simplified, and the frequency divider 31a, the clock switch 31b, and the comparator 33a are described.

  The frequency divider 31a divides the clock output from the oscillator 40 by three different frequency division ratios, and outputs an AD conversion clock and first and second CPU clocks.

  The first and second CPU clocks are output to the clock switch 31b and are used as operation clocks for the CPU 36 of the computing unit 33 as will be described later.

  Here, if the frequency of the first CPU clock is fcpu, the frequency of the second CPU clock is (fcpu / 4). That is, the frequency of the first CPU clock is set higher than the frequency of the second CPU clock. The AD conversion clock is used as an operation clock for the AD converter 32. The frequency fad of the AD conversion clock is set to a frequency different from the frequency (fcpu) of the first CPU clock and the frequency (fcpu / 4) of the second CPU clock.

  The comparator 33a determines whether or not the sampling value X (that is, AD conversion data) output from the AD converter 32 is larger than the reference data set by the CPU. As the reference data of the present embodiment, data indicating the same value as the specified value used in the first embodiment is used.

  As will be described later, the clock switch 31 b outputs one of the first and second CPU clocks to the CPU 36 in accordance with the output signal of the AD converter 32 or the CPU 33.

  Next, the operation of the automobile acceleration sensor 1 of the present embodiment will be described with reference to FIGS.

  The operations of the sensor element 10, the amplifier circuit 20, the AD converter 32, and the computing unit 33 of the present embodiment are substantially the same as those of the first embodiment. The CPU 36 of the computing unit 33 of the present embodiment performs an operation different from that of the first embodiment. Therefore, in the following description of the acceleration sensor 1 for automobiles, the circuit configuration (10, 20, 32, 33) other than the CPU 36, the frequency divider 31a, the clock switch 31b, and the comparator 33a will be simplified. The CPU 36, the frequency divider 31a, the clock switch 31b, and the comparator 33a will be described.

  First, when the power is turned on, the oscillator 40 starts outputting a clock. The frequency divider 31a outputs an AD conversion clock obtained by dividing the clock from the oscillator 40 to the AD converter 32, and the first and second CPU clocks obtained by dividing the clock from the oscillator 40 are clock switchers 31b. Output to. Then, the clock switch 31b outputs the first CPU clock to the CPU 36. Along with this, the CPU 36 starts operation using the first CPU clock as an operation clock. That is, the CPU 36 executes the main calculation process in a state of operating with the first CPU clock as the operation clock.

  FIG. 11 is a flowchart showing the entire main arithmetic processing of the CPU 36 used in place of FIG.

  The flowchart of FIG. 11 is configured by adding step S135 between steps S130 and S140 in the flowchart of FIG. Step S135 is a step in which the CPU 36 sets reference data for the comparator 33a.

  First, the CPU 36 executes an initialization process of the AD converter 32 in step S100, an initialization process of the communication circuit 34 in step S110, and an initialization process of the calculation result buffer in step S120, and then in step S135. Reference data is set for the comparator 33a. As the reference data, as described above, data indicating the specified value used in the first embodiment is used. Next, the CPU 36 executes processing for setting the count value K of the operation counter in step S130 and processing for permitting interruption from the AD converter 32 in step S140. Thereafter, the CPU 36 alternately performs sleep (step S160) and wake-up (step S170) as in the first embodiment described above.

  The AD converter 32 is reset with the initialization process of the AD converter 32 in step S100. Therefore, the AD converter 32 starts a sampling operation using the AD conversion clock from the frequency divider 31a as an operation clock.

  Accordingly, the AD converter 32 repeatedly performs sampling along with the processing in step S100, and outputs a sampling value to the CPU 36 and the comparator 33a for each sampling. In addition, the AD converter 32 outputs an AD completion signal as an interrupt signal to the CPU 36 every time one sampling is completed.

  Each time the sampling is performed by the AD converter 32, the comparator 33a determines whether or not the sampling value (that is, AD conversion data) output from the AD converter 32 is equal to or higher than a specified value. A determination result signal indicating the determination result is output to the CPU 36. On the other hand, every time the CPU 36 receives an AD completion signal (that is, an AD interrupt) from the AD converter 32, the CPU 36 executes an AD interrupt process using the determination result signal.

  In addition, every time the comparator 33a determines that the sampling value output from the AD converter 32 (that is, AD conversion data) is equal to or greater than the specified value, the comparator 33a is changed from the clock switch 31b to the CPU 36. The clock frequency given to is increased.

  That is, each time the comparator 33a determines that the sampling value output from the AD converter 32 is equal to or higher than the specified value, the frequency of the clock supplied from the clock switch 31b to the CPU 36 is set to the frequency of the first CPU clock. Set. Therefore, every time the comparator 33a determines that the sampling value is equal to or higher than the specified value, the CPU 36 starts operation with the frequency (fcpu) of the first CPU clock as the frequency of the operation clock.

  On the other hand, when the comparator 33a determines that the sampling value is less than the specified value, as will be described later, in step S400 in FIG. 12, the CPU 36 determines the clock according to the determination result signal output from the comparator 33a. The frequency of the clock supplied from the switch 31b to the CPU 36 is set to the frequency of the second CPU clock (fcpu / 4).

  Hereinafter, the pseudo-abbreviation of the AD interrupt processing by the CPU 36 of this embodiment will be described. FIG. 12 is a flowchart used in place of FIG. 4 and shows AD interrupt processing. The execution of the AD interrupt process is started every time an AD completion signal is received from the AD converter 32 as described above. Here, the initial value of the operating frequency of the CPU 36 is set to the frequency of the first CPU clock by the clock switch 31b.

  First, in step S200, the sampling value X from the AD converter 32 is acquired, and in the next step S210a, the determination result by the comparator 33a is confirmed based on the determination result signal from the comparator 33a.

  Here, it is confirmed that the comparator 33a determines that the sampling value X (that is, AD conversion data) output from the AD converter 32 is equal to or greater than a specified value, and the count value K ≧ 0 of the operation counter is determined in step S310. When the determination is YES, as in the first embodiment described above, the determination process of the count value K of the calculation counter in step 310, the calculation result buffer setting process in step S320, and the normal calculation coefficient setting in step S240 are performed. The processing, the filter calculation process in step S250, the calculation result buffer update process in step S260, and the Yn / Y data conversion process in step S270 are executed.

  When the sampling value X (that is, AD conversion data) output from the AD converter 32 is less than the specified value, the process proceeds to step S220 to execute the operation counter increment process, and then proceeds to step S230. It is determined whether the count value K of the counter is equal to or less than zero.

  When the count value K of the calculation counter is less than or equal to zero, it is determined that the current sampling timing is within the falling period, and YES is determined in step S230. In this case, the frequency of the clock output from the clock switch 31b to the CPU 36 is maintained at the frequency of the first CPU clock. Then, in the next steps S240 and S250, as in the first embodiment described above, the coefficient for normal calculation is set as the coefficient in Equation 1, and Yn in Equation 1 is calculated.

  On the other hand, in the above-described step S230, when the count value K of the calculation counter is larger than zero, it is determined as NO because the current sampling timing is out of the falling period. Then, the process proceeds to the next step S400, and the frequency of the CPU clock output from the clock switch 31b to the CPU 36 itself is reduced.

Specifically, the CPU 36 outputs a speed reduction signal to the clock switch 31b. For this reason, when the clock switch 31b receives the speed reduction signal from the CPU 36, the clock switch 31b sets the frequency of the clock supplied to the CPU 36 to the frequency of the second CPU clock.
Therefore, the CPU 36 itself starts an operation using the second CPU clock frequency (fcpu / 4) as the operating frequency.

  Next, in step S410, the coefficient used in Equation 1 above is set as a coefficient for thinning calculation.

  Here, although the frequency of the CPU clock used in the thinning calculation and the frequency of the CPU clock used in the normal calculation are different from each other, the thinning calculation coefficient and the normal calculation coefficient are set so as to form a filter having the same characteristics. Has been.

  Thereafter, in step S420, it is determined whether the count value K of the calculation counter is 1, 2, 3, or 4 or more. One of the following processes (1), (2), (3), and (4) is selected and executed according to the determination result.

  (1) When the count value K of the operation counter is 1 (count value K = 1), in step S430 (denoted as filter operation 1 in the figure), A0 · X, which is the first term of Equation 1, is calculated. This calculation result is assumed to be Yn. Thereafter, the process proceeds to step S270. X is the current sampling value.

  (2) When the count value K of the calculation counter is 2 (count value K = 2), the process proceeds to step S440 (denoted as filter calculation 2 in the figure). In this step S440, (Yn + B0 · Yn-1) is calculated by setting the calculation result of step S430 executed prior to the current step S440 as Yn and the stored value of the Yn-1 calculation result buffer as Yn-1. (B0 · Yn−1) is the second term of Equation 1 above. Then, the calculation result of (Yn + B0 · Yn-1) is set to Yn, and the process proceeds to the next step S270.

  (3) When the count value K of the calculation counter is 3 (count value K = 3), in step S450 (denoted as filter calculation 3 in the figure), the calculation result of step S440 executed prior to this step S450 is represented by Yn. And the stored value of the calculation result buffer for Yn-2 is Yn-2, and (Yn + B1 · Yn-2) is calculated. (B1 · Yn-2) is the third term of Equation 1 above. Then, the calculation result of (Yn + B1 · Yn−2) is set to Yn, and the process proceeds to the next step S270.

  (4) When the count value K of the calculation counter is 4 or more (count value K ≧ 4), in step S460 (denoted as filter calculation 4 in the figure), the calculation result of step S450 executed prior to the current step S460 is obtained. Yn is set, and the stored value of the calculation result buffer for Yn-3 is set to Yn-3, and (Yn + B2 · Yn-3) is calculated. (B2 · Yn-3) is the third term of Equation 1 above. Then, the calculation result of (Yn + B2 · Yn−3) is Yn.

  In the next step S465, similar to step S260 of the first embodiment, the storage value of the calculation result buffer for Yn-1, the storage value of the calculation result buffer for Yn-2, and the storage of the calculation result buffer for Yn-3 are stored. Update the value. In the next step S470, the count value K of the calculation counter is set to zero (K = 0), and the process proceeds to the next step S270.

  Here, steps S430, S440, S450, and S460 each correspond to a process obtained by dividing the filter calculation process of step S250 into four. For this reason, if it determines with NO by the said step S230, a filter calculation process will be divided into four and implemented.

  Further, when receiving a request signal (that is, a communication interrupt) from the communication circuit 34, the CPU 36 controls the communication circuit 34 and transmits the result Yn of the filter operation to the electronic control device as in the first embodiment.

  Next, a specific example of the processing of the computing unit 33 of the present embodiment will be described with reference to FIGS. 13 (a) and 13 (b).

  FIGS. 13A and 13B are diagrams showing the processing state of the computing unit 33. FIG. FIG. 13A shows the case of normal calculation in which the CPU 36 operates with the operating frequency fcpu in the present embodiment, and FIG. 13B shows the operation of the CPU 36 with the operating frequency fcpu / 4 in the present embodiment. The figure at the time of thinning calculation is shown.

  First, when the power is turned on, the clock switch 31b sets the frequency of the clock supplied to the CPU 36 to the frequency of the first CPU clock as its initial value. For this reason, the CPU 36 operates with the frequency of the first CPU clock as the operation clock frequency.

  Thereafter, when the CPU 36 receives an AD interrupt, it starts AD interrupt processing. Then, the CPU 36 confirms that the comparator 33a has determined that the sampling value X <the specified value (step 210a in FIG. 12), and when NO is determined in step S230 as the count value K> 0 of the operation counter, In step S400, the speed reduction signal is output to the clock switch 31b. For this reason, when the clock switch 31b receives the speed reduction signal from the CPU 36, the clock switch 31b sets the frequency of the clock to be supplied to the CPU 36 to the frequency fcpu / 4 of the second CPU clock. As a result, the thinning calculation is started.

  In this case, according to the count value K of the calculation counter, one of steps S430, S440, S450, and S460 in FIG. 12 is selected and the process proceeds to the selected step, and the calculation of Yn in step S260 is performed. A process obtained by dividing the process into four parts (hereinafter referred to as a division process) is performed. Then, the process ends after the Yn / Y conversion process in step S270.

  The thinning calculation process described above is repeatedly performed every time an AD interrupt is received by the CPU 36 as long as the sampling value X <the specified value and the count value K> 0 of the operation counter are maintained.

  For this reason, when the jth AD interrupt (see timing t1 in FIG. 13B) is received, AD interrupt processing (1/4) is executed, and it is determined in step S420 that the count value K of the operation counter is K = 1. In step S430, a division process (referred to as filter calculation process 1 in FIG. 12) is performed.

  Next, when the j + 1th AD interrupt (see timing t2 in FIG. 13B) is received, AD interrupt processing (2/4) is executed, and it is determined in step S420 that the count value K = 2 of the operation counter is reached. In step S440, a division process (referred to as filter calculation process 2 in FIG. 12) is performed.

  Next, when the j + 2th AD interrupt (see timing t3 in FIG. 13B) is received, AD interrupt processing (3/4) is executed, and it is determined in step S420 that the count value K = 3 of the operation counter. In step S450, a division calculation process (denoted as filter calculation process 3 in FIG. 12) is performed.

  Here, when the CPU 36 receives a communication interrupt (see a white inverted triangle in the figure) from the communication circuit 34 while executing the AD interrupt process (3/4) in FIG. 13, the AD interrupt process (3/4) The execution of the communication interrupt process is started at the timing t4 when) ends. In this case, the communication circuit 34 transmits the calculation result Yn of step S460 to the electronic control unit. The calculation result Yn is a calculation result of AD interrupt processing (4/4) (not shown) executed prior to timing t4.

  Next, when the j + 3th AD interrupt (see timing t5 in FIG. 13B) is received, AD interrupt processing (4/4) is executed, and it is determined in step S420 that the count value K ≧ 4 of the operation counter. In step S460, a division process (referred to as filter calculation process 4 in FIG. 12) is performed. Accordingly, in step S470, the count value K of the calculation counter is set to zero (count value K = 0).

  For this reason, when receiving the j + 4th AD interrupt (see timing t6 in FIG. 13B), when executing the AD interrupt process (1/4), the count value of the operation counter is incremented by 1 in step S220. In step S420, it is determined that the count value K = 1 of the operation counter. For this reason, a decentralization process (referred to as filter calculation process 1 in FIG. 12) is performed in step S430.

  After that, when the magnitude of the output signal of the amplifier circuit 20 becomes larger than the specified value and the comparator 33a determines that the sampling value X is equal to or larger than the specified value, the comparator 33a gives the CPU 36 from the clock switch 31b. The frequency of the clock to be set is set to the frequency of the first CPU clock. For this reason, the CPU 36 starts the operation with the frequency (fcpu) of the first CPU clock as the frequency of the operation clock. That is, normal calculation is started.

  In addition to this, the CPU 36 confirms that the comparator 33a has determined that the sampling value X output from the AD converter 32 is greater than or equal to the specified value (step S210a in FIG. 12), and in step S310, the operation counter The count value K ≧ 0 is determined as YES. In step S320, the stored value of the calculation result buffer for Yn-1 is stored in the calculation result buffer for Yn-2 and the calculation result buffer for Yn-3. In step S330, the count value K of the calculation counter is set to -2, and in the next step S250, the product-sum calculator 37 performs filter calculation using a normal calculation coefficient. For this reason, the intermediate result of the division process (that is, the calculation result Yn of the division process in step S430) is discarded.

  Thereafter, when the sampling value X is maintained to be equal to or higher than the specified value, when the comparator 33a determines that the sampling value X is equal to or higher than the specified value, the comparator 33a is supplied from the clock switch 31b to the CPU 36. The frequency of the clock is maintained at the frequency of the first CPU clock. For this reason, the frequency of the operation clock of the CPU 36 is maintained at the frequency (fcpu) of the first CPU clock.

  In addition to this, the CPU 36 confirms that the comparator 33a has determined that the sampling value X output from the AD converter 32 is greater than or equal to the specified value (step S210a in FIG. 12), and in step S310, the operation counter NO is determined as the count value K <0. In the next step S330, the count value K of the calculation counter is set to −2, and in the next step S250, the product-sum calculator 37 performs a filter calculation using a normal calculation coefficient.

  Such normal calculation processing is repeatedly performed every time an AD interrupt is received by the CPU 36 as long as the sampling value X ≧ the specified value (see FIG. 13A).

  Thereafter, when the magnitude of the output signal of the amplifier circuit 20 becomes smaller than the specified value, it is confirmed in step S210a that the comparator 33a has determined that the sampling value X is less than the specified value. At this time, the count value K of the calculation counter is incremented by 1 in step S220, and the count value K of the calculation counter becomes -1. That is, the count value K ≦ 0 of the operation counter is satisfied, and YES is determined in step S230. For this reason, the operation clock frequency of the CPU 36 is maintained at the frequency (fcpu) of the first CPU clock. In the next step S250, a filter calculation using a normal calculation coefficient is performed.

  After that, if it is maintained that sampling value X ≧ specified value, it is confirmed in step S210a that comparator 33a has determined that sampling value X is less than the specified value, and count value K of the operation counter is determined in step S220. Is incremented by 1, the count value K of the operation counter becomes 0. For this reason, it determines with YES in step S230. For this reason, the operation clock frequency of the CPU 36 is maintained at the frequency (fcpu) of the first CPU clock, and in the next step S250, a filter calculation using a normal calculation coefficient is performed.

  Thereafter, it is maintained in step S210a that the sampling value X ≧ specified value is maintained, and the comparator 33a determines that the sampling value X is less than the specified value. In step S220, the count value K of the calculation counter is determined. When incremented by one, the count value K of the operation counter becomes 1. For this reason, in step S230, it is determined that the current sampling timing has ended the falling period, NO. Next, in step S400, the CPU clock frequency output from the clock switch 31b to the CPU 36 itself is reduced. Along with this, the above-described thinning calculation is started.

  According to the embodiment described above, when the sampling value X ≧ the specified value, the CPU 36 operates with the frequency (fcpu) of the first CPU clock as the operation clock frequency, and every time an AD interrupt is received, the filter 36 The calculation is performed and the calculation result Yn is calculated.

  On the other hand, when the sampling value X <the specified value (however, only when the count value K> 0 of the operation counter in step S230), the CPU 36 sets the second CPU clock frequency (fcpu / 4) as the operation clock. The above dividing process is performed every time an AD interrupt is received.

  As described above, when it is determined NO in step S230 that the sampling value X <the specified value and the current sampling timing has finished the falling period, the CPU 36 determines the frequency of the second CPU clock (fcpu / 4). The operation clock frequency is used. For this reason, the CPU 36 reduces the power consumed by the CPU 36 as compared with the case where the CPU 36 operates using the first CPU clock frequency (fcpu) as the operation clock frequency regardless of whether the sampling value X and the specified value are large or small. be able to.

  In addition to this, in the present embodiment, as in the first embodiment described above, the CPU 36 sleeps in an extra period other than the main arithmetic processing, AD interrupt processing, and communication interrupt processing. For this reason, the power consumption of the CPU 36 and thus the computing unit 33 can be reduced.

  In the present embodiment, as in the first embodiment described above, when performing the normal calculation, the filter calculation is performed using Formula 1 using the normal calculation coefficients (A, B0, B1, B2). When performing the decimation operation, the filter operation is performed using Equation 1 using the decimation operation coefficients (A, B0, B1, B2). Here, the thinning calculation coefficient and the normal calculation coefficient are set so as to constitute a filter having the same characteristic during normal calculation and during thinning calculation. Therefore, as in the first embodiment, the thinning calculation and the normal calculation can obtain the calculation result Yn of the filter calculation equivalent to the conventional one, although the frequency of the operation clock of the CPU 36 is different from each other.

  In the present embodiment, as in the first embodiment described above, when the count value K ≦ 0 of the operation counter, the magnitude of the output signal of the amplifier circuit 20 is changed from a state larger than the prescribed value to a state smaller than the prescribed value. Suppose that it has changed. That is, it is determined that the current sampling timing is in the falling period. Accordingly, a normal calculation is performed as a filter calculation. Therefore, it is possible to suppress the fluctuation of the calculation result Yn accompanying the decrease in the frequency of the CPU clock.

  In the present embodiment, as in the first embodiment described above, it is assumed that the current sampling timing is in the rising period when YES is determined in step S310 because the count value K ≧ 0 of the operation counter. In this case, Yn-3 and Yn-2 used when calculating the calculation result Yn of Formula 1 are set to the same value as Yn-1 by the setting process in step S320. Accordingly, it is possible to suppress the fluctuation of Yn by giving the influence of Yn-3 and Yn-2 to the filter characteristics substantially in the same manner as in the first embodiment described above. Note that the AD interrupt processing of this embodiment may be configured without using step S320 for the same reason as in the first embodiment described above.

(Other embodiments)
In the first embodiment described above, an example has been shown in which a time four times the filter processing period at the time of normal calculation is used as the filter processing period at the time of thinning calculation. As long as the period of the filtering process at the time of the thinning calculation is longer than the period, any time may be set as the period of the filtering process at the time of the thinning calculation.

  In the second embodiment described above, an example was shown in which the value fcpu / 4, which is a quarter of the frequency fcpu of the operation clock of the CPU 36 at the time of normal calculation, is used as the frequency of the operation clock of the CPU 36 at the time of decimation. Not limited to this, as long as the frequency of the operation clock of the CPU 36 during normal calculation is higher than the frequency of the operation clock of the CPU 36 during thinning calculation, what is the frequency of the operation clock of the CPU 36 during thinning calculation? It may be set to a value.

  In the first and second embodiments described above, when YES is determined in step 320, the calculation result buffer for Yn-1 is compared with the calculation result buffer for Yn-2 and the calculation result buffer for Yn-3 in step S320. In this example, the stored value is stored and Yn-2 and Yn-3 are set to the same value as Yn-1, and the filter calculation is performed. However, the present invention is not limited to this, and the processing of steps 320 and S320 may be deleted. Good.

  In the first embodiment described above, when the sampling value X is less than the specified value (when the amount of change in the acceleration of the automobile is small) and when the sampling value X is equal to or greater than the specified value (the amount of change in the acceleration of the automobile). In order to match the filter characteristics of the filter), the coefficient of the filter calculation formula is changed. Alternatively, the following may be used.

  That is, filter characteristics when the amount of change in acceleration is small (that is, suitable for a case where the acceleration changes slowly at several G or less during vehicle travel) and when the amount of change in acceleration changes greatly (that is, vehicle collision) It is also possible to set different filter characteristics (suitable when the acceleration of time changes rapidly).

  In the first embodiment described above, when the output signal X of the sensor element is equal to or greater than the specified value, the cycle for performing the filter operation is set to a short cycle, and when the output signal X of the sensor element is less than the specified value, the filter The example in which the cycle for performing the filter operation is changed in two stages by setting the cycle for performing the calculation to a long cycle has been described. However, the present invention is not limited to this, and the filter according to the sampling value X is used. You may make it change the period which performs a calculation in multiple steps | paragraphs of three steps or more.

  For example, in addition to a specified value (hereinafter referred to as a first specified value) set for determining whether the vehicle is traveling or a collision, a first value for determining whether or not the vehicle is stopped. A specified value of 2 (e.g., corresponding to acceleration 1G) is used.

  In the case of the above-described first embodiment, when the sampling value X is less than the second specified value, it is assumed that the vehicle is stopped, and the filter calculation cycle is made longer than when the vehicle is running and when the vehicle collides. Thus, the number of filter operations can be reduced and the power consumption can be further reduced.

  Also in the above-described second embodiment, the frequency of the operation clock of the CPU 36 may be changed in three or more stages according to the sampling value X.

  Specifically, when the sampling value X is less than the second specified value, it is assumed that the vehicle is stopped, and the frequency of the operation clock of the CPU 36 is further lowered as compared with the time when the vehicle is traveling and when the vehicle is colliding. Power consumption can be reduced.

In the first and second embodiments described above, the number of determinations used to determine whether or not the current sampling timing is within the falling period in step S230 is 3, and after the YES determination in step S210, the step The example in which it is determined whether or not the current sampling timing is within the falling period in step S230 has been described by determining whether or not the number of determinations for determining NO in S210 is less than 3. Not limited to this, it may be as follows:
That is, if the number of times of determination used to determine whether or not the current sampling timing is within the falling period in step S230 is a value of 1 or more, a value other than 3 may be used.

  In the first and second embodiments described above, the example in which the filter operation processing is performed using the product-sum operation unit 37 as a hardware circuit other than the CPU 36 has been described. However, the present invention is not limited thereto, and the CPU 36 performs the filter operation processing. You may make it implement.

  In the first and second embodiments described above, the example in which the filtered signal of the bandpass filter is calculated by the filter calculation using Formula 1, but instead of this, the low-pass filter or the filter signal by Formula 1 is used. You may make it calculate the filtration signal of various filters, such as a high pass filter.

  In the first embodiment described above, when the output signal of the amplifier circuit 20 (that is, the output signal of the sensor element) is less than the specified value, the digital filter process is repeatedly performed in a long cycle, and the magnitude of the output signal of the amplifier circuit 20 is increased. Although the example in which the digital filter process is repeatedly performed in a short period when the value is larger than the specified value has been described, the following may be used instead.

  When the change amount of the output signal of the amplifier circuit 20 (that is, the output signal of the sensor element) is less than the specified value, the digital filter process is repeatedly performed in a long cycle, and the change amount of the output signal of the amplifier circuit 20 is less than the specified value. When it is large, the digital filter processing may be repeatedly performed in a short cycle.

  Specifically, every time the AD converter 32 performs sampling, the CPU 36 calculates a difference between the current sampling value and the previous sampling value (= current sampling value−previous sampling value). It is determined whether or not is greater than a specified value. When it is determined that the difference is less than the specified value, the digital filter process is repeatedly performed with a long period. When it is determined that the difference is greater than the specified value, the digital filter process is repeatedly performed with a short period.

  The difference between the current sampling value and the previous sampling value is not limited to (current sampling value−previous sampling value), and the difference is (current sampling value−previous sampling value). (= | Current sampling value−previous sampling value |).

  In the second embodiment described above, the CPU 36 operates when the magnitude of the output signal of the amplifier circuit 20 is less than the specified value and when the magnitude of the output signal of the amplifier circuit 20 is greater than the specified value. Although an example of changing the clock frequency has been described, the following may be used instead.

  That is, each time the AD converter 32 performs sampling, the comparator 33a determines whether or not the difference between the current sampling value and the previous sampling value is greater than or equal to a specified value, and indicates the determination result. The result signal is output to the CPU 36.

  Here, every time the comparator 33a determines that the difference is greater than or equal to the specified value, the comparator 33a outputs a determination result signal indicating the determination result to the clock switch 31b. Along with this, when receiving the determination result signal, the clock switch 31b gives the first CPU clock to the CPU. That is, each time the comparator 33a determines that the difference is greater than or equal to the specified value, the comparator 33a sets the clock switch 31b so that the CPU 36 outputs the first CPU clock from the clock switch 31b. To control. Thereby, the frequency of the operation clock of the CPU 36 is set to the frequency of the first CPU clock.

  On the other hand, when the comparator 33a determines that the difference is less than the specified value, the comparator 33a outputs a determination result signal to the CPU 36. The CPU 36 controls the clock switch 31b so as to give the CPU a second clock lock from the clock switch 31b. Thereby, the frequency of the operation clock of the CPU 36 is set to the frequency of the second CPU clock.

  In the first and second embodiments described above, an example of calculating Yn using B0 · Yn-1, B1 · Yn-2, and B2 · Yn-3 in addition to A0 · X based on Equation 1 As described above, the present invention is not limited to this, and B · Yn−d obtained by multiplying the calculation result Yn−d (d is an integer) calculated prior to the nth calculation result Yn and the sampling value X is used. If so, the calculation result Yn may be obtained by any method, and the calculation result Yn is not limited to the use of Equation 1.

  In the first and second embodiments described above, the example in which the filtered signal of the bandpass filter is calculated by the filter calculation using Formula 1, but instead of this, the low-pass filter or the filter signal by Formula 1 is used. You may make it calculate the filtration signal of various filters, such as a high pass filter.

  In the first and second embodiments described above, an example in which an automobile sensor is used as the physical quantity sensor of the present invention has been described. However, instead of this, the present invention is applied to a sensor used in various devices such as a motorcycle other than an automobile. May be applied.

  In the first and second embodiments described above, an example is shown in which an acceleration sensor is used as the physical quantity sensor of the present invention. However, the present invention is not limited to this, and the present invention is applied to various sensors such as a temperature sensor and a humidity sensor. May be.

DESCRIPTION OF SYMBOLS 1 Acceleration sensor for motor vehicles 10 Sensor element 20 Amplification circuit 30 Control apparatus 30A Control apparatus 31 Low power consumption circuit 32 AD converter 33 Calculator 34 Communication circuit 35 Memory 36 CPU
37 multiply-add calculator 31a frequency divider 31b clock switcher 33a comparator 40 oscillator circuit

Claims (24)

A sensor element (10) for detecting a physical quantity to be detected;
An AD converter (32) for sampling the output signal of the sensor element at regular intervals;
Arithmetic means (S250) for repeatedly performing a filter operation for filtering the sampling value output from the AD converter;
Determination means (S210) for determining whether or not a sampling value output from the AD converter is a specified value or more,
When the determination means determines that the sampling value is less than a specified value, the calculation means repeatedly performs the filter calculation with a long period, and when the determination means determines that the sampling value is equal to or greater than a specified value The physical quantity sensor, wherein the calculation means repeatedly performs the filter calculation in a short cycle. Decreasing period determining means for determining whether or not the current sampling timing is within a falling period in which the sampling value output from the AD converter shifts from a state larger than the specified value to a smaller state (S230). With
When the falling period determining means determines that the current sampling timing is in the falling period, the calculating means repeatedly performs the filter calculation in a short cycle,
2. The filter unit according to claim 1, wherein when the falling period determining unit determines that the current sampling timing has finished the falling period, the calculating unit repeatedly performs the filter calculation with a long cycle. Physical quantity sensor. Each time the AD converter performs the sampling, the determination means determines whether or not the sampling value is a specified value or more,
The descent period determining means (S230) is less than a predetermined number of times that the determining means determines that the sampling value is less than a specified value after the determining means determines that the sampling value is greater than or equal to a specified value. The physical quantity sensor according to claim 2, wherein it is determined whether or not the current sampling timing is within the falling period by determining whether or not the current sampling timing is within the falling period. The calculation result of the nth filter operation is Yn, the calculation result of the (n-1) th filter operation calculated before the nth filter operation is Yn-1, and the (n-1) th filter operation result. The calculation result of the (n−S) -th filter operation that is calculated prior to the filter operation is Yn−S,
When the sampling value is X, the coefficient for multiplying X is A0, the coefficient for multiplying Yn-1 is B0, and the coefficient for multiplying Yn-S is BS,
The calculation means calculates Yn using A0 · X, B0 · Yn-1, and BS · Yn-S,
Rising period determination means for determining whether or not the current sampling timing is within a rising period in which the sampling value output from the AD converter shifts from a state smaller than the specified value to a larger state (S310) With
When the rising period determining means determines that the current sampling timing is within the rising period, the calculating means calculates Yn by setting Yn-S to the same value as Yn-1. The physical quantity sensor according to claim 1, wherein: Each time the AD converter performs the sampling, the determination means determines whether or not the sampling value is a specified value or more,
The rising period determination means (S310), when the determination means determines that the sampling value is less than a specified value prior to the determination means determining that the current sampling value is greater than or equal to a specified value. Is that the sampling timing of this time is within the rising period,
The rising period determination means (S310), when the determination means determines that the sampling value is equal to or greater than a specified value prior to the determination means determining that the current sampling value is equal to or greater than a specified value. The physical quantity sensor according to claim 4, wherein the sampling timing of the current time has finished the falling period. A sensor element (10) for detecting a physical quantity to be detected;
An AD converter (32) for sampling the output signal of the sensor element at regular intervals;
A calculation means (S250) for repeatedly performing a filter calculation for filtering the sampling value output from the AD converter;
Determining means (S210) for determining whether or not a difference between a sampling value output from the AD converter and a sampling value output last time from the AD converter is a specified value or more;
When the determination means determines that the difference is less than a specified value, the calculation means repeatedly performs the filter calculation in a long cycle, and when the determination means determines that the difference is equal to or greater than a specified value, A physical quantity sensor, wherein the calculation means repeatedly performs the filter calculation in a short cycle. Decrease based on the sampling value output from the AD converter to determine whether or not the current sampling timing is within the falling period in which the difference shifts from a state larger than the specified value to a smaller state Period determining means (S230),
When the falling period determining means determines that the current sampling timing is in the falling period, the calculating means repeatedly performs the filter calculation in a short cycle,
7. The filter unit according to claim 6, wherein when the falling period determination unit determines that the current sampling timing has finished the falling period, the calculation unit repeatedly performs the filter calculation with a long cycle. Physical quantity sensor. Each time the AD converter samples the output signal of the sensor element, the determination means determines whether or not the difference is a specified value or more,
The descent period determining means (S230) determines whether or not the number of times the determining means determines that the difference is less than a specified value after the determining means determines that the difference is greater than or equal to a specified value. The physical quantity sensor according to claim 7, wherein it is determined whether or not the current sampling timing is within the falling period. The calculation result of the nth filter operation is Yn, the calculation result of the (n-1) th filter operation calculated before the nth filter operation is Yn-1, and the (n-1) th filter operation result. The calculation result of the (n−S) -th filter operation that is calculated prior to the filter operation is Yn−S,
When the sampling value is X, the coefficient for multiplying X is A0, the coefficient for multiplying Yn-1 is B0, and the coefficient for multiplying Yn-S is BS,
The calculation means calculates Yn using A0 · X, B0 · Yn-1, and BS · Yn-S,
A rising period determining means (S310) for determining whether or not the current sampling timing is within a rising period in which the difference shifts from a state smaller than the specified value to a larger state;
When the rising period determining means determines that the current sampling timing is within the rising period, the calculating means calculates Yn by setting Yn-S to the same value as Yn-1. The physical quantity sensor according to claim 6, wherein: Each time the AD converter performs the sampling, the determination means determines whether or not the difference is a specified value or more,
If the determination means determines that the difference is less than a specified value prior to the determination means determining that the difference is greater than or equal to a specified value, the rising period determination means (S310) The sampling timing is within the rising period,
The rising period determining means (S310), when the determining means determines that the difference is equal to or greater than a specified value prior to the determination means determining that the current difference is equal to or greater than a specified value. The physical quantity sensor according to claim 9, wherein the sampling timing of the current time ends the falling period. Each time the AD converter (32) performs the sampling, the calculation means performs the filter calculation, so that the calculation means performs the filter calculation in a short cycle,
Each time the AD converter (32) performs the sampling a plurality of times, the calculation means performs the filter calculation one time, so that the calculation means performs the filter calculation in a long cycle. The physical quantity sensor according to any one of claims 1 to 10. The calculation result of the nth filter calculation is Yn, the calculation result of the (n−d) th filter calculation calculated prior to the nth filter calculation is Yn−d,
When the sampling value is X, the coefficient for multiplying X is A0, and the coefficient for multiplying Yn-d is B,
The calculating means calculates Yn using A0 · X and B · Yn-d,
When the calculation means performs the filter calculation with a long period and when the calculation means performs the filter calculation with a short period, the calculation means is configured so that the filter characteristics of the filter calculation are the same. 9. A physical quantity sensor according to claim 1, wherein A0 and B as the coefficients used in the filter calculation are switched. A sensor element (10) for detecting a physical quantity to be detected;
An AD converter (32) for sampling the output signal of the sensor element at regular intervals;
Clock generation means (31b) for outputting any one of a first clock and a second clock having a frequency lower than the first clock;
Comparing means (33a) for determining whether or not the sampling value output from the AD converter is equal to or greater than a specified value;
A CPU (36) that operates using the clock output from the clock generation means as an operation clock and repeatedly performs a filter operation for filtering the sampling value output from the AD converter;
When the comparison means (33a) determines that the sampling value is equal to or greater than a specified value, the comparison means sets the frequency of the clock supplied from the clock generation means to the CPU as the frequency of the first clock. And
When the comparison means (33a) determines that the sampling value is less than the specified value, the comparison means outputs a determination result signal indicating that the sampling value is determined to be less than the specified value to the CPU. The physical quantity sensor is characterized in that the frequency of the clock that the CPU gives to the CPU itself from the clock generation means is set to the frequency of the second clock. The CPU determines whether or not the current sampling timing is within a falling period in which the sampling value output from the AD converter shifts from a state larger than the specified value to a smaller state. ,
When the CPU determines that the current sampling timing is in the falling period, the clock frequency supplied from the clock generation means to the CPU is maintained at the frequency of the first clock. And
When the CPU determines that the current sampling timing has finished the falling period, the CPU sets the frequency of the clock supplied from the clock generation means to the CPU itself as the frequency of the second clock. The physical quantity sensor according to claim 13, wherein Each time the AD converter performs the sampling, the comparing means determines whether or not the sampling value is a specified value or more,
The CPU determines whether or not the number of times the comparison unit has determined that the sampling value is less than a predetermined value after the comparison unit has determined that the sampling value is greater than or equal to a predetermined value. The physical quantity sensor according to claim 14, wherein it is determined whether or not the timing of the current sampling is within the falling period. The calculation result of the nth filter operation is Yn, the calculation result of the (n-1) th filter operation calculated before the nth filter operation is Yn-1, and the (n-1) th filter operation result. The calculation result of the (n−S) -th filter operation that is calculated prior to the filter operation is Yn−S,
When the sampling value is X, the coefficient for multiplying X is A0, the coefficient for multiplying Yn-1 is B0, and the coefficient for multiplying Yn-S is BS,
The CPU calculates Yn using A0 · X, B0 · Yn-1, and BS · Yn-S,
The CPU determines whether or not the current sampling timing is within a rising period in which the sampling value output from the AD converter shifts from a state smaller than the specified value to a larger state. ,
When the CPU determines that the current sampling timing is within the rising period, the CPU calculates Yn by setting Yn-S to the same value as Yn-1. The physical quantity sensor according to claim 13. Each time the AD converter performs the sampling, the comparing means determines whether or not the sampling value is a specified value or more,
If the CPU determines that the sampling value is less than the specified value prior to determining that the current sampling value is greater than or equal to the specified value, the timing of the current sampling is within the rising period. And
If the CPU determines that the sampling value is equal to or greater than a specified value prior to determining that the current sampling value is equal to or greater than a specified value, the timing of the current sampling indicates the rising period. The physical quantity sensor according to claim 16, wherein the physical quantity sensor is finished. A sensor element (10) for detecting a physical quantity to be detected;
An AD converter (32) for sampling the output signal of the sensor element at regular intervals;
Clock generation means (31b) for outputting any one of a first clock and a second clock having a frequency lower than the first clock;
Comparison means (33a) for determining whether or not a difference between a sampling value output from the AD converter and a sampling value output last time from the AD converter is equal to or greater than a specified value;
A CPU (36) that operates using the clock output from the clock generation means as an operation clock and repeatedly performs a filter operation for filtering the sampling value output from the AD converter;
When the comparison means determines that the difference is equal to or greater than a specified value, the comparison means sets the frequency of the clock supplied from the clock generation means to the CPU as the frequency of the first clock. And
When the comparison means determines that the difference is less than a specified value, the comparison means outputs a determination result signal indicating that the difference is less than a specified value to the CPU, and the CPU A physical quantity sensor characterized in that a frequency of a clock given from the clock generation means to the CPU itself is set to a frequency of the second clock. The CPU determines whether or not the current sampling timing is within a falling period in which the difference shifts from a state larger than the specified value to a smaller state based on a sampling value output from the AD converter. Is determined,
When the CPU determines that the current sampling timing is in the falling period, the clock frequency supplied from the clock generation means to the CPU is maintained at the frequency of the first clock. And
When the falling period determining means determines that the current sampling timing has finished the falling period, the frequency of the clock that the CPU gives to the CPU itself from the clock generating means is set to the frequency of the second clock. The physical quantity sensor according to claim 18, wherein the physical quantity sensor is set. Each time the AD converter performs the sampling, the comparison means determines the difference and the specified value,
The CPU determines whether or not the number of times the comparison unit has determined that the difference is less than a specified value after the comparison unit has determined that the difference is greater than or equal to a specified value is less than a predetermined number. 20. The method according to claim 19, wherein it is determined whether or not the current sampling timing is within a falling period in which the difference shifts from a state larger than the specified value to a smaller state. The physical quantity sensor described. The calculation result of the nth filter operation is Yn, the calculation result of the (n-1) th filter operation calculated before the nth filter operation is Yn-1, and the (n-1) th filter operation result. The calculation result of the (n−S) -th filter operation that is calculated prior to the filter operation is Yn−S,
When the sampling value is X, the coefficient for multiplying X is A0, the coefficient for multiplying Yn-1 is B0, and the coefficient for multiplying Yn-S is BS,
The CPU calculates Yn using A0 · X, B0 · Yn-1, and BS · Yn-S,
The CPU determines whether or not the current sampling timing is within a rising period in which the difference shifts from a state smaller than the specified value to a larger state,
When the CPU determines that the current sampling timing is within the rising period, the CPU calculates Yn by setting Yn-S to the same value as Yn-1. The physical quantity sensor according to claim 18. Each time the AD converter performs the sampling, the comparing means determines whether or not the difference is a specified value or more,
If the CPU determines that the difference is less than the specified value prior to determining that the difference is greater than or equal to the specified value, the sampling timing of the current time is within the rising period. age,
If the CPU determines that the difference is greater than or equal to a specified value prior to determining that the current difference is greater than or equal to a specified value, the timing of the current sampling ends the rising period. The physical quantity sensor according to claim 21, wherein The calculation result of the nth filter calculation is Yn, the calculation result of the (n−d) th filter calculation calculated prior to the nth filter calculation is Yn−d,
When the sampling value is X, the coefficient for multiplying X is A0, and the coefficient for multiplying Yn-d is B,
The CPU calculates Yn using A0 · X and B · Yn-d,
When the frequency of the clock given from the clock generation means to the CPU is set to the frequency of the first clock, the frequency of the clock given from the clock generation means to the CPU is the frequency of the second clock 14. The CPU is configured to switch between A0 and B as coefficients used in the filter calculation so that the filter characteristics of the filter calculation are the same when set to. Thru | or 15, the physical quantity sensor as described in any one of 18 thru | or 20. When the frequency of the operation clock of the CPU is set to the frequency of the second clock by the clock generation means, the CPU performs one filtering operation in a distributed manner. Item 24. The physical quantity sensor according to any one of Items 13 to 23 .

Images