JP5397195B2 - Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device - Google Patents

Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device Download PDF

Info

Publication number
JP5397195B2
JP5397195B2 JP2009274567A JP2009274567A JP5397195B2 JP 5397195 B2 JP5397195 B2 JP 5397195B2 JP 2009274567 A JP2009274567 A JP 2009274567A JP 2009274567 A JP2009274567 A JP 2009274567A JP 5397195 B2 JP5397195 B2 JP 5397195B2
Authority
JP
Japan
Prior art keywords
optical semiconductor
semiconductor element
wiring member
adhesive film
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009274567A
Other languages
Japanese (ja)
Other versions
JP2011119393A (en
Inventor
勇人 小谷
直之 浦崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Showa Denko Materials Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP2009274567A priority Critical patent/JP5397195B2/en
Publication of JP2011119393A publication Critical patent/JP2011119393A/en
Application granted granted Critical
Publication of JP5397195B2 publication Critical patent/JP5397195B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

本発明は、光半導体素子搭載用基板及びその製造方法、並びに、光半導体装置及びその製造方法に関する。   The present invention relates to an optical semiconductor element mounting substrate and a manufacturing method thereof, and an optical semiconductor device and a manufacturing method thereof.

電子機器は小型・軽量・高性能・多機能化が進み、電子機器に使用される電子部品は高密度に実装されることが望まれている。このような電子部品は、プリント基板上に配置される表面実装部品(SMD:surface mount device)としたものが多く、リフローはんだ付け等によりプリント基板上の配線パターンに接続される(例えば、特許文献1参照)。   Electronic devices are becoming smaller, lighter, higher performance, and multifunctional, and electronic components used in electronic devices are desired to be mounted with high density. Many of such electronic components are surface mount devices (SMD) arranged on a printed circuit board, and are connected to a wiring pattern on the printed circuit board by reflow soldering (for example, Patent Documents). 1).

電子部品の一例として、LED(Light Emitting Diode:発光ダイオード)は、例えば光半導体素子と蛍光体とを組み合わせた光半導体装置であり、省電力で寿命が長い発光装置として注目されている。また、CCD(Charge Coupled Device:電荷結合素子)イメージセンサや、CMOS(Complementary Metal Oxide Semiconductor:相補性金属酸化膜半導体)等の固体撮像デバイスは、レンズを介して形成された光信号の像を電気信号に変換する装置としてテレビカメラやデジタルカメラに適用されている。   As an example of an electronic component, an LED (Light Emitting Diode) is an optical semiconductor device that combines, for example, an optical semiconductor element and a phosphor, and has attracted attention as a light-emitting device that has low power consumption and long life. In addition, solid-state imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) electrically convert an image of an optical signal formed through a lens. It is applied to television cameras and digital cameras as devices that convert signals.

光半導体装置では、光半導体素子を搭載する基板として、所定の形状を有する成形体がトランスファーモールドによりプリモールドされた基板が用いられている。このような成形体は、光半導体素子を実装する実装面が露出するように成形されている。また、LED等の光半導体装置の製造方法として、近年、外部接続用のリード端子がパッケージ内部に取り込まれた形態のパッケージが小型化及び高集積化の観点から特に注目されている。   In an optical semiconductor device, a substrate on which a molded body having a predetermined shape is pre-molded by transfer molding is used as a substrate on which an optical semiconductor element is mounted. Such a molded body is molded such that the mounting surface on which the optical semiconductor element is mounted is exposed. In recent years, as a method for manufacturing an optical semiconductor device such as an LED, a package in which lead terminals for external connection are taken into the package has attracted particular attention from the viewpoint of miniaturization and high integration.

光半導体素子搭載用基板としては、QFN(Quad Flat Nonleaded package)と呼ばれる形態が検討されている。QFNの製造方法としては、複数のQFNを一括成形した後に個片化するMAP(Mold array package)成形が特に注目されている。MAP成形では、パターン描画したリードフレームにおける凹部内の露出した実装面(光半導体素子搭載領域)上に複数の光半導体素子を配列し、光半導体素子を透明樹脂で一括封止した後、切断によって個別のQFN型パッケージに切り分けることにより、複数のQFNを得る。MAP成形により、リードフレームあたりの生産性を飛躍的に向上させることができる。   As a substrate for mounting an optical semiconductor element, a form called QFN (Quad Flat Nonleaded package) has been studied. As a QFN manufacturing method, MAP (Mold array package) molding, in which a plurality of QFNs are collectively molded and then separated into individual pieces, has attracted particular attention. In MAP molding, a plurality of optical semiconductor elements are arranged on an exposed mounting surface (optical semiconductor element mounting region) in a recess in a patterned lead frame, the optical semiconductor elements are collectively sealed with a transparent resin, and then cut. A plurality of QFNs are obtained by dividing into individual QFN type packages. By MAP molding, productivity per lead frame can be dramatically improved.

また、複数の光半導体素子搭載領域を有するリードフレーム上に、成形体をトランスファー成形して片面モールドすることが知られている(例えば、特許文献2参照)。成形体の材料としては、リードフレーム等の配線部材との接着力に優れる熱硬化性樹脂組成物が用いられている。   In addition, it is known that a molded body is transfer-molded on a lead frame having a plurality of optical semiconductor element mounting regions and is single-sided molded (see, for example, Patent Document 2). As the material of the molded body, a thermosetting resin composition having excellent adhesive strength with a wiring member such as a lead frame is used.

特開2003−218398号公報JP 2003-218398 A 特開平11−126785号公報JP-A-11-126785

しかしながら、このような従来の光半導体素子搭載用基板(プリモールド型パッケージ)の製造方法では、金型を用いてトランスファーモールドにより成形体を成形するに際し、光半導体素子搭載領域と、これに対向する金型の表面との隙間に熱硬化性樹脂組成物のフラッシュ等の汚れが発生し、光半導体素子とリードフレーム等の配線部材との接着強度の低下や導通不良等の接続不良が発生する。このような接続不良を抑制するため、ウェットブラストやプラズマ処理等のバリ取り工程を行なうことも可能であるが、工程数の増加や、工程中に成形物が破損して歩留まりが悪化してしまい、光半導体装置の生産性が低下してしまう。   However, in such a conventional method for manufacturing a substrate for mounting an optical semiconductor element (pre-molded package), when forming a molded body by transfer molding using a mold, the optical semiconductor element mounting region faces the area. Contamination such as flashing of the thermosetting resin composition occurs in the gap with the surface of the mold, resulting in poor connection strength between the optical semiconductor element and a wiring member such as a lead frame and poor connection such as poor conduction. In order to suppress such connection failure, it is possible to perform a deburring process such as wet blasting or plasma processing, but the number of processes increases or the molded product is damaged during the process, resulting in a deterioration in yield. The productivity of the optical semiconductor device is reduced.

また、リードフレーム上にトランスファー成形で片面モールドする方法では、マトリックス状の大型(例えば、20mm角以上)の成形物を一体成形した場合、加熱を施すと樹脂成形体と配線部材との間の線膨張率の相違に起因して応力が発生してしまう。これにより、光半導体素子搭載用基板に反りが発生してしまい、その後の工程を進めることが困難となるため、光半導体装置の生産性が低下してしまう。   Also, in the method of single-sided molding on the lead frame by transfer molding, when a matrix-like large-sized molded product (for example, 20 mm square or more) is integrally molded, the wire between the resin molded body and the wiring member when heated Stress is generated due to the difference in expansion coefficient. As a result, the optical semiconductor element mounting substrate is warped, and it is difficult to proceed with the subsequent steps, so that the productivity of the optical semiconductor device is lowered.

本発明は上記課題を解決するためになされたものであり、生産性の低下を抑制しつつ、光半導体素子の接続不良や基板の反りの発生を抑制することが可能な光半導体素子搭載用基板及びその製造方法、並びに、光半導体装置及びその製造方法を提供することを目的とする。   The present invention has been made in order to solve the above-described problems, and an optical semiconductor element mounting substrate capable of suppressing the occurrence of poor connection of an optical semiconductor element and the warpage of the substrate while suppressing a decrease in productivity. An object of the present invention is to provide an optical semiconductor device and a manufacturing method thereof.

本発明は、熱硬化性樹脂組成物が充填される凹部と、成形体において光半導体素子が配置されるキャビティ部となる凸部と、を有する金型を用いた光半導体素子搭載用基板の製造方法であって、光半導体素子が配置される素子配置領域を一方面に有する配線部材の他方面同士を接着フィルムを介して対向させる配線部材配置工程と、凸部が素子配置領域に当接するように、配線部材及び接着フィルムを介して一対の金型を互いに対向させる金型配置工程と、凹部に熱硬化性樹脂組成物を充填し、トランスファー成形により配線部材の一方面上に成形体を形成する成形体形成工程と、を備える。   The present invention relates to an optical semiconductor element mounting substrate using a mold having a concave portion filled with a thermosetting resin composition and a convex portion serving as a cavity in which an optical semiconductor element is disposed in a molded body. A wiring member placement step in which the other surface of the wiring member having an element placement region on one side where the optical semiconductor element is placed is opposed to each other via an adhesive film; and the convex portion is in contact with the element placement region In addition, a mold placement step in which a pair of molds face each other via a wiring member and an adhesive film, and a thermosetting resin composition is filled in the recess, and a molded body is formed on one surface of the wiring member by transfer molding A formed body forming step.

本発明に係る光半導体素子搭載用基板の製造方法では、配線部材の他方面同士を接着フィルムを介して対向させ、更に、金型の凸部が素子配置領域に当接するように、配線部材及び接着フィルムを介して一対の金型を互いに対向させた上で、配線部材の一方面上に成形体を形成している。これにより、接着フィルムを介して対向するそれぞれの配線部材が、上記一方面側から金型及び成形体(熱硬化性樹脂組成物)によって接着フィルム側に向かって押圧されることとなり、成形体(熱硬化性樹脂組成物)と配線部材との線膨脹係数の相違に起因して生じる応力が相殺されて緩和される。このような応力の緩和によって光半導体素子搭載用基板における反りの発生を抑制することが可能であり、生産性の低下を抑制することができる。また、このように光半導体素子搭載用基板の変形が抑制されると共に、金型の凸部が配線部材の素子配置領域に当接するように一対の金型を対向させるため、配線部材と金型との間における汚れの発生が抑制される。これにより、汚れを除去する工程を別途要することなく、生産性の低下を抑制しつつ光半導体素子と配線部材との接続不良を抑制することができる。   In the method for manufacturing a substrate for mounting an optical semiconductor element according to the present invention, the wiring member and the other side of the wiring member are opposed to each other through an adhesive film, and the convex portion of the mold is in contact with the element arrangement region. A molded body is formed on one surface of the wiring member with a pair of molds opposed to each other via an adhesive film. Thereby, each wiring member which opposes via an adhesive film will be pressed toward the adhesive film side by the metal mold | die and a molded object (thermosetting resin composition) from the said one surface side, and a molded object ( The stress caused by the difference in coefficient of linear expansion between the thermosetting resin composition) and the wiring member is offset and relaxed. Such relaxation of stress can suppress the occurrence of warpage in the substrate for mounting an optical semiconductor element, and can suppress a decrease in productivity. Further, since the deformation of the substrate for mounting the optical semiconductor element is suppressed in this way and the pair of molds are opposed so that the convex part of the mold is in contact with the element arrangement region of the wiring member, the wiring member and the mold The occurrence of dirt between the two is suppressed. Thereby, the connection defect of an optical semiconductor element and a wiring member can be suppressed, suppressing the fall of productivity, without requiring the process of removing dirt separately.

本発明に係る光半導体素子搭載用基板の製造方法は、配線部材配置工程の前に、配線部材のそれぞれの上記他方面に接着フィルムの一方面を接着するフィルム接着工程を備え、配線部材配置工程において、接着フィルムの他方面同士を貼り合わせることが好ましい。この場合、生産性の低下を更に抑制しつつ、光半導体素子の接続不良や基板の反りの発生を更に抑制することができる。   The method for manufacturing an optical semiconductor element mounting substrate according to the present invention includes a film adhering step of adhering one surface of an adhesive film to each of the other surfaces of the wiring member before the wiring member arranging step, and the wiring member arranging step. It is preferable that the other surfaces of the adhesive film are bonded together. In this case, generation | occurrence | production of the connection defect of an optical semiconductor element and the curvature of a board | substrate can further be suppressed, suppressing further the fall of productivity.

本発明に係る光半導体素子搭載用基板の製造方法は、配線部材配置工程の前に、配線部材のそれぞれの上記他方面を接着フィルムの同一面に接着するフィルム接着工程を備え、配線部材配置工程において、接着フィルムを折り返して配線部材の他方面同士を接着フィルムを介して対向させることが好ましい。この場合、生産性の低下を更に抑制しつつ、光半導体素子の接続不良や基板の反りの発生を更に抑制することができる。   The method for manufacturing an optical semiconductor element mounting substrate according to the present invention includes a film adhering step for adhering the other surface of each of the wiring members to the same surface of the adhesive film before the wiring member arranging step. It is preferable that the adhesive film is folded back so that the other surfaces of the wiring members are opposed to each other with the adhesive film interposed therebetween. In this case, generation | occurrence | production of the connection defect of an optical semiconductor element and the curvature of a board | substrate can further be suppressed, suppressing further the fall of productivity.

本発明に係る光半導体素子搭載用基板の製造方法は、配線部材配置工程において、両面が接着性を有する接着フィルムの両面のそれぞれに配線部材の上記他方面を接着することが好ましい。この場合、生産性の低下を更に抑制しつつ、光半導体素子の接続不良や基板の反りの発生を更に抑制することができる。   In the method for manufacturing an optical semiconductor element mounting substrate according to the present invention, in the wiring member arranging step, it is preferable that the other surface of the wiring member is bonded to each of both surfaces of the adhesive film having adhesiveness on both surfaces. In this case, generation | occurrence | production of the connection defect of an optical semiconductor element and the curvature of a board | substrate can further be suppressed, suppressing further the fall of productivity.

本発明に係る光半導体素子搭載用基板は、上記光半導体素子搭載用基板の製造方法により製造され、成形体には、キャビティ部が複数形成されており、光反射性を有する熱硬化性樹脂組成物によりキャビティ部の少なくとも内周側面が形成されている。   A substrate for mounting an optical semiconductor element according to the present invention is manufactured by the above-described method for manufacturing a substrate for mounting an optical semiconductor element, the molded body has a plurality of cavity portions, and a thermosetting resin composition having light reflectivity. At least the inner peripheral side surface of the cavity portion is formed by the object.

本発明に係る光半導体素子搭載用基板では、上記光半導体素子搭載用基板の製造方法により製造されることから、生産性の低下を抑制しつつ、光半導体素子の接続不良や基板の反りの発生を抑制することができる。   Since the optical semiconductor element mounting substrate according to the present invention is manufactured by the above-described optical semiconductor element mounting substrate manufacturing method, the optical semiconductor element connection failure and the warpage of the substrate occur while suppressing the decrease in productivity. Can be suppressed.

本発明に係る光半導体装置の製造方法は、上記光半導体素子搭載用基板のキャビティ部内のそれぞれに光半導体素子を配置する光半導体素子配置工程と、光半導体素子を覆うようにキャビティ部に透光性を有する封止樹脂を充填する封止樹脂充填工程と、成形体をキャビティ部毎に分割して複数の光半導体装置を得る分割工程と、を備える。   An optical semiconductor device manufacturing method according to the present invention includes: an optical semiconductor element disposing step of disposing an optical semiconductor element in each of the cavity portions of the optical semiconductor element mounting substrate; and transmitting light to the cavity portion so as to cover the optical semiconductor element. A sealing resin filling step of filling a sealing resin having a property, and a dividing step of obtaining a plurality of optical semiconductor devices by dividing the molded body for each cavity portion.

本発明に係る光半導体装置の製造方法では、上記光半導体素子搭載用基板を用いていることから、生産性の低下を抑制しつつ、光半導体素子の接続不良や基板の反りの発生を抑制することができる。   In the method of manufacturing an optical semiconductor device according to the present invention, since the optical semiconductor element mounting substrate is used, the optical semiconductor element connection failure and the occurrence of warping of the substrate are suppressed while suppressing a decrease in productivity. be able to.

分割工程では、ダイシングにより成形体を分割することが好ましい。この場合、成形体を生産性良く分割することができる。   In the dividing step, it is preferable to divide the formed body by dicing. In this case, the molded body can be divided with high productivity.

本発明に係る光半導体装置は、上記光半導体装置の製造方法により製造される。   The optical semiconductor device according to the present invention is manufactured by the above-described method for manufacturing an optical semiconductor device.

本発明に係る光半導体装置では、上記光半導体装置の製造方法により製造されることにより、生産性の低下を抑制しつつ、光半導体素子の接続不良や基板の反りの発生を抑制することができる。   In the optical semiconductor device according to the present invention, the optical semiconductor device is manufactured by the method for manufacturing an optical semiconductor device, so that it is possible to suppress the occurrence of poor connection of the optical semiconductor element and the warpage of the substrate while suppressing the decrease in productivity. .

本発明によれば、生産性の低下を抑制しつつ、光半導体素子の接続不良や基板の反りの発生を抑制することが可能な光半導体素子搭載用基板及びその製造方法、並びに、光半導体装置及びその製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the optical semiconductor element mounting board | substrate which can suppress generation | occurrence | production of the connection failure of an optical semiconductor element, and generation | occurrence | production of the curvature of a board | substrate, suppressing the fall of productivity, and its optical semiconductor device And a manufacturing method thereof.

本発明に係る光半導体装置の一実施形態を示す斜視図である。1 is a perspective view showing an embodiment of an optical semiconductor device according to the present invention. 本発明に係る光半導体装置の一実施形態を示す模式断面図である。1 is a schematic cross-sectional view showing an embodiment of an optical semiconductor device according to the present invention. 本発明に係る光半導体装置の他の一実施形態を示す模式断面図である。It is a schematic cross section which shows other one Embodiment of the optical semiconductor device which concerns on this invention. 本発明に係る光半導体装置の製造方法の一実施形態を示す模式断面図である。It is a schematic cross section which shows one Embodiment of the manufacturing method of the optical semiconductor device which concerns on this invention. 本発明に係る光半導体装置の製造方法の一実施形態を示す模式断面図である。It is a schematic cross section which shows one Embodiment of the manufacturing method of the optical semiconductor device which concerns on this invention. 本発明に係る光半導体装置の製造方法の一実施形態を示す模式断面図である。It is a schematic cross section which shows one Embodiment of the manufacturing method of the optical semiconductor device which concerns on this invention. 本発明に係る光半導体装置の製造方法の一実施形態を示す模式断面図である。It is a schematic cross section which shows one Embodiment of the manufacturing method of the optical semiconductor device which concerns on this invention. 本発明に係る光半導体装置の製造方法の他の一実施形態を示す模式断面図である。It is a schematic cross section which shows other one Embodiment of the manufacturing method of the optical semiconductor device which concerns on this invention. 本発明に係る光半導体装置の製造方法の他の一実施形態を示す模式断面図である。It is a schematic cross section which shows other one Embodiment of the manufacturing method of the optical semiconductor device which concerns on this invention.

以下、必要に応じて図面を参照しつつ、本発明の好適な実施形態について詳細に説明する。なお、図面中、同一要素には同一符号を付すこととし、重複する説明は省略する。更に、図面の寸法比率は図示の比率に限られるものではない。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings as necessary. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

(光半導体装置)
図1は、本発明に係る光半導体装置の一実施形態を示す斜視図である。図2は、本発明に係る光半導体装置の一実施形態を示す模式断面図である。図3は、本発明に係る光半導体装置の他の一実施形態を示す模式断面図である。
(Optical semiconductor device)
FIG. 1 is a perspective view showing an embodiment of an optical semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional view showing an embodiment of an optical semiconductor device according to the present invention. FIG. 3 is a schematic cross-sectional view showing another embodiment of the optical semiconductor device according to the present invention.

図1,2に示すように、光半導体装置100は、光半導体素子搭載用基板10と、光半導体素子20と、封止樹脂部30とを備える。なお、図1では、封止樹脂部30の図示を省略している。   As shown in FIGS. 1 and 2, the optical semiconductor device 100 includes an optical semiconductor element mounting substrate 10, an optical semiconductor element 20, and a sealing resin portion 30. In addition, illustration of the sealing resin part 30 is abbreviate | omitted in FIG.

光半導体素子搭載用基板10は、プリモールド型パッケージ用基板であり、表面(一方面)12a及び表面12aと反対側の裏面(他方面)12bを有する配線部材12と、配線部材12の表面12a上に配置されたリフレクター(光反射層)14とを備える。   The optical semiconductor element mounting substrate 10 is a pre-molded package substrate, and includes a wiring member 12 having a front surface (one surface) 12a and a back surface (other surface) 12b opposite to the front surface 12a, and a front surface 12a of the wiring member 12. And a reflector (light reflecting layer) 14 disposed thereon.

配線部材12としては、特に限定されないが、リードフレーム、プリント配線板、フレキシブル配線板及びメタルベース配線板から選ばれる少なくとも1種を使用することができる。リードフレームは、銅や42アロイ等の基板に公知の手法を用いて回路を形成することにより得ることができる。   Although it does not specifically limit as the wiring member 12, At least 1 sort (s) chosen from a lead frame, a printed wiring board, a flexible wiring board, and a metal base wiring board can be used. The lead frame can be obtained by forming a circuit on a substrate such as copper or 42 alloy using a known method.

配線部材12は、例えば一対の配線部分からなり、当該配線部分同士のライン間が熱硬化性樹脂組成物の硬化物層16で埋められた平板構造を有している。LED等の発光装置の場合、配線部分の表面上には、光半導体素子20からの光を効率よく反射できるように、例えば銀めっきやニッケル/銀めっきにより導体層18a,18bが形成されていることが好ましい。導体層18aは、一方の配線部分上に形成されており、導体層18bは、他方の配線部分上に形成されている。   The wiring member 12 includes, for example, a pair of wiring portions, and has a flat plate structure in which a line between the wiring portions is filled with a cured product layer 16 of a thermosetting resin composition. In the case of a light emitting device such as an LED, conductor layers 18a and 18b are formed on the surface of the wiring portion by, for example, silver plating or nickel / silver plating so that the light from the optical semiconductor element 20 can be efficiently reflected. It is preferable. The conductor layer 18a is formed on one wiring portion, and the conductor layer 18b is formed on the other wiring portion.

リフレクター14は、板状の成形体であり、表面から裏面にかけて中央に一つの貫通孔が形成されている。光半導体素子搭載用基板10では、リフレクター14の貫通孔が配線部材12に塞がれることによりキャビティ部(凹部)14aが形成されている。キャビティ部14aの底面に位置する表面12a上の領域は、光半導体素子搭載領域(素子搭載領域)となる。   The reflector 14 is a plate-like molded body, and one through hole is formed in the center from the front surface to the back surface. In the optical semiconductor element mounting substrate 10, a cavity (recess) 14 a is formed by closing the through hole of the reflector 14 with the wiring member 12. A region on the surface 12a located on the bottom surface of the cavity portion 14a is an optical semiconductor element mounting region (element mounting region).

リフレクター14は、光反射性を有する熱硬化性樹脂組成物の硬化物を含む。リフレクター14は、光反射性を有する熱硬化性樹脂組成物により全体が形成されていることが好ましいが、キャビティ部14aの少なくとも内周側面が光反射性を有する熱硬化性樹脂組成物により形成されていればよい。光反射性を有する熱硬化性樹脂組成物は、例えば、(A)エポキシ樹脂、(B)硬化剤及び(C)硬化促進剤を含む熱硬化性樹脂と、(D)無機充填材と、(E)白色顔料と、(F)カップリング剤とを混融、混練して得られる樹脂組成物である。   The reflector 14 includes a cured product of a thermosetting resin composition having light reflectivity. The reflector 14 is preferably formed entirely by a light-reflective thermosetting resin composition, but at least the inner peripheral side surface of the cavity portion 14a is formed by a light-reflective thermosetting resin composition. It only has to be. The thermosetting resin composition having light reflectivity includes, for example, (A) an epoxy resin, (B) a curing agent and (C) a thermosetting resin containing a curing accelerator, (D) an inorganic filler, E) A resin composition obtained by mixing and kneading a white pigment and (F) a coupling agent.

上記(A)エポキシ樹脂としては、電子部品封止用のエポキシ樹脂成形材料として一般に使用されているものであれば特に限定されるものではない。(A)エポキシ樹脂としては、例えば、フェノールノボラック型エポキシ樹脂及びオルソクレゾールノボラック型エポキシ樹脂等のフェノール類とアルデヒド類のノボラック樹脂をエポキシ化したもの、ビスフェノールA、ビスフェノールF、ビスフェノールS及びアルキル置換ビフェノール等のジグリシジエーテル、ジアミノジフェニルメタン及びイソシアヌル酸等のポリアミンとエピクロルヒドリンとの反応により得られるグリシジルアミン型エポキシ樹脂、オレフィン結合を過酢酸等の過酸で酸化して得られる線状脂肪族エポキシ樹脂、並びに脂環族エポキシ樹脂等が挙げられる。これらは1種を単独で又は2種以上を併用してもよい。   The (A) epoxy resin is not particularly limited as long as it is generally used as an epoxy resin molding material for sealing electronic components. (A) Epoxy resins include, for example, epoxidized phenol and aldehyde novolak resins such as phenol novolac type epoxy resins and orthocresol novolak type epoxy resins, bisphenol A, bisphenol F, bisphenol S and alkyl-substituted biphenols. Glycidylamine type epoxy resins obtained by reaction of polyamines such as diglycidyl ether, diaminodiphenylmethane and isocyanuric acid with epichlorohydrin, linear aliphatic epoxy resins obtained by oxidizing olefinic bonds with peracids such as peracetic acid, Moreover, an alicyclic epoxy resin etc. are mentioned. These may be used alone or in combination of two or more.

(A)エポキシ樹脂は、比較的着色の少ないものが好ましい。このようなエポキシ樹脂としては、例えば、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、ビスフェノールS型エポキシ樹脂、トリグリシジルイソシアヌレートが挙げられる。   (A) As for an epoxy resin, a thing with comparatively little coloring is preferable. Examples of such an epoxy resin include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, and triglycidyl isocyanurate.

(B)硬化剤としては、(A)エポキシ樹脂と反応するものであれば特に制限なく用いることができるが、比較的着色の少ないものが好ましい。(B)硬化剤としては、例えば、酸無水物系硬化剤、フェノール系硬化剤等が挙げられる。酸無水物系硬化剤としては、例えば、無水フタル酸、無水マレイン酸、無水トリメリット酸、無水ピロメリット酸、ヘキサヒドロ無水フタル酸、テトラヒドロ無水フタル酸、無水メチルナジック酸、無水ナジック酸、無水グルタル酸、メチルヘキサヒドロ無水フタル酸、メチルテトラヒドロ無水フタル酸等が挙げられる。これら酸無水物系硬化剤の中では、無水フタル酸、へキサヒドロ無水フタル酸、テトラヒドロ無水フタル酸、メチルヘキサヒドロ無水フタル酸を用いることが好ましい。フェノール系硬化剤としては、例えばフェノール、クレゾール、レゾルシン、カテコール、ビスフェノールA、ビスフェノールF、フェニルフェノール、アミノフェノール等のフェノール類及び/又はα−ナフトール、β−ナフトール、ジヒドロキシナフタレン等のナフトール類とホルムアルデヒド等のアルデヒド基を有する化合物とを酸性触媒下で縮合又は共縮合させて得られる樹脂、フェノール類及び/又はナフトール類とジメトキシパラキシレン又はビス(メトキシメチル)ビフェニルから合成されるフェノール・アラルキル樹脂、ナフトール・アラルキル樹脂等のアラルキル型フェノール樹脂等が挙げられる。これらの硬化剤は、1種を単独で又は2種以上を併用してもよい。酸無水物系硬化剤は、重量平均分子量が140〜200程度であることが好ましく、無色ないし淡黄色であることが好ましい。   (B) The curing agent can be used without particular limitation as long as it reacts with (A) the epoxy resin, but those with relatively little coloring are preferred. (B) As a hardening | curing agent, an acid anhydride type hardening | curing agent, a phenol type hardening | curing agent, etc. are mentioned, for example. Examples of the acid anhydride curing agent include phthalic anhydride, maleic anhydride, trimellitic anhydride, pyromellitic anhydride, hexahydrophthalic anhydride, tetrahydrophthalic anhydride, methyl nadic anhydride, nadic anhydride, glutaric anhydride. Examples include acid, methylhexahydrophthalic anhydride, methyltetrahydrophthalic anhydride and the like. Among these acid anhydride curing agents, phthalic anhydride, hexahydrophthalic anhydride, tetrahydrophthalic anhydride, and methylhexahydrophthalic anhydride are preferably used. Examples of phenolic curing agents include phenols such as phenol, cresol, resorcin, catechol, bisphenol A, bisphenol F, phenylphenol, aminophenol, and / or naphthols such as α-naphthol, β-naphthol, dihydroxynaphthalene, and formaldehyde. A resin obtained by condensing or co-condensing a compound having an aldehyde group such as an acid catalyst, a phenol / aralkyl resin synthesized from phenols and / or naphthols and dimethoxyparaxylene or bis (methoxymethyl) biphenyl, Examples include aralkyl type phenol resins such as naphthol / aralkyl resins. These curing agents may be used alone or in combination of two or more. The acid anhydride curing agent preferably has a weight average molecular weight of about 140 to 200, and is preferably colorless or light yellow.

(B)硬化剤の含有量は、(A)エポキシ樹脂中のエポキシ基1当量に対して、(B)硬化剤におけるエポキシ基と反応可能な活性基(酸無水物基又は水酸基)の割合が0.5〜1.5当量であることが好ましく、0.7〜1.2当量であることがより好ましい。上記活性基の割合が0.5当量未満の場合には、熱硬化性樹脂組成物の硬化速度が遅くなると共に、得られる硬化物のガラス転移温度が低くなる傾向があり、1.5当量を超える場合には、硬化物の耐湿性が低下する傾向がある。   The content of the (B) curing agent is such that the proportion of the active group (an acid anhydride group or hydroxyl group) capable of reacting with the epoxy group in the (B) curing agent is equivalent to 1 equivalent of the epoxy group in the (A) epoxy resin. It is preferably 0.5 to 1.5 equivalents, and more preferably 0.7 to 1.2 equivalents. When the ratio of the active group is less than 0.5 equivalent, the curing rate of the thermosetting resin composition is slow, and the glass transition temperature of the resulting cured product tends to be low. When exceeding, there exists a tendency for the moisture resistance of hardened | cured material to fall.

(C)硬化促進剤(硬化触媒)としては、特に限定されるものではないが、例えば、1,8−ジアザ−ビシクロ(5,4,0)ウンデセン−7、トリエチレンジアミン、トリ−2,4,6−ジメチルアミノメチルフェノール等の3級アミン類、2−エチル−4−メチルイミダゾール、2−メチルイミダゾール等のイミダゾール類、トリフェニルホスフィン、テトラフェニルホスホニウムテトラフェニルボレート、テトラ−n−ブチルホスホニウム−o,o−ジエチルホスホロジチオエート等のリン化合物、4級アンモニウム塩、有機金属塩類、及びこれらの誘導体等が挙げられる。これらは1種を単独で又は2種以上を併用してもよい。これら硬化促進剤の中では、3級アミン類、イミダゾール類、リン化合物を用いることが好ましい。   (C) Although it does not specifically limit as a hardening accelerator (curing catalyst), For example, 1,8- diaza-bicyclo (5,4,0) undecene-7, a triethylenediamine, a tri-2,4. Tertiary amines such as 2,6-dimethylaminomethylphenol, imidazoles such as 2-ethyl-4-methylimidazole and 2-methylimidazole, triphenylphosphine, tetraphenylphosphonium tetraphenylborate, tetra-n-butylphosphonium- Examples thereof include phosphorus compounds such as o, o-diethyl phosphorodithioate, quaternary ammonium salts, organometallic salts, and derivatives thereof. These may be used alone or in combination of two or more. Among these curing accelerators, it is preferable to use tertiary amines, imidazoles, and phosphorus compounds.

(C)硬化促進剤の含有量は、(A)エポキシ樹脂100質量部に対して、0.01〜8.0質量部が好ましく、0.1〜3.0質量部がより好ましい。(C)硬化促進剤の含有率が0.01質量部未満であると、十分な硬化促進効果を得られない傾向があり、8.0質量部を超えると、得られる硬化物に変色が見られる傾向がある。   (C) 0.01-8.0 mass parts is preferable with respect to 100 mass parts of (A) epoxy resins, and, as for content of a hardening accelerator, 0.1-3.0 mass parts is more preferable. (C) If the content of the curing accelerator is less than 0.01 parts by mass, there is a tendency that a sufficient curing acceleration effect cannot be obtained. If the content exceeds 8.0 parts by mass, the resulting cured product is discolored. Tend to be.

(D)無機充填材としては、例えばシリカが挙げられる。(D)無機充填材としては、優れた熱伝導性、光反射特性、成形性、難燃性の点から、シリカ、後述する(E)白色顔料のアルミナ、酸化アンチモン、水酸化アルミニウムのうちの2種以上を含む混合物であることが好ましい。   (D) As an inorganic filler, a silica is mentioned, for example. (D) As the inorganic filler, from the viewpoint of excellent thermal conductivity, light reflection characteristics, moldability, and flame retardancy, silica, among the (E) white pigment alumina described later, antimony oxide, aluminum hydroxide It is preferable that it is a mixture containing 2 or more types.

(D)無機充填材の中心粒径は、特に限定されるものではないが、(E)白色顔料とのパッキング効率を向上させる観点から、1〜100μmの範囲であることが好ましい。優れた熱伝導性、光反射特性の点から、中心粒径の異なる(D)白色顔料を複数添加してもよい。   (D) Although the center particle diameter of an inorganic filler is not specifically limited, It is preferable that it is the range of 1-100 micrometers from a viewpoint of improving the packing efficiency with (E) white pigment. A plurality of (D) white pigments having different center particle diameters may be added from the viewpoint of excellent thermal conductivity and light reflection characteristics.

(E)白色顔料としては、例えば、酸化チタン、アルミナ、酸化マグネシウム、酸化アンチモン、水酸化アルミニウム、硫酸バリウム、炭酸マグネシウム、炭酸バリウム、無機中空粒子等を挙げることができる。(E)白色顔料としては、優れた熱伝導性、光反射特性の点から、アルミナ、酸化マグネシウム、無機中空粒子またはそれらの混合物が好ましい。無機中空粒子としては、珪酸ソーダガラス、アルミ珪酸ガラス、硼珪酸ソーダガラス、シラス等がある。これらは1種を単独で又は2種以上を併用してもよい。   Examples of (E) white pigments include titanium oxide, alumina, magnesium oxide, antimony oxide, aluminum hydroxide, barium sulfate, magnesium carbonate, barium carbonate, and inorganic hollow particles. (E) As the white pigment, alumina, magnesium oxide, inorganic hollow particles, or a mixture thereof is preferable from the viewpoint of excellent thermal conductivity and light reflection characteristics. Examples of the inorganic hollow particles include sodium silicate glass, aluminum silicate glass, borosilicate soda glass, and shirasu. These may be used alone or in combination of two or more.

(E)白色顔料の中心粒径は、0.1〜50μmの範囲であることが好ましい。中心粒径が0.1μm未満であると、粒子が凝集しやすく、分散性が悪くなる傾向があり、50μmを超えると、反射特性が十分に得られなくなる傾向がある。   (E) The center particle diameter of the white pigment is preferably in the range of 0.1 to 50 μm. If the center particle size is less than 0.1 μm, the particles tend to aggregate and the dispersibility tends to deteriorate, and if it exceeds 50 μm, the reflection characteristics tend not to be sufficiently obtained.

(D)無機充填材及び(E)白色顔料の含有量の合計は、熱硬化性樹脂組成物全体に対して、75〜95質量%の範囲であることが好ましい。この含有量の合計が75質量%未満であると、熱伝導性や光反射特性が不十分になる傾向があり、95質量%を超えると、樹脂組成物の成形性が悪くなり、光半導体素子搭載用基板の作製が難化する傾向がある。   The total content of (D) inorganic filler and (E) white pigment is preferably in the range of 75 to 95 mass% with respect to the entire thermosetting resin composition. If the total content is less than 75% by mass, thermal conductivity and light reflection characteristics tend to be insufficient, and if it exceeds 95% by mass, the moldability of the resin composition deteriorates, and an optical semiconductor element. There is a tendency that the production of the mounting substrate becomes difficult.

(F)カップリング剤としては、特に限定されないが、例えば、シラン系カップリング剤やチタネート系カップリング剤等を用いることができる。シラン系カップリング剤としては、例えば、エポキシシラン系、アミノシラン系、カチオニックシラン系、ビニルシラン系、アクリルシラン系、メルカプトシラン系、及びこれらの複合系等を用いることができる。(F)カップリング剤の処理条件は特に限定されるものではない。(F)カップリング剤の含有量は、熱硬化性樹脂組成物全体に対して、5質量%以下であることが好ましい。   (F) Although it does not specifically limit as a coupling agent, For example, a silane coupling agent, a titanate coupling agent, etc. can be used. As the silane coupling agent, for example, epoxy silane, amino silane, cationic silane, vinyl silane, acryl silane, mercapto silane, and composites thereof can be used. (F) The processing conditions for the coupling agent are not particularly limited. (F) It is preferable that content of a coupling agent is 5 mass% or less with respect to the whole thermosetting resin composition.

また、熱硬化性樹脂組成物には、必要に応じて、酸化防止剤、離型剤、イオン補足剤等の添加剤を添加してもよい。   Moreover, you may add additives, such as antioxidant, a mold release agent, and an ion supplement agent, to a thermosetting resin composition as needed.

光半導体素子20は、キャビティ部14a内の光半導体素子搭載領域においてダイボンド材(図示せず)を介して導体層18a上に配置されている。光半導体素子20は、ボンディングワイヤ40により導体層18bと電気的に接続されている。光半導体素子20は、図3に示すように、ボンディングワイヤを用いることなく、はんだバンプ42により導体層18a,18bのそれぞれと電気的に接続されていてもよい。なお、光半導体素子20は、キャビティ部14a内に一つ配置されていることに限定されるものではなく、複数配置されていてもよい。   The optical semiconductor element 20 is disposed on the conductor layer 18a via a die bond material (not shown) in the optical semiconductor element mounting region in the cavity portion 14a. The optical semiconductor element 20 is electrically connected to the conductor layer 18 b by a bonding wire 40. As shown in FIG. 3, the optical semiconductor element 20 may be electrically connected to each of the conductor layers 18a and 18b by solder bumps 42 without using bonding wires. The optical semiconductor element 20 is not limited to being arranged in the cavity portion 14a, and a plurality of optical semiconductor elements 20 may be arranged.

封止樹脂部30は、キャビティ部14aの内部に充填されており、光半導体素子20を封止している。封止樹脂部30は、透光性を有する透明封止樹脂により形成されている。透明封止樹脂としては、例えばエポキシ樹脂及び酸無水物の混合物が用いられる。封止樹脂部30には、YAG(イットリウム・アルミニウム・ガーネット)系蛍光体等の蛍光体30aが分散されている。   The sealing resin part 30 is filled in the cavity part 14 a and seals the optical semiconductor element 20. The sealing resin part 30 is formed of a transparent sealing resin having translucency. As the transparent sealing resin, for example, a mixture of an epoxy resin and an acid anhydride is used. A phosphor 30 a such as a YAG (yttrium, aluminum, garnet) phosphor is dispersed in the sealing resin portion 30.

(光半導体装置の製造方法)
次に、光半導体装置100の製造方法について説明する。光半導体装置100の製造方法は、光半導体素子搭載用基板製造工程と、光半導体素子配置工程と、封止樹脂充填工程と、分割工程とを有する。
(Manufacturing method of optical semiconductor device)
Next, a method for manufacturing the optical semiconductor device 100 will be described. The manufacturing method of the optical semiconductor device 100 includes an optical semiconductor element mounting substrate manufacturing process, an optical semiconductor element arranging process, a sealing resin filling process, and a dividing process.

まず、図4〜7を用いて、光半導体素子搭載用基板製造工程を説明する。図4〜7は、本発明に係る光半導体装置の製造方法の一実施形態を示す模式断面図である。光半導体素子搭載用基板10の製造方法は、フィルム接着工程と、配線部材配置工程と、金型配置工程と、成形体形成工程と、金型除去工程と、接着フィルム剥離工程とを備える。   First, an optical semiconductor element mounting substrate manufacturing process will be described with reference to FIGS. 4 to 7 are schematic cross-sectional views showing an embodiment of a method for manufacturing an optical semiconductor device according to the present invention. The manufacturing method of the optical semiconductor element mounting substrate 10 includes a film adhering step, a wiring member arranging step, a mold arranging step, a molded body forming step, a die removing step, and an adhesive film peeling step.

フィルム接着工程では、まず、複数の配線部材12と、一対の接着フィルム50とを用意する。配線部材12は、金属箔から打ち抜きやエッチング等の公知の方法により得ることができる。次に、光半導体装置搭載領域が所定間隔をおいて離れるように配線部材12をマトリクス状に配列し、図4(a)に示すように、配線部材12のそれぞれの裏面12bに接着フィルム50の表面(一方面)50aを接着する。   In the film bonding step, first, a plurality of wiring members 12 and a pair of adhesive films 50 are prepared. The wiring member 12 can be obtained from a metal foil by a known method such as punching or etching. Next, the wiring members 12 are arranged in a matrix so that the optical semiconductor device mounting regions are separated from each other at a predetermined interval, and the adhesive film 50 is formed on each back surface 12b of the wiring member 12 as shown in FIG. The surface (one surface) 50a is bonded.

接着フィルム50は、少なくとも表面50aが接着性を有していればよく、表面50a及び裏面(他方面)50bの両面が接着性を有していてもよい。接着フィルム50は、両面から均等に圧力を印加して光半導体素子20の接続不良や基板の反りの発生を更に抑制する観点から、互いに同一の形状(例えば厚み、面積)、同一の物性(例えば線膨張率)を有していることが好ましい。   As for the adhesive film 50, at least the surface 50a should just have adhesiveness, and both surfaces of the surface 50a and the back surface (other side) 50b may have adhesiveness. The adhesive film 50 has the same shape (for example, thickness, area) and the same physical properties (for example, the same) from the viewpoint of further suppressing the occurrence of poor connection of the optical semiconductor element 20 and warping of the substrate by applying pressure equally from both sides. It is preferable to have a linear expansion coefficient.

接着フィルム50としては、接着性を有するフィルムであれば特に限定されるものではないが、成形体成形工程や、光半導体素子搭載時やワイヤーボンド時の加熱温度に耐性があるフィルムであることが好ましい。接着フィルム50としては、MAP成形のように面積が大きい基板を用いる場合には、加熱時の寸法変化が少ないフィルムを用いることが好ましい。接着フィルム50としては、成形体成形工程において、配線部材12と共に金型中で型締めされるため、フラッシュ等の汚れの発生を更に抑制する観点から、クランプ圧力に対して大きな変形や歪が生じないようにある程度高い弾性を有するフィルムが好ましい。これらの目的を満足する接着フィルム50の材料としては、例えばポリイミド樹脂が挙げられる。   The adhesive film 50 is not particularly limited as long as it is an adhesive film, but may be a film that is resistant to the molding temperature, the heating temperature at the time of optical semiconductor element mounting, and wire bonding. preferable. As the adhesive film 50, when a substrate having a large area is used as in MAP molding, it is preferable to use a film with little dimensional change during heating. Since the adhesive film 50 is clamped in the mold together with the wiring member 12 in the molding process, a large deformation or distortion occurs with respect to the clamp pressure from the viewpoint of further suppressing the occurrence of dirt such as flash. A film having a certain degree of elasticity is preferred. Examples of the material of the adhesive film 50 that satisfies these purposes include polyimide resin.

配線部材配置工程では、配線部材12の裏面12b同士を接着フィルム50を介して対向させる。配線部材配置工程では、例えば、図4(b)に示すように、接着フィルム50の裏面50b同士を貼り合わせることにより、配線部材12の裏面12b同士を対向させる。この場合、配線部材12は、両面から均等に圧力を印加して光半導体素子20の接続不良や基板の反りの発生を更に抑制する観点から、互いに同一の形状(例えば厚み、面積)、物性(例えば硬度、線膨張率)を有していることが好ましく、接着フィルム50を介して互いに対称となる位置に配置されることが好ましい。   In the wiring member arranging step, the back surfaces 12b of the wiring member 12 are opposed to each other with the adhesive film 50 interposed therebetween. In the wiring member arranging step, for example, as shown in FIG. 4B, the back surfaces 12b of the wiring members 12 are opposed to each other by bonding the back surfaces 50b of the adhesive film 50 together. In this case, the wiring member 12 has the same shape (for example, thickness, area) and physical properties (for example, from the viewpoint of further suppressing the occurrence of connection failure of the optical semiconductor element 20 and warping of the substrate by applying pressure equally from both sides. For example, it preferably has a hardness and a linear expansion coefficient, and is preferably arranged at positions symmetrical to each other via the adhesive film 50.

配線部材配置工程の後に、金型配置工程を行う。金型配置工程では、熱硬化性樹脂組成物が充填される複数の凹部52aと、成形体において光半導体素子20が配置されるキャビティ部14aとなる複数の凸部52bと、を有する金型52を用いる。凹部52aは、例えば、配線部材12の光半導体装置搭載領域の配置間隔に一致するようにマトリクス状に配列されており、凸部52bは、凹部52a間に介在している。金型52は、接着フィルム付配線部材を2つ重ねてクランプする際に生じる応力を更に緩和するという目的から、上型と下型とが対称に合わさるようにクランプされることが好ましい。   After the wiring member placement step, a mold placement step is performed. In the mold placement step, a mold 52 having a plurality of recesses 52a filled with the thermosetting resin composition and a plurality of projections 52b serving as the cavity portions 14a in which the optical semiconductor element 20 is placed in the molded body. Is used. For example, the recesses 52a are arranged in a matrix so as to coincide with the arrangement interval of the optical semiconductor device mounting region of the wiring member 12, and the protrusions 52b are interposed between the recesses 52a. The mold 52 is preferably clamped so that the upper mold and the lower mold are aligned symmetrically for the purpose of further relieving the stress generated when clamping the two wiring members with adhesive films.

金型52は、熱硬化性樹脂組成物が流動可能な樹脂注入口52cを有する。樹脂注入口52cとなるゲートや樹脂の流路となるランナーの幅や深さは、樹脂注入開始後に金型52の凹部52a内において配線部材12にかかる圧力が対向する配線部材12同士で均等となるように設計されていることが好ましい。   The mold 52 has a resin inlet 52c through which the thermosetting resin composition can flow. The width and depth of the gate serving as the resin injection port 52c and the runner serving as the resin flow path are uniform between the wiring members 12 facing each other with the pressure applied to the wiring member 12 in the recess 52a of the mold 52 after the resin injection is started. It is preferable that it is designed to be.

金型配置工程では、図5(a)に示すように、金型52の凸部52bが配線部材12の表面12aにおける光半導体素子搭載領域に当接するように、配線部材12及び接着フィルム50を介して一対の金型52を互いに対向させて型締めする。この際、一対の金型52の凸部52bは、配線部材12及び接着フィルム50を介して互いに対向するように配置される。一対の金型52の凹部52aは、内周側面が光半導体素子搭載領域を囲むように、配線部材12のそれぞれの表面12a上に位置合わせされる。   In the mold placement step, as shown in FIG. 5A, the wiring member 12 and the adhesive film 50 are placed so that the convex portion 52b of the mold 52 contacts the optical semiconductor element mounting region on the surface 12a of the wiring member 12. The pair of molds 52 are opposed to each other and clamped. At this time, the convex portions 52 b of the pair of molds 52 are arranged to face each other with the wiring member 12 and the adhesive film 50 interposed therebetween. The recesses 52a of the pair of molds 52 are aligned on the respective surfaces 12a of the wiring member 12 so that the inner peripheral side surfaces surround the optical semiconductor element mounting region.

一対の金型52は、両面から均等に圧力を印加して光半導体素子20の接続不良や基板の反りの発生を更に抑制する観点から、同一の形状(例えば厚み、面積)、物性(例えば硬度、線膨張率)を有していることが好ましい。一対の金型52は、配線部材12及び接着フィルム50を介して互いに対称となる位置に配置されて、凹部52a同士、及び、凸部52b同士が対称となるように配置されることが好ましい。配線部材12と金型52とは、位置合わせピン54により互いの相対位置が固定されている。   The pair of molds 52 has the same shape (for example, thickness, area) and physical properties (for example, hardness) from the viewpoint of further suppressing the occurrence of poor connection of the optical semiconductor element 20 and warping of the substrate by applying pressure evenly from both sides. , Linear expansion coefficient). The pair of molds 52 are preferably arranged so as to be symmetrical with each other via the wiring member 12 and the adhesive film 50 so that the concave portions 52a and the convex portions 52b are symmetrical with each other. The relative position of the wiring member 12 and the mold 52 is fixed by the alignment pin 54.

成形体形成工程では、図5(b)に示すように、凹部52aに熱硬化性樹脂組成物を充填し、トランスファー成形により配線部材12の表面12a上にリフレクター14となる成形体を形成する。この際に、配線部材12の配線部分間の空隙にも熱硬化性樹脂組成物を充填し、硬化物層16を形成する。熱硬化性樹脂組成物は、樹脂注入口52cを通じて金型52内に注入される。トランスファー成形において、配線部材12は、金型52内に注入された熱硬化性樹脂組成物、及び金型52によって厚み方向に押圧される。トランスファー成形では、例えば、金型温度170〜190℃で60〜120秒、アフターキュア温度120〜180℃で1〜3時間の条件にて、熱硬化性樹脂組成物を熱硬化させて硬化物を得る。   In the molded body forming step, as shown in FIG. 5B, the recess 52a is filled with a thermosetting resin composition, and a molded body that becomes the reflector 14 is formed on the surface 12a of the wiring member 12 by transfer molding. At this time, the space between the wiring portions of the wiring member 12 is also filled with the thermosetting resin composition to form the cured product layer 16. The thermosetting resin composition is injected into the mold 52 through the resin injection port 52c. In transfer molding, the wiring member 12 is pressed in the thickness direction by the thermosetting resin composition injected into the mold 52 and the mold 52. In the transfer molding, for example, the thermosetting resin composition is thermoset under conditions of a mold temperature of 170 to 190 ° C. for 60 to 120 seconds and an after cure temperature of 120 to 180 ° C. for 1 to 3 hours to obtain a cured product. obtain.

ところで、QFN構造のパッケージを成型する場合には、成形体形成工程において、金型52に注入された熱硬化性樹脂組成物が配線部材12の裏面12bに回りこんでしまう場合がある。この場合、バリ等の不具合が生じる。しかし、上記製造方法では、配線部材12の裏面12bに接着フィルム50を接着することで、接着フィルム50が裏面保護用接着フィルムとなり、樹脂組成物の回り込みを抑制することができる。   By the way, when a QFN structure package is molded, the thermosetting resin composition injected into the mold 52 may wrap around the back surface 12b of the wiring member 12 in the molded body forming step. In this case, defects such as burrs occur. However, in the said manufacturing method, the adhesive film 50 becomes an adhesive film for back surface protection by adhere | attaching the adhesive film 50 on the back surface 12b of the wiring member 12, and it can suppress the surroundings of a resin composition.

上記熱硬化性樹脂組成物は、(A)エポキシ樹脂等の各種成分を均一に分散混合することで得ることができるが、分散混合する手段や条件等は特に限定されない。熱硬化性樹脂組成物を作製する一般的な方法として、各成分を押出機、ニーダー、ロール、エクストルーダー等によって混練した後、混練物を冷却し、粉砕する方法を挙げることができる。各成分を混練する際には、分散性を向上する観点から、溶融状態で行うことが好ましい。混練の条件は、各成分の種類や配合量により適宜決定すればよく、例えば、15〜100℃で5〜40分間混練することが好ましく、20〜100℃で10〜30分間混練することがより好ましい。混練温度が15℃未満であると、各成分を混練させ難くなり、分散性も低下する傾向にあり、100℃を超えると、樹脂組成物の高分子量化が進行し、樹脂組成物が硬化してしまう可能性がある。また、混練時間が5分未満であると、トランスファー成形時に樹脂バリが発生してしまう可能性がある。混練時間が40分を超えると、樹脂組成物の高分子量化が進行し、樹脂組成物が硬化してしまう可能性がある。   The thermosetting resin composition can be obtained by uniformly dispersing and mixing (A) various components such as an epoxy resin, but means and conditions for dispersing and mixing are not particularly limited. As a general method for producing a thermosetting resin composition, there can be mentioned a method in which each component is kneaded with an extruder, a kneader, a roll, an extruder, etc., and then the kneaded product is cooled and pulverized. When kneading each component, it is preferable to carry out in a molten state from the viewpoint of improving dispersibility. The kneading conditions may be appropriately determined depending on the type and blending amount of each component. For example, kneading is preferably performed at 15 to 100 ° C. for 5 to 40 minutes, and kneading at 20 to 100 ° C. for 10 to 30 minutes is more preferable. preferable. When the kneading temperature is less than 15 ° C., it becomes difficult to knead each component and the dispersibility also tends to decrease. When the kneading temperature exceeds 100 ° C., the resin composition increases in molecular weight, and the resin composition is cured. There is a possibility that. If the kneading time is less than 5 minutes, resin burrs may be generated during transfer molding. If the kneading time exceeds 40 minutes, the resin composition may be increased in molecular weight and the resin composition may be cured.

成形体形成工程の後、金型除去工程を行う。金型除去工程では、図6(a)に示すように、金型52を配線部材12の表面12a上から除去すると共に、位置合わせピン54を除去する。   After the molded body forming step, a mold removing step is performed. In the mold removing step, as shown in FIG. 6A, the mold 52 is removed from the surface 12a of the wiring member 12, and the alignment pins 54 are removed.

金型除去工程の後、接着フィルム剥離工程を行う。接着フィルム剥離工程では、図6(b)に示すように、配線部材12の裏面12bから接着フィルム50を除去し、リフレクター14が形成された配線部材12を得る。   An adhesive film peeling process is performed after a metal mold | die removal process. In the adhesive film peeling step, as shown in FIG. 6B, the adhesive film 50 is removed from the back surface 12b of the wiring member 12 to obtain the wiring member 12 on which the reflector 14 is formed.

以上により、複数のキャビティ部が形成された光半導体素子搭載用基板10が得られる。   Thus, the optical semiconductor element mounting substrate 10 in which a plurality of cavities are formed is obtained.

光半導体素子搭載用基板製造工程の後、光半導体素子配置工程を行う。光半導体素子配置工程では、まず、キャビティ部の底面から露出する配線部材12の表面12a上に導体層18a,18bを形成する。次に、キャビティ部14a内のそれぞれの導体層18a上に光半導体素子20を配置する。   After the optical semiconductor element mounting substrate manufacturing process, an optical semiconductor element arrangement process is performed. In the optical semiconductor element arranging step, first, conductor layers 18a and 18b are formed on the surface 12a of the wiring member 12 exposed from the bottom surface of the cavity portion. Next, the optical semiconductor element 20 is disposed on each conductor layer 18a in the cavity portion 14a.

次に、光半導体素子20と導体層18bとを電気的に接続する。例えば、図7(a)に示すように、光半導体素子20と導体層18bとをボンディングワイヤ40により電気的に接続する。また、図3に示すように、光半導体素子20を配置する前に導体層18a,18bのそれぞれにはんだバンプ42を形成し、はんだバンプ42上に光半導体素子20を配置してもよい。   Next, the optical semiconductor element 20 and the conductor layer 18b are electrically connected. For example, as shown in FIG. 7A, the optical semiconductor element 20 and the conductor layer 18 b are electrically connected by a bonding wire 40. In addition, as shown in FIG. 3, the solder bumps 42 may be formed on the conductor layers 18 a and 18 b before the optical semiconductor element 20 is disposed, and the optical semiconductor element 20 may be disposed on the solder bump 42.

光半導体素子配置工程の後、封止樹脂充填工程を行う。封止樹脂充填工程では、図7(a)に示すように、光半導体素子20を覆うようにキャビティ部に透光性を有する封止樹脂を充填し、封止樹脂部30を形成する。樹脂の充填には、例えばポッティングを用いることができる。   After the optical semiconductor element arranging step, a sealing resin filling step is performed. In the sealing resin filling step, as shown in FIG. 7A, the cavity resin is filled with a light-transmitting sealing resin so as to cover the optical semiconductor element 20, thereby forming the sealing resin portion 30. For example, potting can be used for filling the resin.

封止樹脂充填工程の後、分割工程を行う。分割工程では、図7(b)に示すように、複数のリフレクター14が連なった成形体をキャビティ部毎に分割して単体化する。分割工程では、例えば、成形体の表面に水平な方向において互いに直行する2方向から成形体をダイシングすることにより単体に分離する。分割手法はこれに限定されるものではなく、レーザ加工、ウォータージェット加工、金型加工等の公知の手法を用いることができる。以上の工程により、複数の光半導体装置100が得られる。   After the sealing resin filling step, a dividing step is performed. In the dividing step, as shown in FIG. 7 (b), the formed body in which the plurality of reflectors 14 are connected is divided into individual cavities. In the dividing step, for example, the molded body is separated into single bodies by dicing from two directions orthogonal to each other in a horizontal direction on the surface of the molded body. The dividing method is not limited to this, and known methods such as laser processing, water jet processing, and die processing can be used. Through the above steps, a plurality of optical semiconductor devices 100 are obtained.

光半導体装置100の製造方法では、配線部材12の裏面12b同士を接着フィルム50を介して対向させ、更に、金型52の凸部52bが光半導体素子搭載領域に当接するように、配線部材12及び接着フィルム50を介して一対の金型52を互いに対向させた上で、配線部材12の表面12a上にリフレクター14となる成形体を形成している。これにより、接着フィルム50を介して対向するそれぞれの配線部材12が、表面12a側から金型52及び成形体(熱硬化性樹脂組成物)によって接着フィルム50側に向かって押圧されることとなり、成形体(熱硬化性樹脂組成物)と配線部材12との線膨脹係数の相違に起因して生じる応力が相殺されて緩和される。このような応力の緩和によって光半導体素子搭載用基板10における反りの発生を抑制することが可能であり、生産性の低下を抑制することができる。   In the method for manufacturing the optical semiconductor device 100, the wiring members 12 are arranged such that the back surfaces 12b of the wiring members 12 are opposed to each other through the adhesive film 50, and the convex portions 52b of the mold 52 are in contact with the optical semiconductor element mounting region. In addition, a pair of molds 52 are opposed to each other via the adhesive film 50, and a molded body that becomes the reflector 14 is formed on the surface 12 a of the wiring member 12. Thereby, each wiring member 12 which opposes via the adhesive film 50 will be pressed toward the adhesive film 50 side by the metal mold | die 52 and a molded object (thermosetting resin composition) from the surface 12a side, The stress caused by the difference in the coefficient of linear expansion between the molded body (thermosetting resin composition) and the wiring member 12 is offset and relaxed. Such relaxation of stress can suppress the occurrence of warpage in the optical semiconductor element mounting substrate 10 and can suppress a reduction in productivity.

また、このように光半導体素子搭載用基板10の変形が抑制されると共に、金型52の凸部52bが配線部材12の光半導体素子搭載領域に当接するように一対の金型52を対向させるため、配線部材12と金型52との間における汚れの発生が抑制される。これにより、汚れを除去する工程を別途要することなく、生産性の低下を抑制しつつ光半導体素子20と配線部材12との接続不良を抑制することができる。   Also, the deformation of the optical semiconductor element mounting substrate 10 is suppressed in this way, and the pair of molds 52 are opposed so that the convex portion 52b of the mold 52 contacts the optical semiconductor element mounting region of the wiring member 12. Therefore, the occurrence of dirt between the wiring member 12 and the mold 52 is suppressed. Thereby, the connection defect of the optical semiconductor element 20 and the wiring member 12 can be suppressed, suppressing the fall of productivity, without requiring the process of removing dirt separately.

また、光半導体装置100の製造方法では、接着フィルム50の両面側でそれぞれ光半導体素子搭載用基板10を得ることができるため、光半導体装置100を効率良く低コストで得ることができる。   Moreover, in the manufacturing method of the optical semiconductor device 100, since the optical semiconductor element mounting substrate 10 can be obtained on both sides of the adhesive film 50, the optical semiconductor device 100 can be obtained efficiently and at low cost.

光半導体素子搭載用基板製造工程は、上記の工程に限定されるものではない。図8に示すように、フィルム接着工程において、配線部材12のそれぞれの裏面12bを接着フィルム50の同一面に接着した後、配線部材配置工程において、接着フィルム50を折り返して配線部材12の裏面12b同士を接着フィルム50を介して対向させてもよい。このような工程により光半導体装置100を得た場合にも、生産性の低下を抑制しつつ、光半導体素子20の接続不良や基板の反りの発生を抑制することができる。更に、フィルム接着工程では、接着フィルム50を折り返した際に対向する複数の配線部材12同士を対称に位置させるため、隣接する配線部材12同士が互いに所定間隔をおいて配置されるように各配線部材12を接着フィルム50に接着することが好ましい。   The optical semiconductor element mounting substrate manufacturing process is not limited to the above process. As shown in FIG. 8, after the respective back surfaces 12b of the wiring members 12 are bonded to the same surface of the adhesive film 50 in the film bonding step, the adhesive film 50 is folded back in the wiring member placement step, so that the back surface 12b of the wiring member 12 is returned. They may be opposed to each other with the adhesive film 50 interposed therebetween. Even when the optical semiconductor device 100 is obtained by such a process, it is possible to suppress the occurrence of poor connection of the optical semiconductor element 20 and the warpage of the substrate while suppressing a decrease in productivity. Further, in the film bonding step, the wiring members 12 facing each other when the adhesive film 50 is folded back are positioned symmetrically so that the adjacent wiring members 12 are arranged at predetermined intervals from each other. It is preferable to adhere the member 12 to the adhesive film 50.

また、図9に示すように、配線部材配置工程において、表面50a及び裏面50bの両面が接着性を有する接着フィルム50の両面のそれぞれに配線部材12の裏面12bを接着し、配線部材12の裏面12b同士が接着フィルム50を介して対向するように配線部材12を配置してもよい。このような工程により光半導体装置100を得た場合にも、生産性の低下を抑制しつつ、光半導体素子20の接続不良や基板の反りの発生を抑制することができる。更に、配線部材配置工程では、接着フィルム50を介して対向する配線部材12同士が対称に位置するように、各配線部材12を接着フィルム50に接着することが好ましい。   Further, as shown in FIG. 9, in the wiring member placement step, the back surface 12b of the wiring member 12 is bonded to each of both surfaces of the adhesive film 50 in which both the front surface 50a and the back surface 50b are adhesive, and the back surface of the wiring member 12 The wiring member 12 may be arranged so that 12b face each other with the adhesive film 50 interposed therebetween. Even when the optical semiconductor device 100 is obtained by such a process, it is possible to suppress the occurrence of poor connection of the optical semiconductor element 20 and the warpage of the substrate while suppressing a decrease in productivity. Furthermore, in the wiring member arrangement step, it is preferable that each wiring member 12 is bonded to the adhesive film 50 so that the wiring members 12 facing each other through the adhesive film 50 are positioned symmetrically.

以下に、本発明を実施例に基づいて具体的に説明するが、本発明はこれに限定されるものではない。   Hereinafter, the present invention will be specifically described based on examples, but the present invention is not limited thereto.

(実施例1)
[光半導体装置の作製]
<光反射用熱硬化性樹脂組成物の作製>
表1に示す配合量で各配合成分を配合し、ミキサーによって十分混練した後、ミキシングロールにより40℃で15分溶融混練して混合物を得た。この混合物を冷却した後、粉砕し、光反射用熱硬化性樹脂組成物を得た。なお、表1中の各成分の配合量の単位は質量部である。
Example 1
[Fabrication of optical semiconductor device]
<Preparation of thermosetting resin composition for light reflection>
Each blending component was blended in the blending amounts shown in Table 1, sufficiently kneaded with a mixer, and then melt-kneaded with a mixing roll at 40 ° C. for 15 minutes to obtain a mixture. After cooling this mixture, it was pulverized to obtain a thermosetting resin composition for light reflection. In addition, the unit of the compounding quantity of each component in Table 1 is a mass part.

Figure 0005397195
Figure 0005397195

表1中、*1〜8は以下の通りである。
*1:トリスグリシジルイソシアヌレート(エポキシ当量100、日産化学社製、商品名:TEPIC−S)
*2:ヘキサヒドロ無水フタル酸(和光純薬工業社製)
*3:テトラ−n−ブチルホスホニウム−o,o−ジエチルホスホロジチエート(日本化学工業社製、商品名:PX−4ET)
*4:トリメトキシエポキシシラン(東レダウコーニング社製、商品名:A−187)
*5:溶融シリカ(電気化学工業社製、商品名:FB−950)
*6:溶融シリカ(アドマテックス社製、商品名:SO−25R)
*7:酸化チタン(堺化学工業社製、商品名:FTR−700)
*8:中空粒子(住友3M社製、商品名:S60−HS)
In Table 1, * 1 to 8 are as follows.
* 1: Trisglycidyl isocyanurate (epoxy equivalent 100, manufactured by Nissan Chemical Co., Ltd., trade name: TEPIC-S)
* 2: Hexahydrophthalic anhydride (manufactured by Wako Pure Chemical Industries, Ltd.)
* 3: Tetra-n-butylphosphonium-o, o-diethyl phosphorodithioate (manufactured by Nippon Chemical Industry Co., Ltd., trade name: PX-4ET)
* 4: Trimethoxyepoxysilane (manufactured by Toray Dow Corning, trade name: A-187)
* 5: Fused silica (manufactured by Denki Kagaku Kogyo, trade name: FB-950)
* 6: Fused silica (manufactured by Admatechs, trade name: SO-25R)
* 7: Titanium oxide (made by Sakai Chemical Industry Co., Ltd., trade name: FTR-700)
* 8: Hollow particles (manufactured by Sumitomo 3M, trade name: S60-HS)

<光半導体素子搭載用基板の作製>
まず、配線部材として、表面をAgめっきした0.25μm厚みの複数の銅製リードフレームを準備した。各リードフレームの表面には、一対の陰極及び陽極を有するパターンとなるように光半導体素子搭載領域を形成した。
<Fabrication of optical semiconductor element mounting substrate>
First, as the wiring member, a plurality of 0.25 μm thick copper lead frames whose surfaces were Ag-plated were prepared. An optical semiconductor element mounting region was formed on the surface of each lead frame so as to form a pattern having a pair of cathode and anode.

次に、光半導体装置搭載領域が所定間隔をおいて離れるようにリードフレームをマトリクス状に配列し、リードフレームのそれぞれの裏面に裏面保護用接着フィルムの表面を接着した。裏面保護用接着フィルムとしては、表面及び裏面が接着性を有する一括封止成形用テープ(日立化成工業社製、商品名:RT−521)を2つ用いた。   Next, the lead frames were arranged in a matrix so that the optical semiconductor device mounting areas were separated from each other by a predetermined interval, and the surface of the back surface protective adhesive film was adhered to the back surface of each of the lead frames. As the adhesive film for protecting the back surface, two batch sealing molding tapes (made by Hitachi Chemical Co., Ltd., trade name: RT-521) having adhesiveness on the front and back surfaces were used.

続いて、リードフレーム付き接着フィルムの裏面同士を互いに接着した。この場合、リードフレームの光半導体素子搭載領域が一対の裏面保護用接着フィルムを介して互いに対称となる位置となるように位置あわせした。   Subsequently, the back surfaces of the adhesive film with a lead frame were bonded to each other. In this case, the optical semiconductor element mounting region of the lead frame was aligned so as to be symmetrical with each other via the pair of back surface protective adhesive films.

次いで、一対のリードフレームの表面上に成形金型をそれぞれ配置した。成形金型としては、リードフレームの光半導体装置搭載領域の配置間隔に一致するようにマトリクス状に配列された複数の凹部と、凹部間に介在する複数の凸部とを有する金型を用いた。金型の凸部がリードフレームの光半導体素子搭載領域に当接するように、一対の金型をリードフレーム及び接着フィルムを介して互いに対称となる位置に配置してクランプした。その際には、位置合わせピンを設置し、重ねた一対の裏面保護用接着フィルム付リードフレームが成形時に位置ずれしないよう配慮した。キャビティ部への樹脂注入口となるゲートや、樹脂の流路となるランナーの幅や深さは、樹脂注入開始後にキャビティ部内でリードフレームにかかる両面側の圧力が均等となるように設計した。   Next, molding dies were respectively disposed on the surfaces of the pair of lead frames. As the molding die, a die having a plurality of concave portions arranged in a matrix so as to coincide with the arrangement interval of the optical semiconductor device mounting region of the lead frame and a plurality of convex portions interposed between the concave portions was used. . The pair of molds were arranged and clamped at positions symmetrical to each other via the lead frame and the adhesive film so that the convex portions of the mold contacted the optical semiconductor element mounting region of the lead frame. In that case, the positioning pin was installed and it was considered that the paired lead frame with the adhesive film for protecting the back surface would not be displaced during molding. The width and depth of the gate serving as the resin injection port into the cavity and the runner serving as the resin flow path were designed so that the pressure on both sides applied to the lead frame in the cavity was uniform after the resin injection was started.

次に、トランスファー成形によりリードフレームの表面上に成形体を形成すると共に、配線部材における配線部分間の空隙に硬化物層を形成した。成形金型の内部に上記光反射用熱硬化性樹脂組成物を充填した後、樹脂組成物を硬化させた。トランスファー成形機としては、MTEX社製のATOM−FX(商品名)を用いた。成形条件は金型温度180℃、クランプ圧力20t、注入圧7MPa、成形時間90秒とした。   Next, a molded body was formed on the surface of the lead frame by transfer molding, and a cured product layer was formed in a gap between wiring portions in the wiring member. After filling the inside of the molding die with the thermosetting resin composition for light reflection, the resin composition was cured. As the transfer molding machine, ATOM-FX (trade name) manufactured by MTEX was used. The molding conditions were a mold temperature of 180 ° C., a clamp pressure of 20 t, an injection pressure of 7 MPa, and a molding time of 90 seconds.

成形体を形成した後、成形金型及び位置合わせピンを除去した。更に、接着フィルムをそれぞれの配線部材から剥し、複数のキャビティ部が形成された光半導体素子搭載用基板を得た。   After forming the molded body, the molding die and the alignment pin were removed. Further, the adhesive film was peeled off from each wiring member to obtain an optical semiconductor element mounting substrate on which a plurality of cavities were formed.

<光半導体素子の実装>
光半導体素子搭載用基板上の各光半導体素子搭載領域の陽極及び陰極にニッケル/銀めっきを施し、一対の導体層(端子)を形成した。次に、一方の導体層上にダイボンド材を塗布した後、光半導体素子をダイボンド材上に配置した。続いて、150℃、1時間加熱することにより、光半導体素子(LED素子)を固着した。その後、金線で光半導体素子の表面及び他方の導体層を電気的に接続した。
<Mounting of optical semiconductor elements>
Nickel / silver plating was applied to the anode and cathode of each optical semiconductor element mounting region on the optical semiconductor element mounting substrate to form a pair of conductor layers (terminals). Next, after apply | coating the die-bonding material on one conductor layer, the optical semiconductor element was arrange | positioned on the die-bonding material. Subsequently, the optical semiconductor element (LED element) was fixed by heating at 150 ° C. for 1 hour. Thereafter, the surface of the optical semiconductor element and the other conductor layer were electrically connected with a gold wire.

<光半導体素子の封止>
次に、光半導体素子を実装した光半導体素子搭載用基板のキャビティ部に以下の樹脂組成の透明封止樹脂をポッティングにより流し込み、光半導体素子を封止した。ポッティングの後、透明封止樹脂を150℃、2時間加熱硬化した。
(樹脂組成)
・水素添加ビスフェノールA型エポキシ樹脂、デナコールEX252(ナガセケムテックス社製)、90質量部
・脂環式エポキシ樹脂、CEL−2021P(ダイセル化学社製)、10質量部
・4−メチルヘキサヒドロフタル酸無水物、HN−5500E(日立化成工業製)、90質量部
・2、6−ジ−tert−ブチル−4−メチルフェノール(BHT)、0.4質量部
・2−エチル−4−メチルイミダゾール、0.9質量部
<Encapsulation of optical semiconductor element>
Next, a transparent sealing resin having the following resin composition was poured into the cavity of the optical semiconductor element mounting substrate on which the optical semiconductor element was mounted, thereby sealing the optical semiconductor element. After potting, the transparent sealing resin was cured by heating at 150 ° C. for 2 hours.
(Resin composition)
・ Hydrogenated bisphenol A type epoxy resin, Denacol EX252 (manufactured by Nagase ChemteX Corporation), 90 parts by mass Anhydride, HN-5500E (manufactured by Hitachi Chemical), 90 parts by mass, 2,6-di-tert-butyl-4-methylphenol (BHT), 0.4 parts by mass, 2-ethyl-4-methylimidazole, 0.9 parts by mass

<ダイシング>
透明封止樹脂を硬化した後、光半導体素子搭載用基板をダイシングによりキャビティ部毎に個片化し、複数の光半導体装置を得た。
<Dicing>
After the transparent sealing resin was cured, the optical semiconductor element mounting substrate was separated into individual cavities by dicing to obtain a plurality of optical semiconductor devices.

[光半導体装置の評価]
実施例1で得られた光半導体装置では、熱硬化性光反射用樹脂を用いてトランスファー成形により成形体を作製した際に、反りの発生が確認されなかった。また、樹脂バリが原因である樹脂汚れの発生が確認されず、バリ取り工程を要することなく、接続不良を抑制することができた。以上のように、実施例1では、生産性良く光半導体装置を得ることができた。
[Evaluation of optical semiconductor devices]
In the optical semiconductor device obtained in Example 1, no warpage was observed when a molded body was produced by transfer molding using a thermosetting light reflecting resin. Further, the occurrence of resin contamination due to resin burrs was not confirmed, and connection failure could be suppressed without requiring a deburring step. As described above, in Example 1, an optical semiconductor device could be obtained with high productivity.

(比較例1)
配線部材としては、実施例1と同様のリードフレームを1つ準備した。次に、リードフレームの裏面の全面を覆う金型(下型)、及び、マトリクス状に配列された複数の凹部と凹部間に介在する複数の凸部とを有し、リードフレームの表面上に配置される金型(上型)を用いて、上型の凸部が光半導体素子搭載領域に当接するように、上型及び下型をそれぞれリードフレーム上に配置した。続いて、実施例1と同様の熱硬化性樹脂組成物を上型の凹部に充填し、トランスファー成形によりリードフレームの表面上に成形体を形成した。
(Comparative Example 1)
As a wiring member, one lead frame similar to that in Example 1 was prepared. Next, a mold (lower mold) that covers the entire back surface of the lead frame, a plurality of concave portions arranged in a matrix, and a plurality of convex portions interposed between the concave portions, are provided on the surface of the lead frame Using the mold (upper mold) to be arranged, the upper mold and the lower mold were respectively arranged on the lead frame so that the convex portion of the upper mold was in contact with the optical semiconductor element mounting region. Subsequently, the same thermosetting resin composition as in Example 1 was filled in the concave portion of the upper mold, and a molded body was formed on the surface of the lead frame by transfer molding.

比較例1では、光半導体素子搭載用基板に反りが発生していることが確認された。また、凹部へ樹脂組成物を充填した結果、光半導体素子搭載用基板が変形したことにより、光半導体素子搭載領域と上型の凸部との隙間に樹脂組成物が流れ込み、光半導体素子搭載領域に樹脂汚れが発生した。このように反りや樹脂汚れが発生したため、光半導体素子の実装等の後工程を行えず、光半導体装置を得ることができなかった。   In Comparative Example 1, it was confirmed that the optical semiconductor element mounting substrate was warped. Further, as a result of filling the resin composition into the recess, the optical semiconductor element mounting substrate is deformed, so that the resin composition flows into the gap between the optical semiconductor element mounting area and the upper mold convex part, and the optical semiconductor element mounting area Resin soiling occurred. Since warping and resin contamination occurred in this way, post-processes such as mounting of an optical semiconductor element could not be performed, and an optical semiconductor device could not be obtained.

10…光半導体素子搭載用基板、12…配線部材、12a…配線部材の表面(一方面)、12b…配線部材の裏面(他方面)、14…リフレクター(成形体)、14a…キャビティ部、20…光半導体素子、30…封止樹脂部、50…接着フィルム、50a…接着フィルムの表面(一方面)、50b…接着フィルムの裏面(他方面)、52…金型、52a…金型の凹部、52b…金型の凸部、100…光半導体装置。   DESCRIPTION OF SYMBOLS 10 ... Board | substrate for optical semiconductor element mounting, 12 ... Wiring member, 12a ... The surface (one side) of a wiring member, 12b ... The back surface (other side) of a wiring member, 14 ... Reflector (molded object), 14a ... Cavity part, 20 DESCRIPTION OF SYMBOLS ... Optical semiconductor element, 30 ... Sealing resin part, 50 ... Adhesive film, 50a ... Adhesive film surface (one side), 50b ... Adhesive film back surface (other side), 52 ... Mold, 52a ... Mold concave part 52b, convex portions of the mold, 100, an optical semiconductor device.

Claims (6)

熱硬化性樹脂組成物が充填される凹部と、成形体において光半導体素子が配置されるキャビティ部となる凸部と、を有する金型を用いた光半導体素子搭載用基板の製造方法であって、
前記光半導体素子が配置される素子配置領域を一方面に有する配線部材の他方面同士を接着フィルムを介して対向させる配線部材配置工程と、
前記凸部が前記素子配置領域に当接するように、前記配線部材及び前記接着フィルムを介して一対の前記金型を互いに対向させる金型配置工程と、
前記凹部に前記熱硬化性樹脂組成物を充填し、トランスファー成形により前記配線部材の前記一方面上に前記成形体を形成する成形体形成工程と、を備える、光半導体素子搭載用基板の製造方法。
A method for manufacturing an optical semiconductor element mounting substrate using a mold having a concave portion filled with a thermosetting resin composition and a convex portion serving as a cavity in which an optical semiconductor element is arranged in a molded body. ,
A wiring member placement step in which the other surfaces of the wiring member having an element placement region on one side where the optical semiconductor element is placed are opposed to each other via an adhesive film;
A mold placement step of causing a pair of molds to face each other via the wiring member and the adhesive film so that the convex portion comes into contact with the element placement region;
And a molded body forming step of filling the recess with the thermosetting resin composition and forming the molded body on the one surface of the wiring member by transfer molding. .
前記配線部材配置工程の前に、前記配線部材のそれぞれの前記他方面に前記接着フィルムの一方面を接着するフィルム接着工程を備え、
前記配線部材配置工程において、前記接着フィルムの他方面同士を貼り合わせる、請求項1に記載の光半導体素子搭載用基板の製造方法。
Before the wiring member placement step, comprising a film bonding step of bonding one surface of the adhesive film to each other surface of the wiring member,
The method for manufacturing a substrate for mounting an optical semiconductor element according to claim 1, wherein in the wiring member arranging step, the other surfaces of the adhesive film are bonded together.
前記配線部材配置工程の前に、前記配線部材のそれぞれの前記他方面を前記接着フィルムの同一面に接着するフィルム接着工程を備え、
前記配線部材配置工程において、前記接着フィルムを折り返して前記配線部材の前記他方面同士を前記接着フィルムを介して対向させる、請求項1に記載の光半導体素子搭載用基板の製造方法。
Before the wiring member placement step, comprising a film bonding step of bonding the other surface of the wiring member to the same surface of the adhesive film,
The method for manufacturing a substrate for mounting an optical semiconductor element according to claim 1, wherein, in the wiring member arranging step, the adhesive film is folded back so that the other surfaces of the wiring member are opposed to each other through the adhesive film.
前記配線部材配置工程において、両面が接着性を有する前記接着フィルムの前記両面のそれぞれに前記配線部材の前記他方面を接着する、請求項1に記載の光半導体素子搭載用基板の製造方法。   2. The method for manufacturing a substrate for mounting an optical semiconductor element according to claim 1, wherein, in the wiring member arranging step, the other surface of the wiring member is bonded to each of the both surfaces of the adhesive film having adhesiveness on both surfaces. 請求項1〜4のいずれか一項に記載の光半導体素子搭載用基板の製造方法により光半導体素子搭載用基板を製造する工程と、
前記光半導体素子搭載用基板の前記キャビティ部内のそれぞれに前記光半導体素子を配置する光半導体素子配置工程と、
前記光半導体素子を覆うように前記キャビティ部に透光性を有する封止樹脂を充填する封止樹脂充填工程と、
前記成形体を前記キャビティ部毎に分割して複数の光半導体装置を得る分割工程と、を備える、光半導体装置の製造方法。
A step of manufacturing an optical semiconductor element mounting substrate by the method for manufacturing an optical semiconductor element mounting substrate according to any one of claims 1 to 4,
An optical semiconductor element arranging step of arranging the optical semiconductor element to each of the cavity portion of the optical element mounting substrate,
A sealing resin filling step of filling the cavity part with a light-transmitting sealing resin so as to cover the optical semiconductor element;
A dividing step of dividing the molded body into the cavity portions to obtain a plurality of optical semiconductor devices.
前記分割工程では、ダイシングにより前記成形体を分割する、請求項に記載の光半導体装置の製造方法。 The method for manufacturing an optical semiconductor device according to claim 5 , wherein in the dividing step, the molded body is divided by dicing.
JP2009274567A 2009-12-02 2009-12-02 Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device Expired - Fee Related JP5397195B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009274567A JP5397195B2 (en) 2009-12-02 2009-12-02 Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009274567A JP5397195B2 (en) 2009-12-02 2009-12-02 Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device

Publications (2)

Publication Number Publication Date
JP2011119393A JP2011119393A (en) 2011-06-16
JP5397195B2 true JP5397195B2 (en) 2014-01-22

Family

ID=44284399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009274567A Expired - Fee Related JP5397195B2 (en) 2009-12-02 2009-12-02 Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device

Country Status (1)

Country Link
JP (1) JP5397195B2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5865038B2 (en) 2011-11-30 2016-02-17 日東電工株式会社 ELECTRODE CONNECTION BOARD, ITS MANUFACTURING METHOD, AND LIGHT EMITTING DIODE DEVICE
JP2013179271A (en) 2012-01-31 2013-09-09 Rohm Co Ltd Light emitting device and manufacturing method of the same
JP2013206895A (en) * 2012-03-27 2013-10-07 Shin Etsu Chem Co Ltd Substrate for optical semiconductor device, manufacturing method of substrate for optical semiconductor device, optical semiconductor device, and manufacturing method of optical semiconductor device
JP2014138088A (en) * 2013-01-17 2014-07-28 Dainippon Printing Co Ltd Multiple mounted component of lead frame with resin, and multiple mounted component of optical semiconductor device
CN105830240B (en) * 2014-01-07 2019-11-01 亮锐控股有限公司 Light emitting device package
US10605730B2 (en) 2015-05-20 2020-03-31 Quantum-Si Incorporated Optical sources for fluorescent lifetime analysis
US11466316B2 (en) 2015-05-20 2022-10-11 Quantum-Si Incorporated Pulsed laser and bioanalytic system
JP7050068B2 (en) 2016-12-16 2022-04-07 クアンタム-エスアイ インコーポレイテッド Compact beam forming and steering assembly
US10283928B2 (en) * 2016-12-16 2019-05-07 Quantum-Si Incorporated Compact mode-locked laser module
AU2019287768A1 (en) 2018-06-15 2020-12-24 Quantum-Si Incorporated Data acquisition control for advanced analytic instruments having pulsed optical sources
JP7206483B2 (en) * 2018-12-10 2023-01-18 日亜化学工業株式会社 Semiconductor device manufacturing method and package member manufacturing method
US11747561B2 (en) 2019-06-14 2023-09-05 Quantum-Si Incorporated Sliced grating coupler with increased beam alignment sensitivity

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006318999A (en) * 2005-05-10 2006-11-24 Nitto Denko Corp Adhesive film for manufacturing semiconductor device
JP5232369B2 (en) * 2006-02-03 2013-07-10 日立化成株式会社 Manufacturing method of package substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device using the same
JP2007294715A (en) * 2006-04-26 2007-11-08 Renesas Technology Corp Method for manufacturing semiconductor device
JP5144294B2 (en) * 2008-02-06 2013-02-13 オンセミコンダクター・トレーディング・リミテッド Lead frame and method of manufacturing circuit device using the same

Also Published As

Publication number Publication date
JP2011119393A (en) 2011-06-16

Similar Documents

Publication Publication Date Title
JP5397195B2 (en) Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device
US11810778B2 (en) Optical semiconductor element mounting package and optical semiconductor device using the same
US8212271B2 (en) Substrate for mounting an optical semiconductor element, manufacturing method thereof, an optical semiconductor device, and manufacturing method thereof
JP5232369B2 (en) Manufacturing method of package substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device using the same
KR20130127379A (en) Substrate for optical semiconductor device and method for manufacturing the same, and optical semiconductor device and method for manufacturing the same
JP6021416B2 (en) Lead frame with reflector for optical semiconductor device, optical semiconductor device using the same, and manufacturing method thereof
JP5956937B2 (en) Method for manufacturing package substrate for mounting optical semiconductor element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121102

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130625

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130626

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130806

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130924

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131007

R151 Written notification of patent or utility model registration

Ref document number: 5397195

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

LAPS Cancellation because of no payment of annual fees