JP5390006B2 - Nonvolatile memory device - Google Patents

Description

  The present invention relates to setting of operation information in a nonvolatile memory device, and more particularly to an initialization operation at power-on or reset.

  In the nonvolatile semiconductor memory device disclosed in Patent Document 1, when the power is turned on, the initial setting data is latched from the initial setting data area provided in the memory cell array into the data latch circuit. Specifically, as shown in FIG. 11, when power-on is detected, a power-on reset is applied (S110), and after waiting for a predetermined time (S120), the ready / busy signal (R / B) is set to the Busy state. (S130). Then, defective address data, control voltage value data, and other initial setting data are read and set (S140 to S160). When all the initial setting data has been read, the R / B is set to the Ready state (standby state) (S170). The access prohibition is notified to the outside by the busy state of R / B.

The initial setting operation from the detection of power-on to the latching of the initial setting data to the data latch circuit is programmed in advance in a control circuit that controls the operation of writing and erasing so that it is automatically controlled in response to power-on. ing. When the control circuit is activated, the initial setting data is read by the same decode circuit and sense amplifier circuit as those for normal data reading.
Patent Document 2 is similar to Patent Document 1. In Patent Document 2, in addition to Patent Document 1, it is assumed that reading of initial setting data is performed based on an internal clock generated inside the chip, and this internal clock is trimming data for canceling process variations. If there is no adjustment due to the above, the variation in the cycle will be large, and the waiting time will become long if it varies to the long cycle side. Clock cycle adjustment data for adjusting the cycle is first read out, and the cycle of the clock generated by the clock generation circuit is adjusted. After this adjustment is completed, the remaining initial setting data is read. That is, it is disclosed that the remaining initial setting data is read based on the operation clock adjusted based on the clock cycle adjustment data. In Patent Document 2, similarly to Patent Document 1, until the defective address data S6, control voltage value data S7, and other initial setting data S8 are read and set, the access prohibition is notified to the outside by the R / B Busy state. It is done.
In addition, there exists patent document 3 as another related technical document.

JP 2001-176290 A (paragraphs 0009 and 0021) JP 2003-178589 A (paragraphs 0008 and 0010) JP-A-60-205428

  In Patent Documents 1 and 2, the R / B in the Busy state in which access from the outside is prohibited is output after the power is turned on until all initial setting data is latched in the data latch circuit. This prevents erroneous external access when the initial setting is not completed.

  However, the initial setting data of the nonvolatile memory device is, for example, circuit constant setting information during various operations, as well as redundant address setting information for repairing defective memory cells and the like, and a sector. Whether or not data can be written to a predetermined storage area, so-called write protect function setting information, and the like are included. These pieces of information tend to increase as the capacity of the nonvolatile storage device increases. This means that the required time for reading the initial setting data from the initial setting data area and latching it in the data latch circuit increases when the power is turned on. Further, in storing increasing initial setting data, it is convenient to assign a portion of the memory cell array, which is a normal data storage area, as the initial setting data area.

  During the reading of the initial setting data from the initial setting data area provided in one section of the memory cell array, the normal access operation cannot be performed on the memory cell array, and the length of the initial setting data increases. As a result of maintaining the busy state of time, there is a possibility that a large amount of time may be required for the initial setting when the power is turned on.

  In particular, when a non-volatile storage device is built into the system and a boot program or application program at the time of system startup is stored, the time from when the power is turned on until the boot program starts, or when the application program is started from power on There is a possibility that the time to do this may be long, which is a problem.

  The present invention has been made to solve at least one of the problems of the background art described above. In the initialization operation of the nonvolatile memory device performed at power-on or reset, the initialization operation and the external access operation are performed. It is an object to enable a read access operation to a nonvolatile memory device in a short time from the start of an initialization operation by suitably controlling and efficiently reading operation information.

The nonvolatile memory device according to the present invention is a nonvolatile memory device in which operation information set during the initialization operation is stored in the memory cell array, and information is read from the memory cell array during a read access operation. a read amplifier for performing a configuration in which the number of placement from the read amplifier is reduced, with a verify amplifier to check the rewriting state when the rewrite access operation, an automatic rewrite control circuit for controlling rewriting access operation, the initial time of operation, to activate the read out amplifier in place of the verification amplifier by utilizing the check operation of the rewriting state by the automatic rewrite control circuit, wherein the read out operation information.

In the nonvolatile memory device according to the present invention, the automatic rewrite control circuit for controlling the rewrite access operation performs the read control of the operation information at the time of the initialization operation, and confirms the rewrite state at the time of the rewrite access operation. Instead, the read amplifier is activated. Operation information is read from the memory cell array by a larger number of read amplifiers than the verify amplifier .

  As a result, when the operation information is read and set using the automatic rewrite control circuit during the initialization operation, the read operation is not limited to the amplifier (verify amplifier) for performing the rewrite state check (verify amplifier), and the continuous read access operation can be performed. In order to cope with this, a plurality of read amplifiers can be used, and a large number of operation information can be read at a time.

  According to the present invention, the operation information at the time of initialization operation performed at power-on or reset is preferentially read out of the operation information, and the operation information read operation and the read access operation are performed. Since the amplifiers used for each are used properly, the initialization operation and the external access operation are suitably controlled, the operation information read operation is performed efficiently, and the read access operation to the nonvolatile memory device can be performed early. can do.

1 is a circuit block diagram of a nonvolatile memory device that implements an embodiment of the present invention. It is a flowchart which shows the initialization operation | movement of 1st Embodiment of this invention. It is a wave form diagram which illustrates a status signal at the time of initialization operation of a 1st embodiment. In the first embodiment, it is a circuit block that controls a sense amplifier that reads information. It is a flowchart which shows the rewriting control operation | movement containing the initialization operation | movement of 2nd Embodiment of this invention. It is a flowchart which shows the process of a preprogram among the flows of FIG. In the second embodiment, it is a circuit block that controls a sense amplifier that reads information. FIG. 5 is a circuit block diagram showing a circuit configuration of a bit line and a read sense amplifier capable of a burst read operation. (A) is an operation waveform diagram when a burst read operation is performed in the circuit configuration of FIG. FIG. 9B is an operation waveform diagram when the initialization operation is performed in the circuit configuration of FIG. It is a circuit diagram which shows the circuit structural example of the reference cell part connected to a verification amplifier. 10 is a flowchart showing the initialization operation of Patent Document 1. FIG.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile memory device initialization control method and a nonvolatile memory device according to the present invention will be described below in detail with reference to the drawings based on FIGS.

  FIG. 1 is a circuit block diagram for realizing nonvolatile memory devices according to first and second embodiments described later. In the nonvolatile memory device of FIG. 1, each of the memory cell array regions 5A and 5B is provided with a plurality of banks 21A and 21B capable of independent access control (non-exclusive operation). The memory cell array regions 5A and 5B are constituted by a small block memory array called a large sector or a small sector having an arbitrary number of nonvolatile memory cells as a minimum unit of erasure. Here, the small sector and the large sector generally have different memory element capacities in one sector, and the number of arbitrary nonvolatile memory cells in the large sector is larger than that of the small sector. Furthermore, a redundant sector (not shown) for relieving a defect in a large sector or a small sector is also included. In addition, column redundant memory cells for redundant relief in bit line units are also provided in the large sector, small sector, and redundant sector, respectively. Each bank 21A, 21B includes non-redundant memory areas 1 and 2 that do not have a redundant repair configuration. In the non-redundant memory areas 1 and 2, there are boot sectors configured with an arbitrary number of nonvolatile memory cells. Generally, the boot sector stores a boot program at the time of system startup, the small sector stores an application program, and the large sector stores general data such as moving image and audio information.

  The access operation to these memory areas is performed by the command decoder 16 decoding the command signal input from the command terminal CMD. The command signal decoded by the command decoder 16 is sent to the control circuit 7. The control circuit 7 controls the address register 12, the voltage generation circuit 14, the read sense amplifier 3, the verify sense amplifier 4, and the operation information latch unit 6 which is a volatile storage unit for storing operation information in accordance with the command signal. . The circuit format of the operation information latch unit may be a general register format or an inverter latch format. Here, the voltage generation circuit 14 is a circuit that supplies a bias voltage necessary for the read / rewrite access operation to the row decoders 18A and 18B, the column decoders 19A and 19B, the memory area, and the like. The read sense amplifier 3 is connected to the output buffer 17 and outputs the data of the nonvolatile memory to the output terminal D0 which is an external I / O terminal. The verify sense amplifier 4 is used when rewriting (programming or erasing) the nonvolatile memory described later. This is a verification sense amplifier used, and the verification sense amplifier 4 is not connected to the external I / O terminal.

  The address signal input to the address register 12 from the address terminal ADD via the address buffer 15 is subjected to redundancy repair determination by the coincidence detection unit 13 as necessary, and then the row coders 18A and 18B and the column decoder 19A. , 19B, an address in the memory area is selected. In response to the command signal indicating the read access operation, information read from the column decoder is amplified by the read sense amplifier 3 in accordance with the input address signal, and output from the output buffer 17 to the output terminal DO via the read data line RDB. Is output.

  In the nonvolatile memory device, read operation information such as operation timing information of various circuits and bias voltage value setting information required for read access operation, redundant information such as row address and column address for performing redundancy relief, and rewriting Rewrite operation information such as bias voltage value setting information and write protect information necessary for the access operation is stored in advance in the memory area, for example, in a non-redundant memory area. In the initialization operation, it is necessary to read and set the operation information latch unit 6 in advance. For read / rewrite access operations and redundancy relief, these pieces of operation information are required. If these pieces of information stored in the memory area are read each time, the access operations are performed between the normal access operations. As a result, the access operation may be delayed or may not operate normally.

  In addition, as the capacity of the nonvolatile memory device increases, the operation information to be set in advance also increases, and the occupied area increases when a dedicated memory area is provided separately from the normal memory area. It will be enormous. In order to solve this problem, a control configuration in which a portion of a normal memory area is allocated and operation information is stored in advance and read to the operation information latch unit 6 in accordance with an initialization operation has been generally used. Yes.

  A control signal from the power-on reset circuit 11 that detects power-on and a reset signal (not shown) are input to the control circuit 7. The control circuit 7 controls the read sense amplifier 3 and the verify sense amplifier 4 to read operation information stored in the non-redundant memory area 1 and / or the non-redundant memory area 2. Further, the operation information latch unit 6 is controlled to latch the operation information read by these sense amplifiers 3 and 4. Further, various kinds of operation information are read from the operation information latch unit 6 at a predetermined timing described later, and the voltage generation circuit 14 and the coincidence detection unit 13 are controlled.

  The control circuit 7 receives a command signal from the command decoder 16 and an address signal from the address buffer 15 in accordance with the command signal. This is a case where a command for a read / rewrite access operation for a predetermined address is input from the outside. When the initialization operation is being executed, the control circuit 7 outputs a status signal indicating whether or not the access operation is possible according to the type of the command signal input and the address signal to be accessed. The status signal is output to the status terminal ST via the status output unit 8.

  Here, the status terminal ST may be configured to include a dedicated terminal, and may use a data terminal DQx (x is, for example, 0 to 2) (not shown) as will be described later with reference to FIG. it can. Here, the data terminal DQx refers to a data output terminal or a data input / output terminal which is an external I / O terminal. In FIG. 1, for example, the output terminal DO.

  The operation information read in the initialization operation is stored in a portion of the memory area, but this area is stored in the non-redundant memory area 1 or / and 2 in which no redundant relief is performed. Is preferred. Redundant information such as information about an address to be redundantly repaired is also stored as operation information, and should not be redundantly repaired by the coincidence detection unit 13 unless the redundant information is latched in the operation information latch unit 6. The memory cell is not fixed. For this reason, at the stage of reading the operation information until the redundant information is latched, the access operation to the memory cell array regions 5A and 5B capable of redundant relief cannot be performed.

  As will be described later, it is preferable to preferentially read out the read operation information for setting the read condition as the read order of the operation information. As a result, the operation conditions for performing the read access operation can be set, so that the read access operation from the non-redundant memory area 1 or / and 2 is possible even if the initialization operation for reading other operation information continues. Because it becomes. If a boot program, which is a system startup program, is stored in the non-redundant memory area 1 or / and 2, a normal read access operation can be executed in parallel with the initialization operation to read the boot program. it can. The system can be started, and the system startup time after power-on or reset can be shortened.

  In this case, the operation information and the boot program are stored in the non-redundant memory areas 1 and 2 in the different banks 21A and 21B, the operation information is read by the verify sense amplifier 4, and the boot program is read by the sense amplifier. By performing the control of reading in step 3, it is possible to perform the reading of the operation information during the initialization operation and the read access operation of the boot program in parallel. Here, in FIG. 1, each bank has a configuration including one set of read sense amplifier 3 and one set of verify sense amplifier 4. However, the implementation requirement of the invention is not limited to this, and one set of read is provided for each bank. The sense amplifier 3 and a set of verify sense amplifiers 4 may be provided.

  FIG. 2 is a flow showing the first embodiment. This will be described with reference to the circuit block diagram of FIG. In response to input of a power-on or reset command, the nonvolatile memory device starts an initialization operation. First, in response to an access request by a command signal or the like from the command terminal CMD, the control circuit 7 has a busy state indicating that the access operation is impossible because the operation information is not latched at the start of the initialization operation. The status flag shown is set (S11), and a busy signal is output via the status output unit 8 in response to an external access request.

  The control circuit 7 starts latch control of the initialization operation. In this case, first, the read operation information for setting the read condition is read preferentially (S12). Specifically, the control circuit 7 acts on the address register 12, and the address register 12 outputs an address signal indicating the position of the address space in which the read operation information is stored among the operation information. Further, the read sense amplifier 3 and / or the verify sense amplifier 4 are activated to read the read information.

  In reading the read operation information, the verify sense amplifier 4 can be used, and since the external access request is prohibited, the read sense amplifier 3 can also be used. In general, the read sense amplifier 3 used for the read access operation can perform a read operation at a higher speed than the verify sense amplifier 4 used for the rewrite operation, and also supports a burst operation and the like. Many are provided according to what is comprised. Therefore, in the read operation of the read operation information in the initialization operation, the number of sense amplifiers to be read simultaneously increases by activating the read sense amplifier 3 instead of or together with the verify sense amplifier 4, High-speed operation information can be read out.

  When the latching of the read operation information to the operation information latch unit 6 is completed (S13: Y), the control circuit 7 determines that the operation condition related to the read operation is latched by the operation information latch unit 6, and the non-redundant memory region 1 2 is set (S14), and a status output unit 8 responds to a read access request to the non-redundant memory areas 1 and 2 from the outside. The ready signal is output via At the same time, the latched read operation information acts on the voltage generation circuit 14 to supply the bias voltage at the time of the read operation to the memory regions of the row decoders 18A and 18B, the column decoders 19A and 19B, and the banks 21A and 21B. . Further, it acts on the read sense amplifier 3 and the verify sense amplifier 4 to control the sense amplifier that performs the read access operation and the reading of the operation information accompanying the initialization operation. For the read access request to the memory cell array regions 5A and 5B, a busy signal is output because the latching of redundant information is not completed. In response to the rewrite access request, since the rewrite operation information is not latched, a busy signal is output for all memory area access requests.

  A read access operation is possible for the non-redundant memory areas 1 and 2 to which a ready signal is output in response to a read access request. Since a bank different from the bank in which the operation information is stored can be operated in parallel, the boot program and the like can be read in parallel with the reading of the operation information. The initialization operation from the start of the initialization operation until the read access operation to the non-redundant memory areas 1 and 2 is enabled is step I.

  Subsequent to the latching of the read operation information, redundant information related to redundant relief is read (S15). Specifically, the control circuit 7 acts on the address register 12, and an address signal indicating the position of the address space in which redundant information is stored is output from the address register 12. Further, the verify sense amplifier 4 is activated to read the read information.

  The verify sense amplifier 4 can be used for reading redundant information. This is because the read access operation of the boot program is executed based on the read operation information that has been latched in the previous stage, and the read sense amplifier 3 may be occupied. The boot program is read to the output terminal DO via the read data line RDB and the output buffer 17 by the read sense amplifier 3, and redundant information is read by the verify sense amplifier 4 and latched in the operation information latch unit 6. The The initialization operation of the nonvolatile memory device and the startup operation associated with the reading of the boot program from the nonvolatile memory device can be performed in parallel. If each bank has one set of read sense amplifiers 3 and one set of verify sense amplifiers 4, the bank in which the read access operation of the boot program is executed and the operation information of the redundant information is read out. If the bank is different, the read sense amplifier 3 is used for reading the boot program, while the read sense amplifier 3 is used for reading the operation information of the redundant information, and the verify sense amplifier 4 is used. Both can be used.

  When the redundancy information latching to the operation information latch unit 6 is completed (S16: Y), the control circuit 7 determines that the address information of the memory cell to be redundantly repaired is latched by the operation information latch unit 6. The match detection unit 13 refers to the redundant information output from the operation information latch unit 6 to determine whether the address signal output from the address register 12 is an address that should be redundantly repaired. Redundant relief is performed in the memory cell array regions 5A and 5B of 21A and 21B. In addition to the non-redundant memory areas 1 and 2, a status flag indicating a ready state for notifying that the read access operation from the memory cell array areas 5A and 5B is possible is set (S17), and the memory cell array area from the outside A ready signal is output via the status output unit 8 in response to a read access request to 5A and 5B. In response to the rewrite access request, since the rewrite operation information is not latched, a busy signal is output for the access request to all the memory areas.

  The read access operation for the non-redundant memory regions 1 and 2 is already possible in Step I, and in addition, the read access operation can be performed for the memory cell array regions 5A and 5B. Since a bank different from the bank in which the operation information is stored can be operated in parallel, the boot program can be read continuously from step I in parallel with the reading of the operation information. Furthermore, the application program can be read following the completion of reading the boot program or instead of reading the boot program. The initialization operation from the start of reading redundant information in the initialization operation until the read access operation to the memory cell array regions 5A and 5B becomes possible is step II.

  Following the redundancy information latch, the rewrite operation information for setting the rewrite condition is read (S18). Specifically, the control circuit 7 acts on the address register 12, and an address signal indicating the position of the address space where the rewrite operation information is stored is output from the address register 12. Also, the verify sense amplifier 4 is activated to read out the rewrite operation information.

  For reading out the rewrite operation information, the verify sense amplifier 4 can be used. Based on the read operation information and redundancy information that have been latched by the previous stage, the read access operation of the boot program or application program is executed for the non-redundant memory areas 1 and 2 and the memory cell array areas 5A and 5B. This is because the read sense amplifier 3 may be occupied. The read sense amplifier 3 reads the boot program and application program to the output terminal DO via the read data line RDB and the output buffer 17, and the verify sense amplifier 4 reads the rewrite operation information, and the operation information latch unit 6 is latched. The initialization operation of the non-volatile storage device and the system or application start operation accompanying the reading of the program from the non-volatile storage device can be performed in parallel. If each bank has one set of read sense amplifiers 3 and one set of verify sense amplifiers 4, the bank in which the read access operation of the boot program is executed and the operation information of the rewrite operation information can be read. If the bank to be executed is different, the read sense amplifier 3 is used for reading the boot program, while the read sense amplifier 3 is used for reading the operation information of the rewrite operation information, and the verify sense amplifier 4 is used. Both can be used.

  When the rewrite operation information latching to the operation information latch unit 6 is completed (S19: Y), the control circuit 7 determines that the operation condition related to the rewrite operation is latched in the operation information latch unit 6. The rewrite operation information output from the operation information latch unit 6 is input to the voltage generation circuit 14, and the bias voltage during the rewrite operation is the memory area of the row decoders 18A and 18B, the column decoders 19A and 19B, and the banks 21A and 21B. To be supplied. In addition to the non-redundant memory areas 1 and 2, a status flag indicating a ready state for notifying that a rewrite access operation to the memory cell array areas 5A and 5B is possible is set (S20), and a rewrite access request from the outside In response to this, a ready signal is output via the status output unit 8.

  The read access operation is already possible by step II, and in addition to this, a rewrite access operation is possible. Thereby, the initialization operation is completed. The initialization operation from the start of reading of the rewrite operation information until the rewrite access operation becomes possible is defined as Step III.

  In the flow of FIG. 2, when memory cell arrays 5A and 5B in which redundancy relief is performed and non-redundant memory areas 1 and 2 in which redundancy relief is not performed are mixed as memory areas, the read operation is performed as an initialization operation. The flow of the initialization operation that enables the read access operation to the non-redundant memory areas 1 and 2 with priority given to the latch of the operation information has been described. Depending on the nonvolatile storage device, there may be a case where the non-redundant memory areas 1 and 2 do not exist. That is, the boot sector is redundant as in the large sector. In this case, it is preferable to prioritize latching redundant information together with read operation information as an initialization operation. When the latching of these operation information is completed, the read access operation can be performed on all the memory areas.

  FIG. 3 shows an output example of a status signal in response to an access request from the outside. As an external access request, at least one of the / WE signal, the / CE signal, and the / OE signal becomes low level and becomes active and an address signal is input, and a ready signal RDY is output from a dedicated status terminal. Is output. That is, according to the initialization stage of Steps I to III in FIG. 2, when the access operation is possible, the ready signal RDY transitions to a high level to notify that it is in a ready state. When the access operation is not possible, the ready signal RDY transitions to a low level to notify that it is in a busy state.

  In FIG. 3, instead of the ready signal RDY or using the data terminal DQx (x = 0 to 2) together with the ready signal RDY, an input access request is input in accordance with each initialization operation step of steps I to III. It shows a configuration capable of notifying whether or not it is possible. When the toggle signal is output as the data signal DQx in association with the repetitive operation of the / WE signal, the / CE signal, the / OE signal, etc., the busy state is notified. That is, in the initialization operation state of Step I, a toggle signal (in this case, 4 cycles) is output as the data signal DQ0. Similarly, a toggle signal (in this case, 4 cycles) is output as the data signal DQ1 when in the initialization operation state of Step II, and as the data signal DQ2 when in the initialization operation state of Step III. A toggle signal (in this case, 4 cycles) is output. When the latching of the operation information at each step is completed, the valid data signal DQ0 is output when the latch operation at step I is completed. Similarly, a valid data signal DQ1 is output when the latch operation in Step II is completed, and a valid data signal DQ2 is output when the latch operation in Step III is completed. Further, the stage of the initialization operation can be identified by a combination of the data signal DQ0, the data signal DQ1, and the data signal DQ2 instead of the toggle signal (in this case, 4 cycles).

  When there is an access request from the outside, a status signal as to whether or not an input access operation is possible for the input address signal is notified as a ready signal RDY. Accordingly, whether or not each access request can be made can be determined by confirming the logic level of the ready signal RDY. Further, instead of the ready signal RDY or together with the ready signal RDY, the data signals DQ0 to DQ2 can be used as a status signal indicating each stage of the initialization operation. Accordingly, if an access request is made from the outside, it is possible to identify which stage of the initialization operation is performed, and according to this, it is possible to determine the access type and address for which an access request can be made.

  4, when reading operation information from the memory area in the initialization operation shown in FIG. 2, the sense amplifier is preferably selected according to the stage of the initialization operation, and the operation information necessary for the initialization operation, This is a circuit configuration for efficiently reading the boot program and application program. In FIG. 4, as an example, it is assumed that the bit line BL has a 32-bit width, information is read to the read data line RDB in units of 32 bits, and a rewrite operation is performed in units of 16 bits. Here, the reason why the read data line RDB in the read operation is 32 bits wide and has a bit width twice as large as the 16 bit width in the rewrite operation is to perform a high-speed continuous read operation. This is to realize a so-called burst operation in which the bit lines BL are alternately read out with a 16-bit width.

  The bit line BL is connected to the read sense amplifier 3 for each bit line BL via the read column decoder 19R, and either one for every two bit lines BL via the verify column decoder 19W. The book is selected and connected to the verify sense amplifier 4. The read sense amplifier 3 is connected to the output buffer 17 and the operation information latch unit 6 via the read data line RDB. The verify sense amplifier 4 is connected to the operation information latch unit 6.

  The read column decoder 19R receives the bank address ADD_BNK and either the odd lower address ADDO or the even lower address ADDE to the NAND gate and is further inverted by the inverter gate, and the bank address ADD_BNK and the lower address ADDO or A logical product operation with ADDE is performed. The logical product operation result and the step I state signal ST1 indicating that the initialization operation is in step I are logically ORed through the NOR gate and the inverter gate, and the decode signals ENO and ENE are output. Half of the read column decoder 19R receives the decode signal ENO according to the odd lower address ADDO. The remaining half receives the decode signal ENE according to the lower address ADDE of the equal number.

  In a state where normal access operation is possible or in the initialization state, the state after step II is the step I state signal ST1, which is low level, and decoding is performed according to the logical product operation result of the bank address ADD_BNK and the lower address ADDO or ADDE. Done. That is, when an odd lower address ADDO is input to the selected bank, the decode signal ENO goes high, and half of the corresponding column decoders 19R are selected. When an even number of lower addresses ADDE are input to the selected bank, the decode signal ENE goes high, and the corresponding half of the decoders among the read column decoders 19R are selected. In the state of step I in the initialization operation, the step I state signal ST1 is at a high level. In this state, the decode signals ENO and ENE are both at the high level regardless of whether the lower address is strange. Thirty-two bit lines BL are connected to the read sense amplifier 3.

  The read sense amplifier 3 is either when the verify signal ENV for instructing the verification (verification) of the rewrite state during the rewrite operation and the step I state signal ST1 are both at the high level, or when the address transition signal ATD is at the high level. In this case, the timer circuit 31 is started. The timer circuit 31 activates the read sense amplifier 3 at a predetermined timing. The activation timing is performed according to the output of the address transition signal ATD in a state in which a normal access operation is possible or in an initialization operation state after Step II. The address transition signal ATD is a signal issued in response to an address input. The read sense amplifier 3 is activated in response to the address input, and information is read out.

  Here, the control circuit 7 that controls reading of operation information in the initialization operation includes an automatic rewrite control circuit that controls the procedure of the rewrite operation, as will be described later. The reading of the operation information is performed using a rewrite state confirmation (verification) procedure in the automatic rewrite control circuit. The verify signal ENV is output by the automatic rewrite control circuit. In the initialization operation, when the verify signal ENV is output and the operation information is read, if the step I state signal ST1 is at a high level and is in the step I state, the read sense amplifier 3 is activated and the operation information is stored. Read from the read sense amplifier 3.

  The verify column decoder 19W receives the step I state signal ST1 and an inverted signal obtained by inverting either the odd lower address signal ADDO or the even lower address signal ADDE at the inverter gate. Decoded.

In a state in which a normal access operation is possible or in an initialization operation state, the step I state signal ST1 is at a low level in the state after Step II. When either one of the odd lower address signal ADDO or the even lower address signal ADDE is selected and becomes high level, one of the two transistors constituting the verifying column decoder 19W is selected, and 32 bits are selected. Half of the width bit lines BL are connected to the verify sense amplifier 4. In the state of step I in the initialization operation, the step I state signal ST1 is at a high level. In this state, the two transistors constituting the verifying column decoder 19W are both unselected regardless of whether the lower address is strange or not.

  The verify sense amplifier 4 is controlled by inputting a step I state signal ST1 and an inverted signal obtained by inverting the verify signal ENV instructing confirmation (verification) of the rewrite state at the time of the rewrite operation to the NOR gate. . The verify sense amplifier 4 is activated and controlled in accordance with the logical operation result of the step I state signal ST1 and the verify signal ENV. In the state of step I in the initialization operation, the step I state signal ST1 is at a high level.

  In a state where a normal access operation is possible or in a state after Step II in the initialization state, the Step I state signal ST1 is at a low level. In this case, the verify sense amplifier 4 is activated in response to the high level verify signal ENV. In addition to the case where the rewrite state is confirmed (verified) according to the rewrite access operation, the verify sense amplifier is used when the boot program or application program is read from the read sense amplifier 3 in step II and subsequent steps of the initialization operation. 4 can read the operation information. In the state of step I in the initialization operation, the step I state signal ST1 is at a high level. In this case, the verify sense amplifier 4 is inactivated regardless of the verify signal ENV.

During the initialization operation, when reading the read operation information for setting the read conditions in step I, various programs such as a boot program and data are not yet read, so that a read sense capable of high-speed operation is possible. The use of the amplifier 3 increases the number of sense amplifiers that are read simultaneously, so that operation information can be read at high speed. In step II and subsequent steps, which are initialization operations after the read conditions are set, the read sense amplifier 3 can be used for reading the boot program and the like by reading the operation information with the verify sense amplifier 4. An initialization operation and a reading operation such as a boot program can be performed in parallel. In addition to parallel reading of the operation information and the boot program, the read operation information can be read at high speed, and the time until the external access operation such as the boot program can be started can be further shortened.
If each bank has one set of read sense amplifiers 3 and one set of verify sense amplifiers 4, the bank in which the read access operation of the boot program is executed and the operation information of the redundant information is read out. If the bank is different, the read access operation of the boot program is used for the read access operation of the boot program in step II and subsequent steps, which are the initialization operations after the read condition is set, while using the read sense amplifier 3. For reading the operation information, at least one of the read sense amplifier 3 and the verify sense amplifier 4 can be used. In this case, the operation information is controlled and read by the automatic rewrite control circuit included in the control circuit 7, but can be read by the read sense amplifier 3 or the verify sense amplifier 4 according to the control by the automatic rewrite control circuit. It is possible to read out by using both sense amplifiers.

  FIG. 5 is a flow showing the second embodiment. This is a flow controlled by an automatic rewrite control circuit (not shown) included in the control circuit 7 (FIG. 1). FIG. 5 shows a processing flow of the erase operation in the rewrite access operation. When the automatic rewrite control circuit is activated, it is determined whether the activation is based on an initialization operation (S21). If the activation is based on the normal rewrite access operation instead of the initialization operation (S21: F), an erase timeout is executed (S22). An address signal such as a sector to be erased is input during the erase timeout period. If it is an initialization operation, it is not necessary to execute the erase timeout, so S22 is skipped (S21: T).

  Next, it is determined whether pre-program verification is necessary (S23). When it is determined that the preprogram processing routine (S24) is not necessary (S23: T), it is determined whether or not it is an initialization operation (S26). If it is an initialization operation (S26: T), automatic rewriting is performed. The processing by the control circuit ends. When the initialization operation is not performed, a normal erase operation is performed. Erase verify is performed (S27), and if necessary (S27: F), the erase operation is executed (S28), the APDE verify operation (S29), and the APDE operation (S30) are repeated. Thereafter, the soft program verify ( S31) and the soft program operation (S32) are executed to end the erase operation. Note that preprogramming is to temporarily program only the nonvolatile memory cells in the erased state before erasing in order to avoid over-erasing of the nonvolatile memory cells. In addition, APDE and soft program are also steps for improving the distribution width of the threshold characteristic of the nonvolatile memory cell after erasure in the reduction direction.

  If there is an erased memory cell in the erase access operation by the preprogram verify (S23) or in the case of the initialization operation (S23: F), the process proceeds to a preprogram processing routine (S24).

  FIG. 6 shows the contents of the processing routine of the preprogram (S24). In the routine for the preprogram operation, first, it is determined whether or not it is an initialization operation (S41). If it is an initialization operation (S41: T), the initial address of the storage area for the operation information is set (S42). If it is not an initialization operation (S41: F), the initial address to be erased is set (S43). Then, a read operation is executed (S44). Thereafter, if it is an initialization operation (S45: T), the read operation information is transferred to the operation information latch unit 6 (S46). Thereafter, it is determined whether or not the read information is the information of the final address (S49). If the read information is not at the final address (S49: F), the address is updated (S50) and the process returns to S44 to perform a read operation ( After repeating the transfer operation (S46) from S44), the preprogram routine is terminated when the read address is completed (S49: T).

  If it is determined in S45 that the operation is not an initialization operation (S45: F), a verify operation is performed (S47). If it is determined that the read information is not in the program state by the verify operation (S47: F), the pre-program operation is executed (S48), the process returns to S44, and the verify operation (S47) is executed again from the read operation (S44). Is done. If it is determined that the read information is in the programmed state by the verify operation (S47: T), it is determined whether the read information is the information of the final address (S49), and if it is not at the final address (S49). : F), the address is updated (S50), the process returns to S44, the verify operation (S47) is performed from the read operation (S44), and the preprogram routine is terminated when the read address is completed (S49: T).

  Thus, in the preprogram routine (S24) of the automatic rewrite control circuit included in the control circuit 7, the read operation (S44) provided for verifying the preprogram state is used to perform the initialization operation. The operation information can be read out.

  In this case, the read operation (S44) uses the verify sense amplifier 4 in the case of a normal verify operation. However, in order to enable a multiple information read operation at the same time, the read sense amplifier 3 is replaced with the verify sense amplifier 4. FIG. 7 shows the circuit configuration used.

  In FIG. 7, an initialization signal INI indicating an initialization operation state is input instead of the step I state signal ST1 in the circuit configuration shown in FIG. Here, the initialization signal INI is a signal output in response to power-on by the power-on reset circuit 11, or a signal generated in response to the same signal, or generated in response to a reset signal (not shown). Signal. When the initialization operation is performed, the level becomes high, the verify column decoder 19W is deselected, the verify sense amplifier 4 is deactivated, and the read column decoder 19R is selected to activate the read sense amplifier 3.

  Thereby, the read operation (S44) at the time of verification in the preprogram routine (S24) can be executed using the read sense amplifier 3. Since the rewrite access operation including the erase access operation requires a larger current than the read access operation, the bit width during the rewrite access operation is smaller than the bit width during the read access operation shown in FIG. Thus, a further reduced configuration may be considered. When the read access operation enables a burst operation capable of high-speed continuous access operation, coupled with the fact that a larger number of read sense amplifiers 3 can be simultaneously activated than the data width at the time of read access. Thus, a large amount of operation information can be read simultaneously as compared with the rewrite access operation while utilizing a part of the operation sequence in the automatic rewrite control circuit. The initialization operation period can be shortened, and the time from the start of the initialization operation to the start of the external access operation such as reading of the boot program can be shortened.

In the circuit block diagram of FIG. 7, in the reading of the operation information at the time of the initialization operation, the read operation at the time of verification in the automatic rewrite control circuit included in the control circuit 7 is used according to the initialization signal INI. The case where the operation information is read using the read sense amplifier 3 instead of the verify sense amplifier 4 is illustrated. However, the second embodiment is not limited to this. In the circuit block diagram of FIG. 7, instead of the initialization signal INI input to the logic circuit that controls the verify column decoder 19W and the verify sense amplifier 4, it is fixedly input to the low level signal, thereby rewriting The operation information read according to the read operation (S44) at the time of verify can be read by the verify sense amplifier 4 in addition to the read sense amplifier 3. The bit width that can be read simultaneously can be further increased.
In the second embodiment, the verification of the preprogram routine is used. However, the present invention is not limited to this. For example, the verification in the erase routine, the verification in the APDE routine, or the verification in the soft program routine may be used. . In this case, since an ideal threshold value is different for each verify, a reference cell that functions only to read operation information during the initialization operation can be used as a reference threshold for the verify sense amplifier 4.

  According to the circuit block diagram shown in FIG. 8 and the operation waveform diagram shown in FIG. 9, if the second embodiment is applied to the circuit configuration having the burst read operation as the read access operation, the operation information read simultaneously during the initialization operation It will be explained that the bit width is expanded.

  In FIG. 8, each bit line BLO0, BLE0 to BLO15, BLE15 arranged in the memory cell array region includes a read column decoder 19R and a read sense amplifier 3. The read column decoder 19R is selected by the decode signals ENO and ENE at the odd and even positions, respectively, and is connected to each read sense amplifier 3. Each read sense amplifier 3 is connected to selection circuits 32O and 32E via data lines RDBO0 to RDBO15 and RDBE0 to RDBE15 at odd positions and even positions, respectively. The selection circuits 32O and 32E are selected based on the logical product operation result of the inverted signal of the initialization signal INI and the decode signal ENE and the logical product operation result of the inverted signal of the initialization signal INI and the decode signal ENO. RDBO0 to RDBO15 or data lines RDBE0 to RDBE15 are connected to the read data line RDB. The data lines RDBO0, RDBE0 to RDBO15, and RDBE15 are connected to the operation information latch unit 6.

  In FIG. 1, instead of connecting the operation information latch unit 6 and the output buffer 17 from the read sense amplifier 3 via the read data line RDB, in FIG. In this configuration, the amplifier 3 is connected to the output buffer 17 via the selection circuits 32O and 32E.

  As shown in FIG. 9A, in the read access operation, the decode signals ENO and ENE are alternately activated in response to the address signal ADD being sequentially incremented and alternately switched between the odd address and the even address. The The read column decoder 19R at odd positions is selected in accordance with the decode signal ENO, and the information read out by the read sense amplifier 3 at odd positions and output to the data lines RDBOx (x = 0 to 15) is updated. The even column read column decoder 19R is selected in accordance with the decode signal ENE, and the information read by the even position read sense amplifier 3 and output to the data line RDBEx (x = 0 to 15) is updated. That is, the decode signals ENO and ENE are control signals that selectively activate the read sense amplifier 3.

  At this time, since the initialization signal INI is at a low level, the selection circuits 32O and 32E are controlled according to the decode signals EVE and EVO, and the read data line RDB is connected to the unupdated data line. That is, when the data line RDBOx (x = 0 to 15) is updated, the selection circuit 32E is selected in accordance with the decode signal ENO, and the data line RDBEx (x = 0 to 15) is connected to the read data line RDB. Is done. When the data line RDBEx (x = 0 to 15) is updated, the selection circuit 32O is selected according to the decode signal ENE and connected to the read data line RDB. As a result, the odd address bit lines and the even address bit lines are alternately switched with respect to the bit lines BLO0, BLE0 to BLO15, and BLE15 having the bit width of 32 bits, and the read data having the bit width of 16 bits is obtained. A burst operation is performed via line RDB.

  On the other hand, in the initialization operation, as shown in FIG. 9B, the decode signals ENO and ENE are set regardless of whether the address signal is odd or not in accordance with the sequential increment of the address signal ADD. Both are activated (full selection). Regardless of the odd or even number, all the read column decoders 19R are selected, the read operation is performed by all the read sense amplifiers 3, and the information output to the data lines RDBOx and RDBEx (x = 0 to 15) is displayed every address cycle. Updated. Here, since the initialization signal INI is activated to a high level, both the selection circuits 32O and 32E are kept in a non-selected state. It is not output to the outside via the output buffer, but is latched in the operation information latch unit 6 as operation information. As a result, the operation information is read out with a bit width of 32 bits. In other words, during the initialization operation, the operation signals are read out by the number of read sense amplifiers larger than the number of read sense amplifiers 3 activated in the read access operation by the decode signals ENO and ENE which are control signals of the read sense amplifier 3. Take control.

  In this case, since the read sense amplifier 3 is disconnected from the read data line RDB, the load capacity is reduced and the address increment cycle can be shortened.

  When the operation information is read using the control by the automatic rewrite control circuit, it is desirable to change the control of the internal power supply voltage generated inside as follows. In general, in a nonvolatile memory device, a plurality of types of internal voltages are generated simultaneously mainly for programming, erasing and verifying. It is a positive boosted high voltage or a negative boosted high voltage. For example, in the former, a boosted voltage 8V is generated with respect to the external voltage 1.8V at the time of programming. In addition, a boosted voltage 4V with respect to the external voltage 1.8V is generated at the time of reading. In the latter case, a negative boosted voltage of -8V with respect to the external voltage of 1.8V is generated. A dedicated voltage booster circuit is provided for generating each internal voltage. These voltage boosting circuits have a charge pump type composed of a multi-stage capacitor, and each voltage is generated by being regulated to a predetermined voltage value. The generation time becomes longer as the voltage difference between the external voltage and the target internal voltage is larger. In the automatic rewrite control circuit, all types of internal voltages are set to have a sufficient voltage value, and a large amount of time is set in order to ensure a sufficient maximum voltage. More specifically, the time required for reading is 10 ns per time, which is as long as 1 ms or more, and a great amount of time is added each time the steps of the routines shown in FIGS. 5 and 6 are repeated. .

  When reading the operation information in the initialization operation, only one type of internal voltage necessary for the read operation needs to be generated, and it is possible to shorten a great amount of time set by the automatic rewrite control circuit 2. . Specifically, when reading, an internal voltage of about 4 V applied to the word line may be used, and the charge pump type requires only two to three capacitor stages, or a dedicated booster circuit with a small number of stages can be used for generation. The required time can be shortened.

  Therefore, when reading the operation information during the initialization operation, the time until the data latch of the operation information can be speeded up by controlling the read start timing or read cycle to a time shorter than the normal setting time. It is possible to shorten the time until the program is read.

  In the first and second embodiments, when the level of information read by the verify sense amplifier 4 is confirmed, a reference cell for reading is required. FIG. 10 shows a configuration example of the reference cell unit.

  The reference cell unit 33 includes a memory cell MCER for erase verification and a memory cell MCP for program verification, which are necessary for verification. Each gate terminal is connected to an erase word line ERV-WL and a program word line PGMV-WL, and each drain terminal is controlled by an erase verify signal ERV and a program verify signal PGMV. It is connected to the reference data line RefDB via TER and TP. The source terminal is connected to the ground potential. The reference data line RefDB is connected to the verify sense amplifier 4 to read information.

  In the reference cell unit 33, in addition to these, the read storage cell MCR has a gate terminal connected to the read word line READ-WL, a source terminal connected to the ground potential, and a drain terminal connected to the read control signal. It is connected to the reference data line RefDB via a controlled selection transistor TR. Here, the read control signal is a control signal for reading operation information during the initialization operation.

  As a result, the verify sense amplifier 4 performs the erase word line ERV-WL, the program word line PGMV-WL, and the read word line READ-WL in each case of the read operation in addition to the erase operation and the program operation. Further, according to the selection of the erase verify signal ERV, the program verify signal PGMV, and the read control signal, the verify sense amplifier 4 can read the data based on the corresponding reference cell connected to the reference data line RefDB.

  In this case, the current drive capability of the read storage cell MCR can be set smaller than the current drive capability of the reference cell used in the normal read access operation. The number of memory cells in which operation information is stored can be limited according to the number of operation information to be stored, and the number of memory cells connected per bit line can be set to a normal bit line. Compared to a small number. This is because the column leak current per bit line caused by the memory cell storing the operation information can be reduced, and the amount of current flowing through the reference cell can be limited accordingly.

  Instead of providing the read memory cell MCR, it is also conceivable to change the current drive capability of the transistors of the read sense amplifier 3 and the verify sense amplifier 4 that read operation information together with the read memory cell MCR. That is, when reading the operation information, by using the memory cell MCP for program verification, increasing the current drive capability of the transistor to which the reference cell is connected, and also using the memory cell MCER for erase verification However, by reducing the current drive capability of the transistor to which the reference cell is connected, it is possible to make the sense amplifier have the characteristics required for the read operation.

  If a bit line is provided for each memory cell in which operation information is stored, there is no other non-selected memory cell, and the problem of column leakage current can be solved in the operation information read operation.

  For memory cells connected to the same bit line, storing the same operation information can suppress the problem of column leakage current in the operation information read operation.

As is apparent from the above description, according to the present embodiment, the read operation information is preferentially read and set, and the read access operation can be performed in the initial stage of the initialization operation. After the read access operation is enabled, a normal data read operation including a boot program and an application program can be performed in parallel with the operation information read setting.
In this embodiment, the case of high-speed reading of the boot sector has been described, but the present invention can also be applied to high-speed reading of a small sector. That is, if the redundant address setting information is not applied to the small sector, the small sector can also be included in Step I of FIG. 2, and the application program can be read at high speed like the boot program. improves.

If a plurality of banks 21A and 21B that can be accessed independently are provided, the operation information is stored in one bank and the boot program or application program is stored in the other bank. After this setting, the reading of the operation information and the reading of the program can be performed in parallel.
Furthermore, the various types of operation information illustrated in FIG. 1 may be arranged in a region independent of each bank, for example, in a peripheral circuit where a logic circuit for driving the memory cell array exists.

  Further, for reading the operation information during the initialization operation, a verify sense amplifier 4 different from the read sense amplifier 3 used in a normal read access operation can be used, and parallel reading can be performed. In this case, since the normal read access operation is not performed at the stage of reading the read operation information among the operation information, the operation information can be read using the read sense amplifier 3. In general, the read sense amplifier 3 can perform a high-speed read operation as compared with the verify sense amplifier 4, so that operation information can be read at high speed.

  When reading the operation information during the initialization operation, the read information is read using the read sense amplifier 3 used for the read access operation instead of the verify sense amplifier 4 while using the read operation at the time of verification in the control of the automatic rewrite control circuit. be able to. High-speed reading can be performed by using the read sense amplifier 3 that is provided more than the verify sense amplifier 4.

  The time from the start of the initialization operation to the reading of the boot program or application program can be shortened, and the time until the system is activated in the system in which the nonvolatile storage device is incorporated can be shortened.

The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the embodiment, the case where operation information is read using the verify function of the erase access operation in the automatic rewrite control circuit has been described. However, the present invention is not limited to this, and other reading such as a program function is possible. It goes without saying that movement can be used.

The technical ideas related to the present application are listed below.
(1)
During the initialization operation, when reading and setting the operation information from the memory cell array, the read operation information necessary for the normal data read operation is set in preference to the rewrite information necessary for the normal data rewrite operation. A method for controlling initialization of a nonvolatile memory device.
(2)
After setting the read operation information,
Reading and setting the operation information excluding the read operation information;
Enabling a read access operation to a non-redundant memory area not including a redundant configuration,
The initialization control method for a nonvolatile memory device according to (1), which is performed in parallel.
(3)
The non-redundant memory area includes a boot sector, the operation information excluding the read operation information is read and set, and the read access operation of the boot sector is executed in parallel (2) The initialization control method of the non-volatile memory device described in 1.
(4)
After setting the read operation information, or setting the read operation information, the step of setting redundant information among the operation information,
After setting the redundant information,
Reading and setting the operation information excluding the read operation information and the redundant information;
Enabling a read access operation to the memory cell array.
The initialization control method for a nonvolatile memory device according to (1), which is performed in parallel.
(5)
The memory cell array includes a boot sector or / and a small sector, reads and sets the operation information excluding the read operation information and the redundancy information, and reads access operation of the boot sector or / and the small sector Are executed in parallel, the initialization control method for a nonvolatile memory device according to (4).
(6)
After setting the read operation information, the step of setting redundant information among the operation information,
After setting the redundant information,
Reading and setting the operation information excluding the read operation information and the redundant information;
Enabling a read access operation to the memory cell array.
The initialization control method for a nonvolatile memory device according to (2), which is performed in parallel.
(7)
The memory cell array includes a small sector, wherein the operation information excluding the read operation information and the redundant information is read and set, and the read access operation of the small sector is executed in parallel. The initialization control method for a nonvolatile memory device according to (6).
(8)
The operation information set in parallel with the read access operation being enabled for the memory cell array is rewrite operation information,
After setting the rewrite information,
The initialization control method for a nonvolatile memory device according to (4), further comprising a step of enabling a rewrite access operation to the memory cell array.
(9)
The operation information set in parallel with the read access operation being enabled for the memory cell array is rewrite operation information,
After setting the rewrite information,
The initialization control method for a nonvolatile memory device according to (6), further comprising a step of enabling a rewrite access operation to the memory cell array.
(10)
Enabling the read access operation comprises:
Determining whether an address input together with an external access request is in an accessible memory area;
The initialization control method for a nonvolatile memory device according to (2), further comprising a step of notifying whether or not the read access operation is possible according to a result of the determination.
(11)
Enabling the read access operation comprises:
Determining whether an address input together with an external access request is in an accessible memory area;
The initialization control method for a nonvolatile memory device according to (4), further comprising a step of notifying whether or not the read access operation is possible according to the result of the determination.
(12)
Enabling the read access operation comprises:
Determining whether an address input together with an external access request is in an accessible memory area;
The initialization control method for a nonvolatile memory device according to (6), further comprising a step of notifying whether or not the read access operation is possible according to the result of the determination.
(13)
Enabling the read access operation or the rewrite access operation;
Determining whether an address input together with an external access request is in an accessible memory area;
The initialization control method for a nonvolatile memory device according to (8), further comprising a step of notifying whether or not the read access operation or the rewrite access operation is possible according to the determination result.
(14)
Enabling the read access operation or the rewrite access operation;
Determining whether an address input together with an external access request is in an accessible memory area;
The initialization control method for a nonvolatile memory device according to (9), further comprising a step of notifying whether or not the read access operation or the rewrite access operation is possible according to the determination result.
(15)
The non-volatile memory according to (6), wherein the notification of whether or not the access operation is possible is identified and output according to a type of an access operation that can be performed and a memory area that is an access operation target. Device initialization control method.
(16)
The non-volatile storage according to (8), wherein the notification of whether or not the access operation is possible is identified and output according to a type of access operation to be enabled and a memory area to be accessed. Device initialization control method.
(17)
The non-volatile storage according to (9), wherein the notification of whether or not the access operation is possible is identified and output according to a type of an access operation that can be performed and a memory area that is an access operation target. Device initialization control method.
(18)
The initialization control method for a nonvolatile memory device according to (1), wherein the operation information is read by a verify amplifier that checks a rewrite state during a rewrite access operation.
(19)
A read amplifier for reading information from the memory cell array during a read access operation;
Reading the read operation information by the read amplifier; and
The initialization control of the nonvolatile memory device according to (18), further comprising a step of reading information excluding the read operation information out of the operation information by the verify amplifier after reading by the read amplifier. Method.

  In the initialization control method of the nonvolatile memory device according to the above technique, when the operation information is read and set from the memory cell array during the initialization operation, the read operation information necessary for the normal data read operation is normally It is characterized in that it is set in preference to the rewrite information necessary for the data rewrite operation.

  In the initialization control method of the nonvolatile memory device according to the above technique, operation information for setting various operating conditions of the nonvolatile memory device is stored in the memory cell array, and is read from the memory cell array during the initialization operation. When the condition is set, the read operation information necessary for the normal data read operation is read and set in preference to the rewrite information necessary for the normal data rewrite operation.

  As a result, the read operation information necessary for the normal data read operation is preferentially read and set, so that the read condition setting in the nonvolatile memory device is preferentially performed, and at the initial stage of the initialization operation An operating condition capable of performing the read access operation is set. The amount of operation information increases with the increase in capacity of the nonvolatile memory device, and even when this operation information is stored in a section of a memory cell array in which normal data is stored, all the operation information is read out. A read access operation from the nonvolatile memory device can be performed in the initial stage of the initialization operation without waiting. After the read access operation is enabled, it is possible to perform normal data read operations including boot programs and application programs in parallel with the operation information read setting. It becomes possible to start the read access operation including the start operation.

  The non-volatile memory device according to the first concept related to the present invention is a non-volatile memory device in which operation information set at the time of initialization operation is stored in a memory cell array, in which operation information is stored. In parallel with internal access control in which operation information is read from the first memory area, a second memory area that is externally controlled independently from the first memory area is provided. And

  In the nonvolatile memory device according to the first concept related to the present invention, the operation information for setting various operation conditions of the nonvolatile memory device is stored in the memory cell array, but the operation information is stored in the first memory area. The second memory area is subjected to access control from the outside in parallel with the internal access control.

  As a result, the first memory area and the second memory area are subjected to access control independently of each other, so that the normal read from the second memory area is performed while the operation information is read from the first memory area. An access operation can be performed. The amount of operation information increases with the increase in capacity of the nonvolatile memory device, and even when this operation information is stored in a section of a memory cell array in which normal data is stored, all the operation information is read out. Without waiting, the read access operation from the nonvolatile memory device can be performed in parallel with the reading of the operation information in the initialization operation. While performing the operation information read operation from the first memory area, it is possible to perform normal data reading including the boot program and application program from the second memory area.

  The non-volatile memory device according to the second concept related to the present invention is a non-volatile memory device in which operation information set at the time of the initialization operation is stored in the memory cell array. A verify amplifier for verifying the rewrite state is provided, and the operation information is read by the verify amplifier.

  In the nonvolatile memory device according to the second concept related to the present invention, a verification amplifier that performs a verification (verification) of a rewrite state during a normal rewrite access operation is used, and operation information is read out during an initialization operation. Do.

  As a result, since the verify amplifier different from the amplifier used in the normal read access operation is used for reading the operation information performed at the initialization operation, the read access operation is performed while the operation information is read by the verify amplifier. Can be performed in parallel.

1, 2 Non-redundant memory area 3 Read sense amplifier 4 Verify sense amplifier 5 A, 5 B Memory cell array 6 Operation information latch section 7 Control circuit 8 Status output section 11 Power-on reset circuit 12 Address register 13 Match detection section 14 Voltage generation circuit 15 Address Buffer 16 Command decoder 17 Output buffer 18A, 18B Row decoder 19A, 19B Column decoder 19R Read column decoder 19W Verify column decoder 21A, 21B Bank 31 Timer circuit RDB Read data line ENO, ENE Decode signal ENV Verify signal INI Initialization signal ST1 Step I status signal

Claims (8)

The operation information set during the initialization operation is a non-volatile storage device stored in the memory cell array,
A read amplifier for reading information from the memory cell array during a read access operation;
A configuration in which the number of arrangements is reduced from that of the read amplifier, and a verify amplifier that confirms a rewrite state during a rewrite access operation;
And an automatic rewrite control circuit for controlling the rewrite access operation,
At initialization operation, the activated pre-SL read amplifier in place of the verification amplifier by using the confirmation of rewriting state operation by the automatic rewrite control circuit, the nonvolatile memory device characterized by reading the operation information .   2. The nonvolatile memory according to claim 1, wherein the operation information read control is such that a read start timing or read cycle is shorter than a verify start timing or verify cycle in a rewrite access operation. Sex memory device.   The nonvolatile memory device according to claim 2, wherein the shortening of the cycle is performed by controlling a generation time of an internal voltage in the automatic rewrite control circuit.   2. The nonvolatile memory according to claim 1, wherein the number of the read amplifiers simultaneously activated by the automatic rewrite control circuit is larger than the number of the read amplifiers simultaneously activated during the read access operation. Storage device. A verify amplifier is provided to check the rewrite status during the rewrite access operation.
The nonvolatile memory device according to claim 1, wherein the automatic rewrite control circuit activates the verify amplifier in addition to the read amplifier during an initialization operation.   6. The non-volatile memory device according to claim 5, wherein the verify amplifier includes a read reference cell that provides a reference level for reading when the operation information is read.   The non-volatile memory device according to claim 1, wherein the memory cell storing the operation information is connected to the read amplifier via a bit line unique to each memory cell.   2. The nonvolatile memory device according to claim 1, wherein the operation information is stored in each of a plurality of memory cells connected to the same bit line.

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