JP5387705B2 - Programmable controller programming device - Google Patents

Description

  The present invention relates to a technique for converting a sequence program into a machine code format and reversely converting the created machine code into a sequence program.

  The programmable controller is a controller that instructs a procedure to a mechanical system that operates sequentially, for example. The instruction content is described in a sequence program stored in the machine code format in the programmable controller.

  Conventionally, when creating a sequence program to be written to a programmable controller, the array and structure operands in the sequence program are represented by real addresses, so the definition and declaration information of the array and structure is stored in the programmable controller. I did not.

  In such a case, when the sequence program is converted from the machine code format to the format used when creating or changing by the user in order to make corrections to the sequence program due to version upgrade, etc. Body definition / declaration information has been lost. That is, (inverse) conversion could only be performed insufficiently.

  As a result, it is possible to make corrections more easily by searching for the code of the format used at the time of creation and modification by the user corresponding to the sequence program stored in the programmable controller and making changes to the code. Was common.

  However, it is not always possible to find a code in a format used when a corresponding user creates or changes it, and there are many needs to read a sequence program in a machine code format from a programmable controller and modify it directly for maintenance.

In addition, as a programming technique for the programmable controller, there is a technique disclosed in Patent Document 1.
In Patent Document 1, even if a parameter that is considered for future expansion is declared in the form of a reservation, the parameter is not referred to on the sequence program. The case where the declaration information of the parameter is lost, a part of the result of the thinking work is lost, and the work efficiency is lowered is considered. In order to avoid such a situation, in Patent Document 1, all parameters defined and declared at the time of creation of a sequence program are displayed in a display format from a machine language format regardless of whether the sequence program is used or not. Restore when converting to.
JP, 2004-341824, A "Programming device of a programmable controller"

  An object of the present invention is to convert a sequence program in which the definition / declaration information of an array or structure is included in the sequence program from a machine code format to a format used at the time of creation / modification by a user. It is an object to provide a programmable controller programming apparatus and a programmable controller that can restore the definition / declaration information.

The programming device for a programmable controller according to the present invention includes a conversion unit that converts definition information and declaration information of at least one of an array or a structure in a sequence program into a machine code format, and the machine that reads the sequence program from the programmable controller. have a inverse transform unit, to the type used at the time of creation or change by a user with inverse converting at least one of definition information and declaration information sequence or structure of the coding format, the conversion unit, used in the sequence program The array or structure operand is converted to a machine code format in which a value (ID) other than the memory type is added to the device address item indicating that it is an array or structure operand, and stored in the programmable controller. The inverse converter is a programmer When the sequence program is read from the controller, the array or the array is converted based on a value (ID) other than the memory type added to the machine code, which indicates an operand of the array or structure converted into the machine code format. A programmable controller programming device characterized by referring to structure definition / declaration information and performing reverse conversion to display the structure definition / declaration information .

  According to the present invention, when a sequence program in which definition / declaration information of an array or structure is included in the sequence program is converted from a machine code format to a format used at the time of creation / change by the user, the array or structure Since the definition / declaration information can be restored, the work efficiency of the sequence program modification can be improved.

It is a figure which shows schematic structure of the programming apparatus of one Embodiment of this invention. It is a block diagram which shows the structure of the sequence program creation apparatus of FIG. It is a block diagram which shows the structure of the sequence program reference / change apparatus of FIG. It is a figure which shows an example of the definition information of the arrangement | sequence which the user defined via the sequence program creation apparatus of FIG. It is a figure which shows an example of the definition information of the structure defined by the user via the sequence program creation apparatus of FIG. FIG. 4 is a diagram showing array / structure declaration information corresponding to the arrays / structures of FIGS. 4A and 4B declared by the user via the sequence program creation device of FIG. 1. It is a figure which shows an example of the definition information and declaration information of an array and a structure which are stored in the internal memory of a programming device in a machine code format. FIG. 6 is a diagram illustrating a data structure of array definition information restored from a machine code format array definition information such as FIG. 5 to a display format; It is a figure which shows the data structure of the definition information of the structure restored | reconstructed from the definition information of the structure of the machine code format of FIG. It is a figure which shows the data structure of the declaration information of the array or structure restored to the display format from the declaration information of the array or structure in the machine code format of FIG. It is a figure which shows an example of the sequence program (ladder figure) of a display format. It is a figure which shows an example of the array operand on a ladder diagram. It is a figure which shows an example of the structure operand on a ladder diagram. The start or end of the operand of the array or structure is indicated in the line immediately before the start line and the line after the end line of the machine code corresponding to the operand that is an element of the array or structure. It is a figure which shows the state by which the pseudo instruction to show is inserted. When an array or structure operand is used in an MOV instruction, it is a diagram illustrating one or more lines of machine code corresponding to the MOV instruction. In this embodiment, it is a figure which shows the data structure of the sequence program produced by the display format on the sequence program memory | storage part of FIG. It is a figure which shows the value (ID) added to the item of the device address. It is a figure which shows the data structure of the operand information corresponding to the operand which is an element of an array or a structure. It is a flowchart of the process which creates the sequence program of a display format, converts the sequence program of the display format into a machine code format, and outputs it to a programmable controller. It is the flowchart which showed the process of step S105 of FIG. 14 in detail. It is a flowchart of the process which reverse-converts the sequence program of the machine code format read from the programmable controller into the sequence program of a display format, and outputs it on a display part. It is the flowchart which showed the process of step S303 of FIG. 16 in detail. It is a figure which shows the hardware environment of this embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing a schematic configuration of a programming device according to an embodiment of the present invention.
1 is a sequence program creation device 11 as a user interface capable of creating a sequence program stored in the programmable controller, and a user interface capable of referring to and changing the sequence program stored in the programmable controller. As a sequence program reference / change device 12.

  The sequence program creation device 11 has a function of converting a sequence program from a display format (for example, a ladder diagram) used when created / changed by a user to a machine code format used when stored in a programmable controller. The sequence program reference / change device 12 has a function of inversely converting a sequence program from a machine code format to a display format.

  More precisely, the sequence program in the display format should be first converted to the assembler code format and then converted from the assembler code format to the machine code format. However, in this embodiment, the assembler code format and the machine It does not distinguish the code format and is simply called the machine code format.

In the present embodiment, it is assumed that an array or a structure is used as an operand of an instruction in a display format sequence program.
For example, when a programmable controller operates a device having a plurality of belt conveyors sequentially, a plurality of data having the same data length, such as a counter value of each belt conveyor, is stored in an array.

  Further, for example, the attributes of one belt conveyor are an operation state flag (data type = bit), a counter value (data type = double word (D)), an abnormality flag (data type = bit), and so on. Such a data structure can be associated with a structure.

By using an element of an array or a structure as an operand, there is an advantage that the description of the code is simplified and maintenance (work to be performed at the time of version upgrade) can be easily performed.
FIG. 2 is a block diagram showing the configuration of the sequence program creation device of FIG.

  As shown in FIG. 2, the sequence program creation device 11 includes a sequence program storage unit 21, an array / structure storage unit 22, a definition / declaration information conversion unit 24, an array / structure operand instruction conversion unit 26, and another instruction conversion unit. 27 and an output unit 28.

The array / structure storage unit 22 stores array or structure definition information and declaration information in a display format input by the user via the sequence program creation device 11.
The sequence program storage unit 21 stores a sequence program code in a display format input by the user via the sequence program creation device 11.

  The definition / declaration information conversion unit 24 is a pseudo-instruction (a machine that does not affect execution) in the machine code format used when storing the definition / declaration information of an array / structure of a sequence program used by a user in a programmable controller. And pseudo instructions indicating the start / end are inserted at the start and end positions. A pseudo instruction is a machine code that does not affect execution. For example, in the drawing, a line starting with “PSEUDO” corresponds to the pseudo instruction.

  The array / structure operand instruction conversion unit 26 converts an instruction that uses an element of an array or structure in a sequence program described in a display format as an operand into one or more lines of machine code, and the array or structure Are inserted at the start and end positions of machine code corresponding to one or more lines in the machine code format.

The other instruction conversion unit 27 converts an instruction that does not use an array or structure element in a sequence program described in a display format as an operand into one or more lines of machine code.
The output unit 28 outputs the sequence program converted into the machine code format to the programmable controller (for example, writes it in the memory of the programmable controller).

FIG. 3 is a block diagram showing the configuration of the sequence program reference / change apparatus of FIG.
As shown in FIG. 3, the sequence program reference / change device 12 includes a sequence program acquisition unit 31, a sequence program storage unit 32, a definition / declaration information start / end position detection unit 33, a definition / declaration information restoration unit 34, an array / structure. A body operand start / end position detection unit 35, an array / structure operand restoration unit 36, a conversion unit 37, and an output unit 38.

  The sequence program acquisition unit 31 acquires a sequence program described in the machine code format from the programmable controller and writes it in the sequence program storage unit 32.

  The definition / declaration information start / end position detection unit 33 detects the start position and the end position of the sequence / array definition / declaration information of the sequence program stored in the sequence program storage unit 32.

The definition / declaration information restoration unit 34 restores the definition / declaration information between the detected start position and the end position corresponding to the start position to a display format.
The array / structure operand start / end position detection unit 35 starts and ends the code of one or more lines corresponding to an operand which is an element of an array or structure of the sequence program stored in the sequence program storage unit 32. Detect position.

  The array / structure operand restoration unit 36 restores the array / structure of the operand based on one or more lines of code corresponding to the operand of the array or structure between the start position and the end position.

The conversion unit 37 converts the source stored in the machine code format in the sequence program storage unit 32 into a sequence program (in display format).
The output unit 38 outputs the sequence program converted into the display format on a display device (not shown in FIG. 3).

  4A is an example of array definition information defined by the user via the sequence program creation device of FIG. 1, and FIG. 4B is an example of structure definition information defined by the user via the sequence program creation device of FIG. 4C is a diagram showing array / structure declaration information corresponding to the array / structure definition information of FIGS. 4A and 4B, which is declared by the user via the sequence program creation device of FIG.

In the example of FIG. 4A, it is defined that the array named ARY — 0 has 16 bit-format data, and the array named ARY — 1 has five word-format data.
In the example of FIG. 4B, the structure named STR_0 has one bit-format member and one word-format member, and the structure named STR_1 includes two bit-format members and word-format member 2. It is defined to have pieces.

  4C shows that the start addresses of the arrays ARY_0 and ARY_1 in FIG. 4A are “M00100” and “WM00200”, respectively, and the start address of the structure STR_0 in FIG. 4B is “WM00300”.

  The memory includes a non-volatile memory (indicated by type “M”) that retains contents even when the power is turned off, and a volatile memory (indicated by type “L”) that does not retain contents when the power is turned off. And a type “SM” indicating that the memory is a system program storage memory.

  For example, in FIG. 4C, “WM00200” is a word (“W”) having a data length of (16 bits), and indicates the 200th memory of the type “M” whose contents are retained even when the power is turned off. Yes. When there is no designation for the data length such as “M00100”, the data length is interpreted as 1 bit.

FIG. 5 is a diagram showing an example of array and structure definition information and declaration information stored in the machine code format in the internal memory of the programming device.
Each line of the machine code in FIG. 5 starts with the character string “PSEUDO” indicating that it is a pseudo instruction. The portions corresponding to the definition information and declaration information of arrays and structures have a format of “LAB” + “definition information” or “LAB” + “declaration information”.

  As shown in FIG. 5, when array definition information is converted from a display format to a machine code pseudo-instruction, the “definition information” portion includes an array number, which is a number shown after the array name (ARY_), and the array Element information indicating the number of elements and the data type of the element is output as a conversion result. A pseudo instruction having the format “FC” + “value that identifies the start of array definition information (“ 9 ”” in the figure) ”is inserted in the line immediately before the first line of the conversion result. A pseudo-instruction having a format of “FC” + “value for identifying the end of array definition information (“ 32777 ”in the drawing”) ”is inserted in a line immediately after the last line.

  When structure definition information is converted from a display format to a machine code pseudo-instruction, the "definition information" part contains the structure number, which is the number shown after the structure name (STR_), and the structure. The data type (element information) of each member as many as the number of members included is output as the conversion result. A pseudo instruction having the format “FC” + “value for identifying the start of structure definition information (“ 10 ”in the figure”) ”is inserted in the line immediately before the first line of the conversion result. A pseudo-instruction having a format of “FC” + “value for identifying the end of structure definition information (“ 32778 ”in the drawing”) ”is inserted in a line immediately after the last line of“. ”

  Also, when array and structure declaration information is converted from the display format to machine code pseudo-instructions, the “declaration information” portion includes an address type for identifying device address information, a CPU number, an address (upper side), an address Each item on the (lower side) and the number of the array or structure are output as the conversion result. A pseudo instruction having a format of “FC” + “value for identifying the start of declaration information of an array or structure (“ 11 ”in the figure”) ”is inserted in the line immediately before the first line of the conversion result, A pseudo instruction having the format “FC” + “value identifying the end of array or structure declaration information (“ 32779 ”in the figure)” is inserted in the line immediately following the last line of the conversion result. The

  6A is a diagram showing a data structure of array definition information restored from the machine code format array definition information of FIG. 5 to a display format, and FIG. 6B is a machine code format structure of FIG. FIG. 6C is a diagram showing the data structure of the structure definition information restored from the definition information of FIG. 5 to the display format, and FIG. 6C is restored to the display format from the machine code format array or structure declaration information of FIG. It is a figure which shows the data structure of the declaration information of an array or a structure. In FIG. 6C, whether the number is an array number or a structure number is determined by the value of the higher-order bit.

FIG. 7 is a diagram showing an example of a display format sequence program (ladder diagram).
In FIG. 7, the circuit 1 is configured by connecting contacts M0, M1, M2, and a coil M3 between buses. In this case, each of the contact M0, the contact M1, the contact M2, and the coil M3 corresponds to one command. The circuit 2 is configured by connecting a MOV command and a contact M4 preceding the MOV command between buses. In this case, each of the contact M4 and the MOV command corresponds to one command.

FIG. 8A is a diagram illustrating an example of an array operand on a ladder diagram.
In FIG. 8A, elements of the array are used for the contacts and the operand of the MOV instruction.
The array operand is represented by “device address information [element number]”. For example, M00100 [5] indicates the fifth element of the array in which the head is stored at the 100th address of the memory of the memory type M and each data length is 1 bit. WM00200 [3] indicates the third element of the array in which the head is stored at the 200th address of the memory of the memory type M and each data length is 16 bits = 1 word.

FIG. 8B is a diagram illustrating an example of a structure operand on the ladder diagram.
In FIG. 8B, structural elements are used as contacts and operands of the MOV instruction.
The structure operand is represented by, for example, “device address information. Data length R index”. For example, WM00300. R1 is a structure in which the head is stored in the 300th memory of the memory type M, and indicates a data member having a data length (16 bits) defined as the first of the R index.

  FIG. 9 shows that one or more lines of machine code corresponding to an operand that is an element of an array or structure are displayed on the line immediately before the start line and after the end line of the operand of the array or structure. It is a figure which shows the state in which the pseudo instruction (it has the format of "FC" + "the information which identifies the start or the end of the operand of an array or a structure") which shows a start or an end is inserted.

FIG. 10 is a diagram showing one or more lines of machine code corresponding to an MOV instruction when an array or structure operand is used in the MOV instruction.
In FIG. 10, for example, “WM0000: = WM0100 [1]” corresponds to “MOV WM0000 WM0100 [1]”.

  The first row and the second row in FIG. 10 show the MOV instruction and the corresponding machine code (assembler code) when an element of the one-dimensional array is used as the second operand of the MOV instruction.

  The third and fourth stages show the MOV instruction and the corresponding machine code (assembler code) when the data member of the structure is used as the second operand of the MOV instruction.

  The 5th and 6th stages show the MOV instruction and the corresponding machine code (assembler code) when the element of the one-dimensional array that is a member of the structure is used as the second operand of the MOV instruction. Show.

  In the assembler code of FIG. 10, “#” appearing as an operand in each instruction is a constant, “M” is a holding memory, “AX” is an AX register, “WI” is a signed 16-bit integer (1 word = 16 bits) , “DU” means an unsigned 32-bit integer (double word = 32 bits), and “XB” means 1 bit.

The definition and declaration information of arrays and structures used as operands in the MOV instruction in FIG. 10 are shown below.
(Definition information)
TYPE
ARY_01: ARRAY [1..50] OF INT

STR_01: STRUCT
E1: BOOL
E2: BOOL
E3: INT;
E4: ARY_01
END_STRUCT
END_TYPE
(Declaration information)
WM0100 ARY_01
WM0300 STR_01
Next, each assembler code in FIG. 10 will be described.

  First, in the first-stage assembler code in FIG. 10, in the PLD instruction, the contents of ACC (accumulator) are pushed onto the data stack, and then data is read from the address specified by the operand and stored in ACC. In the SUB instruction, data is read from the address specified by the operand, the data read from ACC is subtracted, and the result is stored in ACC. In the LEAAX instruction, the memory position address of the address specified by the operand is stored in the AX register. In the AXADDP instruction, the contents of the AX register and the contents of the ACC are added and the result is stored in the AX register, and the data stack is popped. In the LD instruction, data is read from the memory location address obtained by adding “0” to the contents of the AX register and stored in the ACC. In the ST instruction, data in ACC is stored at the address specified by the operand.

  Here, since the PLD instruction, the SUB instruction, the LEAAX instruction, the AXADDP instruction, and the LD instruction are assembler codes corresponding to the array operand “WM0100 [1]”, one of the first instructions (PLD instructions) of these instructions is used. The array operand start pseudo-instruction is inserted in the previous line, and the array operand end pseudo-instruction is inserted in the line immediately after the last instruction (LD instruction) of those instructions.

  The array operand start pseudo-instruction is, for example, ““ FC ”+“ information indicating that this line is the start position of information related to the array element used for the operand ”+“ pattern used when restoring the array element ” The information indicating that the array operand end pseudo-instruction is, for example, ““ FC ”+“ the end position of the information related to the array element used for the operand ” "".

  For example, in this first assembler code, the array element number “[1]” is obtained from each operand “#”, “WI”, “001” of the PLD instruction, and each operand “M”, “M”, The pattern used for restoring the array elements is to acquire the array start address “WM0100” from “DU” and “100”.

The second assembler code in FIG. 10 is the same as the first tier, so the description is omitted.
In this second assembler code, the PLD instruction, SUB instruction, LEAAX instruction, AXADDP instruction, and LD instruction are assembler codes corresponding to the array operand “WM0100 [WM0001]”. The array operand start pseudo-instruction is inserted in the line immediately before (PLD instruction), and the array operand end pseudo-instruction is in the line after the last instruction (LD instruction) of those instructions. Inserted.

  For example, in the second assembler code, the element number “[WM0001]” of the array is obtained from each operand “M”, “WI”, “001” of the PLD instruction, and each operand “M”, “M”, The pattern used for restoring the array elements is to acquire the array start address “WM0100” from “DU” and “100”.

  In the third assembler code in FIG. 10, in the LEAAX instruction, the memory position address of the address specified by the operand is stored in the AX register. In the LD instruction, data is read from the memory location address obtained by adding the relative address indicated by the third operand “51.0” of the instruction to the contents of the AX register and stored in the ACC. In the ST instruction, data in ACC is stored at the address specified by the operand.

  Here, since the LEAAX instruction and the LD instruction are assembler codes corresponding to the structure operand “WM0300.R1”, the structure operand appears in the line preceding the first instruction (LEAAX instruction) of those instructions. A start pseudo-instruction is inserted, and a structure operand end pseudo-instruction is inserted in a line immediately after the last instruction (LD instruction) of those instructions.

  For example, in the third assembler code, the start address “WM0300” of the structure is obtained from each operand “M”, “XB”, “300” of the LEAAX instruction, and the structure of FIG. Get the structure number by referring to the declaration information. Also, the relative address of the member in the structure is obtained from the third operand “51.0” of the LD instruction, and the relative address is obtained by referring to the structure definition information in FIG. 6B with the relative address and the obtained structure number. The pattern that is used when restoring the members of the structure is used to identify the members that meet the requirements.

The assembler code at the fourth level in FIG. 10 is the same as that at the third level, and a description thereof will be omitted.
In the fifth assembler code in FIG. 10, in the PLD instruction, the contents of ACC (accumulator) are pushed onto the data stack, and then data is read from the address specified by the operand and stored in ACC. In the SUB instruction, data is read from the address specified by the operand, the data read from ACC is subtracted, and the result is stored in ACC. In the LEAAX instruction, the memory position address of the address specified by the operand is stored in the AX register. In the AXADDP instruction, the contents of the AX register and the contents of the ACC are added and the result is stored in the AX register, and the data stack is popped. In the LD instruction, data is read from the memory location address obtained by adding the relative address indicated by the third operand “1” of the instruction to the contents of the AX register and stored in the ACC. In the ST instruction, data in ACC is stored at the address specified by the operand.

  Here, since the PLD instruction, SUB instruction, LEAAX instruction, AXADDP instruction, and LD instruction are assembler codes corresponding to the structure operand “WM0300.WR4 [1]”, the first instruction among them (PLD instruction ) The structure operand start pseudo-instruction is inserted in the line immediately before), and the structure operand end pseudo-instruction is inserted in the line after the last instruction (LD instruction) of those instructions. Is done.

  For example, in this fifth assembler code, the element number “[1]” of the one-dimensional array that is a member of the structure is obtained from each operand “#”, “WI”, “001” of the PLD instruction, and LEAAX The start address “WM0300” of the array is obtained from each operand “M”, “DU”, “300” of the instruction, and the structure number is obtained by referring to the declaration information of the structure in FIG. 6C at the start address. Also, the relative address of the member in the structure is acquired from the third operand “1” of the LD instruction, and the relative address is referenced by referring to the structure definition information in FIG. 6B with the relative address and the acquired structure number. The pattern that is used when restoring the members of the structure is used to identify the members that meet the requirements.

The sixth assembler code in FIG. 10 is the same as that in the fifth tier, so the description is omitted.
FIG. 11 is a diagram showing a data structure of a sequence program created in a display format on the sequence program storage unit of FIG. 2 in the present embodiment.

In FIG. 11, circuit 1, circuit 2,..., Circuit n, and instruction 1, instruction 2,..., Instruction n in each circuit correspond to, for example, those on the ladder diagram shown in FIG. doing.
The mnemonic information includes an instruction code, the number of operands that the instruction has, and operand information for the number of operands following the number of operands.

  Each operand information includes a device type indicating a memory type, a CPU number / station number, a data type (bit, 1 word (16 bits), double word (32 bits)), a spare, and an address for storing the data, Consists of

  Conventionally, since the sequence program created in the display format has been managed with the data structure as shown in FIG. 11, it is impossible to distinguish the array / structure from the simple variable, and the array / structure is used as the operand. When used, the address of the operand of the array or structure was converted to a real address and held.

  On the other hand, it is possible to distinguish an array / structure from a normal variable by adding an item of flag information indicating an array or a structure, but the data structure in FIG. Data compatibility is lost.

  Therefore, in this embodiment, by providing a value other than a meaningful value as a device address (memory type) in the device address (= device type) item, the array / This makes it possible to distinguish between structures and ordinary variables.

FIG. 12 is a diagram illustrating a value (ID) added to the device address item.
In FIG. 12, the device address ID = “xatArray” is an ID indicating that the operand is an element of the array. The device address ID = “xatStruct” is an ID indicating that the operand is an element of the structure.

FIG. 13 is a diagram illustrating a data structure of operand information corresponding to an operand that is an element of an array or a structure.
In FIG. 13, as described above, a value indicating an array or a structure (“xatArray” or “xatStruct”) is specified in the device type item. The address item when the device address value indicates the memory type includes information on each element of the array or each element (data member, array member,...) Of the structure. Pointer information indicating the head position of information is stored.

  From this pointer information, information about each element of the array or information about each element of the structure can be acquired, and an operand that is an element of the array or structure can be expressed.

  FIG. 14 is a flowchart of a process of creating a display format sequence program and converting the display format sequence program into a machine code format and outputting it to a programmable controller. This flowchart is executed by the sequence program creation device of FIG.

  First, in step S101, the user inputs definition information / declaration information of an array or structure whose elements can be operands on a display-format sequence program.

In step S102, the sequence program code in the display format is input by the user.
In step S103, it is determined whether or not the creation of the display format sequence program has been completed.

If it is determined in step S103 that the creation of the display format sequence program has not been completed, the process returns to step S102.
On the other hand, if it is determined in step S103 that creation of the display format sequence program has been completed, in step S104, the definition / declaration information conversion unit 24 in FIG. Pseudo instruction (this instruction has the form "LAB" + "definition information" or "LAB" + "declaration information"), and the line immediately before and the end of the pseudo instruction's start line A machine code pseudo-instruction (this instruction starts with “FC”) indicating the start / end of the line is inserted in the line immediately after the line. An example of the conversion result is shown in FIG.

  In step S105, the sequence program in the display format is converted into the machine code format by the array / structure operand instruction conversion unit 26 and the other instruction conversion unit 27 in FIG.

In step S106, the sequence program converted into the machine code format is stored in the ROM in the programmable controller by the output unit 28 in FIG.
FIG. 15 is a flowchart showing the process of step S105 of FIG. 14 in more detail.

  Note that the flowchart of FIG. 15 shows processing performed for one circuit constituting the ladder diagram. Actually, the processing of FIG. 15 is executed for all the circuits in the ladder diagram.

  In FIG. 15, first, in step S201, the first instruction (mnemonic information) in the current circuit is acquired. As shown in FIG. 11, the mnemonic information includes an instruction code, the number of operands of the instruction, and operand information for the number of operands following the number of operands.

In step S202, it is determined whether or not the mnemonic information has operand information, that is, whether or not a value of 1 or more is set in the operand number item.
If it is determined in step S202 that the mnemonic information does not have operand information, the instruction code or the like is converted into a machine code format by the other instruction conversion unit 27 in FIG. 2 in step S207.

In step S206, it is determined whether or not the program is completed, that is, whether or not there is a subsequent instruction in the current circuit.
If it is determined in step S206 that there is no subsequent instruction, a series of processing, in this case, processing for one circuit is completed. On the other hand, if it is determined in step S206 that there is a subsequent instruction, the process returns to step S201, the subsequent instruction is acquired, and the same processing is repeated for the subsequent instruction.

  On the other hand, if it is determined in step S202 that the mnemonic information has operand information, the value (ID) of the device type item of each operand information included in the mnemonic information is searched in step S203, and the mnemonic information is stored in the operand. It is determined whether it has an array or structure element. If operand information with device type item value = “xatArray” or “xatStruct” is detected, it is determined that the instruction has an element of an array or structure as an operand.

  If it is determined in step S203 that the instruction has an element of an array or structure as an operand, the instruction is converted from the display format to the machine code format by the array / structure operand instruction conversion unit 26 in FIG. 2 in step S204. Converted to obtain one or more lines of machine code corresponding to the acquired instruction, and 1 corresponding to an operand which is an element of an array or structure in one or more lines of machine code corresponding to the acquired instruction Machine code pseudo-instructions (starting with "FC") indicating the start / end are inserted in the line preceding the start line and the line following the end line of machine code that is greater than or equal to the line. . Control then proceeds to step S206.

  More specifically, there are two corresponding machine code templates (templates) for one or more lines for each instruction in the display format. One is when the instruction does not contain an element of the array or structure in the operand, and the other is when the instruction contains an element of the array or structure in the operand. For each instruction that does not contain an element of an array or structure as an operand, it is known how many lines from what line in the machine code (template) corresponding to that instruction corresponds to the operand of that instruction. . A template for an instruction that includes an element of an array or structure as an operand is a line preceding the start line and one after the end line of the operand corresponding part of the template for an instruction that does not include an element of the array or structure. It is obtained by inserting a pseudo instruction of machine code indicating the start / end of the line.

FIG. 10 illustrates several processing results of step S204.
On the other hand, if it is determined in step S203 that the instruction is not an instruction having an array or structure element as an operand, in step S205, the other instruction conversion unit 27 in FIG. 2 (does not have an array or structure element as an operand). Instructions are converted to machine code format. Control then proceeds to step S206.

  FIG. 16 is a flowchart of processing for converting the sequence program in the machine code format read from the programmable controller into the display format sequence program and outputting it to the display unit. This flowchart is executed by the sequence program reference / change device of FIG.

  First, in step S <b> 301, the sequence program described in the machine code format is acquired from the programmable controller by the sequence program acquisition unit 31 of FIG. 3, and is written in the sequence program storage unit 32.

  In step S302, the definition / declaration information start / end position detection unit 33 searches the sequence program in the machine code format stored in the sequence program storage unit 32. Then, a machine code pseudo instruction starting with “PSEUDO FC” is detected from the sequence program in the machine code format, and the start position and the end position corresponding to the start position are detected by the definition / declaration information restoring unit 34. The definition / declaration information (this information starts with “PSEUDO LAB”) of the array or structure in between is restored to the display format.

  In step S303, the sequence program in the machine code format is converted into a display format by the array / structure operand start / end position detection unit 35, the array / structure operand restoration unit 36, and the conversion unit 37.

In step S304, the output unit 38 outputs the sequence program converted into the display format and the definition / declaration information of the array / structure on the display device.
FIG. 17 is a flowchart showing the process of step S303 of FIG. 16 in more detail.

In FIG. 17, first, in step S401, each row of the sequence program stored in the sequence program storage unit 32 of FIG. 3 is acquired.
In step S402, the array / structure operand start / end position detection unit 35 obtains information related to an operand in which the acquired line is a pseudo instruction of a machine code and is “FC” + “element of an array or structure”. It is determined whether or not it includes a value that identifies the start of “.

  If it is determined in step S402 that the acquired line does not include “FC” + “information indicating the start of information related to an operand that is an element of an array or structure”, in step S407, the conversion unit 37 uses the machine code. The instructions of the format sequence program are converted to the display format. Control then proceeds to step S406.

  On the other hand, if it is determined that the line acquired in step S402 includes “FC” + “information indicating the start of information relating to an operand that is an element of an array or structure”, an array / structure operand restoration unit is determined in step S403. 36 until each subsequent line of the sequence program stored in the sequence program storage unit 32 includes a line including “FC” + “information indicating the end of information related to an operand that is an element of an array or structure”. To be acquired.

  In step S403, the array / structure operand restoring unit 36 uses the pattern “FC” + “information indicating the start of information related to the operands that are elements of the array or structure” to be used at the time of restoration. The information necessary for restoring the elements of the array or the members of the structure is acquired from the machine code (assembler code) portion sandwiched between the start and end pseudo-instructions. As described in FIG. 10, the information acquired in step S <b> 403 is an address at which the top address of the array, the element number (index) of the array, or the value of the index is stored when the array element is restored. is there. When restoring a member of a structure, for example, the start address of the structure and the relative address of the member of the structure.

  When restoring the members of the structure, the process of step S404 is further executed. In this step S404, for example, the array / structure operand restoration unit 36 refers to the structure declaration information in FIG. 6C by using the start address of the structure acquired in step S403, and acquires the structure number. The Also, using the structure number and the relative address of the structure member acquired in step S403, the structure definition information in FIG. 6B is referenced to identify the member that matches the relative address.

  In step S405, based on the results of steps S403 and S404, the array / structure operand restoring unit 36 restores the elements of the array or the members of the structure used as the operands to the display format. Control then proceeds to step S406.

FIG. 18 is a diagram illustrating a hardware environment according to the present embodiment.
In FIG. 18, the programming device 50 is connected to a programmable controller 65 that stores a sequence program created via the programming device 50.

  In FIG. 18, the programming device includes a central processing unit (CPU) 51, a ROM 52, a RAM (primary storage) 53, a storage device 55, an input device 58, a display device 61, and an input / output interface (I / O) 62. They are connected via a bus 63.

  In FIG. 18, a CPU 51 controls the entire computer. For example, a program for creating a sequence program and performing processing for referring to and changing the sequence program is read from the ROM 52 to the RAM 53 and executed on the RAM 53.

Through the input device 58, the user inputs definition information or declaration information of an array or structure, or inputs a sequence program code in a display format.
The sequence program in this display format is displayed on the display device 61 at the time of creation, reference or change.

  The storage device 55 includes, for example, an internal memory 56 that stores the definition information of the created array, structure definition information, array and structure declaration information, and a user program that stores a sequence program in a display format or a machine code format. A memory 57 is provided.

  The created display format sequence program is converted into a machine code to be a machine code format sequence program, and is written to, for example, a ROM in the programmable controller 65 via the I / O 62. The machine code format sequence program read from the ROM in the programmable controller 65 is converted into a display format sequence program and displayed on the display device 61, for example.

DESCRIPTION OF SYMBOLS 10 Programming controller programming device 11 Sequence program creation device 12 Sequence program reference / change device 21, 32 Sequence program storage unit 22 Array / structure storage unit 24 Definition / declaration information conversion unit 26 Array / structure operand conversion unit 27 Other instructions Conversion unit 28, 38 Output unit 31 Sequence program acquisition unit 33 Definition / declaration information start / end position detection unit 34 Definition / declaration information restoration unit 35 Array / structure operand start / end position detection unit 36 Array / structure operand restoration unit 37 Conversion Part

Claims (1)

A conversion unit that converts definition information and declaration information of at least one of an array or a structure in a sequence program into a machine code format;
Inverse transform unit to form used during creation or change by users at least one of definition information and declaration information sequence or structure of the machine code format by inverse transformation when reading a sequence program from the programmable controller, have a ,
The conversion unit is a machine code format in which an array or structure operand used in a sequence program is an array or structure operand and a value (ID) other than the memory type is added to the device address item. Stored in the programmable controller,
The inverse conversion unit is a value (ID) other than the memory type added to the machine code, which indicates an operand of an array or structure converted into a machine code format when the sequence program is read from the programmable controller. A programmable controller programming device characterized by referring to the definition / declaration information of an array or structure based on the above, and performing reverse conversion .