JP5381919B2 - FIFO data reading device - Google Patents

Description

  The present invention relates to a FIFO data reading device for processing read requests from a plurality of CPUs for one FIFO circuit that reads previously stored data first.

  In the case where a plurality of CPUs access a common memory, an access right arbitration function is provided on the shared memory side instead of arbitrating access rights between CPUs (for example, Patent Document 1). reference.).

  However, for the shared memory, each CPU can read data by designating an address, but a common FIFO (First In First Out) circuit that reads previously stored data is provided. When a plurality of CPUs read data from a common FIFO circuit independently of each other regardless of read requests from other CPUs, the read pointer is updated in the FIFO circuit when the other CPUs read the data first. CPUs other than cannot read the same data.

  In order to solve this problem, when one CPU requests reading from the FIFO circuit, the reading request from the other CPU to the FIFO circuit is prohibited, and the data read from the FIFO circuit by the CPU is prohibited. A process of allowing a read request to the FIFO circuit to another CPU after sending it to another CPU can be considered.

  However, when the CPU executes such a reading process in order to read data from the FIFO circuit, the original process of the CPU that processes the data read from the FIFO circuit is hindered.

  On the other hand, a configuration is known in which a FIFO circuit is provided for each of a plurality of CPUs, and data is extracted from the FIFO circuit to which each CPU corresponds (see, for example, Patent Document 2).

JP-A-2-281356 Japanese Patent Laid-Open No. 7-262227

However, if a FIFO circuit is provided for each of a plurality of CPUs, there is a problem that the amount of hardware increases.
The present invention has been made to solve the above problems, and an object of the present invention is to provide a FIFO data reading device in which a plurality of CPUs can independently read data stored in one FIFO circuit. To do.

  According to the first to third aspects of the present invention, reading of data is requested from a plurality of CPUs, one FIFO circuit that reads previously stored data first, and reading from the FIFO circuit by a reading request from the CPU. A storage device in which data is stored; a determination unit that determines which CPU among a plurality of CPUs is a preceding CPU with the largest number of read data stored in the FIFO circuit; and a FIFO circuit from the preceding CPU The data stored in the FIFO circuit is sent to the preceding CPU and written to the storage device in response to the read request to the memory, and is stored in the storage device in response to the read request from the CPU other than the preceding CPU to the FIFO circuit. Data processing means for transmitting data.

  Thus, even if the data reading position is updated in the FIFO circuit by the data processing means accessing the FIFO circuit and reading the data in response to the reading request from the preceding CPU, the FIFO circuit from other CPUs other than the preceding CPU When data reading is requested, the data processing means can send the data stored in the storage device to a CPU other than the preceding CPU.

  As a result, a CPU other than the preceding CPU can also read a copy of the data stored in the FIFO circuit from the storage device as data obtained by actually accessing the FIFO circuit.

  In this way, the plurality of CPUs only request the FIFO circuit to read, and the data processing means executes the transmission of the data stored in the FIFO circuit to each CPU. Therefore, it is possible to request reading from the FIFO circuit without being conscious of other CPUs and read out data stored in the FIFO circuit independently without arbitrating reading from the FIFO circuit among a plurality of CPUs. .

  According to the second aspect of the present invention, the storage device is provided for each CPU, and the data processing means writes the data of the FIFO circuit to be sent to the preceding CPU to the storage device corresponding to the CPU other than the preceding CPU, When a CPU other than the preceding CPU requests the FIFO circuit to read data, it reads data from the storage device corresponding to the other CPU that requests the FIFO circuit to read data, and requests the FIFO circuit to read data. To other CPUs.

  That is, the data read from the FIFO circuit when the own CPU is not the preceding CPU and the other CPU is the preceding CPU is stored in the corresponding storage device of the own CPU. Thereby, when the own CPU is not the preceding CPU, the data stored in the FIFO circuit can be read from the storage device corresponding to the own CPU.

  According to the third aspect of the present invention, there are two CPUs, one storage device is provided in common for the two CPUs, and the data processing means has a read address when reading data from the storage device. Reads data from the address position of the storage device shown, updates the read address according to the number of data to be read, and writes the data read from the FIFO circuit to the storage device at the address position of the storage device indicated by the write address And the write address is updated according to the number of write data.

  When the number of CPUs is two, the data read from the FIFO circuit by the preceding CPU is written in the common storage device, whereby the data of the FIFO circuit to be read by the CPU that is not the preceding CPU is stored in the storage device.

  The data in the storage device sent to the CPU that is not the preceding CPU is data read by the preceding CPU from the FIFO circuit, and the preceding CPU does not need to read from the storage device. Therefore, even if the read address is updated according to the number of data read from the common storage device, the data stored in the storage device can be sent to the CPU that is not the preceding CPU without skipping.

  Therefore, in a configuration in which one memory device common to two CPUs is provided, even if two CPUs request reading from one FIFO circuit, the data stored in the FIFO circuit is stored in the FIFO. It can be sent to each CPU from a circuit or a storage device.

1 is a block diagram showing a FIFO data reading device according to a first embodiment. (A) is explanatory drawing which shows the read pointer of a FIFO circuit, (B) is a time chart which shows the signal between a FIFO read circuit and a FIFO circuit. The state transition diagram for CPU reading data from a FIFO circuit. The time chart which shows the signal between CPU and FIFO read-out circuit for CPU reading data from a FIFO circuit. # 1 is a state transition diagram showing reading processing of a FIFO reading circuit for a CPU. # 1 is a state transition diagram showing reading processing of a FIFO reading circuit for a CPU. FIG. 2 is a state transition diagram showing reading processing of the FIFO reading circuit for # 2 CPU. FIG. 2 is a state transition diagram showing reading processing of the FIFO reading circuit for # 2 CPU. The block diagram which shows the FIFO data reading apparatus of 2nd Embodiment. # 1 is a state transition diagram showing reading processing of a FIFO reading circuit for a CPU. FIG. 2 is a state transition diagram showing reading processing of the FIFO reading circuit for # 2 CPU.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 shows a FIFO data reading device 10 of this embodiment.

(FIFO data reading device 10)
The FIFO data reading device 10 includes a FIFO circuit 12, a FIFO reading circuit 20, a # 1 DPRAM (Dual Port RAM) 30, and a # 2 DPRAM 32. Reading data from the # 1 CPU 2 and # 2 CPU 4 to the FIFO circuit 12 is performed. A device that processes requests.

  # 1CPU2 and # 2CPU4 (hereinafter simply referred to as # 1CPU2 is also referred to as CPU2 and # 2CPU4 is also referred to as CPU4) are not in a master-slave relationship and request reading from the FIFO circuit 12 independently of each other. That is, the CPU 2 and the CPU 4 are connected to the FIFO circuit 12 on a one-to-one basis regardless of whether other CPUs are reading data from the FIFO circuit 12 or not. Request reading independently.

Read requests to the FIFO circuit 12 by the CPU 2 and CPU 4 are actually processed by the FIFO read circuit 20. The FIFO read circuit 20 will be described later.
The FIFO circuit 12 is a known circuit that reads the previously stored data first. The FIFO circuit 12 stores, for example, scan data scanned by a radar every scan cycle. Based on the scan data stored in the FIFO circuit 12, for example, the CPU 2 detects the shape of the reflective object, and the CPU 4 executes different processes in parallel, such as tracking the reflective object.

  The data storage unit of the FIFO circuit 12 is composed of a RAM or the like. Since the first embodiment processes reading from the FIFO circuit 12, the data write signal to the FIFO circuit 12 is omitted in FIG. However, in order to describe the configuration of the FIFO circuit 12, a writing process to the FIFO circuit 12 will be described.

  As shown in FIG. 2, data is sequentially written in the FIFO circuit 12 in the order of data1, data2,. From the FIFO circuit 12, data at a position indicated by a read pointer indicated by an arrow in FIG. When the first written data1 is read, the read pointer next indicates data2. In this manner, data is sequentially read from the FIFO circuit 12 in the order of data1, data2,..., DataN. Since the read pointer is a pointer inside the FIFO circuit 12, it cannot be operated from the outside of the FIFO circuit 12.

Next, reading processing from the FIFO circuit 12 will be described.
As shown in FIG. 2B, when the FIFO read circuit 20 reads data from the FIFO circuit 12, a read request signal is output in synchronization with the read clock. When the read request is valid (high = “1”), the FIFO circuit 12 outputs one piece of data stored in the FIFO circuit 12 for one read clock cycle. In FIG. 2B, after one read operation, two read request signals are continuously output to the FIFO circuit 12 at two clocks. When it is determined that the read request signal is valid, the FIFO circuit 12 outputs read data in synchronization with the read clock.

  When all the data written in the FIFO circuit 12 is read, the FIFO circuit 12 outputs the empty signal with high = “1”. Thereby, the FIFO circuit 12 indicates to the outside that the stored data is empty and there is no data to read out. If data is written to the FIFO circuit 12 while the empty signal is valid ('1'), the empty signal becomes invalid (low = '0'), indicating that the FIFO circuit 12 is ready to be read. Show to the outside.

  The FIFO read circuit 20 is composed of hardware such as an FPGA (Field Programmable Gate Array) and an ASIC (Application Specific Integrated Circuit). The FIFO read circuit 20 reads data from the FIFO circuit 12 or the # 1 DPRAM 30 or # 2 DPRAM 32 (hereinafter, simply referred to as # 1 DPRAM 30 as DPRAM 30 and # 2 DPRAM 32 as DPRAM 32) in response to a read request from the CPUs 2 and 4 to the FIFO circuit 12. , Sent to each CPU.

The six interface (IF) signals between the CPUs 2 and 4 and the FIFO readout circuit 20, whether the IF signal is a port signal or a bus signal, and the output source of the IF signal are shown below. The following six IF signals are provided for the number of CPUs. Details of each signal will be described later.
(1) Read start signal: port signal, CPU
(2) Continuous read number signal (number of bits required for number expression): port signal, CPU
(3) Read permission signal: port signal, FIFO read circuit (4) Read strobe signal: bus signal, CPU
(5) Read WAIT signal: bus signal, FIFO read circuit (6) FIFO data signal (number of bits according to data width): bus signal, FIFO read circuit (read processing by CPU)
Based on FIG. 3 and FIG. 4, the state transition when the CPU 2 or CPU 4 requests the FIFO circuit 12 to read will be described. In FIG. 3, “S” represents a step.

  When the CPUs 2 and 4 request the FIFO circuit 12 to read, first, the CPUs 2 and 4 output the number of continuous reads from the FIFO circuit 12 to continuously read data in one read request (S400), and then The read start signal is set to “1” (S402).

  By setting the read start signal to “1”, the CPUs 2 and 4 notify the FIFO read circuit 20 of the start of reading to the FIFO circuit 12. The FIFO reading circuit 20 determines that reading from the CPUs 2 and 4 to the FIFO circuit 12 is requested when the reading start signal becomes “1”. Then, when the FIFO read circuit 20 sets the read permission signal to “1”, the CPUs 2 and 4 determine that the read request to the FIFO circuit 12 has been accepted.

  When the read permission signal output from the FIFO read circuit 20 becomes “1” (S404: Yes), the CPUs 2 and 4 set the read start signal to “0” (S406) and set the read strobe signal to “1” (S406). S408). By setting the read strobe signal to “1”, the CPUs 2 and 4 request the FIFO read circuit 20 to read data. When the read strobe signal becomes “1”, the FIFO read circuit 20 sets the read WAIT signal to “1”, and reads one data from the FIFO circuit 12 or DPRAM.

  When the FIFO read circuit 20 reads one piece of data from the FIFO circuit 12 or DPRAM and the read WAIT signal becomes “0” (S410: Yes), the CPUs 2 and 4 read the data of the FIFO data signal (S412) and read it. The strobe signal is set to “0” (S414).

  The read WAIT signal is a signal normally provided as a bus signal by the CPUs 2 and 4 and is not a newly provided signal. The processing of S408 to S414 by the CPUs 2 and 4 is processing related to bus signals. For example, when * a ++ = * b ++ is executed on a C language program, the pointer value of b, that is, the address position indicated by b This process is executed by the hardware of the CPUs 2 and 4 when reading the data.

  On the other hand, the processes of S400 to S406 and S416 to S420 by the CPUs 2 and 4 are processes related to the port signals of the CPUs 2 and 4, and are processes executed by the programs of the CPUs 2 and 4.

  If the read WAIT signal changes from '1' to '0' when the read strobe signal is '1' (S410: Yes), the data read from the FIFO circuit 12 or DPRAM by the FIFO read circuit 20 is output to the FIFO data signal. It represents that. Thereby, even if the clocks are different between the CPUs 2 and 4 and the FIFO read circuit 20, the CPUs 2 and 4 can correctly read the data of the FIFO circuit 12 or the DPRAM.

  Next, the CPUs 2 and 4 increment the data read count counter (S416). If the data read count has not reached the number of continuous reads (S418: No), the process proceeds to S408.

When the number of data reading reaches the number of continuous reading (S418: Yes), the CPUs 2 and 4 clear the reading number counter (S420) and end the reading process.
In the above description, the read strobe signal and the read WAIT signal are valid when they are high, but may be valid when they are low. Further, since the FIFO data signal is a bidirectional bus signal, the continuous reading number signal may be output from the CPUs 2 and 4 as the FIFO data signal.

The CPUs 2 and 4 can execute the reading of the FIFO circuit 12 independently without being conscious of other CPUs by executing the processes of S400 to S420.
(Reading process for # 1 CPU by FIFO reading circuit 20)
Based on FIGS. 5 and 6, the state transition of processing in the FIFO reading circuit 20 when reading from the FIFO circuit 12 is requested by the # 1 CPU will be described. In FIG. 5 and FIG. 6, “S” represents a step. Note that the state transitions of FIGS. 5 and 6 and FIGS. 7, 8, 10 and 11 described later are performed in synchronization with the read clock for the FIFO circuit 12.

The meanings of variables used in FIGS. 5 and 6 are as follows.
(1) # 1 CPU pointer: The total number of times the # 1 CPU has read data from the FIFO circuit 12 or # 1 DPRAM up to the present time (synonymous with the total number).
(2) # 2 DPRAM pointer: address to which # 1 CPU writes data read from the FIFO circuit 12 into # 2 DPRAM.
(3) # 1 DPRAM address: An address from which # 1 CPU reads data from # 1 DPRAM that stores data read from FIFO circuit 12 by # 2 CPU.
(4) # 1 CPU read count: A count counter in which # 1 CPU continuously reads data from the FIFO circuit 12 or # 1 DPRAM.

  First, when the reset process after power-on is completed (S430: Yes), the FIFO read circuit 20 clears the # 1 CPU pointer, the # 2 DPRAM pointer, the # 1 DPRAM address, and the # 1 CPU read count (S432).

  Then, when the reading start signal of the # 1 CPU becomes “1” (S434: Yes), the FIFO reading circuit 20 reads the # 1 CPU continuous reading number signal output from the # 1 CPU (S436). If the data stored in the FIFO circuit 12 is not empty, that is, if the empty signal = '0' (S438: No), the FIFO read circuit 20 sets the read permission signal for # 1 CPU to '1'. (S440), # 1 The CPU read count is counted up (S442).

  Next, in S444, if the FIFO read circuit 20 is # 1CPU pointer ≧ # 2CPU pointer (S444: Yes), the process proceeds to S446, and if # 1CPU pointer <# 2CPU pointer (S444: No), The process proceeds to S464.

  When # 1CPU pointer ≧ # 2CPU pointer (S444: Yes), since the total number of readings by # 1CPU is equal to or larger than the total number of readings by # 2CPU, the FIFO reading circuit 20 has the FIFO that # 1CPU precedes # 2CPU. It is determined that the circuit 12 is requested to read.

  That is, when # 1 CPU pointer ≧ # 2 CPU pointer, in response to a read request from the # 1 CPU to the FIFO circuit 12, the FIFO read circuit 20 determines to read data from the FIFO circuit 12 and send it to the # 1 CPU. In the first embodiment, when # 1CPU pointer = # 2CPU pointer, data is read from the FIFO circuit 12 with priority given to # 1CPU over # 2CPU.

  If the data stored in the FIFO circuit 12 is not empty (S446: No) and # 1 CPU read strobe signal = '1' (S448: Yes), the read WAIT signal is set to '1' (S450). ), A read request signal for one clock is output to the FIFO circuit 12 (S452). If the data stored in the FIFO circuit 12 in S446 is empty (S446: No), it indicates that the data has become empty during the reading of the data from the FIFO circuit 12, so that the FIFO read circuit 20 12 waits until new data is stored.

  The FIFO read circuit 20 latches one piece of data output from the FIFO circuit 12 and outputs it to the # 1 CPU (S454). Next, one piece of data output from the FIFO circuit 12 is written at the position indicated by the # 2DPRAM pointer of # 2DPRAM (S456).

  When data is read from the FIFO circuit 12, the read pointer indicates the next data position in the FIFO circuit 12. Therefore, when the # 1 CPU reads data from the FIFO circuit 12, the other # 2 CPU reads the already read data. Reading from the FIFO circuit 12 is not possible. Therefore, when the # 1 CPU reads the data from the FIFO circuit 12, in S456, the data is written and copied to the # 2 DPRAM so that the # 2 CPU can read it later.

  When the FIFO data is written in # 2DPRAM, the FIFO read circuit 20 sets the read WAIT signal to '0' (S458), counts up the # 1 CPU pointer (S460), and counts up the # 2DPRAM pointer (S462). , The process proceeds to S476.

When the FIFO read circuit 20 sets the read WAIT signal to “0” in S458, the # 1 CPU reads the data of the FIFO data signal in S412 of FIG.
In the above-described determination of S444, if # 1CPU pointer <# 2CPU pointer (S444: No), the total number of readings by # 1 CPU is smaller than the total number of readings by # 2CPU. It is determined that the FIFO circuit 12 is requested to read later.

  That is, if # 1CPU pointer <# 2CPU pointer, the FIFO read circuit 20 determines that the data corresponding to the read request from the # 1 CPU to the FIFO circuit 12 has already been read from the FIFO circuit 12 and sent to the # 2 CPU. Data read from the # 2 CPU from the FIFO circuit 12 is written in the # 1 DPRAM.

  Then, if the # 1 CPU read strobe signal = '1' (S464: Yes), the FIFO read circuit 20 sets the read WAIT signal to '1' (S466: Yes) and starts from the # 1DPRAM address position of # 1DPRAM. One piece of data is read and latched and output to the # 1 CPU (S468).

  Next, the FIFO read circuit 20 sets the read WAIT signal to “0” (S470), counts up the # 1 CPU pointer (S472), counts up the # 1 DPRAM address (S474), and proceeds to S476. To do.

  In S476, if # 1 CPU read count <# 1 CPU continuous read number (S476: No), it is determined that # 1 CPU has not yet read data for the # 1 CPU continuous read number, and the FIFO read circuit 20 proceeds to S444. To migrate.

  If # 1 CPU read count ≧ # 1 CPU continuous read number (S476: Yes), the FIFO read circuit 20 determines that the # 1 CPU has read data for the # 1 CPU continuous read number, and clears the # 1CPU read count ( S478).

  Next, when the data stored in the FIFO circuit 12 is not empty (S480: No), the FIFO read circuit 20 shifts the processing to S434 in preparation for a read request from the # 1 CPU.

  When the # 1 CPU reads the data corresponding to the # 1 CPU continuous reading number, the data stored in the FIFO circuit 12 is empty (S480: Yes), and if # 1CPU pointer ≧ # 2 CPU pointer (S482: Yes) The FIFO reading circuit 20 waits until # 1CPU pointer = # 2CPU pointer (S484: No).

  This is because if # 1 CPU pointer> # 2 CPU pointer in S482, the unread data of # 2CPU remains in # 2DPRAM, so that # 2CPU waits until all data stored in # 2DPRAM is read. is there.

  If # 1CPU pointer = # 2CPU pointer (S484: Yes), the read counts of # 1CPU and # 2CPU match when the data in the FIFO circuit 12 is empty, so the FIFO read circuit 20 goes to S432. The process is shifted to the initial state.

  If # 1 CPU pointer <# 2 CPU pointer in S482 (S482: No), it is considered that data that has not been read by # 1CPU remains in # 1DPRAM in a state where data in the FIFO circuit 12 is empty. Therefore, when the reading start signal of the # 1 CPU becomes “1” in S486 of FIG. 6 (S486: Yes), the FIFO reading circuit 20 reads the # 1 CPU continuous reading number signal output by the # 1 CPU (S488). Then, the FIFO read circuit 20 sets the read permission signal for # 1 CPU to “1” (S490), and shifts the processing to S442 in FIG. As a result, the # 1 CPU reads unread data stored in the # 1 DPRAM until # 1 CPU pointer = # 2 CPU pointer (S484: Yes).

(Reading process for # 2 CPU by FIFO reading circuit 20)
Based on FIGS. 7 and 8, the state transition of processing in the FIFO reading circuit 20 when reading from the FIFO circuit 12 is requested by the # 2 CPU will be described. In FIG. 7 and FIG. 8, “S” represents a step. The meanings of variables used in FIGS. 7 and 8 are as follows.
(1) # 2 CPU pointer: Total number of times the # 2 CPU has read data from the FIFO circuit 12 or # 2 DPRAM up to the present time (synonymous with the total number).
(2) # 1 DPRAM pointer: address to which # 2 CPU writes data read from the FIFO circuit 12 into # 1 DPRAM.
(3) # 2 DPRAM address: An address from which # 2 CPU reads data from # 2 DPRAM that stores data read from FIFO circuit 12 by # 1 CPU.
(4) # 2 CPU read count: A count counter in which # 2 CPU continuously reads data from the FIFO circuit 12 or # 2 DPRAM.

  The # 1 CPU reading process in FIGS. 5 and 6 and the # 2 CPU reading process in FIGS. 7 and 8 are almost the same except that the CPU name and the variable name are different. Hereinafter, different processes will be described.

  In S504, if the FIFO read circuit 20 is # 1 CPU pointer <# 2 CPU pointer (S504: Yes), the total read count by the # 2 CPU is larger than the total read count by the # 1 CPU. It is determined that reading is requested to the FIFO circuit 12 prior to # 1 CPU.

  That is, if # 1CPU pointer <# 2CPU pointer, in response to a read request from the # 2 CPU to the FIFO circuit 12, the FIFO read circuit 20 determines to read data from the FIFO circuit 12 and send it to the # 2 CPU.

  As described in the reading process for # 1 CPU, in the first embodiment, when the total number of readings by # 1 CPU is equal to the total number of readings by # 2 CPU, data from FIFO circuit 12 is given priority to # 1 CPU over # 2 CPU. Therefore, the FIFO read circuit 20 sends the data read from the FIFO circuit 12 to the # 2 CPU only when # 1CPU pointer <# 2 CPU pointer.

  Moreover, the point that the processing of S528 is added after S526 is different from the reading processing for # 1 CPU in FIG. When # 1CPU pointer ≧ # 2CPU pointer in S504 (S504: No), if # 1CPU pointer = # 2CPU pointer, the total number of readings is the same for # 1CPU and # 2CPU, so # 2 No data is read from the FIFO circuit 12 prior to the CPU. That is, it indicates that data that can be read by the # 2 CPU has not yet been written in the # 2 DPRAM.

  Therefore, in S528, the FIFO read circuit 20 waits if # 1CPU pointer = # 2CPU pointer (S528: No), # 1CPU reads data from the FIFO circuit 12 prior to # 2CPU, and # 2DPRAM # When data that can be read by the 2CPUs is written, so that # 1CPU pointer> # 2CPU pointer (S528: Yes), the processing from S530 is executed, and the data stored in the # 2DPRAM is sent to the # 2CPU.

  In the first embodiment described above, the FIFO read circuit 20 processes read requests from the # 1 CPU and # 2 CPU to the FIFO circuit 12, so that the # 1 CPU and # 2 CPU are mutually connected to the FIFO circuit 12. Regardless of whether or not reading is requested, it is possible to independently request reading from one FIFO circuit 12.

  In addition, since two CPUs read data from one FIFO circuit 12, although the DPRAM is installed for each CPU, the amount of hardware can be reduced as compared with the configuration in which the FIFO circuit 12 is installed for each CPU.

  Even if read requests from the CPUs 2 and 4 are simultaneously generated for the FIFO circuit 12, the read requests are distributed to either the FIFO circuit 12 or the DPRAM by the FIFO read circuit 20. Therefore, in response to a read request from the CPUs 2 and 4, the FIFO circuit 12 or DPRAM is not requested to read simultaneously.

  In the first embodiment, the example in which two CPUs read data from one FIFO circuit 12 has been described. When the number of CPUs is three or more, as in the case of two CPUs, a DPRAM is provided for each CPU, and the preceding CPU in which the number of readings for one FIFO circuit 12 precedes is determined. The data read from the FIFO circuit may be written in the DPRAM for the CPU other than the preceding CPU.

  As a result, even in a configuration in which one FIFO circuit is installed in a plurality of CPUs of three or more, each CPU independently stores data stored in the FIFO circuit regardless of the read request to the FIFO circuit by other CPUs. Can be read out.

  In the first embodiment, the FIFO data reading device 10 corresponds to the FIFO data reading device of the present invention, the # 1 DPRAM 30 and # 2 DPRAM 32 correspond to the storage device of the present invention, and the FIFO reading circuit 20 includes the determination means and data of the present invention. It functions as a processing means.

  The processing of S444, S482, S504, and S544 corresponds to the function executed by the determination means of the present invention, and the processing of S454, S456, S468, S514, S516, and S530 is executed by the data processing means of the present invention. Corresponds to function.

[Second Embodiment]
FIG. 9 shows a FIFO data reading device 40 of this embodiment. In the second embodiment, there is only one DPRAM 42 to which the data read from the FIFO circuit 12 by the # 1 CPU and # 2 CPU are written.

  In the second embodiment, when data read from the FIFO circuit 12 by two CPUs is written to one DPRAM 42, as shown in S626 of FIG. 10 and S726 of FIG. 11, a # 1DPRAM pointer for writing and a # 2DPRAM Writing is performed with the pointer value obtained by adding the pointer. When two CPUs read from one DPRAM 42, as shown in S638 of FIG. 10 and S740 of FIG. 11, the reading is performed with an address value obtained by adding the # 1 DPRAM address for reading and the # 2 DPRAM address. Do. Other read processing is substantially the same as in the first embodiment. Also, the process when the determination result of S652 in FIG. 10 is No is substantially the same as FIG. 6, and the process when the determination result of S754 in FIG. 11 is No is substantially the same as FIG. Illustration is omitted.

  When there are two CPUs, in one DPRAM 42, the data read from the FIFO circuit 12 by the preceding CPU is written to the address position obtained by adding the write pointers provided for the two CPUs. The data of the FIFO circuit 12 to be read by the CPU that is not the preceding CPU is stored in the DPRAM 42.

  The data in the DPRAM 42 sent to the CPU that is not the preceding CPU is data read by the preceding CPU from the FIFO circuit 12, and the preceding CPU does not need to read from the DPRAM 42. Therefore, even if the read address obtained by adding the read addresses provided for the two CPUs is updated according to the number of data read from the common DPRAM 42, it is stored in the DPRAM 42 in the CPU that is not the preceding CPU. Data can be sent without skipping.

  In the second embodiment, since only one DPRAM 42 for writing data read from the FIFO circuit 12 by two CPUs is provided, the amount of hardware can be reduced as compared with the first embodiment.

  In the second embodiment, the FIFO data reading device 40 corresponds to the FIFO data reading device of the present invention, the DPRAM 42 corresponds to the storage device of the present invention, and the FIFO reading circuit 50 functions as the determination means and data processing means of the present invention. To do.

  The processing of S614, S652, S714, and S754 corresponds to the function executed by the determination means of the present invention, and the processing of S624, S626, S638, S724, S726, and S740 is the function executed by the data processing means of the present invention. It corresponds to.

[Other Embodiments]
In the above-described embodiment, the configuration in which a plurality of CPUs read data from one FIFO circuit 12 that stores scan data by radar is described. However, the data stored by the FIFO circuit is not limited to scan data by radar. Any data may be used as long as the data is sequentially transmitted by the above method.

Further, the storage device for copying the data stored in the FIFO circuit is not limited to the DPRAM, and any storage device may be used.
In the second embodiment, for one DPRAM 42, a read address and a write pointer are provided in each of the two CPUs. On the other hand, a common write pointer and read address are provided for two CPUs, and the common write pointer and read address are updated according to the number of data to be written and the number of data to be read. However, substantially the same write process and read process as in the second embodiment can be executed on one DPRAM 42.

  As described above, the present invention is not limited to the above-described embodiment, and can be applied to various embodiments without departing from the gist thereof.

2, 4: CPU, 10, 40: FIFO data reading device, 12: FIFO circuit, 20, 50: FIFO reading circuit (determination means, data processing means), 30, 32, 42: DPRAM (storage device)

Claims (3)

One FIFO circuit that is requested to read data from a plurality of CPUs and reads the data stored first;
A storage device for storing data read from the FIFO circuit in response to a read request from the CPU;
Determining means for determining which CPU among the plurality of CPUs is a preceding CPU having the largest number of reading data stored in the FIFO circuit;
In response to a read request to the FIFO circuit from the preceding CPU determined by the determining means, the data stored in the FIFO circuit is sent to the preceding CPU and written to the storage device. Data processing means for sending out data stored in the storage device in response to a read request from the CPU to the FIFO circuit;
A FIFO data reading device comprising: The storage device is provided for each CPU,
The data processing means writes the data of the FIFO circuit to be sent to the preceding CPU to the storage device corresponding to the CPU other than the preceding CPU, and the CPU other than the preceding CPU causes the FIFO circuit to When reading is requested to the FIFO circuit, data is read from the storage device corresponding to the other CPU that requests reading from the FIFO circuit, and the other CPU that requests reading from the FIFO circuit is requested. Send out,
The FIFO data reading device according to claim 1, wherein: The plurality of CPUs are two, and the storage device is provided in common for the two CPUs.
The data processing means reads data from the address position of the storage device indicated by a read address when reading data from the storage device, updates the read address according to the number of data to be read, and reads the data from the FIFO circuit. When writing data to the storage device, the data of the FIFO circuit is written to the address position of the storage device indicated by the write address, and the write address is updated according to the number of data to be written.
The FIFO data reading device according to claim 1, wherein:

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