JPH07262227A - Process input/output device and computer system - Google Patents

Abstract

PURPOSE:To appropriately transmit data obtained from a plant to respective CPU. CONSTITUTION:Data obtained from a process are transmitted to plural CPU 1 and 2. FIFO buffers 11-l and 11-2 inputting/outputting data obtained from the process by an FIFO system are correspondingly provided for plural CPU 1 and 2. A process input/output device is provided with transmission/reception parts 13-1 and 13-2 taking out data from the FIFO buffers 11-1 and 11-2 and transmitting them to CPU 1 or 2 to which the transmission of data is permitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process input / output device applied to various plants such as a power generation system and a computer system using the process input / output device.

[0002]

2. Description of the Related Art In a system in which various plants are controlled by a computer, C
A plurality of PUs are provided and configured. That is, the configuration as shown in FIG. 2 is adopted.

Here, the structure of the monitoring unit for obtaining data from the process has conventionally been structured as shown in FIG. That is, the controllers 101 and 201 connected to the two CPUs 100 and 200 are provided. A PIO bus (parallel input / output bus) 301 is provided between the controllers 101 and 201.
I / O boards 102 and 202 are connected to the. I
/ O boards 102 and 202 are the same sensor 300-1.
It is connected to 300-m, and the sensors 300-1 to 30
0-m is the event data of the plant (for example, in the case of a power generation system, turbine speed, temperature, etc.)
It is sent to the O boards 102 and 202. I / O board 10
Reference numerals 2 and 202 interrupt the corresponding controllers 101 and 201 and receive data by accepting the interrupt. Then, the controllers 102 and 201 are
The corresponding CPUs 100, 20 are provided on condition that the interrupt permission of each CPU 100, 200 is given.
An interrupt is sent to 0 and data is transmitted in response to the acceptance of the interrupt.

In such a system, two C
The PUs 100 and 200 are operating to fetch the same data when fetching the data, and one of the Cs
The PU controls the plant, and when a failure occurs in either one, the CPU on the normal side is switched (or the current state is maintained). After that, when the faulty CPU is restored, the operation in the normal state is restored again.

[0005]

However, according to the above system, the CPU on the side recovered from the failure does not have the data immediately before it, and the CPU on the other side as it is.
The PU cannot be backed up. Therefore, there is a problem that a process of tracing the status and data of the normally operating CPU is required, and the recovery work is troublesome and takes time. Furthermore, for each CPU,
It is necessary to provide a controller and an I / O board correspondingly. Especially, when a CPU failure occurs, the corresponding controller and I / O board are in idle state, which is a wasteful configuration. It was

The present invention has been made as a solution to the problems of the conventional process input / output device and the computer system using this process input / output device. The purpose of the present invention is to store data obtained from a plant in each CPU. It is to provide a process input / output device capable of appropriately transmitting data to the device. Also, for other purposes, recovery work is easy,
It is an object of the present invention to provide a process input / output device that requires a short time and a computer system using the process input / output device. Still another object is to provide a process input / output device with less wasteful configuration.

[0007]

Therefore, in the invention described in claim 1 of the present application, the data obtained from the process are stored in a plurality of Cs.
FIFO for inputting / outputting data obtained from the process to / from the process input / output device for transmitting to the PU by the FIFO method
A buffer is provided corresponding to the plurality of CPUs, and the corresponding FI is given to the CPU for which data transmission permission has been obtained.
The process input / output device is configured by including a transmitting / receiving unit that takes out data from the FO buffer and transmits the data.

Further, according to the invention described in claim 2 of the present application,
The process input / output device that transmits the data obtained from the process to the plurality of CPUs is fed with the data obtained from the process.
When the data is obtained from the FIFO buffer, which is provided corresponding to the plurality of CPUs, for inputting / outputting by the IFO method, the timer, and the process, the current time is obtained by referring to the timer, and the process is performed. With respect to the registration means for registering the data at the time together with the obtained data in the FIFO buffer, and the CPU for which the data transmission permission has been obtained,
The process input / output device is configured by including a transmitting / receiving unit that takes out data from the corresponding FIFO buffer and transmits the data.

In the invention according to claim 3 of the present application,
The process input / output device that transmits the data obtained from the process to the plurality of CPUs is fed with the data obtained from the process.
When the data is obtained from the FIFO buffer, which is provided corresponding to the plurality of CPUs, for inputting / outputting by the IFO method, the timer, and the process, the current time is obtained by referring to the timer, and the process is performed. Regarding the registration means for registering the obtained data together with the data at the time in the FIFO buffer, the memory provided for the plurality of CPUs for storing the data, and the data stored in the FIFO buffer. The time data is referred to, the data that has timed out is detected based on the timer, and the data is transmitted to the saving means for saving it in the memory and the CPU for which the data transmission permission has been obtained. When data transmission permission is given from the transmission unit and the CPU, the data stored in the corresponding memory and the FIFO buffer Data by a transmitting management means for transmitting to said transmission unit is configured to process input-output device.

Further, in the invention according to claim 4 of the present application,
FI data from multiple processes with multiple CPUs
When data is obtained from a FIFO buffer provided corresponding to the plurality of CPUs for input and output by the FO method, a timer, and the process, the current time is obtained by referring to the timer, and the process is performed. Regarding the registration means for registering the obtained data together with the data at the time in the FIFO buffer, the memory provided for the plurality of CPUs for storing the data, and the data stored in the FIFO buffer. The time data is referred to, the data that has timed out is detected based on the timer, and the data is transmitted to the saving means for saving it in the memory and the CPU for which the data transmission permission has been obtained. When data transmission permission is given from the transmission unit and the CPU, the data stored in the corresponding memory and the F
A computer system comprising a process input / output device, characterized in that it comprises a transmission management means for transmitting the data of the IFO buffer to the transmission part, and the CPU
Includes a timer and a determination means for determining the validity of the data transmitted from the process input device from the time data added to the data and the time data of the timer. Characterize.

[0011]

In the process input / output device according to the present invention having the above structure, since the FIFO buffer for inputting / outputting the data obtained from the process by the FIFO method is provided corresponding to the plurality of CPUs, the CPUs are provided in the CPUs. Correspondingly, FIFO
Data can be stocked in a buffer and sent to the CPU when it is ready to be sent.

In the process input / output device according to the second aspect of the present invention, it is possible to add the data of the time when the data was obtained to the FIFO buffer and stock the data, and the CPU can store the data. It can be judged whether it is valid or not.

In the process input / output device according to the third aspect of the present invention, the data stored in the FIFO buffer is monitored for a predetermined time or more and transferred to the memory. The capacity can be reduced.

In the computer system according to the fourth aspect of the present invention, in the CPU, the validity of the data transmitted from the process input device is checked based on the time data added to the data and the time data of the timer. Therefore, the necessary data can be obtained without relying on the trace from another CPU.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same constituents will be referred to with the same signs while omitting their overlapping descriptions. FIG. 2 is a configuration diagram of a process control system using the process input / output device according to the embodiment of the present invention. For plant 400,
Two CPUs 1 and 2 are provided. CPU1, 2
Obtains event data of the plant 400 from the monitoring unit 3B connected to the plant 400. In addition, CPU1, 2
One of the two supplies data for controlling the plant 400 to the control unit 3A and causes the control to be performed. CPU
1 and 2 mutually monitor the occurrence of a failure, send and receive necessary data and the like (status and data necessary for restoration), and send and receive information as to which is used for controlling the plant 400. .

FIG. 1 shows details of essential parts of the process control system shown in FIG. 8-1 to 8-i, 9
-1 to 9-j are sensors for obtaining event data from the plant 400, and these sensors 8-1 to 8-i, 9-1
The data obtained by ~ 9-j is I / O board 7-1,
It is taken in by 7-2. I / O boards 7-1 and 7-2
Interrupts the controller 4 via the PIO bus (parallel input / output bus) 6 and receives data by accepting the interrupt.

The controller 4 is composed of, for example, a microcomputer, and has a flag 41 for setting information of interrupt permission / non-permission from the CPU1 and CPU2.
42. In addition, the controller 4 includes a timer 5, FIFO buffers 11-1 and 11-2, memories 12-1 and 12-2 including a RAM, a CPU 1,
Transmission / reception units 13-1 and 13 for transmitting / receiving data to / from
-2 is connected. FIFO buffers 11-1 and 1
Reference numeral 1-2 is for inputting and outputting data obtained from the plant 400 by the FIFO method, and is provided corresponding to the CPUs 1 and 2. The memories 12-1 and 12-2 are also used to save the data of the FIFOs 11-1 and 11-2 which have timed out.

The controller 4 is provided with, for example, a registration means 43 implemented by a program, a save means 44, and a transmission management means 45. When the registration unit 43 obtains the data from the plant 400, the registration unit 43 refers to the timer 5 to obtain the current time, and the data obtained at the time together with the data obtained from the plant 400 are stored in the FIFO buffers 11-1 and 11-.
Register to 2. The evacuation means 44 uses the FIFO buffer 11
-1, 11-2, the time data is referred to for the data stored in 11-2, the time-out data is detected based on the timer 5, and this is stored in the respective memory 12-
Evacuate to 1, 12-2. The transmission management means 45 is a CP
When data transmission permission is given from U1 and U2, the data and FI stored in the corresponding memories 12-1 and 12-2 are given.
The data in the FO buffers 11-1 and 11-2 is transmitted and received by the transmission / reception unit 1
It works to let 3-1 and 13-2 transmit.

On the other hand, the CPUs 1 and 2 respectively include timers 1-3 and 2-3, and time data and timer 1-added to the data transmitted from the process input device.
Judging means 1-2 and 2-2 for judging the validity of the data from the time data of 3 and 2-3 are provided.

FIG. 3 shows a FIFO buffer 11 (11-
The data stored in No. 1, 11-2) is shown. The FIFO buffer 11 inputs and outputs data by a first-in first-out method, and stores event data obtained from the plant 400 and data at the time when the event data was obtained, paired with each other.

The controller 4 is provided with the programs of the flow charts shown in FIGS. 4 to 6, and by executing the programs, it operates as each unit shown in FIG. The operation will be described below based on this flowchart. The flowchart of FIG. 4 relates to a program for controlling the flags 41 and 42 for setting information of interrupt permission / non-permission from the CPU1 and CPU2. The controller 4 includes transmission / reception units 13-1, 13
It waits for an instruction (command) to be sent from the CPUs 1 and 2 via -2 (21). When an instruction (command) is sent from the CPU 1 or 2, the controller 4
It is detected whether the transmission is from 1 or 2 (2
2). Here, if it is detected whether the transmission is from the CPU 1, it is detected whether an instruction regarding permission of interruption is sent (23). As a result, when an instruction regarding permission of interruption is sent, information on permission of interruption (for example, “1”) is set in the flag 41, and the data saved in the memory 12-1. Also, the data accumulated in the FIFO buffer 11-1 is transmitted to the CPU 1 (24). On the contrary, when an instruction regarding disapproval of interrupt is sent, the flag 41 indicates disapproval of interrupt. Information (for example, "0") is set (25). On the other hand, when it is detected in step 22 that the transmission is from the CPU 2, it is detected whether an instruction regarding permission of interrupt is sent (26). As a result, when the instruction regarding the permission of the interrupt is sent, the information of the permission of the interrupt (for example, “1”) is set in the flag 42, and the data saved in the memory 12-2 is set. And the data accumulated in the FIFO buffer 11-2 are transmitted to the CPU 2 (27), and conversely, if an instruction regarding disapproval of interrupt is transmitted, the flag 4
Information (for example, "0") indicating that interruption is not permitted is set in 2 (28). Thus, the flags 41 and 42 are set with information relating to permission / non-permission of interruption.

The flow chart shown in FIG. 5 is a FIFO.
This is for a program for transmitting the data (event data and time data) stored in the buffers 11-1 and 11-2 to the CPU1 and CPU2. The controller 4 waits for an interrupt from the I / O boards 7-1 and 7-2 (31), accepts the interrupt when there is an interrupt, and receives the PIO from the corresponding I / O board 7-1 (or 7-2). The data is fetched via the bus 6, the current time data is obtained by referring to the timer 5 and added (32), and these are paired to form the FIFO buffer 11- as shown in FIG.
It is registered in 1, 11-2 (33). At this time, the FIFO
When the overflow occurs in the buffer 11-1 (or 11-2), the pair of data pushed out by the FIFO method is saved in the memory 12-1 (or 12-2). Next, the controller 4 refers to the flag 41 (34) and checks whether the interrupt permission is given (3
5) When the interrupt permission is given, the transmission / reception unit 13-1 is instructed to transmit the data in the FIFO buffer 11-1 to the CPU 1 (36). In other words, the transmission / reception unit 13-1 that has received the transmission instruction interrupts the CPU 1, and when this is accepted and transmission is permitted, the FIFO is transmitted.
All the data in the O buffer 11-1 is fetched by the FIFO method and transmitted to the CPU 1. Controller 4 is this CP
When the transmission to U1 is completed, or when the interrupt permission from the CPU1 is not given, the flag 42 is referred to (37), it is checked whether the interrupt permission is given (38), and the interrupt permission is given. If so, the transmission / reception unit 13-2 is instructed to transmit the data in the FIFO buffer 11-2 to the CPU 2 (39).
That is, the transmission / reception unit 13-2 that has received the transmission instruction is the CPU 2
Interrupt, and when this is accepted and transmission is permitted, all data in the FIFO buffer 11-2 is FIFO
It is taken out by the method and transmitted to the CPU 2. Controller 4
When the transmission to this CPU2 is completed, or C
If the interrupt permission from PU2 is not given, the process returns to the main process. Thus, the FIFO
The data in the buffers 11-1 and 11-2 is transmitted.

In the flow chart of FIG. 6, the data in the FIFO buffers 11-1 and 11-2 are stored in the memories 12-1 and 12-.
It is for the program of the operation when saving to 2. The controller 4 has a timer interrupt function, receives a timer interrupt at an appropriately set time interval, and executes the operation of the flowchart of FIG.
The controller 4 uses the FIFO buffers 11-1, 11-
2 has a pointer for search, and when the program of the flowchart of FIG. 6 is started, the pointer is initialized to "1" (corresponding to the area of the head address of the FIFO buffer) (51). Next, the controller 4 obtains the difference between the time data added to the event data in the area corresponding to the pointer value "1" and the current time data, and detects the storage time (52). The controller 4
It has a time-up value of the storage time for the data stored in the FIFO buffers 11-1 and 11-2 in advance, and it is detected by comparing this with the storage time obtained above. (53) When the time is up, the pair of the relevant data is stored in the corresponding memory 12
It is saved to -1 (or 12-2) (54). After this evacuation process or when the time has not expired, the pointer is incremented by "1" (55) FIFO.
It is detected whether the number of areas in the buffer 11-1 (or 11-2) has been exceeded (56). If it does not exceed, the process returns to step 52, the difference between the time data added to the event data in the storage data area corresponding to the value of the pointer and the current time data is obtained, and the storage time is detected (5
2) Then, the same processing as above is repeated. This operation is performed for each of the FIFO buffers 11-1 and 11-2. In this way, the time-up data pair is stored in the memories 12-1 and 12-2 and transmitted in steps 24 and 27 in FIG. 4 of the description. In other words, when recovering from a failure, the corresponding CPU 1, 2
Sent to.

In the CPUs 1 and 2 which have received the pair of data stored in the memories 12-1 and 12-2,
Time data is taken out from each data, timers 1-3 and 2-3 are referred to, how long the data has arrived, is detected, and the validity of the data is judged from the content of the event data. However, it retains usable data and uses it, and discards unusable data. For this reason, the FIFO has a more complicated structure than a normal memory.
By reducing the capacity of the buffers 11-1 and 11-2, it is possible to prevent data from being lost on the process input / output device side by the memories 12-1 and 12-2. Then, the CPU 1 determines whether the data is necessary (or valid).
According to the judgment of 2, the data while it is down due to the failure can be obtained regardless of the trace from the other CPU.

Although the FIFO buffer and the memory are provided in the above embodiment, a FIFO buffer having a large capacity is provided in another embodiment in which the complexity of the configuration and the cost are not taken into consideration. Even in this case, it is possible to prevent the data from being lost. In addition, the memories 12-1 and 12-2 and the transmission / reception unit 13
-1, 13-2 need not be physically two, but it is sufficient if data can be stored and transmitted / received corresponding to the respective CPUs 1, 2.

[0026]

As described above, according to the process input / output device according to the first aspect of the present invention, the FIFO buffer for inputting / outputting the data obtained from the process has a plurality of CPUs.
Since it is provided in correspondence with the CPU,
Data can be stocked in the O buffer and sent to the CPU when it can be sent, and the loss of data can be prevented.

Further, according to the process input / output device of the second aspect of the present application, the data of the time when the data is obtained can be added and stocked in the FIFO buffer, and the CPU is concerned. It becomes possible to judge whether or not the data is valid, and it is possible to perform appropriate process control by using necessary data.

Further, according to the process input / output device of the third aspect of the present application, the stock of the data stored in the FIFO buffer is monitored for a predetermined time or more and transferred to the memory. The capacity of the buffer can be reduced, the configuration can be simplified, and the cost can be reduced.

According to the computer system of claim 3 of the present application, in the CPU, based on the time data added to the data transmitted from the process input device and the time data of the timer, The validity can be judged and necessary data can be obtained regardless of the tracing from other CPUs. For example, the process when recovering from a failure can be simplified, and recovery can be performed in a shorter time than in the past.

[Brief description of drawings]

FIG. 1 is a block diagram of a process input / output device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a process control system using a process input / output device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a pair of data stored in a FIFO buffer used in the process input / output device according to the embodiment of the present invention.

FIG. 4 is a flowchart for explaining the operation of the process input / output device according to the embodiment of the present invention.

FIG. 5 is a flowchart for explaining the operation of the process input / output device according to the embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation of the process input / output device according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of a process control system configured using a process input / output device according to a conventional example.

[Explanation of symbols]

1, 2 CPU 3A control unit 1-2, 2-1 judgment means 2-1, 2-2 timer 3B monitoring unit 4 controller 5 timer 6 PIO bus 7-1, 7-2 I / O board 8-1 to 8 -I, 9
-1 to 9-j Sensor 11-1, 11-2 FIFO buffer 12-1, 12-2 Memory 13-1, 13-2
Transmitter / receiver 41, 42 Flag 43 Registration means 44 Evacuation means 45 Transmission management means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G06F 15/16 310 V

Claims (4)

[Claims] 1. The data obtained from the process is used for a plurality of CPs.
In the process input / output device for transmitting to the U, a FIFO buffer for inputting / outputting the data obtained from the process by the FIFO method is provided corresponding to the plurality of CPUs, and the CPU for which the data transmission permission has been obtained , A process input / output device comprising a transmission / reception unit for extracting data from a corresponding FIFO buffer and transmitting the data. 2. The data obtained from the process is used for a plurality of CPs.
In a process input / output device for transmitting to a U, a FI provided corresponding to the plurality of CPUs for inputting / outputting data obtained from the process by a FIFO method
An FO buffer, a timer, and a registration unit that, when data is obtained from the process, obtains the current time by referring to the timer, and registers the data at the time together with the data obtained from the process in the FIFO buffer, A process input / output device, comprising: a transmission / reception unit that extracts data from a corresponding FIFO buffer and transmits the data to a CPU for which data transmission permission has been obtained. 3. The data obtained from the process is used for a plurality of CPs.
In a process input / output device for transmitting to a U, a FI provided corresponding to the plurality of CPUs for inputting / outputting data obtained from the process by a FIFO method
An FO buffer, a timer, and a registration unit that, when data is obtained from the process, obtains the current time by referring to the timer, and registers the data at the time together with the data obtained from the process in the FIFO buffer, In order to store the data, the time data is referenced with respect to the data stored in the memory provided in the memory corresponding to the plurality of CPUs and the FIFO buffer, and the timed data is detected based on the timer. Then, the saving means for saving the data in the memory, the transmitting unit for transmitting the data to the CPU for which the data transmission permission is obtained, and the data transmission permission from the CPU, the corresponding memory Transmission management means for transmitting the data stored in the memory and the data in the FIFO buffer to the transmission unit. Process input and output device that. 4. A plurality of CPUs, a FIFO buffer provided corresponding to the plurality of CPUs for inputting and outputting data obtained from the process by a FIFO method, a timer, and data obtained from the process. In this case, the present invention refers to the timer to obtain the current time, and registers the data obtained at the time together with the data obtained from the process in the FIFO buffer. And a FIFO provided in the memory
Reference is made to the time data for the data stored in the buffer, the time-out data is detected based on the timer, the saving means for saving the data in the memory, and the data transmission permission are obtained. A transmission unit that transmits data to the CPU, and a transmission management unit that transmits the data stored in the corresponding memory and the data in the FIFO buffer to the transmission unit when the CPU permits the data transmission. A process input / output device characterized in that the CPU is provided with a timer, data transmitted from the process input device, time data added thereto, and time data of the timer, A computer system comprising a determination means for determining the validity of the data.