JP5381823B2 - Pixel driving device, light emitting device, electronic device, and driving control method for light emitting device - Google Patents

Description

  The present invention relates to a pixel driving device, a light emitting device, an electronic apparatus, and a driving control method for the light emitting device.

  An organic EL element is formed of a fluorescent organic compound that emits light when an electric field is applied. An organic light emitting diode (hereinafter referred to as organic EL) element using the organic EL element is used for each pixel. A light-emitting device including a display panel is attracting attention as a next-generation display device.

  An organic EL element is a current-controlled light-emitting element (display element) that emits light using a phenomenon in which light is emitted by excitons generated by recombination of electrons and holes injected into an organic compound. The organic EL element has an anode and a cathode, and a current supplied to the anode flows to the cathode and emits light with a luminance corresponding to the current value of the supplied current.

  In a light emitting device using such an organic EL element, a pixel driving circuit is provided for each pixel. The pixel driving circuit includes a driving transistor (n-channel FET) that supplies current to the organic EL element and a gate of the driving transistor. A capacitor connected between the sources;

  In the light emitting device, a voltage is written (applied) to the capacitor of each pixel, and the capacitor holds this voltage as the gate voltage of the driving transistor.

  As a method for writing a voltage to the capacitor, there is a current writing method. In the current writing method, a current generation circuit that supplies a gradation current having a current value corresponding to gradation data for each pixel is provided for each anode line, and a gradation current is supplied from the current generation circuit to supply a drain of the driving transistor. -A method of writing a voltage in a capacitor by passing a current between the sources.

  However, in this current writing method, there is a variation in the characteristics of each current generation circuit, and if there is a variation in the current value of the gradation current with respect to the gradation value of the gradation data in each current generation circuit, this variation will remain as it is. Luminance unevenness is caused and image quality is degraded.

  In order to solve such a problem, there is a light-emitting device in which a current generation circuit that generates a gray-scale current corresponding to display data and an anode line are switched and connected every frame period (for example, see Patent Document 1). ).

  In order to simplify the description, for example, when the pixel circuit is 4 rows × 4 columns and the current generation circuits connected to the anode lines of the respective columns are A1, B1,. In the apparatus, as shown in FIGS. 25A and 25B, the current generation circuits A1 and B1,..., A4 and B4 are switched every frame period.

JP 2003-255880 A (5th page, FIG. 1)

  However, even if the current generation circuits A1 and B1,..., A4 and B4 are switched for each frame period in this way, the current generation circuit for supplying the grayscale current to the pixels in each column is the same in one frame unit. is there. For this reason, when there are variations in the characteristics of the current generation circuits, luminance unevenness such as so-called black stripes and white stripes along the column direction may be visually recognized.

  The present invention has been made in view of such a conventional problem, and even if there is a variation in the characteristics of each current generation circuit that supplies a grayscale current, it is possible to make it difficult to visually recognize uneven luminance. It is an object to provide a driving device, a light emitting device, an electronic apparatus, and a driving control method for the light emitting device.

In order to achieve this object, a pixel driving device according to the first aspect of the present invention provides:
An optical element controlled according to a supplied current, and a plurality of pixels arranged in a matrix, according to driving data via a plurality of data lines connected to each pixel in each column A pixel driving device that supplies the gradation current to drive the plurality of pixels for each frame period ,
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuit groups, each of which includes a plurality of current generation circuits that generate the gradation current, provided corresponding to each of the plurality of contacts;
A current switching circuit that switches connection between each of the contacts and any of the plurality of current generation circuits of the current generation circuit group corresponding to the contact;
A data line switching circuit for switching the connection between each contact and each data line;
Equipped with a,
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The plurality of current generation circuit groups include a first current generation circuit group and a second current generation circuit group,
Each of the first current generation circuit group and the second current generation circuit group includes a first current generation circuit and a second current generation circuit,
In each frame period, the data line switching circuit connects the first data line to the first contact and the second contact to the second contact in the first selection period in each selection period. And the second data line is connected to the first contact and the first data line is connected to the second contact in a second selection period following the first selection period. Connect
The current switching circuit connects the first current generation circuit of the first current generation circuit group to the first contact in the first frame period in each frame period, and connects the first contact to the second contact. The first current generation circuit of the second current generation circuit group is connected, and in the second frame period subsequent to the first frame period, the first contact point of the first current generation circuit group is connected to the first contact point. characterized that you connect said second current generating circuit of the second current generating circuits by connecting the second current generation circuit to the second contact.
Et al is, in the pixel driving device according to the first aspect,
A current source for supplying a reference current;
Each of the current generation circuits is supplied with the reference current and generates a gradation current based on a voltage holding unit that holds a voltage component corresponding to the reference current and a voltage component held in the voltage holding unit A current generator,
A reference current switching circuit for sequentially switching the supply of the reference current from the current source to each of the current generation circuits and supplying the reference current to each of the plurality of current generation circuits within the one frame period; May be.

A pixel driving device according to a second aspect of the present invention provides:
An optical element controlled in accordance with a supplied current, and in accordance with drive data via a plurality of data lines provided in a plurality of pixels arranged in rows and columns connected to the respective pixels. A pixel driving device that supplies the gradation current to drive the plurality of pixels for each frame period ,
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuits which are provided corresponding to each of the plurality of contacts and generate the gradation current;
An auxiliary current generation circuit for generating the gradation current;
The auxiliary current generator circuit is replaced with the one specific current generation circuit of the plurality of current generation circuits, the and the contacts, the specific current generation circuit and the plurality of current generation count Michi及 beauty the auxiliary excluding a current switching circuit connects the current generating circuit, and switching the specific current generation circuit to one of said plurality of current generation circuits,
A data line switching circuit for switching the previous SL connection between each contact and the respective data lines,
Equipped with a,
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The data line switching circuit connects the first data line to the first contact and connects the second data line to the second contact in the first frame period of each frame period. , In a second frame period following the first frame period, connecting the second data line to the first contact and connecting the first data line to the second contact;
Said current switching circuit, in each of frame periods, in each of the selection period, the specific current generation circuit, and said switching Rukoto sequentially different the current generation circuit in the plurality of current generation circuits.
In addition, a pixel driving device according to the second aspect,
A current source for supplying a reference current;
Each of the current generation circuits and the auxiliary current generation circuit is supplied with the reference current and holds a voltage component corresponding to the reference current, and the voltage holding unit holds the voltage component based on the voltage component held by the voltage holding unit. A current generation unit for generating a gradation current,
The current switching circuit is connected to the voltage holding unit of either one of the current generation circuit or the auxiliary current generation circuit that is not connected to each of the contacts for each period in which the selection circuit selects the pixels of the rows. The reference current may be switched to supply.
In the pixel driving device according to the second aspect,
The current switching circuit may perform switching so as to supply the reference current to the voltage holding unit of the auxiliary current generation circuit during a vertical blanking period .

A light emitting device according to a third aspect of the present invention provides:
A light-emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines connected to the respective pixels for each column;
A pixel driving device that supplies gradation currents according to driving data to the plurality of data lines to drive the plurality of pixels for each frame period ;
With
The pixel driving device includes:
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuit groups, each of which includes a plurality of current generation circuits that generate the gradation current, provided corresponding to each of the plurality of contacts;
A current switching circuit that switches connection between each of the contacts and any of the plurality of current generation circuits of the current generation circuit group corresponding to the contact;
A data line switching circuit for switching the connection between each contact and each data line;
With
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The plurality of current generation circuit groups include a first current generation circuit group and a second current generation circuit group,
Each of the first current generation circuit group and the second current generation circuit group includes a first current generation circuit and a second current generation circuit,
In each frame period, the data line switching circuit connects the first data line to the first contact and the second contact to the second contact in the first selection period in each selection period. And the second data line is connected to the first contact and the first data line is connected to the second contact in a second selection period following the first selection period. Connect
The current switching circuit connects the first current generation circuit of the first current generation circuit group to the first contact in the first frame period in each frame period, and connects the first contact to the second contact. The first current generation circuit of the second current generation circuit group is connected, and in the second frame period subsequent to the first frame period, the first contact point of the first current generation circuit group is connected to the first contact point. characterized that you connect said second current generating circuit of the second current generating circuits by connecting the second current generation circuit to the second contact.

A light emitting device according to a fourth aspect of the present invention provides:
A light-emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines connected to the respective pixels for each column;
A pixel driving device that supplies gradation currents according to driving data to the plurality of data lines to drive the plurality of pixels for each frame period ;
With
The pixel driving device includes:
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuits which are provided corresponding to each of the plurality of contacts and generate the gradation current;
An auxiliary current generation circuit for generating the gradation current;
Said auxiliary current generator circuit is replaced with the one specific current generation circuit of the plurality of current generation circuits, the and the contacts, the plurality of current generation circuits and the auxiliary current except for the specific current generation circuit generates A current switching circuit that connects the specific current generation circuit to any one of the plurality of current generation circuits ,
A data line switching circuit for switching the pre-Symbol connection between each contact and the respective data lines,
Equipped with a,
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The data line switching circuit connects the first data line to the first contact and connects the second data line to the second contact in the first frame period of each frame period. , In a second frame period following the first frame period, connecting the second data line to the first contact and connecting the first data line to the second contact;
Said current switching circuit, in each of frame periods, in each of the selection period, the specific current generation circuit, and said switching Rukoto sequentially different the current generation circuit in the plurality of current generation circuits.
In addition, the light emitting device according to the fourth aspect,
The pixel driving device has a current source for supplying a reference current,
Each of the current generation circuits is supplied with the reference current and generates a gradation current based on a voltage holding unit that holds a voltage component corresponding to the reference current and a voltage component held in the voltage holding unit A current generator,
The current switching circuit is connected to the voltage holding unit of either one of the current generation circuit or the auxiliary current generation circuit that is not connected to each of the contacts for each period in which the selection circuit selects the pixels of the rows. The reference current may be switched to supply .

An electronic apparatus according to a fifth aspect of the present invention is
The light emitting device according to the third aspect or the light emitting device according to the fourth aspect is provided.

A drive control method for a light emitting device according to a sixth aspect of the present invention includes:
A light emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines provided connected to the respective pixels for each column. A driving control method of a light emitting device having a pixel driving device that supplies gradation currents according to driving data to the plurality of data lines and drives the plurality of pixels for each frame period ,
The pixel driving device includes a plurality of current generation circuit groups each including a plurality of current generation circuits that generate the gray-scale current, and are provided corresponding to each of a plurality of contacts having the same number as the plurality of data lines. The plurality of contacts include a first contact and a second contact adjacent to each other, and the plurality of data lines include a first data line and a second data line adjacent to each other. And the plurality of current generation circuit groups include a first current generation circuit group and a second current generation circuit group, and the first current generation circuit group and the second current generation circuit group include: , Each having a first current generation circuit and a second current generation circuit,
In each frame period, between the first selection period in each selection period for selecting each pixel of each row of the light emitting panel, the first contact to the first and connect the data line and the second Connecting the second data line to a contact, and connecting the second data line to the first contact and the second contact in a second selection period following the first selection period. A data line switching step for switching the connection between each contact and each data line so as to connect the first data line;
Wherein between the first frame period in each frame period, the first said the contact of the first current generation circuit group of said first current generating circuit connected to said second current to said second contact The first current generation circuit of the generation circuit group is connected, and the second current of the first current generation circuit group is connected to the first contact in a second frame period subsequent to the first frame period. connect the generating circuit the second current generation circuit of the second current generating circuits to said second contact to connect said second current generating circuit, each current generation with the respective contacts A current switching step for switching the connection with the circuit;
It is characterized by including.

A drive control method for a light emitting device according to a seventh aspect of the present invention includes:
A light emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines provided connected to the respective pixels for each column. A driving control method of a light emitting device having a pixel driving device that supplies gradation currents according to driving data to the plurality of data lines and drives the plurality of pixels for each frame period ,
The pixel driving device includes a plurality of current generation circuits that generate the gray-scale current, and an auxiliary current generation that generates the gray-scale current, which is provided corresponding to each of a plurality of contacts equal to the plurality of data lines. A plurality of contacts, a first contact adjacent to each other, and a second contact; and the plurality of data lines include a first data line adjacent to each other; Two data lines,
For each selection period for selecting each pixel in each row of the light emitting panel in each frame period , the auxiliary current generation circuit is replaced with one specific current generation circuit among the plurality of current generation circuits, The plurality of current generation circuits excluding the specific current generation circuit and the auxiliary current generation circuit are connected to a contact, and the specific current generation circuit is connected to each other in the plurality of current generation circuits for each selection period. A current switching step for sequentially switching to different current generation circuits ;
In the first frame period in each frame period, the first connecting the first data line to the contact connecting the second data line to the second contact, the first frame period in the second frame period following the first as by connecting the second data line to the contact connecting the first data line to said second contact, said the previous SL each contact each A data line switching step for switching the connection with the data line;
It is characterized by including.

  According to the present invention, it is possible to make it difficult to visually recognize luminance unevenness even if there are variations in the characteristics of the current generation circuits that supply gradation currents.

It is a figure which shows the electronic device (digital camera) in which the light-emitting device based on this invention is integrated. It is a figure which shows the electronic device (computer) in which the light-emitting device based on this invention is integrated. It is a figure which shows the electronic device (cellular phone) in which the light-emitting device based on this invention is integrated. It is a figure which shows the structure of the light-emitting device which concerns on 1st Embodiment of this invention. FIG. 5 is a circuit diagram illustrating an example of a configuration of a pixel circuit illustrated in FIG. 4. It is a figure which shows the structure of the data driver concerning 1st Embodiment of this invention. It is a circuit diagram which shows an example of a structure of a current generation circuit. It is a timing chart which shows operation | movement of the light-emitting device shown in FIG. FIG. 7 is a diagram showing an operation (1) of the data driver shown in FIG. 6. It is a figure which shows operation | movement (2) of the data driver shown in FIG. FIG. 7 is a diagram showing an operation (3) of the data driver shown in FIG. 6. It is a figure which shows operation | movement (4) of the data driver shown in FIG. It is a figure which shows the relationship between the pixel and electric current generation circuit in 1st frame and 2nd frame in 1st Embodiment. It is a figure which shows the structure of the data driver which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of the switch switching circuit of the data driver shown in FIG. It is a timing chart which shows operation | movement of the light-emitting device concerning 2nd Embodiment of this invention. It is a figure which shows operation | movement (1) of the data driver shown in FIG. It is a figure which shows operation | movement (2) of the data driver shown in FIG. It is a figure which shows operation | movement (3) of the data driver shown in FIG. It is a figure which shows operation | movement (4) of the data driver shown in FIG. It is a figure which shows operation | movement (5) of the data driver shown in FIG. It is a figure which shows operation | movement (6) of the data driver shown in FIG. It is a figure which shows the relationship between the pixel and electric current generation circuit in the 1st frame and 2nd frame in 2nd Embodiment. It is a figure which shows the example of the other circuit structure of a structure of a current generation circuit. It is a figure which shows the relationship between the pixel of the conventional light-emitting device, and a current generation circuit.

Hereinafter, a pixel driving device, a light emitting device, and a driving control method for the light emitting device according to an embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
The light emitting device 10 is incorporated in an electronic device such as a digital camera as shown in FIG. 1, a computer as shown in FIG. 2, or a mobile phone as shown in FIG.

  As shown in FIGS. 1A and 1B, the digital camera 200 includes a lens unit 201, an operation unit 202, a display unit 203, and a viewfinder 204. The light emitting device 10 is used for the display unit 203.

  A computer 210 illustrated in FIG. 2 includes a display unit 211 and an operation unit 212, and the light emitting device 10 is used for the display unit 211.

  A mobile phone 220 illustrated in FIG. 3 includes a display unit 221, an operation unit 222, a receiving unit 223, and a transmitting unit 224, and the light emitting device 10 is used for the display unit 221.

  As shown in FIG. 4, the light emitting device 10 includes an organic EL panel 11, a display signal generation circuit 12, a system controller 13, a gate (select) driver 14, an anode (source) drive circuit 15, And a data driver 16.

The organic EL panel 11 includes a plurality of pixel circuits 11 [i, j] (i = 1 to m, j = 1 to n, m, n; natural numbers).
Each pixel circuit 11 [i, j] is a display pixel corresponding to one pixel of the image, and is arranged in a matrix. Each pixel circuit 11 [i, j] includes, for example, an organic EL element 111, transistors T1, T2, T3, and a capacitor Cs as shown in FIG. Here, the transistors T1, T2, and T3 and the capacitor Cs form a pixel driving circuit DC.

  The organic EL element 111 is a current-controlled light-emitting element (display element) that emits light using a phenomenon in which light is emitted by excitons generated by recombination of electrons and holes injected into an organic compound. It emits light with a luminance corresponding to the current value of the current.

  Transistors T1, T2, and T3 in the pixel driving circuit DC are TFTs (Thin Film Transistors) configured by n-channel FETs (Field Effect Transistors).

  The transistor T3 is a drive transistor that supplies current to the organic EL element 111 while controlling the current value. The drain as the current upstream end of the transistor T3 is connected to the anode line La [j], and the source as the current downstream end is connected to the anode of the organic EL element 111. The transistor T3 supplies a current having a current value corresponding to the gate voltage Vgs as the control voltage to the organic EL element 111.

  The transistor T1 is a switch transistor for connecting or blocking between the gate and the drain of the transistor T3.

  The drain (terminal) of the transistor T1 of each pixel 11 [i, j] is connected to the anode line La [j] (drain of the transistor T3), and the source is connected to the gate as the control terminal of the transistor T3.

  The gate (terminal) of the transistor T1 of each pixel 11 [1,1] to 11 [m, 1] is connected to the gate line Lg [1]. Similarly, the gate of the transistor T1 of each pixel 11 [1,2] to 11 [m, 2] is connected to the gate line Lg [2],..., And each pixel 11 [1, n] to 11 [m, 2]. The gate of the transistor T1 of n] is connected to the gate line Lg [n], respectively.

  In the case of the pixel 11 [1,1], when the H (High) level signal is output from the gate driver 14 to the gate line Lg [1], the transistor T1 is turned on. Thereby, since the drain and the gate of the transistor T3 are connected, the transistor T3 is in a diode connection state.

  When an L (Low) level signal is output to the gate line Lg [1], the transistor T1 is turned off and the transistor T2 is also turned off. At the same time, when the transistor T1 is turned off, the charge charged in the capacitor Cs is held.

  The transistor T2 is a switch transistor that is selected and turned on / off by the gate driver 14 to connect / cut off the anode of the organic EL element 111 and the data line Ld [1].

  The drain of the transistor T2 of each pixel 11 [i, j] is connected to the anode (electrode) of the organic EL element 111.

  The gates of the transistors T2 of the pixels 11 [1,1] to 11 [m, 1] are connected to the gate line Lg [1]. Similarly, the gate of the transistor T2 of each pixel 11 [1,2] to 11 [m, 2] is connected to the gate line Lg [2],..., Each pixel 11 [1, n] to 11 [m, n ] Of the transistor T2 is connected to the gate line Lg [n].

  Further, the source as the other end of the transistor T2 of each of the pixels 11 [1,1] to 11 [n, 1] is connected to the data line Ld [1]. Similarly, the source of the transistor T2 of each pixel 11 [2,1] to 11 [2, n] is connected to the data line Ld [2],..., Each pixel 11 [m, 1] to 11 [m, The source of the transistor T2 of n] is connected to the data line Ld [m].

  In the case of the pixel 11 [1,1], the transistor T2 is turned on when an H level signal is output from the gate driver 14 to the gate line Lg [1], and the anode of the organic EL element 111 and the data line Ld [1]. ] And connect.

  When an L level signal is output to the gate line Lg [1], the transistor T2 is turned off, and the anode of the organic EL element 111 and the data line Ld [1] are disconnected.

  The capacitor Cs is a capacitance component that holds the gate Vgs of the transistor T3. One end of the capacitor Cs is connected to the source of the transistor T1 and the gate of the transistor T3, and the other end is connected to the source of the transistor T3 and the anode of the organic EL element 111. Connected to.

  When a drain current flows from the anode line La [j] toward the drain of the transistor T2 in the capacitor Cs, the transistor T3 is turned on and charged by the gate voltage Vgs of the corresponding transistor T3, and the charge is accumulated.

  When the transistors T1 and T2 are turned off, the capacitor Cs holds the gate voltage Vgs of the transistor T3.

  Returning to FIG. 4, the display signal generation circuit 12 is supplied with a video signal Image such as a composite video signal and a component video signal from the outside, and display data d [1 such as a luminance signal from the supplied video signal Image. ] To d [m], the synchronization signal Sync is acquired. The display signal generation circuit 12 supplies the acquired synchronization signal Sync to the system controller 13 and supplies display data d [1] to d [m] to the data driver 16. Here, the display data d [1] to d [m] correspond to the pixels 11 [1, j] to 11 [m, j] in one row of the organic EL panel 11.

  The system controller 13 generates start pulses Sp1, Sp2, Sp3 clock signals CK1, CK2, CK3 and other control signals from the supplied synchronization signal Sync.

  The start pulses Sp1, Sp2, Sp3 and the clock signals CK1, CK2, CK3 are pulse signals for operating the gate driver 14, the anode drive circuit 15, and the data driver 16.

  The system controller 13 supplies the generated start pulses Sp1, Sp2, Sp3, clock signals CK1, CK2, CK3 and other control signals to the gate driver 14, the anode drive circuit 15, and the data driver 16.

  Further, the system controller 13 supplies the data driver 16 with current selection signals ISEL [1], ISEL [2], ISEL [3], ISEL [4], various switching control signals Csw11 [[1a], Csw11 [[1b], ..., Csw11 [[ma], Csw11 [[mb] are supplied.

  The current selection signals ISEL [1] and ISEL [2] are control signals for selecting the current generation circuit 64 [1a] or 64 [1b] provided for each data line Ld [1] to Ld [m]. It is. The system controller 13 switches the data to H level or L level each time the gate driver 14 outputs the gate signals Sg [1] to Sg [n] to the gate lines Lg [1] to Lg [n], respectively. This is supplied to the driver 16.

  The current selection signals ISEL [3] and ISEL [4] are used for the data lines Ld [1] for supplying the grayscale currents Idata [1] or Idata [2], ..., Idata [m-1] or Idata [m]. ] To Ld [m]. The system controller 13 controls the light emission of the organic EL elements of all the pixels 11 [1,1] to 11 [m, 1],..., 11 [1, n] to 11 [m, n]. The current selection signals ISEL [3] and ISEL [4] are switched to H level or L level for each period and supplied to the data driver 16.

  The switching control signals Csw11 [1a], Csw11 [1b],..., Csw11 [[ma], Csw11 [mb] are current generation circuits 64 [1a], 64 [1b],. , 64 [ma], 64 [mb]. The system controller 13 sequentially switches and supplies the switching control signals Csw11 [1a], Csw11 [1b],..., Csw11 [ma], Csw11 [mb] to the data driver 16.

  The gate driver 14 is a driver that selects the pixels 11 [1,1] to 11 [m, 1],..., 11 [1, n] to 11 [m, n] for each row. Consists of registers.

  The gate driver 14 is connected to the gates of the transistors T1 and T2 of the pixel 11 [i, j] (i = 1 to m) via the gate line Lg [j] (j = 1 to n), respectively.

  The anode drive circuit 15 is connected to the transistor T3 of each pixel 11 [i, j] (i = 1 to m, j = 1 to n) via the anode line La [j] (j = 1 to n), respectively. Connected to the drain. The anode drive circuit 15 outputs an anode signal Sa of L level or H level.

  The H level of the anode signal Sa is a voltage level for bringing the organic EL element 111 of each pixel 11 [i, j] into a light emitting state, and is set to + 15V, for example. The L level is set to GND (0 V).

  The data driver 16 generates gradation currents Idata [1] to Idata [m] corresponding to the supplied display data d [1] to d [m], and the pixels 11 [i, j] ( i = 1 to m, j = 1 to n) is a driver to be applied (written) to each capacitor Cs.

  As shown in FIG. 6, the data driver 16 according to the first embodiment includes a shift register 61, a data latch unit 62, a constant current source 63, a current generation unit 64, a reference current switching circuit Sw11, and a switch circuit. A current switching circuit 65 having Sw21 [1] to Sw21 [m] and a data line switching circuit Sw22 [1] to Sw22 [m / 2] are provided.

  The shift register 61 is a circuit that sequentially shifts the start signal Sp2 supplied from the system controller 13 in accordance with the clock signal CK2 supplied from the system controller 13 and outputs it as a shift signal.

  The data latch unit 62 includes a latch circuit (denoted as “Latch” in the drawing) 62 [1a], 62 [1b],..., 62 [ma], 62 [mb]. The circuits 62 [1a],..., 62 [ma] and the latch circuits 62 [1b],..., 62 [mb] are arranged in one row according to the shift signal output from the shift register 61. This is a circuit that alternately latches (holds) the display data d [1] to d [m] for each frame period.Latch circuit 62 [1a], ..., 62 [ma] and latch circuit 62 [1b .., 62 [mb], while one of the display data is latched, the other latch circuit operates to output the display data latched in the previous frame period.

  In the first embodiment, each current generation circuit 64 [1a],..., 64 [mb] in the data driver 16 and the organic EL panel for each row in one frame period and for each frame period. 11, the data driver 16 uses the current generation circuit 64 that uses the supplied display data d [1] to d [m]. [1a], ..., rearrange so as to correspond to 64 [mb]. For this purpose, the data driver 16 includes, for example, a memory, and temporarily stores the display data d [1] to d [m] in the memory, and uses the current generation circuits 64 [1a],. ] Is read out from the memory in the order corresponding to Further, the display signal generation circuit 12 may be configured to perform similar rearrangement of the display data d [1] to d [m] and supply the data to the data driver 16.

  The constant current source 63 is a circuit for supplying the reference current Iref to the current generator 64.

  The current generator 64 is a circuit for generating gradation currents Idata [1] to Idata [m] corresponding to the display data d [1] to d [m], and is a single data line Ld [i]. For (i = 1 to m), two current generation circuits 64 [1a], 64 [1b],..., 64 [ma], [mb] are provided.

  When the display data d [1] to d [m] is, for example, 4-bit data, the current generation circuit 64 [1a] has, for example, transistors T11 and T12 [0] to T12 [ 3], T13 [0] to T13 [3], and a capacitor C11.

  Transistors T11, T12 [0] to T12 [3], T13 [0] to T13 [3] are TFTs configured by n-channel FETs, and currents are generated by T11, T12 [0] to T12 [3]. A mirror circuit is configured.

  The drain of the transistor T11 is connected to the current downstream end of the constant current source 63 via the changeover switch Sw [1a], and the voltage VEE (<0 V) is applied to the source. The drain and gate of the transistor T11 are connected, and the capacitor C11 is connected between the gate and source of the transistor T11.

  The transistors T13 [0] to T13 [3] are switch transistors that are turned on and off based on the bit values of the bits bit [0] to bit [3] of the display data d [1]. The bit value of each bit bit [0] to bit [3] of the display data d [1] is supplied.

  The drains of the transistors T12 [0] to T12 [3] are connected to the current downstream end of the changeover switch Sw21 [1a] of the switch circuit Sw21 [1] of the current changeover circuit 65.

  The transistors T12 [0] to T12 [3] are transistors whose channel lengths are equal and channel widths are set to 1: 2: 4: 8. The drains of the transistors T12 [0] to T12 [3] The voltage VEE is applied to the source.

  In the current generation circuit 64 [1a] configured as described above, when the switch control signal Csw11 [1a] of H level is supplied and the switch Sw11 [1a] is turned on and closed, the transistor T11 is supplied from the constant current source 63. A reference current Iref is supplied between the drain and the source. As a result, the voltage component corresponding to the reference current Iref is held in the capacitor C11. Next, when the display data d [1] is supplied, the transistors T13 [0] to T13 [3] are based on the bit values of the bits bit [0] to bit [3] of the display data d [1]. Turn on and off.

  When the transistors T13 [0] to T13 [3] are turned on, the current value of the current flowing between the drain and source of the transistors T13 [0] to T13 [3] is set to the current value of the reference current Iref. It is a value obtained by multiplying the ratio of the channel width of 0] to T12 [3] to the channel width of the transistor T11. The ratio of the current values of the current flowing between the drain and source of the transistors T13 [0] to T13 [3] is 1: 2 corresponding to the ratio of the channel widths of the transistors T12 [0] to T12 [3]. : 4: 8. The currents flowing between the drains and sources of the transistors T13 [0] to T13 [3] that are turned on are combined, and the combined current becomes the gradation current Idata [1].

  In this way, when the current generation circuit 64 [1a] generates the gradation current Idata [1] corresponding to the display data d [1] and is connected to the data line Ld [1] or Ld [2]. Then, the generated gradation current Idata [1] is drawn. The current generation circuits 64 [1b],..., 64 [ma], [mb] are similarly configured.

  The reference current switching circuit Sw11 shown in FIG. 6 includes changeover switches Sw11 [1a], Sw11 [1b],..., Sw11 [ma], Sw11 [mb].

  The changeover switches Sw11 [1a], Sw11 [1b],..., Sw11 [ma], Sw11 [mb] are respectively a constant current source 63 and current generation circuits 64 [1a], 64 [1b],. .., 64 [ma], 64 [mb] are switches for connecting / disconnecting.

  The current upstream end of the changeover switch Sw11 [1a] is connected to the current downstream end of the constant current source 63. The changeover switches Sw11 [1b],..., Sw11 [ma], Sw11 [mb] are similarly configured.

  The changeover switches Sw11 [1a], Sw11 [1b],..., Sw11 [ma], Sw11 [mb] are the changeover control signals Csw11 [1a], Csw11 [1b],. ... Connection is switched each time Csw11 [ma] and Csw11 [mb] are switched to H level.

  The switch circuits Sw21 [1] to Sw21 [m] of the current switching circuit 65 include two current generation circuits 64 [1a], 64 [1b],... For the data lines Ld [i] (i = 1 to m). , 64 [ma], [mb], and includes changeover switches Sw21 [1a], Sw21 [1b],... Sw21 [ma], Sw21 [mb].

  The changeover switches Sw21 [1a], Sw21 [1b],... Sw21 [ma], Sw21 [mb] are opened and closed according to the signal levels of the current selection signals ISEL [1] and ISEL [2] supplied from the system controller 13. (ON, OFF). The current upstream ends of the changeover switches Sw21 [1a] and Sw21 [1b] are connected to the contact N1 [1], and the current upstream ends of the changeover switches Sw21 [2a] and Sw21 [2b] are connected to the contact N1 [2]. .

  The data line switching circuits Sw22 [1] to Sw22 [m / 2] are connected to the data lines Ld [1] or Ld [1] according to the signal levels of the current selection signals ISEL [3] and ISEL [4] supplied from the system controller 13. 2] and the current generation circuit 64 [1a] or 64 [1b], ..., the data line Ld [m-1] or Ld [m] and the current generation circuit 64 [ma] or 64 [mb], This is a circuit for blocking.

  The data line switching circuit Sw22 [1] includes changeover switches Sw22 [11] to Sw22 [14]. The current upstream ends of the changeover switches Sw22 [11] and Sw22 [12] are connected to the data line Ld [1], and the current upstream ends of the changeover switches Sw22 [13] and Sw22 [14] are connected to the data line Ld [2]. Is done.

The current downstream ends of the changeover switches Sw22 [11] and Sw22 [14] are connected to the contact N1 [1]. The current downstream ends of the changeover switches Sw22 [12] and Sw22 [13] are connected to the contact N1 [2].
The data line switching circuits Sw22 [2] to Sw22 [m / 2] are similarly configured.

Next, the operation of the light emitting device 10 according to Embodiment 1 will be described.
The light emitting device 10 operates according to the timing chart shown in FIG.
Time t1 to t2 is the first frame period T1. At times t1 to t10 in the first frame period T1, the reference current is sequentially supplied to the current generation circuits 64 [1a], 64 [1b] to 64 [ma], 64 [mb], and the capacitor C11 of each current generation circuit is supplied. Is a holding period T1r in which the voltage component corresponding to the reference current Iref is held, and at time t10 to t2, the pixel circuit 11 [i, j] (i = 1 to m, j = 1 to n) is in the first frame. Is a writing period T1w in which the gradation current Idata [j] is supplied and voltages corresponding to the display data d [1] to d [m] are written to the capacitors Cs.

  Time t2 to t3 is the second frame period T2. At times t2 to t20 in the second frame period T2, the reference current is sequentially supplied to the current generation circuits 64 [1a], 64 [1b] to 64 [ma], 64 [mb], and the capacitor C11 of each current generation circuit is supplied. Is the holding period T2r during which the voltage component corresponding to the reference current Iref is held, and during the time t20 to t3, the gradation current Idata [j] of the second frame is supplied to the pixel circuit 11 [i, j] to display This is a writing period T2w in which a voltage corresponding to the data d [1] to d [m] is written to each capacitor Cs.

  When the video signal Image is supplied from the outside to the display signal generation circuit 12, the display signal generation circuit 12 acquires the display data d [1] to d [m] and the synchronization signal Sync from the supplied video signal Image. The display signal generation circuit 12 supplies the acquired synchronization signal Sync to the system controller 13 and supplies display data d [1] to d [m] to the data driver 16.

  The system controller 13 supplies the data driver 16 with the H level current selection signal ISEL [1] and the L level current selection signal ISEL [2] at time t1.

  When the current selection signal ISEL [1] becomes H level, the changeover switches Sw21 [1a], Sw21 [2a],..., Sw21 [ma] of the switch circuits Sw21 [1] to Sw21 [m] of the current switching circuit 65. ], The data line switching circuit Sw22 [1] and the current generation circuits 64 [1a], 64 [2a],..., The data line switching circuit Sw22 [m / 2] and the current generation circuit 64 [(m-1 ) a] and 64 [ma] are connected.

  When the current selection signal ISEL [2] becomes L level, each switch SW21 [1b], Sw21 [2b],..., Sw21 [mb] of the switch circuits Sw21 [1] to Sw21 [m] of the current switching circuit 65. ], The data line switching circuit Sw22 [1] and the current generation circuits 64 [1b], 64 [2b],..., The data line switching circuit Sw22 [m / 2] and the current generation circuit 64 [(m-1 b) and 64 [mb] are blocked.

  Further, the system controller 13 supplies a start pulse Sp and a clock signal CK to the gate driver 14, the anode drive circuit 15, and the data driver 16. The gate driver 14, the anode driving circuit 15, and the data driver 16 are started to operate by receiving the start pulse Sp and the clock signal CLK.

Then, the system controller 13 supplies the H level switching control signal Csw11 [1a] to the data driver 16 at time t1. Thus, Sw11 [1a] is turned on and closed, and the reference current Iref is supplied from the constant current source 63 to the drain and source of the transistor T11 of the current generation circuit 64 [1a], and the capacitor C11 corresponds to the reference current Iref. The voltage component is retained. Next, at time ta1, the system controller 13 supplies the data driver 16 with an L level switching control signal Csw11 [1a] and an H level switching control signal Csw11 [1b]. As a result, Sw11 [1a] is turned off and opened, Sw11 [1b] is turned on and closed, and the reference current Iref is supplied from the constant current source 63 to the drain and source of the transistor T11 of the current generation circuit 64 [1b]. The voltage component corresponding to the reference current Iref is held in the capacitor C11. Similarly, from time ta2 to t10, the voltage component corresponding to the reference current Iref is held in each capacitor C11 of the current generation circuits 64 [2a] to 64 [mb].
Next, at time t10, the gate driver 14 outputs an H level gate signal Sg [1] to the gate line Lg [1], and the pixel circuits 11 [1,1] to [m, 1] in the first row Selected.

  The system controller 13 supplies the data driver 16 with an H level current selection signal ISEL [3] and an L level current selection signal ISEL [4].

  When the current selection signals ISEL [3] and ISEL [4] become H and L levels, respectively, as shown in FIG. 9A, the changeover switches Sw22 [11] and Sw22 of the data line switching circuit Sw22 [1]. [13] is closed and the changeover switches Sw22 [12] and Sw22 [14] are opened.

  When the changeover switch Sw22 [11] is closed, the data line Ld [1] and the current generation circuit 64 [1a] are connected via the contact N1 [1], and as shown by the arrows in the figure, the gradation current Idata [1] flows from the pixel circuit 11 [1,1] to the current generation circuit 64 [1a] via the data line Ld [1].

  For this reason, as shown in FIG. 9B, the gradation current Idata [generated by the current generation circuit 64 [1a] is applied to the capacitor Cs of the pixel circuit 11 [1,1] in the first row and the first column. The voltage corresponding to 1] is written (applied). The capacitor Cs of the pixel circuit 11 [1,1] holds this voltage as the gate voltage Vgs of the transistor T3.

  When the changeover switch Sw22 [13] is closed, the data line Ld [2] and the current generation circuit 64 [2a] are connected via the contact N1 [2], and as shown by the arrows in the figure, the gradation current Idata [2] flows from the pixel circuit 11 [2,1] to the current generation circuit 64 [2a] via the data line Ld [2].

  For this reason, as shown in FIG. 9B, the gradation current Idata [2] of the current generation circuit 64 [2a] is connected to the capacitor Cs of the pixel circuit 11 [2,1] in the first row and the second column. A voltage corresponding to is written (applied). The capacitor Cs of the pixel circuit 11 [2,1] holds this voltage as the gate voltage Vgs of the transistor T3.

  Similarly, voltages corresponding to the gradation currents Idata [3] to Idata [m] are written to the capacitors Cs of the pixel circuits 11 [3,1] to 11 [m, 1] in the first row, respectively. The voltage is held as the gate voltage Vgs of the transistor T3.

  Next, at time t11 shown in FIG. 8, the gate driver 14 applies the L level gate signal Sg [1] and the H level gate signal Sg [2] to the gate lines Lg [1] and Lg [2], respectively. When output, the pixel circuits 11 [1,2] to [m, 2] in the second row are selected.

  The system controller 13 switches the signal levels of the current selection signals ISEL [3] and ISEL [4] supplied to the data driver 16 to L and H levels, respectively.

  When the current selection signals ISEL [3] and ISEL [4] become L and H levels, respectively, as shown in FIG. 10A, the changeover switches Sw22 [11] and Sw22 of the data line switching circuit Sw22 [1]. [13] is opened, and the changeover switches Sw22 [12] and Sw22 [14] are closed.

  When the changeover switches Sw22 [11] and Sw22 [13] are opened, the data line Ld [1] and the current generation circuit 64 [1a] are disconnected from the data line Ld [2] and the current generation circuit 64 [2a]. The

  When the changeover switch Sw22 [12] is closed, the data line Ld [2] and the current generation circuit 64 [2a] are connected via the contact N1 [2], and as shown by the arrows in the figure, the gradation current Idata [2] flows from the pixel circuit 11 [1,2] to the current generation circuit 64 [2a] via the data line Ld [1].

  For this reason, as shown in FIG. 10B, the gradation current Idata [generated by the current generation circuit 64 [2a] is applied to the capacitor Cs of the pixel circuit 11 [1,2] in the second row and first column. 2] is written (applied). The capacitor Cs of the pixel circuit 11 [1,2] holds this voltage as the gate voltage Vgs of the transistor T3.

  When the changeover switch Sw22 [14] is closed, the data line Ld [2] and the current generation circuit 64 [1a] are connected via the contact N1 [2], and as shown by the arrows in the figure, the gradation current Idata [1] flows from the pixel circuit 11 [2,2] to the current generation circuit 64 [1a] via the data line Ld [2].

  Therefore, as shown in FIG. 10B, the gradation current Idata [generated by the current generation circuit 64 [1a] is applied to the capacitor Cs of the pixel circuit 11 [2,2] in the second row and second column. The voltage corresponding to 1] is written (applied). The capacitor Cs of the pixel circuit 11 [2,2] holds this voltage as the gate voltage Vgs of the transistor T3.

  Similarly, the data line Ld [1] and the current generation circuit 64 [2a], the data line Ld [2] and the current generation circuit 64 [1a],..., The data line Ld [m] and the current generation circuit 64 [ma]. ] Is connected.

  Then, the capacitors Cs of the pixel circuits 11 [3,2] to 11 [m, 2] in the second row have gradation currents Idata [4], Idata [3],. A voltage corresponding to Idata [m−1] is written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  In this way, at times t10 to t2, the capacitors Cs of the pixel circuits 11 [1,2j-1] to 11 [m, 2j-1] (j = 1 to n) in the odd-numbered rows are supplied with the gradation current Idata. [1], Idata [2],..., Idata [m−1], Idata [m] are written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  Further, each capacitor Cs of the pixel circuits 11 [1,2j] to 11 [m, 2j] in the even-numbered rows has gradation currents Idata [2], Idata [1],..., Idata [m], Idata [ m-1] is written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  At times t10 to t13, the anode driving circuit 15 outputs H-level anode signals Sa [n / 2] to [n] to the anode lines La [n / 2] to La [n], respectively.

  When the signal levels of the anode signals Sa [n / 2] to [n] become H level, the pixel circuits 11 [1, n / 2] to 11 [m, n / 2],. ] To 11 [m, n], a current flows through the GND via the drain-source of the transistor T3 and the anode-cathode of each organic EL element 111.

  Each transistor T3 controls the current value with the gate voltage Vgs held by each capacitor Cs, and each organic EL element 111 emits light with luminance corresponding to the current value of the supplied gradation current.

  At times t10 to t13, each capacitor of the pixel circuits 11 [1,1] to 11 [m, 1],..., 11 [1, n / 2-1] to 11 [m, n / 2-1] When a voltage is written to Cs, the anode drive circuit 15 outputs the anode signals Sa [1] to [H] at the H level to the anode lines La [1] to La [n / 2-1] at times t13 to t2, respectively. n / 2-1] is output.

  Each transistor T3 of the pixel circuits 11 [1,1] to 11 [m, 1],..., 11 [1, n / 2-1] to 11 [m, n / 2-1] is connected to each capacitor Cs. The organic EL element 111 emits light with a luminance corresponding to the current value of the supplied gradation current.

  Next, at time t2 shown in FIG. 8, the system controller 13 supplies the data driver 16 with the L-level current selection signal ISEL [1] and the H-level current selection signal ISEL [2].

  When the current selection signal ISEL [1] becomes L level, each switch SW21 [1a], Sw21 [2a],..., Sw21 [ma] of the switch circuits Sw21 [1] to Sw21 [m] of the current switching circuit 65 is set. ], The data line switching circuit Sw22 [1] and the current generation circuits 64 [1a], 64 [2a],..., The data line switching circuit Sw22 [m / 2] and the current generation circuit 64 [(m-1 a) and 64 [ma] are interrupted.

  When the current selection signal ISEL [2] becomes the H level, the changeover switches Sw21 [1b], Sw21 [2b],..., Sw21 [mb] of the switch circuits Sw21 [1] to Sw21 [m] of the current switching circuit 65. ], The data line switching circuit Sw22 [1] and the current generation circuits 64 [1b], 64 [2b],..., The data line switching circuit Sw22 [m / 2] and the current generation circuit 64 [(m-1 b) and 64 [mb] are connected.

Then, the system controller 13 supplies an H level switching control signal Csw11 [1a] to the data driver 16 at time t2. Thus, Sw11 [1a] is turned on and closed, and the reference current Iref is supplied from the constant current source 63 to the drain and source of the transistor T11 of the current generation circuit 64 [1a], and the capacitor C11 corresponds to the reference current Iref. The voltage component is retained. Next, at time tb1, the system controller 13 supplies the data driver 16 with an L level switching control signal Csw11 [1a] and an H level switching control signal Csw11 [1b]. As a result, Sw11 [1a] is turned off and opened, Sw11 [1b] is turned on and closed, and the reference current Iref is supplied from the constant current source 63 to the drain and source of the transistor T11 of the current generation circuit 64 [1b]. The voltage component corresponding to the reference current Iref is held in the capacitor C11. Similarly, at time tb2 to t20, a voltage component corresponding to the reference current Iref is held in each capacitor C11 of the current generation circuits 64 [2a] to 64 [mb].
Next, at time t20, the gate driver 14 outputs an H level gate signal Sg [1] to the gate line Lg [1], and the pixel circuits 11 [1,1] to [m, 1] in the first row Selected.

  The system controller 13 supplies the data driver 16 with an H level current selection signal ISEL [3] and an L level current selection signal ISEL [4].

  When the current selection signals ISEL [3] and ISEL [4] become H and L levels, respectively, as shown in FIG. 11A, the changeover switches Sw22 [11] and Sw22 of the data line switching circuit Sw22 [1]. [13] is closed and the changeover switches Sw22 [12] and Sw22 [14] are opened.

  When the changeover switch Sw22 [11] is closed, the data line Ld [1] and the current generation circuit 64 [1b] are connected via the contact N1 [1], and as shown by the arrows in the figure, the gradation current Idata [1] flows from the pixel circuit 11 [1,1] to the current generation circuit 64 [1b] via the data line Ld [1].

  For this reason, as shown in FIG. 11B, the gradation current Idata [generated by the current generation circuit 64 [1b] is applied to the capacitor Cs of the pixel circuit 11 [1,1] in the first row and the first column. The voltage corresponding to 1] is written (applied). The capacitor Cs of the pixel circuit 11 [1,1] holds this voltage as the gate voltage Vgs of the transistor T3.

  When the changeover switch Sw22 [13] is closed, the data line Ld [2] and the current generation circuit 64 [2b] are connected via the contact N1 [2], and as shown by the arrows in the figure, the gradation current Idata [2] flows from the pixel circuit 11 [2,1] to the current generation circuit 64 [2b] via the data line Ld [2].

  For this reason, as shown in FIG. 11B, the capacitor Cs of the pixel circuit 11 [1,1] in the first row and the first column has the gradation current Idata [2] generated by the current generation circuit 64 [2b]. ] Is written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  Similarly, voltages corresponding to the gradation currents Idata [3] to Idata [m] are written to the capacitors Cs of the pixel circuits 11 [3,1] to 11 [m, 1] in the first row, respectively. The voltage is held as the gate voltage Vgs of the transistor T3.

  At time t21 shown in FIG. 8, the gate driver 14 outputs an L level gate signal Sg [1] and an H level gate signal Sg [2] to the gate lines Lg [1] and Lg [2], respectively. The pixel circuits 11 [1,2] to [m, 2] in the second row are selected.

  The system controller 13 switches the signal levels of the current selection signals ISEL [3] and ISEL [4] supplied to the data driver 16 to L and H levels, respectively.

  When the current selection signals ISEL [3] and ISEL [4] become L and H levels, respectively, as shown in FIG. 12A, the changeover switches Sw22 [11] and Sw22 of the data line switching circuit Sw22 [1]. [13] is opened, and the changeover switches Sw22 [12] and Sw22 [14] are closed.

  When the changeover switch Sw22 [12] is closed, the data line Ld [1] and the current generation circuit 64 [2b] are connected via the contact N1 [2], and as shown by the arrows in the figure, the gradation current Idata [2] flows from the pixel circuit 11 [1,2] to the current generation circuit 64 [2b] via the data line Ld [1].

  For this reason, as shown in FIG. 12B, the capacitor Cs of the pixel circuit 11 [1,2] in the second row and first column is connected to the gradation current Idata [2] generated by the current generation circuit 64 [2b]. ] Is written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  When the changeover switch Sw22 [14] is closed, the data line Ld [2] and the current generation circuit 64 [1b] are connected via the contact N1 [1], and as shown by the arrows in the figure, the gradation current Idata [1] flows from the pixel circuit 11 [2,2] to the current generation circuit 64 [1b] via the data line Ld [2].

  For this reason, as shown in FIG. 12B, the capacitor Cs of the pixel circuit 11 [2,2] in the second row and the second column has the gradation current Idata [1] generated by the current generation circuit 64 [1b]. ] Is written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  Similarly, the capacitors Cs of the pixel circuits 11 [3,2] to 11 [m, 2] in the second row respectively have gradation currents Idata [4], Idata [3], ..., Idata [m]. , Idata [m−1] is written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  In this way, at times t20 to t3, the capacitors Cs of the pixel circuits 11 [1,2j-1] to 11 [m, 2j-1] (j = 1 to n) in the odd-numbered rows are supplied with the gradation current Idata. [1], Idata [2],..., Idata [m−1], Idata [m] are written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  Further, each capacitor Cs of the pixel circuits 11 [1,2j] to 11 [m, 2j] in the even-numbered rows has gradation currents Idata [2], Idata [1],..., Idata [m], Idata [ m-1] is written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  FIG. 13 shows a current generation circuit 64 that writes gradation currents Idata [1] to Idata [4] to each pixel circuit 11 [i, j] (i = 1 to 4, j = 1 to 4) in this embodiment. The correspondence of [1b] -64 [4b] is shown. FIG. 13A shows the case of the first frame, and FIG. 13B shows the case of the second frame.

  In the case of the first frame, as shown in FIG. 13A, for example, the current generation circuits 64 [1a] and 64 [2a] corresponding to the first and second columns are alternately switched for each row. The current generation circuits 64 [3a] and 64 [4a] corresponding to the columns and the fourth column are alternately switched. As shown in FIGS. 13A and 13B, the current generation circuits 64 [1a] to 64 [4a] are switched from 64 [1b] to 64 [4b] between one frame and two frames. For this reason, even if the characteristics of the current generation circuits 64 [1a] to 64 [4b] are not uniform, it is possible to make it difficult to visually recognize luminance unevenness.

In the timing chart of FIG. 8, the capacitor C11 of each current generation circuit has a holding period for holding a voltage component corresponding to the reference current Iref in each frame period. However, a plurality of charges held by the capacitor C11 are stored. In the case of having a capacity value that can be held over the frame period, this holding period may be provided only at intervals of a plurality of frame periods. In this case, in the frame period having no holding period, the selection period of the pixel circuits in each row can be lengthened.
As described above, according to this embodiment, the current that draws the grayscale currents Idata [1] to Idata [m] from the pixel circuit 11 [i, j] (i = 1 to m, j = 1 to n). The generation circuits 64 [1a], 64 [1b],..., 64 [ma], 64 [mb] are switched every row and every frame period.

  Therefore, even if the characteristics of the current generation circuits 64 [1a], 64 [1b],..., 64 [ma], 64 [mb] are not equal, it is possible to suppress the luminance unevenness from being visually recognized.

(Second Embodiment)
The current generation unit of the light emitting device according to the second embodiment includes an auxiliary constant current generation circuit, and switches the connection between the current generation circuit and the auxiliary constant current generation circuit for the data line every frame period. Is.

  As shown in FIG. 14, the data driver 16 according to the second embodiment includes a shift register 61, a constant current source 63, a current generation unit 70, a data latch unit 80, a current switching circuit 90, and a switch switching circuit. 95 and data line switching circuits Sw22 [1] to Sw22 [m / 2].

  The current generation unit 70 includes m current generation circuits 71 [1] to 71 [m] and one auxiliary current generation circuit 72. Current generation circuits 71 [1] to 71 [m] are provided corresponding to the data lines Ld [1] to Ld [m], respectively. The auxiliary current generation circuit 72 is used by replacing any of the current generation circuits 71 [1] to 71 [m].

  Each of the current generation circuits 71 [1] to 71 [m] and the auxiliary current generation circuit 72 has, for example, the configuration shown in FIG.

  The data latch unit 80 includes latch circuits 81 [1a], 81 [1b],..., 81 [ma], 81 [mb], 82 [a], 82 [b], selectors 83 [1] to 83 [ m], 84.

  The latch circuits 81 [1a],..., 81 [ma] and 81 [1b],..., 81 [mb] correspond to one row according to the shift signal output from the shift register 61. The display data d [1] to d [m] are alternately latched every frame period. While one of the latch circuits 81 [1a],..., 81 [ma] and the latch circuits 81 [1b],. The display data latched during the frame period is output.

  The latch circuits 82 [a] and 82 [b] are circuits for alternately latching display data for the auxiliary current generating circuit 72 every frame period.

  Note that the data driver 16 uses the display data d [1] to d [m] for each frame period and the current generation circuits 71 [1] to 71 [m] and the auxiliary current generation circuit that are used during the frame period. It rearranges so that it may correspond to the order of 72.

Therefore, the data driver 16 includes, for example, a memory, and temporarily stores the display data d [1] to d [m] in the memory, and the current generation circuits 71 [1] to 71 [m] to be used and the auxiliary current are used. The display data d [1] to d [m] are rearranged by reading in correspondence with the order of the generation circuit 72.
For example, the display signal generation circuit 12 may rearrange the display data d [1] to d [m] and supply the data to the data driver 16.

  The selectors 83 [1] to 83 [m] are latched by the latch circuits 81 [1a],..., 81 [ma], or the latch circuits 81 [1b],. This is a circuit for selecting display data d [1] to [m].

  The selector 84 is a circuit for selecting display data d [1] to [m] latched by the latch circuit 82 [a] or the latch circuit 82 [b].

  As shown in FIG. 14, the current switching circuit 90 includes a switch circuit Sw13 and switch circuits Sw12 [1],..., Sw12 [m]. The switch circuit Sw13 includes changeover switches Sw13 [a] and Sw13 [b]. The switch circuit Sw12 [1] includes changeover switches Sw12 [1a], Sw12 [1b], and Sw12 [1c].

The change-over switch Sw13 [a] is a change-over switch that connects the auxiliary current generation circuit 72 and the constant current source 63 when the control signal Csw13 [a; on] is supplied from the system controller 13 as a control signal.
The changeover switch Sw13 [b] is supplied with a changeover control signal Csw13 [b; on] from the system controller 13 as a control signal, and data is transmitted via the changeover switches Sw12 [1c],..., Sw12 [mc]. This is a changeover switch that connects the lines Ld [1] to Ld [m] and the correction current generation circuit 72.

  The changeover switch Sw12 [1a] is supplied with changeover control signals Csw12 [a], Csw12 [b], Csw14 [1] from the system controller 13 as control signals, and is connected to the constant current source via the changeover circuit 95 [1a]. 63 is a change-over switch that connects and disconnects 63 and the current generation circuit 71 [1].

The changeover switch Sw12 [1b] is supplied with a changeover control signal Csw12 [a], Csw12 [b], Csw14 [1] from the system controller 13 as a control signal, and is connected to the data line Ld [1] or Ld [2]. This is a changeover switch that connects and disconnects the current generation circuit 71 [1].
The changeover switch Sw12 [1c] is supplied with changeover control signals Csw12 [a], Csw12 [b], and Csw14 [1] from the system controller 13 as control signals, and the data line via the changeover switch Sw13 [b]. This is a changeover switch that connects and disconnects Ld [1] or Ld [2] and the correction current generation circuit 72. The current upstream ends of the changeover switches Sw12 [1b] and Sw12 [1c] are connected to the contact N2 [1].

  The current switching circuits Sw12 [2],..., Sw12 [m] are also switch switches Sw12 [2a] to Sw12 [2c],..., Sw12 [ma] to Sw12 [mc] having similar functions, respectively. Is provided.

  The switch switching circuit 95 includes switching circuits 95 [1a], 95 [1b], 95 [1c],..., 95 [ma], 95 [mb], and 95 [mc]. As shown in FIG. 15, the switching circuit 95 [1a] includes an inverter circuit 97 and switches Sw14 [1a] and Sw14 [1b].

  The switch Sw14 [1a] in the switching circuit 95 [1a] is turned on / off (open / closed) by the switching control signal Csw14 [1], and the switching control signal Csw12 to the switching switch Sw12 [1a] of the switching circuit Sw12 [1] is switched. The switch Sw14 [1b] is switched on and off (open / closed) by the inverted signal of the switching control signal Csw14 [1] via the inverter circuit 97, and the switch Sw12 [1b] is switched on and off. This is a changeover switch for intermittently supplying the control signal Csw12 [b] to [1a].

  The switch Sw14 [1c] in the switching circuit 95 [1b] is turned on / off (open / closed) by the switching control signal Csw14 [1], and the switching control signal Csw12 to the switching switch Sw12 [1b] of the switch circuit Sw12 [1] is switched. The switch Sw14 [1d] is switched on and off (open / closed) by the inverted signal of the switching control signal Csw14 [1] via the inverter circuit 97, and the switch Sw12 [1d] is switched on and off. This is a change-over switch that intermittently supplies the control signal Csw12 [a] to [1b].

  The switch Sw14 [1e] in the switching circuit 95 [1c] is turned on / off (open / closed) by the switching control signal Csw14 [1], and the switching control signal Csw12 to the switching switch Sw12 [1c] of the switching circuit Sw12 [1] is switched. The switch Sw14 [1f] is switched on and off (open / closed) by an inverted signal of the switching control signal Csw14 [1] via the inverter circuit 97, and the switch Sw12 [1f] is switched on and off. This is a changeover switch that intermittently supplies the control signal Csw12 [b] to [1c].

  Similarly, the switching circuits 95 [2a], 95 [2b], and 95 [2c] have the inverter circuit 97 and the switches Sw14 [2a], Sw14 [2b], Sw14 [2c], Sw14 [2d], and Sw14 [2e]. ], Sw14 [2f], and is controlled by the switching control signal Csw14 [2]. The switching circuits 95 [3a],..., 95 [mc] have the same configuration, and are controlled by switching control signals Csw14 [3],.

  The system controller 13 sends a switching control signal Csw12 [a; on] or Csw12 [a; off], Csw12 [b; on] or Csw12 [b; off], Csw13 [a; on] or Csw13 [a; off], Csw13 [b; on] or Csw12 [b; off], Csw14 [1; on] or Csw14 [1; off],..., Csw14 [m; on] or Csw14 [m; off] to the data driver 16 Switch SW12 [1a] to Sw12 [1c] of the switch circuit Sw12 [1],..., Sw12 [ma] to Sw12 [mc] of the switch circuit Sw12 [m], Sw13 [ a], Sw13 [b], Sw14 [1a] to Sw14 [1f],..., Sw14 [ma] to Sw14 [mf] of the switch switching circuit 95 are switched on / off (open / close).

  The changeover control signals Csw12 [a; on], Csw13 [a; on], Csw14 [1; on] to Csw14 [m; on] are the changeover switches Sw12 [1a] to Sw12 [ma], Sw13 [a], Sw13 [b], Sw14 [1a] to Sw14 [mf] are turned on (closed), and switching control signals Csw12 [a; off], Csw13 [a; off], Csw14 [1; off] to Csw14 [m; off] turns off (opens) the changeover switches Sw12 [1a] to Sw12 [(m / 2) a], Sw13 [a], Sw13 [b], and Sw14 [1a] to Sw14 [mf]. ).

  The data line switching circuits Sw22 [1], Sw22 [2] to Sw22 [m / 2] are configured in the same manner as in the first embodiment. The current upstream ends of the changeover switches Sw22 [11] and Sw22 [12] of the data line switching circuit Sw22 [1] are connected to the data line Ld [1], and the current upstream ends of Sw22 [13] and Sw22 [14] are data Connected to line Ld [2]. The current downstream ends of changeover switches Sw22 [11] and Sw22 [14] are connected to contact N2 [1], and the current downstream ends of changeover switches Sw22 [12] and Sw22 [13] are connected to contact N2 [2]. Is done.

  The system controller 13 supplies the switching control signal Csw13 [a; on] to the switch circuit Sw13 of the current switching circuit 90 of the data driver 16, for example, during the vertical blanking period.

  The system controller 13 switches the switching control signals Csw12 [a] and Csw12 [b each time the gate driver 14 outputs the gate signals Sg [1] to Sg [n] to the gate lines Lg [1] to Lg [n]. Are supplied to the switch circuits Sw12 [1] to Sw12 [m] of the current switching circuit of the data driver 16.

  Further, the system controller 13 switches the switching control signals Csw14 [a],... Each time the gate driver 14 outputs the gate signals Sg [1] to Sg [n] to the gate lines Lg [1] to Lg [n]. .., Csw4 [m] are sequentially supplied to the switching circuits 95 [1a] to 95 [1c],..., 95 [ma] to 95 [mc] of the switch switching circuit 95.

  The system controller 13 switches the signal levels of the current control signals ISEL [3] and ISEL [4] every frame period, and supplies them to the data line switching circuits Sw22 [1] to Sw22 [m / 2].

Next, the operation of the light emitting device 10 according to the second embodiment will be described.
The light emitting device 10 according to the second embodiment operates according to the timing chart shown in FIG.

  In FIG. 16, times t40 to t41 and t50 to t51 are vertical baseline periods. Time t41 to t50 is the writing period T1, and time t51 to t60 is the writing period T2. The writing periods T1 and T2 are one frame period.

  The gate driver 14 sequentially outputs the gate signals Sg [1] to Sg [n] to the gate lines Lg [1] to Lg [n] at the times t41 to t50 and t51 to t60, and the pixel circuit 11 [ 1,1] to 11 [m, 1],..., 11 [1, n] to 11 [m, n] are selected.

  As shown in FIG. 16, the system controller 13 supplies L-level current selection signals ISEL [3] and ISEL [4] to the data driver 16 at times t40 to t41 and t50 to t51.

  The system controller 13 supplies the H level current selection signal ISEL [3] and the L level current selection signal ISEL [4] to the data driver 16 from time t41 to t50, and from time t51 to t60, the L level current selection signal ISEL [3]. The selection signal ISEL [3] and the H level current selection signal ISEL [4] are supplied to the data driver 16.

  First, when the current selection signals ISEL [3] and ISEL [4] become L level at time t40, as shown in FIG. 17, the selector switches Sw22 [11] to Sw22 [14] of the data line switching circuit Sw22 [1]. Is opened, and the data lines Ld [1] and Ld [2] are disconnected from the current generating circuits 71 [1] and 71 [2] and the auxiliary current generating circuit 72.

  The system controller 13 also switches the switching control signals Csw13 [a; on], Csw13 [b; off], Csw12 [a; off], Csw12 [b; off], Csw14 [1; off] to Csw14 [m; off. ] Is supplied to the data driver 16.

  Accordingly, the changeover switch Sw13 [b] of the switch circuit Sw13, the changeover switches Sw12 [1a] to Sw12 [1c],..., Sw12 [ma] of the switch circuits Sw12 [1],. ... Sw12 [mc] is opened, between the constant current source 63 and the current generation circuits 71 [1] to 71 [m], and the auxiliary current generation circuit 72 and the current generation circuits 71 [1] to 71 [m]. Is interrupted.

  The changeover switch Sw13 [a] is closed by the supply of the changeover control signal Csw13 [a; on], and the constant current source 63 and the auxiliary current generation circuit 72 are connected.

  For this reason, the reference current Iref is supplied from the constant current source 63 to the auxiliary current generating circuit 72 as indicated by an arrow in the figure.

  Next, when the gate driver 14 outputs the H level gate signal Sg [1] to the gate line Lg [1] at the start time t41 of the first frame shown in FIG. 16, the pixel circuit 11 [1 in the first row. , 1] to 11 [m, 1] are selected.

  When the system controller 13 supplies the current selection signal ISEL [3] at H level and the current selection signal ISEL [4] at L level to the data driver 16, as shown in FIG. 18A, the data line switching circuit Sw22 [ The changeover switches Sw22 [11] and Sw22 [13] of 1] are closed, and the changeover switches Sw22 [12] and Sw22 [14] are opened.

  Further, the system controller 13 supplies the switching control signals Csw13 [a; off], Csw13 [b; on], Csw12 [a; on], Csw12 [b; off], Csw14 [1; on] to the data driver 16. To do.

  Therefore, the changeover switch Sw13 [b] of the switch circuit Sw13, Sw12 [1a], Sw12 [1c] of the switch circuit Sw12 [1], the changeover switch Sw12 of the switch circuits Sw12 [2],..., Sw12 [m] [2b],..., Sw12 [mb] are closed, and the changeover switches Sw13 [a], Sw12 [2a], Sw12 [2c],..., Sw12 [ma], Sw12 [mc] are opened.

  When the changeover switch Sw12 [1a] is closed, the reference current Iref flows from the constant current source 63 to the current generation circuit 71 [1] as indicated by an arrow in the figure.

  When the changeover switches Sw22 [11], Sw12 [1c], Sw13 [b] are closed, a path from the data line Ld [1] to the auxiliary current generation circuit 72 through the contact N2 [1] is formed, and the auxiliary switch The current generation circuit 72 draws the gradation current Idata [1] from the pixel circuit 11 [1,1] via this path.

  For this reason, as shown in FIG. 18B, the gradation current Idata [1 generated by the auxiliary current generation circuit 72 is applied to the capacitor Cs of the pixel circuit 11 [1,1] in the first row and the first column. ] Is written (applied). The capacitor Cs of the pixel circuit 11 [1,1] holds this voltage as the gate voltage Vgs of the transistor T3. That is, in this case, the current generation circuit 71 [1] is replaced with the auxiliary current generation circuit 72.

  When the changeover switches Sw22 [13] and Sw12 [2b] are closed, a path from the data line Ld [2] to the current generation circuit 71 [2] through the contact N2 [2] is formed, and the current generation circuit 71 [2] draws the gradation current Idata [2] from the pixel circuit 11 [2,1] through this path.

  Therefore, as shown in FIG. 18B, the gradation current Idata [generated by the current generation circuit 71 [2] is applied to the capacitor Cs of the pixel circuit 11 [2,1] in the first row and the second column. 2] is written (applied). The capacitor Cs of the pixel circuit 11 [2,1] holds this voltage as the gate voltage Vgs of the transistor T3. Similarly, a path from the data lines Ld [3] to Ld [m] to the current generation circuits 71 [3] to 71 [m] through the contacts N2 [3] to N2 [m] is formed, and the third column The gradation currents Idata [3] to Idata generated by the current generation circuits 71 [3] to 71 [m] are applied to the capacitors Cs of the pixel circuits 11 [3,1] to 11 [m, 1] in the m-th column. The voltage corresponding to [m] is written.

  Next, at time t42 shown in FIG. 16, when the gate driver 14 outputs the H level gate signal Sg [2] to the gate line Lg [2], the pixel circuits 11 [1,2] to 11 [m] in the second row. , 2] is selected.

  The system controller 13 supplies the switching control signals Csw13 [a; off], Csw13 [b; on], Csw12 [a; off], Csw12 [b; on], and Csw14 [2; on] to the data driver 16.

  Therefore, as shown in FIG. 19A, the changeover switch Sw13 [b] of the switch circuit Sw13 and the changeover switches Sw12 [2a] and Sw12 [2c] of the switch circuit Sw12 [2] are closed, and the switch circuit Sw12 [1 ], Sw12 [3] ..., Sw12 [m] change-over switches Sw12 [1b], Sw12 [3b], ..., Sw12 [mb] are closed, and change-over switches Sw12 [1a], Sw12 [1c], ..., Sw12 [ma] and Sw12 [mc] open.

  When the changeover switch Sw12 [2a] is closed, the reference current Iref flows from the constant current source 63 to the current generation circuit 71 [2] as indicated by an arrow in the figure.

  When the changeover switch Sw12 [1b] is closed, a path is formed from the data line Ld [1] to the current generation circuit 71 [1] via the contact N2 [1]. The current generation circuit 71 [1] The gradation current Idata [1] is drawn from the pixel circuit 11 [1,2] through

  For this reason, as shown in FIG. 19B, the gradation current Idata [generated by the current generation circuit 71 [1] is applied to the capacitor Cs of the pixel circuit 11 [1,2] in the second row and first column. The voltage corresponding to 1] is written (applied). The capacitor Cs of the pixel circuit 11 [1,1] holds this voltage as the gate voltage Vgs of the transistor T3. Similarly, a path from the data lines Ld [3] to Ld [m] to the current generation circuits 71 [3] to 71 [m] through the contacts N2 [3] to N2 [m] is formed, and the third column The gradation currents Idata [3] to Idata generated by the current generation circuits 71 [3] to 71 [m] are applied to the capacitors Cs of the pixel circuits 11 [3,1] to 11 [m, 1] in the m-th column. The voltage corresponding to [m] is written.

  When the changeover switches Sw13 [b] and Sw12 [2c] are closed, a path from the data line Ld [2] to the auxiliary current generating circuit 72 through the contact N2 [2] is formed, and the auxiliary current generating circuit is formed. 72 draws the gradation current Idata [2] from the pixel circuit 11 [2,2] through this path.

  For this reason, as shown in FIG. 19B, the gradation current Idata [2] generated by the auxiliary current generation circuit 72 is applied to the capacitor Cs of the pixel circuit 11 [2,2] in the second row and second column. A voltage corresponding to is written (applied). The capacitor Cs of the pixel circuit 11 [2,2] holds this voltage as the gate voltage Vgs of the transistor T3. That is, in this case, the current generation circuit 71 [2] is replaced with the auxiliary current generation circuit 72.

  In this way, at the times t41 to t50, the capacitors Cs of the pixel circuits 11 [1,1] to 11 [m, n] in each row have the grayscale currents Idata [1], Idata [2],. , Idata [m−1], Idata [m] are written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  Next, when the system controller 13 supplies the current selection signals ISEL [3] and ISEL [4] of L level to the data driver 16 at time t50, as shown in FIG. 20, the switching of the data line switching circuit Sw22 [1] is performed. The switches Sw22 [11] to Sw22 [14] are opened, and the data lines Ld [1] and Ld [2] are disconnected from the current generation circuits 71 [1] and 71 [2] and the auxiliary current generation circuit 72. The

  The system controller 13 outputs switching control signals Csw13 [a; on], Csw13 [b; off], Csw12 [a; off], Csw12 [b; off], Csw14 [1; off] to Csw14 [m; off]. The data driver 16 is supplied.

  Accordingly, the changeover switch Sw13 [b] of the switch circuit Sw13, the changeover switches Sw12 [1a] to Sw12 [1c], ..., Sw12 [ma] of the switch circuits Sw12 [1],. ... Sw12 [mc] is opened, between the constant current source 63 and the current generation circuits 71 [1] to 71 [m], and the auxiliary current generation circuit 72 and the current generation circuits 71 [1] to 71 [m]. Is interrupted.

  The changeover switch Sw13 [a] is closed by the supply of the changeover control signal Csw13 [a; on], and the constant current source 63 and the auxiliary current generation circuit 72 are connected.

  For this reason, the reference current Iref is supplied from the constant current source 63 to the auxiliary current generating circuit 72 as indicated by an arrow in the figure.

  Next, when the gate driver 14 outputs an H level gate signal Sg [1] to the gate line Lg [1] at the start time t51 of the second frame shown in FIG. 16, the pixel circuit 11 [1 in the first row. , 1] to 11 [m, 1] are selected.

  When the system controller 13 supplies the current selection signal ISEL [3] of L level and the current selection signal ISEL [4] of H level to the data driver 16, as shown in FIG. 21A, the data line switching circuit Sw22 [ The changeover switches Sw22 [11] and Sw22 [13] of 1] are opened, and the changeover switches Sw22 [12] and Sw22 [14] are closed.

  Similarly to time t41, the system controller 13 receives the switching control signals Csw13 [a; off], Csw13 [b; on], Csw12 [a; on], Csw12 [b; off], and Csw14 [1; on]. The data driver 16 is supplied.

  Therefore, the changeover switch Sw13 [b] of the switch circuit Sw13, Sw12 [1a], Sw12 [1c] of the switch circuit Sw12 [1], the changeover switch Sw12 of the switch circuits Sw12 [2],..., Sw12 [m] [2b],..., Sw12 [mb] are closed, and the changeover switches Sw13 [1a], Sw12 [2a], Sw12 [2c],..., Sw12 [ma], Sw12 [mc] are opened.

  For this reason, the reference current Iref flows from the constant current source 63 to the current generation circuit 71 [1] as indicated by an arrow in the figure.

  When the changeover switches Sw22 [12] and Sw12 [2b] are closed, a path from the data line Ld [1] to the current generation circuit 71 [2] through the contact N2 [2] is formed, and the current generation circuit 71 [2] ] Draws the gradation current Idata [2] from the pixel circuit 11 [1,1] through this path.

  For this reason, as shown in FIG. 21B, the gradation current Idata [generated by the current generation circuit 71 [2] is applied to the capacitor Cs of the pixel circuit 11 [1,1] in the first row and the first column. 2] is written (applied). The capacitor Cs of the pixel circuit 11 [1,1] holds this voltage as the gate voltage Vgs of the transistor T3. Similarly, a path from the data line Ld [3] to the current generation circuit 71 [4] through the contact N2 [4] is formed, and the capacitor Cs of the pixel circuit 11 [3,1] in the third column includes A voltage corresponding to the gradation current Idata [3] generated by the current generation circuit 71 [4] is written, and a path from the data line Ld [4] to the current generation circuit 71 [3] via the contact N2 [3]. The voltage corresponding to the gradation current Idata [4] generated by the current generation circuit 71 [3] is written into the capacitor Cs of the pixel circuit 11 [4,1] in the fourth column. The same applies to the data lines Ld [5] to Ld [m].

  Further, when the changeover switches Sw22 [14], Sw12 [2c], Sw13 [b] are closed, a path is formed from the data line Ld [2] to the auxiliary current generating circuit 72 via the contact N2 [1]. The auxiliary current generation circuit 72 draws the gradation current Idata [1] from the pixel circuit 11 [2,1] through this path.

  For this reason, as shown in FIG. 21B, the gradation current Idata [1] generated by the auxiliary current generation circuit 72 is applied to the capacitor Cs of the pixel circuit 11 [2,1] in the first row and the second column. A voltage corresponding to is written (applied). The capacitor Cs of the pixel circuit 11 [2,1] holds this voltage as the gate voltage Vgs of the transistor T3. That is, in this case, the current generation circuit 71 [1] is replaced with the auxiliary current generation circuit 72.

  Next, at time t52 shown in FIG. 16, when the gate driver 14 outputs an H level gate signal Sg [2] to the gate line Lg [2], the pixel circuits 11 [1,2] to 11 [m] in the second row. , 2] is selected.

  Similarly to the time t42, the system controller 13 receives the switching control signals Csw13 [a; off], Csw13 [b; on], Csw12 [a; off], Csw12 [b; on], and Csw14 [2; off] as a data driver. 16 is supplied.

  Therefore, as shown in FIG. 22A, the changeover switch Sw13 [b] of the switch circuit Sw13 and Sw12 [2a] and Sw12 [2c] of the switch circuit Sw12 [2] are closed, and the switch circuit Sw12 [1], Sw12 [3] ..., Sw12 [m] changeover switches Sw12 [1b], Sw12 [3b], ..., Sw12 [mb] are closed, and changeover switches Sw12 [1a], Sw12 [1c], ... • Sw12 [ma] and Sw12 [mc] are opened.

  When the changeover switch Sw12 [2a] is closed, the reference current Iref flows from the constant current source 63 to the current generation circuit 71 [2] as indicated by an arrow in the figure.

  When the changeover switch Sw12 [1b] is closed, a path from the data line Ld [2] to the current generation circuit 71 [1] through the contact N2 [1] is formed, and the current generation circuit 71 [1] The gradation current Idata [1] is drawn from the pixel circuit 11 [2,2] via

  For this reason, as shown in FIG. 22B, the gradation current Idata [generated by the current generation circuit 71 [1] is applied to the capacitor Cs of the pixel circuit 11 [2,2] in the second row and second column. The voltage corresponding to 1] is written (applied). The capacitor Cs of the pixel circuit 11 [2,2] holds this voltage as the gate voltage Vgs of the transistor T3. Similarly, a path from the data line Ld [3] to the current generation circuit 71 [4] through the contact N2 [4] is formed, and the capacitor Cs of the pixel circuit 11 [3,1] in the third column includes A voltage corresponding to the gradation current Idata [3] generated by the current generation circuit 71 [4] is written, and a path from the data line Ld [4] to the current generation circuit 71 [3] via the contact N2 [3]. The voltage corresponding to the gradation current Idata [4] generated by the current generation circuit 71 [3] is written into the capacitor Cs of the pixel circuit 11 [4,1] in the fourth column. The same applies to the data lines Ld [5] to Ld [m].

  When the changeover switches Sw13 [b] and Sw12 [2c] are closed, a path from the data line Ld [1] to the auxiliary current generating circuit 72 through the contact N2 [2] is formed, and the auxiliary current generating circuit is formed. 72 draws the gradation current Idata [2] from the pixel circuit 11 [2,2] through this path.

  Therefore, as shown in FIG. 22B, the gradation current Idata [2 generated by the auxiliary current generation circuit 72 is applied to the capacitor Cs of the pixel circuit 11 [1,2] in the second row and first column. ] Is written (applied). The capacitor Cs of the pixel circuit 11 [1,2] holds this voltage as the gate voltage Vgs of the transistor T3. That is, in this case, the current generation circuit 71 [2] is replaced with the auxiliary current generation circuit 72.

  In this way, at the times t51 to t60, the capacitors Cs of the pixel circuits 11 [1,1] to 11 [m, n] in the respective rows have the gradation currents Idata [2], Idata [1],. , Idata [m], Idata [m−1] are written, and this voltage is held as the gate voltage Vgs of the transistor T3.

  FIG. 23 shows a current generation circuit 71 for writing gradation currents Idata [1] to Idata [4] in each pixel circuit 11 [i, j] (i = 1 to 4, j = 1 to 4) in this embodiment. The correspondence relationship between [1] to 71 [4] and the auxiliary current generation circuit 72 is shown. FIG. 23A shows the case of the first frame, and FIG. 23B shows the case of the second frame.

  As shown in FIGS. 23A and 23B, in each frame, the auxiliary current generation circuit 72 is connected to one pixel circuit in each row, and the pixel circuit to which the auxiliary current generation circuit 72 is connected is in each row. Changes to. In the first frame, as shown in FIG. 23A, the pixel circuit to which the auxiliary current generating circuit 72 is connected in each row is sequentially changed for each column. Then, as shown in FIG. 23B, in the second frame, the current generation circuits 71 [1] and 71 [2] and the auxiliary current generation circuit 72 corresponding to the first and second columns are interchanged. The current generation circuits 71 [3] and 71 [4] and the auxiliary current generation circuit 72 corresponding to the fourth and fourth columns are switched, and the pixel circuit to which the auxiliary current generation circuit 72 is connected in the second frame is one frame. It is different from the eyes. For this reason, even if the characteristics of the current generation circuits 71 [1] to 71 [m] are not uniform, it is difficult to visually recognize luminance unevenness.

  As described above, according to the present embodiment, the auxiliary current generation circuit 72 and the m current generation circuits 71 [1] to 71 [m] are provided, and the current generation circuit 71 [ 1] to 71 [m] are switched between columns every frame period, and the auxiliary current generation circuit 72 is used by replacing any one of the current generation circuits 71 [1] to 71 [m] for each row and The current generation circuits 71 [1] to 71 [m] that are different for each frame period are replaced.

  Therefore, it is possible to suppress the luminance unevenness due to the variation in the current value of the current generation circuit from being visually recognized.

In carrying out the present invention, various forms are conceivable and the present invention is not limited to the above embodiment.
For example, the current generation circuits 64 [1a], 64 [1b],..., 64 [ma], 64 [mb] according to the first embodiment, and the current generation circuits 71 [1] to 71 [m] according to the second embodiment. ], The auxiliary current generation circuit 72 is not limited to the configuration shown in FIG. 7, but may be of the circuit configuration shown in FIG. 24 disclosed in Japanese Patent Laid-Open No. 2003-195812, for example. .

  As shown in FIG. 24A, this current generation circuit uses, for example, display data d [1] (˜d [m]) as 3 bits, 1-bit D / I converters 81 [0], 81 [ 1] and 81 [2].

  The 1-bit D / I converters 81 [0] to 81 [2] respectively convert the bit values of the bits bit [0] to bit [3] of the display data d [1] into the gradation current Ibit [ 0] to Ibit [2].

  The reference currents Iref [0], Iref [1], and Iref [2] are reference currents having different current values corresponding to the bits bit [0] to bit [3], respectively.

  As shown in FIG. 24B, the 1-bit D / I conversion unit 81 [0] includes a transistor T31, a capacitor C21, and switches Sw13 [1] to Sw13 [3].

  When the signal MSW becomes H level, voltage components corresponding to the respective reference currents Iref [0], Iref [1], Iref [2] are held in the capacitor C21.

  The switch Sw [1] is controlled in accordance with the bit value of the bit bit [0] of the display data, and the corresponding reference current is selected. Then, the sum of the selected reference currents is output as the gradation current Ibit [0].

  In the first embodiment described above, two data lines are switched. However, the number of data lines to be switched is not limited to two. Further, the current generation circuit also has two current generation circuits 64 [1a], 64 [1b],..., 64 [ma] for one data line Ld [i] (i = 1 to m). ] And [mb]. However, the current generation circuit may be switched between three or more current generation circuits for one data line.

  DESCRIPTION OF SYMBOLS 10 ... Light-emitting device, 11 ... Organic EL panel, 13 ... System controller, 14 ... Gate (select) driver, 15 ... Anode (source) drive circuit, 16 ... Data driver, 64 [1a], 64 [1b],..., 64 [ma], 64 [mb]... Current generation circuit, Sw11... Reference current switching circuit, 65 and 90. [1] to Sw22 [m / 2] ... data line switching circuit, 71 [1] to 71 [m] ... current generation circuit, 72 ... auxiliary current generation circuit, 90 ... current switching Circuit

Claims (11)

An optical element controlled according to a supplied current, and a plurality of pixels arranged in a matrix, according to driving data via a plurality of data lines connected to each pixel in each column A pixel driving device that supplies the gradation current to drive the plurality of pixels for each frame period ,
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuit groups, each of which includes a plurality of current generation circuits that generate the gradation current, provided corresponding to each of the plurality of contacts;
A current switching circuit that switches connection between each of the contacts and any of the plurality of current generation circuits of the current generation circuit group corresponding to the contact;
A data line switching circuit for switching the connection between each contact and each data line;
Equipped with a,
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The plurality of current generation circuit groups include a first current generation circuit group and a second current generation circuit group,
Each of the first current generation circuit group and the second current generation circuit group includes a first current generation circuit and a second current generation circuit,
In each frame period, the data line switching circuit connects the first data line to the first contact and the second contact to the second contact in the first selection period in each selection period. And the second data line is connected to the first contact and the first data line is connected to the second contact in a second selection period following the first selection period. Connect
The current switching circuit connects the first current generation circuit of the first current generation circuit group to the first contact in the first frame period in each frame period, and connects the first contact to the second contact. The first current generation circuit of the second current generation circuit group is connected, and in the second frame period subsequent to the first frame period, the first contact point of the first current generation circuit group is connected to the first contact point. said second current generating circuit pixel driving device according to claim connected to an Rukoto said second current generating circuit of the second current generating circuits to said second contact to connect. A current source for supplying a reference current;
Each of the current generation circuits is supplied with the reference current and generates a gradation current based on a voltage holding unit that holds a voltage component corresponding to the reference current and a voltage component held in the voltage holding unit A current generator,
A reference current switching circuit for sequentially switching the supply of the reference current from the current source to each of the current generation circuits and supplying the reference current to each of the plurality of current generation circuits within the one frame period; The pixel driving apparatus according to claim 1 . An optical element controlled in accordance with a supplied current, and in accordance with drive data via a plurality of data lines provided in a plurality of pixels arranged in rows and columns connected to the respective pixels. A pixel driving device that supplies the gradation current to drive the plurality of pixels for each frame period ,
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuits which are provided corresponding to each of the plurality of contacts and generate the gradation current;
An auxiliary current generation circuit for generating the gradation current;
The auxiliary current generator circuit is replaced with the one specific current generation circuit of the plurality of current generation circuits, the and the contacts, the specific current generation circuit and the plurality of current generation count Michi及 beauty the auxiliary excluding a current switching circuit connects the current generating circuit, and switching the specific current generation circuit to one of said plurality of current generation circuits,
A data line switching circuit for switching the previous SL connection between each contact and the respective data lines,
Equipped with a,
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The data line switching circuit connects the first data line to the first contact and connects the second data line to the second contact in the first frame period of each frame period. , In a second frame period following the first frame period, connecting the second data line to the first contact and connecting the first data line to the second contact;
Said current switching circuit, wherein in each frame period for each of the selection period, the specific current generation circuit, a pixel driving for the switching Rukoto wherein sequentially different the current generation circuit in the plurality of current generation circuits apparatus. A current source for supplying a reference current;
Each of the current generation circuits and the auxiliary current generation circuit is supplied with the reference current and holds a voltage component corresponding to the reference current, and the voltage holding unit holds the voltage component based on the voltage component held by the voltage holding unit. A current generation unit for generating a gradation current,
The current switching circuit is connected to the voltage holding unit of either one of the current generation circuit or the auxiliary current generation circuit that is not connected to each of the contacts for each period in which the selection circuit selects the pixels of the rows. The pixel driving apparatus according to claim 3 , wherein switching is performed so as to supply the reference current. The pixel driving device according to claim 4 , wherein the current switching circuit performs switching so as to supply the reference current to the voltage holding unit of the auxiliary current generation circuit during a vertical blanking period. A light-emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines connected to the respective pixels for each column;
A pixel driving device that supplies gradation currents according to driving data to the plurality of data lines to drive the plurality of pixels for each frame period ;
With
The pixel driving device includes:
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuit groups, each of which includes a plurality of current generation circuits that generate the gradation current, provided corresponding to each of the plurality of contacts;
A current switching circuit that switches connection between each of the contacts and any of the plurality of current generation circuits of the current generation circuit group corresponding to the contact;
A data line switching circuit for switching the connection between each contact and each data line;
With
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The plurality of current generation circuit groups include a first current generation circuit group and a second current generation circuit group,
Each of the first current generation circuit group and the second current generation circuit group includes a first current generation circuit and a second current generation circuit,
In each frame period, the data line switching circuit connects the first data line to the first contact and the second contact to the second contact in the first selection period in each selection period. And the second data line is connected to the first contact and the first data line is connected to the second contact in a second selection period following the first selection period. Connect
The current switching circuit connects the first current generation circuit of the first current generation circuit group to the first contact in the first frame period in each frame period, and connects the first contact to the second contact. The first current generation circuit of the second current generation circuit group is connected, and in the second frame period subsequent to the first frame period, the first contact point of the first current generation circuit group is connected to the first contact point. the light emitting device characterized that you connect said second current generating circuit of the second current generating circuits by connecting the second current generation circuit to the second contact. A light-emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines connected to the respective pixels for each column;
A pixel driving device that supplies gradation currents according to driving data to the plurality of data lines to drive the plurality of pixels for each frame period ;
With
The pixel driving device includes:
A selection circuit that sequentially selects the pixels arranged in each row for each selection period;
A plurality of contacts equal in number to the plurality of data lines;
A plurality of current generation circuits which are provided corresponding to each of the plurality of contacts and generate the gradation current;
An auxiliary current generation circuit for generating the gradation current;
Said auxiliary current generator circuit is replaced with the one specific current generation circuit of the plurality of current generation circuits, the and the contacts, the plurality of current generation circuits and the auxiliary current except for the specific current generation circuit generates A current switching circuit that connects the specific current generation circuit to any one of the plurality of current generation circuits ,
A data line switching circuit for switching the previous SL connection between each contact and the respective data lines,
Equipped with a,
The plurality of contacts include a first contact and a second contact adjacent to each other,
The plurality of data lines include a first data line and a second data line adjacent to each other,
The data line switching circuit connects the first data line to the first contact and connects the second data line to the second contact in the first frame period of each frame period. , In a second frame period following the first frame period, connecting the second data line to the first contact and connecting the first data line to the second contact;
Said current switching circuit, in each of frame periods, in each of the selection period, the specific current generation circuit, a light emitting device for switching Rukoto wherein sequentially different the current generation circuit in the plurality of current generation circuits . The pixel driving device has a current source for supplying a reference current,
Each of the current generation circuits is supplied with the reference current and generates a gradation current based on a voltage holding unit that holds a voltage component corresponding to the reference current and a voltage component held in the voltage holding unit A current generator,
The current switching circuit is connected to the voltage holding unit of either one of the current generation circuit or the auxiliary current generation circuit that is not connected to each of the contacts for each period in which the selection circuit selects the pixels of the rows. The light emitting device according to claim 7 , wherein the light emitting device is switched to supply the reference current. An electronic apparatus comprising the light emitting device according to any one of claims 6 to 8 . A light emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines provided connected to the respective pixels for each column. A driving control method of a light emitting device having a pixel driving device that supplies gradation currents according to driving data to the plurality of data lines and drives the plurality of pixels for each frame period ,
The pixel driving device includes a plurality of current generation circuit groups each including a plurality of current generation circuits that generate the gray-scale current, and are provided corresponding to each of a plurality of contacts having the same number as the plurality of data lines. The plurality of contacts include a first contact and a second contact adjacent to each other, and the plurality of data lines include a first data line and a second data line adjacent to each other. And the plurality of current generation circuit groups include a first current generation circuit group and a second current generation circuit group, and the first current generation circuit group and the second current generation circuit group include: , Each having a first current generation circuit and a second current generation circuit,
In each frame period, between the first selection period in each selection period for selecting each pixel of each row of the light emitting panel, the first contact to the first and connect the data line and the second Connecting the second data line to a contact, and connecting the second data line to the first contact and the second contact in a second selection period following the first selection period. A data line switching step for switching the connection between each contact and each data line so as to connect the first data line;
Wherein between the first frame period in each frame period, the first said the contact of the first current generation circuit group of said first current generating circuit connected to said second current to said second contact The first current generation circuit of the generation circuit group is connected, and the second current of the first current generation circuit group is connected to the first contact in a second frame period subsequent to the first frame period. connect the generating circuit the second current generation circuit of the second current generating circuits to said second contact to connect said second current generating circuit, each current generation with the respective contacts A current switching step for switching the connection with the circuit;
A drive control method for a light-emitting device, comprising: A light emitting panel having a plurality of pixels arranged in a matrix with optical elements controlled in accordance with a supplied current, and a plurality of data lines provided connected to the respective pixels for each column. A driving control method of a light emitting device having a pixel driving device that supplies gradation currents according to driving data to the plurality of data lines and drives the plurality of pixels for each frame period ,
The pixel driving device includes a plurality of current generation circuits that generate the gray-scale current, and an auxiliary current generation that generates the gray-scale current, which is provided corresponding to each of a plurality of contacts equal to the plurality of data lines. A plurality of contacts, a first contact adjacent to each other, and a second contact; and the plurality of data lines include a first data line adjacent to each other; Two data lines,
For each selection period for selecting each pixel in each row of the light emitting panel in each frame period , the auxiliary current generation circuit is replaced with one specific current generation circuit among the plurality of current generation circuits, The plurality of current generation circuits excluding the specific current generation circuit and the auxiliary current generation circuit are connected to a contact, and the specific current generation circuit is connected to each other in the plurality of current generation circuits for each selection period. A current switching step for sequentially switching to different current generation circuits ;
In the first frame period in each frame period, the first connecting the first data line to the contact connecting the second data line to the second contact, the first frame period in the second frame period following the first as by connecting the second data line to the contact connecting the first data line to said second contact, said the previous SL each contact each A data line switching step for switching the connection with the data line;
A drive control method for a light-emitting device, comprising:

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