JP5381668B2 - Encoding device and decoding device - Google Patents

Description

  The present invention relates to an encoding apparatus and a decoding apparatus, and more particularly to an encoding apparatus that compresses and encodes an image signal and a decoding apparatus that decodes an encoded signal that has been compression encoded.

  In recent years, with the advent of digital high-definition broadcasts and HD (High Definition) compatible video cameras and higher image quality of digital cameras, televisions used at home have become larger and higher in image quality. The demand for a screen size (1920 pixels in the horizontal direction and 1080 pixels in the vertical direction) has increased.

  On the other hand, digital image signals displayed on a TV with an HD size screen as described above are subjected to image processing such as enhancer and frame rate conversion processing. In the image processing, data of one frame or more is received. It must be stored in an external memory such as a dynamic random access memory (DRAM). However, the external memory is expensive, and there are cases where multiple large-capacity external memories are required to store many frames of HD-size image data, increasing the product cost and increasing the number of parts on the board. It becomes a factor of.

  For this reason, the amount of HD-size image data is reduced as much as possible using an image compression technique. As this image compression technique, the MPEG (Moving Picture Experts Group) method is known. In this MPEG system, high-efficiency coding with a high image compression rate is performed by predicting motion compensation in units of macroblocks (16 pixels in the horizontal direction and 16 pixels in the vertical direction) and performing variable-length coding. Realized. However, since this MPEG system has a complicated algorithm, when an image processing circuit is made into a large scale semiconductor integrated circuit (LSI: Large Scale Integration), the MPEG system encoding circuit occupies a large area. Therefore, it is not suitable for a signal processing LSI specialized in high-quality image processing or an inexpensive image processing LSI.

  Therefore, as an encoding method, an encoding method that can easily compress an input image, such as bit compression (for example, converting an 8-bit signal into a 4-bit signal) using a difference from the previous value for the input image is used. May be used in signal processing LSIs specialized in high-quality image processing and inexpensive image processing LSIs.

  On the other hand, image signal processing requires internal processing that involves the use of a frame memory, such as IP conversion for converting an interlace signal into a progressive signal, three-dimensional reduction processing (3DNR: Digital Noise Reduction), and double speed processing. Many of them exist, and a plurality of frames are often stored in an external memory such as a DRAM. For image signal processing, even if the external input is 8 bits, it is common to calculate by increasing the number of bits to 10 bits or the like.

  As for the on-screen display (OSD), basically, the image signal of the main screen is subjected to signal processing for improving the image quality, and then the image signal and the OSD signal are mixed or one of the signals. It is displayed by replacing with.

  There are various types of image signal processing depending on the purpose as described above. In the case of double speed processing or the like, an intermediate frame may be generated using only the upper 8 bits even when the internal signal is 10 bits. In this case, a process of returning to 10 bits by adding the lower 2 bits of the original frame to the lower 8 bits of the upper 8 bits of the intermediate frame generated from the upper 8 bits of the original frame may be performed.

  As for the OSD image, if an image signal on which the OSD image is superimposed is a target of the double speed process, the intermediate frame generated by the double speed process also includes the OSD image. In this case, the OSD image included in the intermediate frame may be unnaturally shaken or emphasized around the OSD image due to erroneous detection of motion vectors or enhancement processing. There is also a method of storing only the OSD image separately from the image signal of the main screen by using compression in consideration of block division and pixel continuity (see, for example, Patent Document 1). However, when performing real-time display, it is not necessary to save only the OSD image. Therefore, the OSD image is inserted so as to be multiplexed with the image signal of the main screen immediately before display.

Japanese Patent Laid-Open No. 9-275563

  The encoding apparatus that employs the encoding method that can easily compress the input image described above, which reduces the number of bits by differential encoding or the like, does not include information on whether or not the OSD is superimposed.

  On the other hand, recent liquid crystal panels are increasing in number corresponding to 10 bits, but for some image signal processing such as double speed processing, 8 bits processing is sufficient. In this case, as in the invention described in Patent Document 1, the lower 2 bits are stored in a frame memory or the like, and the lower 2 bits stored in the lower order of the main screen image or the created intermediate frame image after processing. There is a case where processing such as returning to 10 bits is performed by adding.

  When performing such processing, the 100% OSD screen adds the lower bit of the original frame (main image signal) to the lower bit (2 bits in the above example) of the OSD signal by the above process. When the number of bits is restored, a problem in display occurs such that the OSD screen by the OSD signal restored to the original number of bits appears to sway according to the main screen due to the added lower bits.

  The present invention has been made in view of the above points, and it is an object of the present invention to provide an encoding device and a decoding device that can prevent an OSD signal from erroneously adding lower bits of a main screen signal. .

  In order to achieve the above object, an encoding apparatus according to the present invention includes encoding means for generating first encoded data obtained by encoding a difference value of at least two consecutive pixels of an image signal, On-screen display flag generation means for generating an on-screen display flag indicating whether or not on-screen display information is superimposed in the horizontal direction, and the on-screen display flag is sampled at a sampling interval for each predetermined pixel and the number of bits R is turned on. Sampling means for generating screen display information, the number of bits included in the plurality of first encoded data, and a predetermined number of bits r of the number of bits R of the on-screen display information generated by the sampling means (R is a natural number smaller than R) Bit (N is larger than r natural numbers) and having an output means for outputting the second encoded data in the encoded data block.

  In order to achieve the above object, the decoding apparatus of the present invention samples an on-screen display flag indicating whether or not on-screen display information is superimposed in the horizontal direction of an image signal at a sampling interval for each predetermined pixel. Number of bits N consisting of r bits (r is a natural number smaller than R) in the obtained on-screen display information of R bits and the number of bits included in the plurality of first encoded data. Second encoded data of bits (N is a natural number greater than r) is input in units of encoded blocks, and a plurality of first encoded data in the encoded data block and on-screen display information are separated. Separating and extracting means for extracting, and sequentially decoding a plurality of first encoded data separated and extracted by the separating and extracting means, Decoding means for outputting decoded data is No. characterized in that it has an on-screen display flag decoding means for decoding the on screen display flag from the on-screen display information separated extracted by the separation extraction unit.

  In order to achieve the above object, the decoding apparatus according to the present invention includes a plurality of pieces of first encoded data constituting the second encoded data, each of which has an image signal whose quantization bit number is A bits. When it consists of pixels, the number of high-order bits of the quantization bit number A bits, q bits (q is a natural number smaller than A and N) is divided into blocks every M (M is a natural number of 2 or more). The difference value between the uncoded data that is the first pixel of each divided block and the previous pixel for (M−1) pixels after the uncoded data is The encoded data is composed of a plurality of pieces of data each having a quantization bit number p bits (p <q), and the number of lower bits (Aq) bits (q is A , A natural number smaller than N) And when the on-screen display flag output from the on-screen display flag means does not indicate superposition of the on-screen display information, the number of higher-order bits of the quantization bit number A bits output from the decoding means An image signal composed of each pixel of the number of bits (A−q) of the lower order bits of the image signal read from the storage means is added to the lower order of the decoded data composed of q bits of each pixel. When the on-screen display flag output from the on-screen display flag means indicates the superimposition of the on-screen display information when the multiplexing means for generating the image signal composed of the A-bit pixels and the on-screen display flag means, The higher order bit number q bits The lower the data, and having a bit addition means for adding a predetermined value of the number of bits (A chromatography q) bits.

  According to the present invention, the encoding device embeds the OSD flag in the encoded data block, and the decoding device adds the lower-bit image signal only to the image signal not including the OSD signal based on the OSD flag. Thus, it is possible to return to the original image signal of the number of quantization bits, and to prevent erroneous addition of the lower bits of the image signal to the OSD signal.

It is a block diagram of one embodiment of an encoding device of the present invention. It is a figure explaining sampling of an OSD flag and an OSD flag. It is a figure which shows an example screen image with an OSD screen in a main screen. It is a block diagram of one Embodiment of the encoder in FIG. It is explanatory drawing of an example of the encoding data block produced | generated by the encoding apparatus of FIG. 2 is a timing chart for explaining the operation of FIG. 1. It is a block diagram of carrying of one implementation of the decoding apparatus of this invention. It is a block diagram of one Embodiment of the decoder in FIG. 8 is a timing chart for explaining the operation of FIG. It is a block diagram of one Example of the decoding apparatus of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a block diagram of an embodiment of an encoding apparatus according to the present invention. As shown in the figure, the encoding apparatus 100 of the present embodiment includes an encoding module 101a for a luminance signal Y, an encoding module 101b for a color difference signal U, an encoding module 101c for a color difference signal V, and a comparison. The device 110 is configured. It is assumed that the luminance signal Y and the color difference signals U and V, which are input image data of the encoding device 100, are in 4: 4: 4 format with the same resolution.

  Each of the encoding modules 101a, 101b, and 101c has the same configuration, and includes a block division flag generation and on-screen display (OSD) flag sampling units 102a, 102b, and 102c, encoders 103a, 103b, and 103c, a delay unit 104a, 104b and 104c, and coding block and on-screen display (OSD) flag generation units 105a, 105b, and 105c. The block division flag generation and OSD flag sampling units 102a to 102c and the encoders 103a to 103c constitute an encoding unit, and the encoding block and OSD flag generation units 105a to 105c constitute an output unit.

  The block division flag generation and OSD flag sampling unit 102a receives a YUV discrimination signal, an image signal (in this case, a luminance signal Y), and an on-screen display (OSD) flag from the comparator 110. The block division flag generation and OSD flag sampling unit 102b receives the YUV discrimination signal, the image signal (here, the color difference signal U), and the OSD flag from the comparator 110. The block division flag generation and OSD flag sampling unit 102c receives the YUV discrimination signal, the image signal (here, the color difference signal V), and the OSD flag from the comparator 110. As described above, the encoding modules 101a, 101b, and 101c have the same configuration except for the types of input image signals. Therefore, in the following description, the encoding module 101a will be described as a representative for convenience. However, the encoding modules 101b and 101c perform the same processing as the encoding module 101a.

  The comparator 110 compares the luminance signal of the on-screen display (OSD) signal indicating the on-screen display (OSD) information with the set value (Talfa) as a threshold value. A signal “0” is generated as an on-screen display (OSD) flag indicating whether or not OSD information is superimposed in the horizontal direction of the image signal. The set value (Talfa) is a value that determines the mixing ratio of the OSD signal and the image signal not including the OSD signal. FIG. 2A shows an example of the OSD flag. The OSD flag shown in FIG. 2A changes from “0” to “1” from a certain pixel. For example, when the OSD screen 302 exists in the main screen 301 shown in FIG. A part of one line in which the OSD screen exists on the right side of the screen indicates one encoded data block section (to be described later).

  The block division flag generation and OSD flag sampling unit 102a inputs an upper bit number q bits (here, q = 8) of the luminance signal Y having the quantization bit number A bits (here, A = 10). The luminance signal Y is divided into encoded block units each consisting of M pixels (M is a natural number equal to or greater than 2) and output to the encoder 103a. Note that (Aq) bits (here, Aq = 2), which is the number of remaining lower bits, are stored in an external memory (storage means).

  In addition, the block division flag generation and OSD flag sampling unit 102a outputs “first_word” having a logical value “1” for identifying the first pixel (first data) of each block to the encoder 103a. . Note that each pixel of data to be encoded (first encoded data) other than the top data is output to the encoder 103a together with “first_word” having a logical value “0”.

  Further, the block division flag generation and OSD flag sampling unit 102a samples the OSD flag from the comparator 110 at the sampling interval f pixels to generate the encoded OSD flag shown in FIG. Output to. FIG. 2B shows a pixel to be encoded (input luminance signal Y). The above-mentioned sampling interval f pixel is the number of bits in the encoded data (second encoded data) block of N bits (N is a natural number of 2 or more), which will be described later, and r bits (r is a natural number smaller than N). It is assumed that the sampled OSD flag is embedded.

  Here, the OSD information indicating whether or not the OSD signal is superimposed includes an OSD flag encoded with R bits. The 2-bit YUV discrimination signal is obtained by dividing the R bit into three for three signals of the luminance signal Y and the color difference signals U and V, and the encoded data block of the luminance signal and the encoded data of the color difference signals U and V. It is a signal for selecting which encoded data block to embed in the block. As an example, when R = 6, as shown in FIG. 2D, for example, in the encoded data block of the luminance signal, the 0th bit (LSB: Least Significant Bit) and 1 of 6-bit OSD information are included. The lower 2 bits of the bit are embedded, 2 bits of the 2nd and 3rd bits of the 6-bit OSD information are embedded in the encoded data block of the color difference signal U, and 6 bits are embedded in the encoded data block of the color difference signal V. The upper 2 bits of the fourth and fifth bits (MSB: Most Significant Bit) of the OSD information of the bits are embedded.

  The encoder 103a is configured, for example, as shown in the block diagram of FIG. The encoder 103 a is an encoding device that performs bit compression using a difference from the previous value for an input image, and includes a subtractor 401, a local decoding circuit 402, a quantization unit 403, and a selector 404. . The local decoding circuit 402 includes an inverse quantization unit 411, an adder 412, a selector 413, and a buffer 414.

  Next, the operation of the encoder 103a will be described. First, in the subtracter 401, the encoder 103a generates a difference value obtained by subtracting a local decoded signal obtained by local decoding in the local decoding circuit 402 from an input pixel signal (in this case, a luminance signal) in units of pixels. Therefore, this difference value is a difference value between the input pixel signal and the local decoded signal of the pixel signal input immediately before.

  Next, the encoder 103 a quantizes the difference value from the subtractor 401 in the quantization unit 403, supplies the obtained quantized signal to the local decoding circuit 402, performs local decoding, and supplies it to the selector 404. To do. In the local decoding circuit 402, the inverse quantization unit 411 performs inverse quantization on the quantized signal output from the quantization unit 403, and generates a difference value before quantization. Subsequently, the local decoding circuit 402 adds the signal from the buffer 414 and the difference value from the inverse quantization unit 411 in the adder 412, and converts the local decoded signal of the previous input pixel signal into pixel units. Get in.

  When the first pixel signal that is the first data of the input pixel signal is input to the subtractor 401, the selector 413 has the logical value of “first_word” indicating the first data described above as “1”, and the first data at that time Select as is. Further, when the pixel signal after the head data is input, the logical value of “first_word” indicating the head data is “0”, so that the signal from the buffer 414 and the difference value from the inverse quantization unit 411 are added in the adder 412. A locally decoded signal obtained by adding is selected. The buffer 414 sequentially accumulates the head data selected by the selector 413 and the local decoded signal input subsequently thereto, and then supplies the accumulated data to the subtracter 401 and the adder 412.

  When the first pixel signal, which is the first data, is input to the subtractor 401, the selector 404 receives the “first_word” having the logical value “1” at the same time. Output to. The selector 404 receives the “first_word” of the logical value “0” at the same time when the pixel signal after the first data is input, and therefore selects and encodes the quantized signal output from the quantization unit 403. Output as data (first encoded data) to the outside. Then, one encoded data (second encoded data) block is constituted by the head data and a predetermined number of encoded data subsequent thereto.

  Accordingly, when viewed in one encoded data block, the leading data is not quantized, that is, not encoded, but the other encoded data is the difference value between the two pixel signals that are subsequently input. Is a quantized signal obtained by quantizing the signal, that is, an encoded signal.

  In this encoder 103a, the encoding process itself is encoded using a difference value from the previous value, but the leading data is not encoded, so that the data recovery time at the time of decoding is shortened. Output as is. For this reason, the head data of the encoded data block is the same as the number of bits of the input data, but the subsequent encoded data is quantized by quantization so that the number of bits is smaller than the number of bits of the input data. In this way, the encoder 103a sequentially generates one non-encoded head data and (M−1) pieces of encoded data (M is a natural number of 2 or more) as an encoded block and an OSD flag. To the unit 105a.

  Returning to FIG. The delay unit 104a delays the time required for the encoding process of the encoder 103a, the encoding OSD flag from the block division flag generation and OSD flag sampling unit 102a, and outputs the encoded data block output from the encoder 103a. Is output to the coding block and OSD flag generation unit 105a.

  The encoded block and OSD flag generation unit 105a is not encoded as described above, as schematically shown in FIGS. 5A and 5B, the head data and encoded data supplied from the encoder 103a. A coded data block that is block-formed every N bits, including head data (pixels), second and subsequent (M-1) coded data (pixels), and r bits for OSD information transmission. The r bits in each N-bit encoded data block are embedded with r bits of the OSD information obtained by sampling the OSD flag supplied from the delay unit 104a. As described above, whether to embed the OSD information for r bits (R> r) of the RD bits of the entire OSD information in one encoded data block is selected by the YUV discrimination signal.

  As shown in FIG. 5A, the head data (pixel) of the encoded data block is not encoded as described above and remains the same q bits as the input, but the second and subsequent (M−1) ) Pieces of encoded data (pixels) are compressed to p bits (p <q) by encoding. The number N of bits of the encoded data block is preferably a power of 2 in consideration of storage in an external memory such as DRAM or DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory). For this reason, the total number of bits of M pixels including one head data and (M−1) encoded data is configured to be a power of 2, but it is not necessarily a power of 2. There are not too many bits. The extra bits (r bits) are used for transmitting r bits of the OSD information as described above. For example, assuming that the number of bits N of the encoded data block is “256”, q = 8, p = 6, and M−1 = 41, r is 2 (= 256−8−6 × 41) bits.

  In this way, the encoding module 101a has the clock shown in FIG. 6A, the YUV discrimination signal shown in FIG. 6B, the OSD flag shown in FIG. The received enable signal and the image signal (luminance signal Y) shown in FIG. 5E are received as inputs, and the encoded data block shown in FIG. 5F and the strobe signal shown in FIG. To do. The encoding module 101a takes in an image signal when the enable signal (not shown in FIG. 1) is at a high level. The strobe signal is a signal for the next stage circuit (not shown) to capture the encoded data block when it is at a high level.

  As described above, according to the encoding apparatus 100 of the present embodiment, the OSD flag indicating whether the OSD signal is superimposed on the image signal of the main screen is obtained by sampling for each f pixel of the encoding target pixel. Since the encoded signal is output in units of the encoded data block by being included (embedded) in the encoded data block as the R-bit OSD information, the encoded data block is decoded in the decoding apparatus described later In this case, it is possible to grasp for each f pixel from which position the OSD signal is superimposed by the OSD flag.

  Next, the decoding apparatus according to the present invention will be described.

  FIG. 7 shows a block diagram of an embodiment of a decoding apparatus according to the present invention. As shown in the figure, the decoding apparatus 200 according to the present embodiment includes a decoding module 201a for the luminance signal Y, a decoding module 201b for the color difference signal U, a decoding module 201c for the color difference signal V, and an on-state. A screen display (OSD) decoding circuit 206 is configured.

  Decoding modules 201a, 201b and 201c are respectively divided into bit division and on-screen display (OSD) flags extraction units 202a, 202b and 202c, decoders 203a, 203b and 203c, delay units 204a, 204b and 204c, output circuit 205a, 205b and 205c. The decoding module 201a receives the encoded data block of the luminance signal Y generated by the encoding module 101a shown in FIG. 1 and the strobe signal (strb) as inputs, and decodes the luminance signal Y and the data The enable signal and the OSD flag_Y of the luminance signal Y are output.

  The decoding module 201b receives the encoded data block of the color difference signal U generated by the encoding module 101b shown in FIG. 1 and the strobe signal (strb) as inputs, and receives the decoded data of the color difference signal U and The data enable signal and the OSD flag_U of the color difference signal U are output. Further, the decoding module 201c receives the encoded data block of the color difference signal V generated by the encoding module 101c shown in FIG. 1 and the strobe signal (strb) as inputs, and receives the decoded data of the color difference signal V and The data enable signal and the OSD flag _V of the color difference signal V are output.

  As described above, the decoding modules 201a, 201b, and 201c have the same configuration except for the signal types of the input encoded data blocks. Therefore, in the following description, the decoding module 201a will be described as a representative for convenience. It shall be.

  The bit division and OSD flag extraction unit 202a schematically shows a plurality of pieces of data (the first data having the number of uncoded bits of q bits and the number of encoded bits of r bits shown in FIG. 5A). 1B) and an N-bit encoded data (second encoded data) block of a luminance signal composed of an OSD flag having a bit number of r bits, as schematically shown in FIG. Is input in units of encoded data blocks, and the encoded data blocks are captured and bit-divided during the high level period of the strobe signal that becomes high level every T clocks (T is the number of pixels included in the encoded data block). I do.

  This bit division is a process of dividing into even-numbered encoded data (pixels) and odd-numbered encoded data (pixels) in order to decode in two phases. . The head data (pixels) in the encoded data block is not encoded as described above, but is divided as even-numbered encoded data (pixels). The second and subsequent encoded data arranged after the head data are alternately divided in the order of odd-numbered encoded data (pixels) and even-numbered encoded data (pixels).

  The bit division and OSD flag extraction unit 202a also outputs a flag “first_word” indicating whether or not the divided data is the top data. The flag “first_word” indicates the first data when the logical value is “1”. Further, the bit division and OSD flag extraction unit 202a extracts and outputs the OSD flag embedded in the last r bits (r = 2 in the above example) in the encoded data block.

  The decoder 203a decodes the encoded data output by the bit division and output from the bit division and OSD flag extraction unit 202a. FIG. 8 shows a block diagram of an embodiment of decoder 203a. In FIG. 8, among the divided data of the encoded data block, the head data is input to the input terminal 1 of the selector 53, and the even-numbered encoded data (pixel) is input to the inverse quantization unit 501a. The odd-numbered encoded data (pixels) is input to the inverse quantization unit 501b.

  The inverse quantization units 501a and 501b perform inverse quantization on the input encoded data (pixel), and decode the difference value that is the input signal of the quantization unit 403 in the encoder 103a illustrated in FIG. To do. The selector 503 selects the leading data input when the logical value of the flag “first_word” is “1”, outputs the selected data to the outside as even-numbered decoded data, and supplies the data to the adder 504. And used as the previous value of the next odd-numbered encoded data.

  Here, the decoded difference value is a difference value between the odd-numbered or even-numbered data and the even-numbered or odd-numbered data input to the encoder 103a one clock before the data. . Therefore, the odd-numbered or even-numbered data is decoded by adding the leading data or decoded data of the data input to the encoding unit one clock before the even-numbered or odd-numbered clock as the previous value and the above difference value. Can be

  Paying attention to the above points, the adder 502 is the decoded difference value of the even-numbered encoded data input from the inverse quantization unit 501a and the previous previous value input from the buffer 505. The even-numbered decoded data is generated by adding the odd-numbered decoded data.

  The selector 503 selects the decoded data from the adder 502 based on the flag “first_word” set to the logical value “0” during the input period other than the top data, and outputs it as the even-numbered decoded data as it is. , And supplied to the adder 504 as a previous value. The adder 504 decodes the odd-numbered encoded data input from the inverse quantization unit 501b and the even-numbered decoded data that is the previous previous value input from the selector 503. Are added to generate odd-numbered decoded data, which are output to the outside and supplied to the buffer 505 to be held as the next previous value.

  As described above, according to the decoder 503a illustrated in FIG. 8, the even-numbered difference value obtained by decoding the even-numbered encoded data from the inverse quantization unit 501a is converted into the previous one from the buffer 505. The odd-numbered decoded data and the adder 502 add the odd-numbered differential data obtained by decoding the odd-numbered encoded data at the same time as obtaining the even-numbered decoded data having the quantization bit number q bits. Are added to the previous even-numbered decoded data from the selector 503 in the adder 504, whereby odd-numbered decoded data having a quantization bit number q bits can be obtained.

  Returning again to FIG. The delay unit 204a delays the time required for the decoding process by the decoder 203a, the OSD flag from the bit division and OSD flag extraction unit 202a, and adjusts the time with the decoded data output from the decoder 203a. To output to the output circuit 205a.

  The output circuit 205a synchronizes the even-numbered decoded data and the odd-numbered decoded data supplied from the decoder 203a and the OSD flag whose number of bits supplied from the delay unit 204a is r bits with the clock. Output in parallel. The output circuit 205a generates and outputs a data enable signal (a flag indicating that the output data is valid).

  The OSD decoding circuit 206 combines the OSD flag_Y output from the decoding module 201a, the OSD flag_U output from the decoding module 201b, and the OSD flag_V output from the decoding module 201c. By decoding the OSD information of 3r bits (6 bits in the above example), the 1-bit OSD flag sampled every f pixels as shown in FIG. 2 is decoded and output.

  The OSD flag is supplied to an image selection circuit that selects either the main screen image signal obtained from the decoded data or the OSD signal on which the OSD information is superimposed, and is also stored in an external memory. Is supplied to the lower-order bit selection circuit for selecting one of the lower-order bit image signals of the predetermined number of bits and the lower-order bits of the signal selected by the image selection circuit by selecting one of the predetermined number of bits 0 .

  In this way, the decoding module 201a receives the clock shown in FIG. 9A, the encoded data block shown in FIG. 9B, and the strobe signal shown in FIG. The OSD flag shown in FIG. 4D, the data enable signal shown in FIG. 4G, and the decoded data shown in FIG.

  As described above, according to the decoding apparatus 200 of the present embodiment, the OSD flag indicating whether the OSD signal is superimposed on the image signal of the main screen is sampled and encoded for each f pixel of the encoding target pixel. It is possible to output the decoded data from the encoded data block included (embedded) in the encoded data block and to know for each f pixel from which position the OSD signal is superimposed by the decoded OSD flag. It becomes. As a result, the image signal of the main screen of the lower (Aq) bits is added to the image signal of the main screen obtained from the decoded data having the quantization bit number of A bits, and the main screen of the quantization bit number of A bits is added. When returning to the image signal, it is possible to prevent the image signal of the lower (Aq) bit main screen from being erroneously added to the OSD signal. As a result, according to the present embodiment, 100% OSD screen is prevented from causing display defects such as appearing to swing in accordance with the main screen by the image signal of the added (Aq) bit main screen. can do.

  FIG. 10 shows a block diagram of an embodiment of a decoding apparatus according to the present invention. In the figure, a decoding apparatus 600 includes an external memory 601, buffers 603a, 603b and 603c, decoding modules 604a, 604b and 604c, an OSD decoding circuit 605, image signal selection circuits 606a, 606b and 606c, and a lower bit selection circuit 607a. , 607b and 607c. The image signal selection circuits 606a to 606c and the lower bit selection circuits 607a to 607c constitute multiplexing means and bit addition means.

  The external memory 601 includes a luminance signal Y storage area 602a, a color difference signal U storage area 602b, and a color difference signal V storage area 602c. In the storage area 602a, the lower 2-bit storage area 701a in which the lower-order 2-bit image data of the luminance signal image data for the main screen having the quantization bit number of 10 bits is stored, and the encoding module 101a shown in FIG. A frame 0 storage area 702a in which the generated encoded data block group of frame 0 is stored, and an encoded data block group of frame 1 which is the next frame of frame 0 generated by the encoding module 101a shown in FIG. Are stored in a frame 1 storage area 703a and a selection unit 704a that selects one of the encoded data block groups of frame 0 and frame 1. Similar to the storage area 601a, the lower two-bit storage areas 701b and 701c, the frame 0 storage areas 702b and 702c, the frame 1 storage areas 703b and 703c, and the selection units 704b and 704c are formed in the storage areas 602b and 602c. Yes.

  In each of the storage areas 702a to 702c and 703a to 703c, the upper 8-bit image data of the main screen image data having 10-bit quantization bits of the luminance signal Y, the color difference signal U, and the color difference signal V are shown in FIG. As shown in FIG. 5B, the encoded data block schematically shown in FIG. 5A is obtained by compression encoding by the encoding modules 101a to 101c shown in FIG. 1 frame is multiplexed and stored.

  In FIG. 10, the decoding modules 604a, 604b, and 604c have the same configuration as the decoding modules 201a, 201b, and 201c in the decoding apparatus 200 shown in FIG. The OSD decoding circuit 605 has the same configuration as the OSD decoding circuit 206 shown in FIG. The image signal selection circuits 606a, 606b, and 606c each have a luminance signal OSD_Y having an 8-bit quantization bit number of OSD information input to the terminal 1 when the value of the OSD flag from the OSD decoding circuit 605 is “1”. When the color difference signal OSD_U and the color difference signal OSD_V are selected and the value of the OSD flag is “0”, the decoded data having the quantization bit number of 8 bits from the decoding modules 604a, 604b, and 604c input to the terminal 0 is obtained. select. If the decoded data is two-phase, it is output in parallel with two phases.

  Further, when the value of the OSD flag from the OSD decoding circuit 605 is “1”, the lower bit selection circuits 607a, 607b, and 607c output the 2-bit value “00” input to the terminal 1 and the value of the OSD flag When “0” is “0”, the luminance signal Y, the color difference signal U, and the color difference signal V corresponding to the lower 2 bits from the buffers 603a, 603b, and 603c input to the terminal 0 are selected.

  According to the decoding apparatus 600 configured as described above, when performing double speed processing on image data of a main screen having a quantization bit rate of 10 bits, frames generated as an original frame and an intermediate frame for frame memory capacity reduction and memory performance Is stored as an encoded data block in which the 10 bits of the upper 8 bits of quantization bits are compression-encoded to 6 bits except the leading data by the encoding modules 101a to 101c shown in FIG. They are stored in areas 702a to 702c and 703a to 703c.

  The selectors 704a, 704b, and 704c perform one of the encoded data block of frame 0 from the storage areas 702a to 702c and the encoded data block of frame 1 from the storage areas 703a to 703c when performing the above double speed processing. Is supplied to the decryption modules 604a, 604b, and 604c, respectively. The encoding modules 604a, 604b, and 604c perform the same decoding operation as the decoding module 201a described with reference to FIG. 7 on the input encoded data block.

  The OSD decoding circuit 605 decodes the OSD flag by performing the same decoding operation as the OSD decoding circuit 206 of FIG. 7 on the OSD flag decoded and output by the decoding modules 604a, 604b, and 604c. The flags are supplied as selection control signals to the image signal selection circuits 606a to 606c and the lower bit selection circuits 607a to 607c, respectively.

  As a result, when the OSD flag has a value “0” indicating that the decoded data is the main screen, the image signal selection circuits 606a to 606c have 8 quantization bits output from the decoding modules 604a to 604c, respectively. Selects bit-decoded data. In parallel with this, the lower bit selection circuits 607a to 607c select the lower 2 bits main screen image data stored in advance in the lower 2 bit storage areas 701a to 701c supplied through the buffers 603a to 603c. .

  As a result, when double speed processing is performed, the low-order bit selection circuits 607a to 607c convert the low-order bit number of the decoded data having 8-bit quantization bits output from the image signal selection circuits 606a to 606c to 2 bits. The selected lower 2 bits of image data are added, returned to the original image data of the main screen with 10 bits of quantization bits, and output.

  When the OSD flag output from the OSD decoding circuit 605 is “1” indicating that the OSD information is superimposed, the image signal selection circuits 606a, 606b, and 606c are OSD signals having a quantization bit number of 8 bits. Select OSD_Y, OSD_U, OSD_V. In parallel with this, the lower bit selection circuits 607a to 607c select a 2-bit fixed value “00”.

  As a result, in the case of OSD information, “00” is added to the lower 2 bits of the OSD signal, which is decoded data composed of each pixel of 8 bits of quantization bits output from the image signal selection circuits 606a to 606c. As a signal having a quantization bit number of 10 bits. Therefore, when the OSD information becomes 100%, it is possible to prevent the OSD image information from being displayed with noise synchronized with the image signal of the main screen. Note that the bit added to the lower 2 bits in the case of OSD information is not “00” but may be a predetermined fixed value.

  The present invention is not limited to the above embodiment. For example, the decoding apparatus is not limited to a configuration that outputs two-phase decoded data, and outputs one-phase decoded data. Alternatively, decoded data of three or more phases may be output.

100 Encoder 101a, 101b, 101c Encoding module 102a, 102b, 102c Block division flag generation and on-screen display (OSD) sampling unit 103a, 103b, 103c Encoder 104a, 104b, 104c, 204a, 204b, 204c Delay 105a, 105b, 105c Coding block and on-screen display (OSD) flag generator 110 Comparator 200, 600 Decoding device 201a, 201b, 201c, 604a, 604b, 604c Decoding module 202a, 202b, 202c Bit division and On-screen display (OSD) flag extraction unit 203a, 203b, 203c Decoder 205a, 205b, 205c Output circuit 206, 605 OSD Decoding circuit 403 Quantization unit 402 Local decoding circuit 404, 413, 503 Selector 501a, 501b Inverse quantization unit 505, 603a, 603b, 603c Buffer 601 External memory 602a, 602b, 602c Storage area 606a, 606b, 606c Image signal selection circuit 607a, 607b, 607c Lower bit selection circuit 701a, 701b, 701c Lower 2 bit storage area 702a, 702b, 702c Frame 0 storage area 703a, 703b, 703c Frame 1 storage area 704a, 704b, 704c selection unit

Claims (3)

Encoding means for generating first encoded data obtained by encoding the difference value for every two consecutive pixels of the image signal;
On-screen display flag generating means for generating an on-screen display flag indicating whether or not on-screen display information is superimposed in the horizontal direction of the image signal;
Sampling means for sampling the on-screen display flag at a sampling interval for each predetermined pixel to generate on-screen display information having a bit number of R bits;
A predetermined number of bits r of the number of bits included in the plurality of first encoded data and the number of bits R of the on-screen display information generated by the sampling means (r is smaller than R) Output means for outputting second encoded data of N bits (N is a natural number greater than r) consisting of a natural number) in units of encoded data blocks. The number of bits r in the R-bit on-screen display information obtained by sampling the on-screen display flag indicating whether or not the on-screen display information is superimposed in the horizontal direction of the image signal at a sampling interval for each predetermined pixel. Second encoded data having N bits (N is a natural number greater than r) of bits (r is a natural number smaller than R) and the number of bits included in the plurality of first encoded data is Separation and extraction means that is input in units of coding blocks and separates and extracts the plurality of first coded data and the on-screen display information in the coded data block;
Decoding means for sequentially decoding the plurality of first encoded data separated and extracted by the separation and extraction means and outputting decoded data that is the image signal;
An on-screen display flag decoding unit that decodes the on-screen display flag from the on-screen display information separated and extracted by the separation and extraction unit. The plurality of first encoded data constituting the second encoded data may include, when the image signal is composed of pixels each having a quantization bit number of A bits, The number of high-order bits, q bits (q is a natural number smaller than A and N), is divided into M blocks (M is a natural number of 2 or more), and one pixel at the head of each divided block And the non-encoded data and (M-1) pixels after the non-encoded data are encoded with the difference value between the previous pixel and the quantization bit number p bits. (P <q) and a plurality of data,
Storage means for preliminarily storing bit numbers (Aq) bits (q is a natural number smaller than A and N) of the lower-order bits of the image signal having the quantization bit number A bits;
When the on-screen display flag output from the on-screen display flag means does not indicate superposition of the on-screen display information, an upper bit of the quantization bit number A bits output from the decoding means An image signal consisting of each pixel of the number of bits (Aq) bits of the lower order bits of the image signal read from the storage means is added to the lower order of the decoded data consisting of each pixel of q bits. A multiplexing means for generating the image signal composed of each pixel having a total number of bits of A bits;
When the on-screen display flag output from the on-screen display flag means indicates the superposition of the on-screen display information, from each pixel of the upper bit number q bits of the quantization bit number q bits The decoding apparatus according to claim 2 , further comprising: a bit adding unit that adds a predetermined value of the number of bits (Aq) bits to the lower order of the decoded data.

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