JP5366159B2 - Semiconductor device and microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow the number of data items constituting an emulation writing unit (data group) in EEPROM emulation to be freely set not using a common value (fixed value) among data groups. <P>SOLUTION: In the present invention, when a first data item is written to a flash memory 4, a first additional bit for identifying the first data item is written. When a second data item is written to the flash memory 4, a second additional bit for identifying the second data item, which is different from the first additional bit, is written. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a flash memory, a memory control circuit, a microcomputer, and a memory control method, and more particularly to a flash memory, a memory control circuit, a microcomputer, and a memory control method that execute data writing and reading using additional bits.

  2. Description of the Related Art In recent years, a semiconductor device including both a flash memory and an EEPROM (Electrically Erasable Programmable Read Only Memory) has been used. Even in the same nonvolatile memory, flash memory and EEPROM have different characteristics such as data erasing unit, number of rewrites, circuit area, and the like.

  In order to write data to the flash memory or the EEPROM, new data cannot be written unless the data stored in the memory cells that are storage elements constituting the flash memory or the EEPROM is erased. The unit for erasing is different between the flash memory and the EEPROM. The flash memory is erased in units of blocks, while the EEPROM is erased in units selectable by word lines and bit lines. (Hereinafter, this unit is referred to as a minimum writing unit.) For this reason, the flash memory that is restricted to erasing in units of blocks is limited in its use with respect to EEPROM.

  Further, the number of rewriting (erasing) is different between the flash memory and the EEPROM. For example, in a memory mounted on a microcomputer, a flash memory is guaranteed a rewrite count of about 100 to 1000 times, whereas an EEPROM is guaranteed a rewrite count of about 10,000 to 100,000 times.

  Thus, from the viewpoint of the erase unit and the number of rewrites (erase), the EEPROM is considered to be technically superior to the flash memory, but the circuit configuration for enabling the erase in the minimum write unit, A device structure that can withstand the influence of a high electric field applied at the time of erasing is required to guarantee a rewrite frequency of 10 to 1000 times that of a flash memory, resulting in an increase in circuit scale. Since an increase in circuit scale leads to an increase in manufacturing cost, from this point of view, it can be said that a flash memory is more advantageous than an EEPROM.

  Therefore, both the flash memory and the EEPROM are mounted on the semiconductor device, and a large amount of data needs to be stored, but the flash memory is used for data that needs to be rewritten less frequently and is stored. For data that has a small amount of data but needs to be rewritten frequently, an EEPROM is used, and the data is used properly so as to take advantage of both the flash memory and the EEPROM.

  However, the manufacturing process of a semiconductor device having both of a plurality of types of memories having different structures as described above is a mixed mounting process, which is much larger than the manufacturing process of a semiconductor device having only one of the memories. Process steps must be added, which increases manufacturing costs.

  In view of this, a technique has been devised that avoids a mixed process by using only a flash memory as a non-volatile memory and using a part of the flash memory like an EEPROM instead. A technique of using such a flash memory as if it is an EEPROM is generally called EEPROM emulation.

  EEPROM emulation makes full use of an area that is not yet used in the storage area in the flash memory, that is, an empty (blank) area in which no data is written, and blocks are used after all areas have been used. This is a technique for reducing the number of times of erasure attached at the time of data update, and as a result, increasing the apparent number of times of rewriting as in the case of EEPROM.

  In FIG. 11, (a) data A stored in the EEPROM is rewritten (updated) to data A ′, and (b) data A stored in the flash memory is rewritten to data A ′ using EEPROM emulation. Indicates (updating) case.

  When data A is rewritten to data A ′, data A is usually overwritten on data A ′. However, since the flash memory and the EEPROM cannot be written unless they are erased, specifically, the charge is extracted from the floating gates of all the memory cells existing in the block unit or the minimum write unit ( Rewriting is performed by injecting (writing) a charge into a floating gate of an arbitrary memory cell based on write data.

  Since the erase unit of the EEPROM is the minimum write unit, the data A to be rewritten is erased as shown in FIG. Rewriting in EEPROM is completed.

  On the other hand, the rewrite unit of the flash memory is a block unit. Therefore, when data A, B, and C are written in one block as shown in FIG. If the entire block is erased, the data B and C are also erased at the same time. Therefore, the data B and C are temporarily saved in another area, and the data A ′, B and C are rewritten to the data A ′ in the flash memory by erasing the data in blocks and then writing the data A ′, B and C. To complete.

  However, in the EEPROM emulation, if there is an unused (blank) area where data A 'can be written in the block as shown in FIG. 11B, the data A' is written in the blank area. Since the data A and A 'coexist, the data A is invalidated by a predetermined method, assuming that the data A is already invalidated data.

  In this way, if EEPROM emulation is used, erasing in units of blocks can be made unnecessary as long as there is a blank area for writing new data, and other data (data in FIG. (Equivalent to B, C)) can be avoided. In other words, since the number of times of rewriting (erasing) can be reduced, the apparent number of times of rewriting can be increased as in the case of EEPROM, and data can be rewritten without considering protection for other data as in the case of EEPROM. To.

  Next, EEPROM emulation will be described in detail with reference to FIGS.

  FIG. 12 shows a data writing unit (hereinafter referred to as an emulation writing unit) in the conventional EEPROM emulation.

  The data included in the emulation write unit is composed of n + 1 DATA_0 to DATA_n and a data number (ID) which is the name of the n + 1 DATA group (that is, the ID is associated with a plurality of DATA). Data). However, the ID value must be a value other than the erased state, that is, the value read from the unused area. The number (n) of DATA included in each data group must be the same (common) for each ID, and cannot be different. For example, if the number of DATA included in the data group 0 assigned with the identification number ID = 0 is 5, the number of DATA included in the data group 1 assigned the identification number ID = 1 is also 5. There must be. A plurality of data constituting the emulation writing unit are collectively referred to as a data group.

  FIG. 13 shows an operation flowchart showing a writing process at the time of conventional EEPROM emulation. FIGS. 14, 15 and 16 show flash memories in which data group 0 to data group 2 are stored. The flash memory shown in FIGS. 14, 15 and 16 is composed of one block (that is, the erase unit is the entire flash memory) and has a minimum write unit area (address) from address 0000H to address FFFFH. The size of data that can be stored is 8 bits (00H to FFH). Data group 0 to data group 2 are written at addresses 0000H to 0011H, and each of the written data group 0 to data group 2 is DATA_0 to DATA_4 and ID (ID = 0 to 2). It is configured. If the erase state of the flash memory in FIG. 17 is FFH, as described above, the ID must be different from the value read from the data area in the erase state. 00H to FEH. Also, as shown in FIG. 12, a data area is a place where DATA and ID are stored.

  The writing process at the time of EEPROM emulation will be described together with a specific example of the process of writing the data group 1 with reference to FIGS. 13, 14, 15, and 16. As shown in FIG. 13, in the writing process, blank search steps (S13-1 to S13-4) for specifying an area in which new data is to be written, and DATA_0 to ID are sequentially written in the specified blank area. This is performed in two stages of processes (S13-5 to S13-6).

  (S13-1) Data is read in the search direction starting from the FFFFH address, which is the final address of the flash memory, and starting from FFFFH address → FFFEH address → FFFFDH address →... → 0001H address → 0000H address. That is, the reading process is performed from the blank area side of the flash memory in FIG.

  (S13-2) It is determined whether or not the read value is a value other than FFH (FFH is a value indicating an erased state (unused state)). When a value other than FFH is read, the process proceeds to S13-4. On the other hand, when FFH is read, the process proceeds to S13-3.

  (S13-3) Decrement the address of the read destination by +1 (the search direction is the direction from the last address to the start address, so the address of the read destination is incremented by -1 address, and so on). Do. In FIG. 14, the addresses FFFFH to 0012H are unused (blank) areas, and thus the processes of S13-2 and S13-3 are repeated up to address 0012H.

  (S13-4) In S13-2, when a value other than FFH is read, the address read immediately before the address from which the value other than FFH is read is set to the head address of the blank area (writing starts. Specified address). When data other than FFH is read, the boundary between the used area and the unused (blank) area can be specified, so that the address at which FFH is read last is the head address of the blank area. Judgment can be made.

  In FIG. 14, since ID = 2 (value other than FFH) is read at address 0011H, it is determined that address 0011H is the last address (boundary) of the use area, and address 0012H, which is the address read immediately before, is determined. It can be determined that it is the head address of the blank area. It should be noted that the values that can be taken by the ID are 00H to FEH. However, if the ID value is FFH, it cannot be distinguished from the blank area, so FFH as the ID value is prohibited. Is.

  (S13-5) Data (DATA_0 to DATA_n) is written. Writing is performed in the order of DATA_0 → DATA_1 →... → DATA_n. In FIG. 15, DATA_0 to DATA_4 of data group 0 are written.

  (S13-6) ID is written. Since ID writing is performed at the end of the emulation writing unit, a series of writing processing of a data group having a plurality of data is completed upon completion of ID writing.

  In FIG. 16, the writing of ID = 1 in the data group 0 is completed, and the writing of the data group 1 composed of DATA_0 to DATA_4 and ID = 1 is completed.

  The writing process at the time of conventional EEPROM emulation is performed by such steps, and when a new data group is written thereafter, the additional writing process is performed by the same steps. In FIG. 16, a new data group is written from address 0018H.

  In FIG. 14, there are already written data group 0 to data group 2. However, when there is no written data group, data is written from address 0000H. As a result of the blank search, if there is no blank area in which all data included in the data group to be written is not written, erasing is necessary. In this case, erasing while protecting the necessary data as described above. Need to do.

  Subsequently, a read operation during conventional EEPROM emulation will be described.

  FIG. 17 is an operation flowchart showing a conventional reading process. As shown in FIG. 17, in the read process, ID search steps (S17-1 to S17) for specifying a read target data group by searching for IDs associated with a plurality of DATA included in the read target data group. -6) and a process of reading the specified read target data group from the flash memory (S17-7).

  As a specific example, a case will be described in which data groups 0 and 1 are read from the flash memory of FIG. However, in the flash memory of FIG. 16, since the data group 1 is written (updated) for the second time, the last written data group 1 (addresses 0012H to 0017H) is an effective data group. Yes, previously written data group 1 (addresses 0006H to 000BH) is treated as an invalid data group.

(S17-1) Start from the FFFFH address which is the last address of the flash memory, and the FFFFH address → FFFEH address → FFFFH address →... → 0001H address → 0000H
Data is read in the address search direction. That is, the reading process is performed from the blank area side of the flash memory of FIG. This is the same as S13-1 of the writing process described above.

  (S17-2) It is determined whether or not the read value is a value other than FFH (value indicating the erased state). When a value other than FFH is read, the process proceeds to S17-4. On the other hand, when FFH is read, the process proceeds to S17-3.

  (S17-3) The read destination address is decremented by +1 and read again. In FIG. 16, the addresses FFFFH to 0018H are unused (blank) areas, so the processes of S17-2 and S17-3 are repeated up to address 0018H.

  (S17-4) When a value other than FFH is read in S17-2, whether or not the read value is an ID (target ID) associated with DATA of the read target data group. Determine.

  In FIG. 16, when the data group to be read is data group 0, if the read value is ID = 0, it can be determined that the target ID is the target ID. In S17-2, a value other than FFH is detected at address 0017H, and the value stored at address 0017H is ID = 1. Therefore, since the data group to be read is the data group 0, it can be determined that the read value is not the target ID. On the other hand, assuming that the data group to be read is data group 1, since the data stored at address 0017H is ID = 1, it can be determined that the read value is the target ID.

  (S17-5) If the read value is not the target ID, the read process is performed again for the address decremented by +6 from the read address. Then, the determination in S17-4 is performed on the value read again.

  In FIG. 16, when the data group to be read is data group 0, the address decremented by +6 from address 0017H becomes address 0011H, and the value read from this address 0011 is ID = 2. It is not (ID = 0). Therefore, the read address is decremented by +6 again.

  (S17-6) If the value read in S17-4 is the target ID, the address decremented by +5 from the address from which the target ID is read is the head address of the read target data group. Identify.

  In FIG. 16, when reading the data group 0, it can be determined in S17-4 that the target ID is stored at the address 0005H, so the address 0000H decremented by +5 from the address 0005H is set as the read target data group. Specify the first address. When data group 1 is read, it can be determined in S17-4 that the target ID is stored at address 0017H. Therefore, address 0012H decremented by +5 from address 0017H is read as the first address of the data group to be read. To be identified.

  (S17-7) DATA_0 is read from the head address of the read target data group specified in S17-6, and DATA_1 to DATA_n are read while sequentially incrementing the address by +1. In FIG. 16, the reading of data group 0 is completed by reading DATA_0 to DATA_4 from addresses 0000H to 0004H. Further, the reading of data group 1 is completed by reading DATA_0 to DATA_4 from addresses 0012H to 0016H.

  In the flash memory of FIG. 16, the data group 1 has been updated, and the data related to the data group 1 is stored in two locations in the flash memory, but the valid data group is the last written one, that is, a blank. The one closer to the region side. In the method described in S17-1 to S17-6, the ID is searched from the blank area side, and when the read value becomes the same as the target ID, the search of the data group to be read is terminated. Even if a plurality of data groups having the same ID are stored in the memory, the newest data group, that is, an effective data group can be read out appropriately.

  In the example of the reading process in which the data group to be read in FIG. 16 is the data group 1, the valid data group 1 (address 0012H to address 0017H) is selected without selecting the invalid data group 1 (address 0006H to 000BH). Is selected.

  In the write processing flow and the read processing flow of FIGS. 13 and 17, it has been described that the direction of blank search and ID search is performed from the address FFFFH (final address), but conversely, it may be performed from address 0000H (start address). Good. However, in that case, in the write processing flow, the address incremented by +1 to the address where the value other than FFH was read last becomes the start address of the unused (blank) area, and in the read processing flow, In this method, only the ID is read by incrementing the address of the reading destination by +6, and when the read value becomes FFH, the ID is read back in order from the ID read immediately before, and the target ID is searched. Can be specified.

  Further, Non-Patent Document 1 describes a technique related to such EEPROM emulation. In Non-Patent Document 1, the emulation write unit is composed of data number, data 1, delimiter, and data 2, and FFH (erased state) is prohibited as the data number. The data number is stored in the flash memory every 4 bytes. The latest data is searched by reading the data number while incrementing every 4 bytes from the beginning of the block. If multiple data numbers with the same number are found, the data near the end of the data is updated to the latest data. It is described that it is handled as.

“Application Note U17057JJ3V0AN00”, 3rd edition, NEC Electronics Corporation, November 2004, p. 25-27

  As described above, the data group written using EEPROM emulation is read out by searching for the data number (ID) associated with each emulation writing unit (data group), and the retrieved ID is read target data. This is done by determining whether or not the ID is the same. At this time, the ID cannot be searched unless the ID stored in the data written in the flash memory is known. Therefore, conventionally, by making the number of data included in an emulation write unit (data group) common to each emulation write unit (data group), by regularly storing IDs in each address of the flash memory, ID search is possible. In FIG. 15, in data group 0 to data group 2, the emulation write unit (data group) is composed of six data consisting of ID and DATA_0 to DATA_4, and the ID is assigned to the flash memory every six addresses. In this configuration, the data is arranged and written.

  However, the number of data composing the emulation write unit must be common (fixed value) in the emulation write unit (data group) from the user's point of view. It becomes merit.

  If the value used as the ID is prohibited from being used as the value of DATA_0 to DATA_n, the number of data constituting the emulation write unit (data group) is common (fixed) to each emulation write unit (data group). Even if it is not set to (value), the ID can be searched. However, in this case, a limit is imposed on the value of DATA_0 to DATA_n used by the user, which is very inconvenient for the user and is not practical.

  The flash memory according to the present invention includes a data area for storing 1 (1> 0) bits of first and second data, a first additional bit of m bits for identifying the first data, and the first data And an additional bit area for storing a second additional bit of m (m> 0) bits for identifying two data, wherein the first additional bit is a value different from the second additional bit. It is characterized by having.

  The memory control circuit of the present invention is a memory control circuit that accesses the flash memory in units of data composed of first data and second data, and the memory control circuit includes the first data When writing data to the flash memory, a first additional bit for identifying the first data is written, and when writing the second data to the flash memory, the second data is identified. A second additional bit different from the first additional bit is written.

  The microcomputer according to the present invention accesses the flash memory in accordance with an instruction from the central processing unit in a data unit composed of a flash memory, a central processing unit, and first data and second data. A memory control circuit, wherein the memory control circuit writes a first additional bit for identifying the first data when writing the first data to the flash memory, When writing the second data to the flash memory, a second additional bit different from the first additional bit for identifying the second data is written.

  The memory control method of the present invention is a memory control method for accessing a flash memory in units of data composed of first data and the first data, wherein the first data and the first data A first step of writing a first additional bit for identifying the data to the flash memory and a first additional bit different from the first additional bit for identifying the second data and the second data And a second step of writing two additional bits to the flash memory.

  According to the present invention, the number of data in the emulation writing unit, that is, the value n of DATA_0 to DATA_n does not have to be common to each data group, and can be freely set for each data group. Design freedom is improved.

It is a block diagram which shows the structure of the microcomputer which concerns on Embodiment 1 of this invention. It is a conceptual diagram which shows the structure of the flash memory with which the microcomputer of Embodiment 1 of this invention is provided. It is a figure which shows the data structure of the write data (emulation write unit) which concerns on Embodiment 1 of this invention. It is an operation | movement flowchart which shows the write-in processing flow which concerns on Embodiment 1 of this invention. It is a figure (flash memory) which shows the write-in process based on Embodiment 1 of this invention. It is a figure (flash memory) which shows the write-in process based on Embodiment 1 of this invention. It is a figure which shows the modification of allocation of the address of the flash memory which concerns on Embodiment 1 of this invention. It is a figure which shows the modification of allocation of the address of the flash memory which concerns on Embodiment 1 of this invention. It is an operation | movement flowchart which shows the read-out process flow which concerns on Embodiment 1 of this invention. It is a figure which shows the data write order which concerns on Embodiment 2 of this invention. It is a figure which shows the rewriting (update) of the data with respect to the conventional EEPROM and flash memory (EEPROM emulation use). It is a figure which shows the data structure of the conventional write data (emulation write unit). It is an operation | movement flowchart which shows the conventional write-in processing flow. It is a figure (flash memory) which shows the conventional write processing. It is a figure (flash memory) which shows the conventional write processing. It is a figure (flash memory) which shows the conventional write processing. It is an operation | movement flowchart which shows the conventional read-out processing flow.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1
FIG. 1 is a block diagram showing the configuration of the microcomputer according to the first embodiment. The microcomputer 1 includes a central processing unit (CPU) 2, a memory control circuit 3, and a flash memory 4. The CPU 2 is connected to the memory control circuit 3 and the flash memory 4 via buses 5 and 6, respectively. The CPU 2 outputs a write / read command, a write / read destination address (address), and write data to the memory control circuit 3. Further, data read from the flash memory 4 is acquired. The memory control circuit 3 is connected to the flash memory 4 via the wiring 7, and for the flash memory, a write / read control signal (write / read mode control signal), a write / read destination address (address), and Write data is output. The flash memory 4 performs a write / read operation based on a control signal from the memory control circuit 3, and outputs the read data to the CPU in the case of reading.

  FIG. 2 is a conceptual diagram showing a configuration of the flash memory 4 mounted on the microcomputer 1 according to the first embodiment. The flash memory 4 shown in FIG. 2 is composed of one block (that is, the erase unit is the entire flash memory 4), has a minimum write unit area (address) from addresses 0000H to FFFFH, and can store each address. Is 9 bits long (000H to 1FFH). That is, the flash memory 4 according to the first embodiment has a configuration in which one bit of a memory cell is added to each address with respect to the conventional flash memory of FIG.

  The 9-bit data is constituted by adding an additional bit (described later) to the 8-bit data originally handled. In this description, the data to be handled is assumed to be 8-bit length data. However, regardless of the 8-bit length, it may be 1 bit (where l> 0), and the additional bits are also 1-bit length. Regardless, m bits (where m> 0) are sufficient. However, when writing / reading data of 1-bit length and additional bits of m-bit length to the flash memory 4 at the same time, the wiring 7 needs to have at least l + m-bit width. However, a terminal capable of inputting a signal having a width of 1 + m bits is required. An area where 8-bit data is stored is a data area, and an area where additional bits are stored is an additional bit area.

  Further, it is assumed that data group 0 to data group 2 have already been written in addresses 0000H to 000EH of the flash memory 4, and the read value of the unused area, that is, the read value in the erased state is set to 1FFH (addition of 1H). Bit + FFH data).

  3A to 3D show a general data structure of the emulation write unit (data group) according to the first embodiment and data group 0 to data group 2 written in the flash memory 4 of FIG. .

  FIG. 3A shows a general data structure of an emulation write unit (data group). As in the prior art, the emulation write unit (data group) 8 is composed of n DATA9 of DATA_0 to DATA_n and a data number (ID) 10 which is the name of the n + 1 DATA group (that is, there are a plurality of IDs). Data associated with the other DATA).

  However, there are two differences compared to the conventional case. The first point is that 1-bit data called additional bits is added to each of a plurality of data constituting the data group. As shown in FIG. 3A, an additional bit 10 of 1H is added to DATA_0 to DATA_n, and an additional bit 11 of 0H is added to ID. These additional bits are added to enable identification of DATA_0 to DATA_n and ID.

  The second point is that the value of n can be freely set without taking a common value in each data group. Although the data structures of data group 0 to data group 2 shown in (b) to (d) are shown, each data group has five data groups 0, three data groups 1, and two data groups 2. It consists of 7 pieces of data. Note that n = 1, that is, a data group composed of DATA_0 and ID may be used.

  Next, a write operation during EEPROM emulation according to the first embodiment of the present invention will be described.

  FIG. 4 shows an operation flowchart showing the writing process according to the first embodiment.

  1, 2, and 4, according to the write processing flow of FIG. 4, the microcomputer 1 shown in FIG. 1 stores data group 1 (FIG. 3) in an unused (blank) area of the flash memory 4 shown in FIG. 2. (B) will be described together with a specific example of the process of writing. As shown in FIG. 4, in the writing process, a blank search process (S4-1 to S4-4) for specifying a writing destination and 1H + DATA_0 to 1H + DATA_n and 0H + ID are sequentially written in the specified blank area. This is performed in two stages of processes (S4-5 to S4-6).

  (S4-1) The CPU 2 starts from the FFFFH address which is the last address of the flash memory 4, and reads the additional bits in the search direction of FFFFH address → FFFEH address → FFFFDH address →... → 0001H address → 0000H address. Do.

  Specifically, the CPU 2 outputs a read command and a read destination address (the first read destination is an FFFFH address) to the memory control circuit 3. The memory control circuit 3 that has received the read command from the CPU 2 controls the flash memory 4 to read out the 9-bit data stored at the address designated as the read destination. The flash memory 4 outputs the read 9-bit data to the CPU 2. The CPU 2 determines and acquires additional bits from the 9-bit data read from the flash memory 4.

  (S4-2) The CPU 2 determines whether or not the read additional bit is 0H. When the additional bit of 0H is read, the process proceeds to S4-4. On the other hand, when the additional bit of 1H is read, the process proceeds to S4-3.

  (S4-3) The CPU 2 decrements the address of the reading destination by +1 (since the search direction is the direction from the last address to the starting address, the address of the reading destination is added by -1 address. The same applies hereinafter). Then, the additional bit is read again.

  In FIG. 2, since it is an unused (blank) area from address FFFFH to address 000FH and the read value of the additional bit area is 1H in the erased state, the processing of S4-2 and S4-3 is performed until address 000FH. Will repeat.

  (S4-4) When the CPU 2 reads the additional bit of 0H in S4-2, the CPU 2 sets the address where the reading process was performed immediately before the address where the additional bit of 0H was read out (the write address of the blank area) Is specified). When the additional bit of 0H is read, data is written from the address to the start address, and it is determined that the address is a boundary between the used area and the unused (blank) area. be able to. Therefore, it is possible to specify that the address from which the 1H additional bit is read last is the head address of the blank area.

  In FIG. 2, since an additional bit of 0H is read at the address 000EH, it is determined that the address 000EH is the last address (boundary) of the use area, and the address 000FH which is the address where the read process was performed immediately before is the head of the blank area. It is possible to specify the address, that is, the address from which new data writing is started.

  (S4-5) The CPU 2 writes DATA (DATA_0 to DATA_n) and additional bits.

  Specifically, the CPU 2 designates the head address of the blank area identified in S4-4 as the write destination address, and outputs the write data to the memory control circuit 3 as 1H + DATA_0. The memory control circuit 3 controls writing of 1H + DATA_0 to the designated address of the flash memory 4. Subsequently, the CPU 2 increments the write destination address by +1, designates the address, and outputs the write data to the memory control circuit 3 as 1H + DATA_1. The memory control circuit 3 controls writing of 1H + DATA_1 to the designated address of the flash memory 4. Similarly, the writing process to the flash memory 4 is performed from 1H + DATA_2 to 1H + DATA_n. In the process of writing the data group 1 (consisting of DATA_0, DATA_1, and ID) to the flash memory 4 of FIG. 2, 1H + DATA_0 is written to address 000FH and 1H + DATA_1 is written to address 0010H (FIG. 5).

  (S4-6) The CPU 2 writes the additional bit (0H) and ID via the memory control circuit 3. Since the additional bit added to the ID is 0H, the address that was last written in S4-5 is incremented by +1, the address is designated, and 0H + ID is written. Since the ID writing is performed at the end of the emulation writing unit, the series of writing processes in the emulation writing unit is completed upon completion of the ID writing. In FIG. 6, 0H + ID is written at address 0011H.

  The writing process at the time of EEPROM emulation according to the first embodiment of the present invention is performed with such steps. When a new data group is subsequently written, additional writing is performed with the same steps. . In FIG. 6, new data is written from address 0012H.

  In S4-1, when reading additional bits from the flash memory 4, 8-bit data stored in the data area in the same address is simultaneously read, but only one additional bit is read. It may be configured to read. In this case, for example, as shown in FIG. 7, an address is assigned to each of the additional bit area in which the additional bits are stored and the data area in which DATA and ID are stored (therefore, the address assigned to the flash memory 4). Are addresses 00000000H to FFFFFFFFH, each of which is a minimum writing unit), and the CPU 2 instructs the memory control circuit 3 to specify only the address assigned to the additional bit area. Specifically, the address of the reading destination in S4-1 is FFFFFFFEH address → FFFFFFFCH address → FFFFFFFA address → ... → 00000001H address → 00000000H address.

  Further, as shown in FIG. 8, an additional address indicating 0H address specifying the additional bit area and 1H address specifying the data area is created, and only the additional bits can be read using the two addresses. Also good.

  As in the prior art, if there is no data group already written, data is written from address 0000H. Although omitted in the description of the blank search process of S4-1 to S4-4, even if there is a blank area, there is no blank area for writing all the data included in the data group to be written. In this case, it is determined that there is no blank area in the flash memory 4, and the entire flash memory 4 is erased while protecting a necessary data group (data group not related to the current writing), and the flash memory after erasure is performed. 4 performs a data write-back process and a new data group write process.

  Next, a read operation during EEPROM emulation according to Embodiment 1 of the present invention will be described.

  FIG. 9 shows an operation flowchart showing the read processing according to the first embodiment. In the reading process, the 0H additional bit is searched, the ID of the data area stored at the same address as the 0H additional bit found by the search is read, and the read ID is included in a plurality of data groups to be read. By determining whether or not the ID is associated with DATA, an ID search process (S9-1 to S9-5) for specifying read target data and a process for reading the specified read target data (S9-6) This is done in two stages.

  As a specific example, a case where data groups 0 and 1 are read from the flash memory 4 of FIG. 6 will be described. In the flash memory 4 in FIG. 6, since the data group 1 is written (updated) for the second time, the last written data group 1 (addresses 000FH to 0011H) is an effective data group. The previously written data group 1 (addresses 0005H to 0007H) is treated as an invalid data group.

  (S9-1) The CPU 2 starts from the FFFFH address which is the final address of the flash memory 4, and reads the additional bits in the search direction of FFFFH address → FFFEH address → FFFFDH address → ... → 0001H address → 0000H address. Do.

  Specifically, the CPU 2 outputs a read command and a read destination address (the first read destination is an FFFFH address) to the memory control circuit 3. The memory control circuit 3 that has received the read command from the CPU 2 controls the flash memory 4 to read out the 9-bit data stored at the address designated as the read destination. The flash memory 4 outputs the read 9-bit data to the CPU 2. The CPU 2 determines and acquires additional bits from the 9-bit data read from the flash memory 4. This step is the same process as S4-1 of the writing process.

  (S9-2) The CPU 2 determines whether or not the acquired additional bit is 0H. If it is 0H, the process proceeds to S9-4, and if it is 1H, the process proceeds to S9-3.

(S9-3) If the additional bit acquired by the CPU 2 is 1H in S9-2, the address of the read destination is decremented by +1, read again, and the process proceeds to S9-2.
In FIG. 6, since it is an unused (blank) area from address FFFFH to address 0012H and the read value of the additional bit area is 1H in the erased state, the processes of S9-2 and S9-3 are repeated until address 0012H. It will be.

  (S9-4) When CPU 2 acquires 0H as the value of the additional bit in S9-2, the 8-bit data (ID) read from the same address where the additional bit of 0H is stored is It is determined whether or not the ID (target ID) associated with DATA of the read target data group. If the read ID is the target ID, the process proceeds to S9-5. On the other hand, if the read ID is not the target ID, the process proceeds to S9-3, and the processes of S9-2 and S9-3 are repeated until an additional bit of 0H is found again.

  In FIG. 6, when the read target is a data group 0, if the read ID is ID = 0, it can be determined that the ID is associated with the read target data. In S9-2, the ID is read out at address 0011H, and the value stored at address 0011H is ID = 1. Therefore, since the read target is the data group 0, it can be determined that this ID is not the target ID. Therefore, the process proceeds to S9-3, the address of the read destination is decremented by +1, and the processing of S9-2 and S9-3 is repeated until the additional bit of 0H is read from the flash memory 4 again, and the additional bit of 0H is read. If issued, it is determined whether or not the ID stored in the data area of the same address is the target ID. The additional bits of 0H are read out at addresses 000EH, 0007H, and 0004H, but since the target ID (ID = 0) is stored at address 0004H, up to address 0004H, S9− The processing of 2 to S9-4 is repeated. On the other hand, if the read target is the data group 1, since the data stored at address 0011H is ID = 1, it can be determined that this ID is the target ID, and the process proceeds to S9-5.

  (S9-5) If the target ID can be specified in S9-4, the address decremented by +5 from the address from which the target ID is read is the head address of the read target data group. Identify.

  In FIG. 6, when the data group 0 is read, it is determined in S9-4 that the address 0004H is the target ID, so the address decremented by +4 from the address 0004H becomes the address 0000H, and this address 0000H is It identifies that it is the head address of the data group 0 to be read. Since it is known that the data group 0 is composed of five data items DATA_0 to DATA_3 and ID, the address where DATA_0 is stored is from the address where the ID is stored. This is because the address is decremented by +4.

  When data group 1 is read, since address 0011H is the target ID, the address decremented by +2 from address 0011H (data group 1 is composed of three data) becomes address 000FH. The address 000FH is specified as the head address of the data group 1 of the read target data.

(S9-6) DATA_0 is read from the head address of the read target data specified in S9-5, and DATA_1 to DATA_n are read while sequentially incrementing the address by +1.
In FIG. 6, data group 0 is read by reading DATA_0 to DATA_3 from addresses 0000H to 0003H. Data group 1 is read by reading DATA_0 and DATA_1 from addresses 000FH to 0010H.

  In the flash memory 4 of FIG. 6, the data group 1 is updated, and therefore the data group related to the data group 1 is stored in two places, but the valid data group is the last written one, that is, a blank area. Closer to the side. In the method described in S9-1 to S9-6, a search is performed for an additional bit (ID) of 0H from the blank area side, and the search for data to be read is terminated when a target ID is specified. Even if a plurality of data groups having the same ID are stored in 4, the most recent data group, that is, an effective data group can be read out appropriately. In the example of reading data group 1 in FIG. 6, valid data group 1 (address 000FH to address 0011H) is selected without selecting invalid data group 1 (address 0005H to address 0007H).

  In S9-5, the method of specifying the address where DATA_0 of the data group to be read is stored is described with reference to the address where the ID of the data group to be read is stored. A method may be used in which 1H is sequentially decremented from the issued address, 1H additional bit + DATA is read, and when the 0H additional bit + ID is read, reading of the data group to be read is terminated. This method is effective when it is not known in advance whether or not the data group is composed of the number of data.

  In the write processing flow and the read processing flow of FIGS. 4 and 9, it has been described that the direction of blank search and ID search is performed from the address FFFFH (last address). However, as described in the conventional description, address 0000H is reversed. You may go from (start address). However, in that case, in the write processing flow, the address incremented by +1 to the address from which the 0H additional bit was read last becomes the first address of the unused (blank) area. The address from which the target ID is read out is specified as the ID of a valid data group.

  As described above, according to the present embodiment, the number of data constituting an emulation write unit at the time of EEPROM emulation does not have to be a common value between emulation write units with different IDs, that is, between data groups. Therefore, the user can freely set the number of data included in the data group, and as a result, the user's design freedom is improved.

  In addition, in the blank search process in the writing process and the ID search process in the reading process, only the additional bits need to be checked to search for the ID.

Embodiment 2
FIG. 10 shows the data writing order according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in the writing order when writing 0H + ID in the writing process. Accordingly, since the other points are the same as those in the first embodiment, description thereof will be omitted.

  In the EEPROM emulation writing process, a plurality of data (DATA_0 to DATA_n, ID) and additional bits are written to the flash memory 4 for each emulation writing unit (S4-4 and S4-5). In the first embodiment, it has been described that 0H + ID is written last (S4-5), but in the second embodiment, writing is performed in two steps of 1H + ID → 0H + FFH.

  Since the flash memory 4 has an erased state (for example, a state in which there is no charge in the floating gates of a plurality of memory cells constituting the flash memory 4) as 1H, 1H additional bit write or FFH (11111111B) data Is actually not performed on the memory cells constituting the flash memory 4. That is, 1H + ID in the first step is a process of writing only to the data area in the flash memory 4, and the writing process to the additional bit area is not performed. Conversely, 0H + FFH in the second step is a process of writing only to the additional bit area in the flash memory 4, and the writing process to the data area is not performed. In other words, the ID is written in the first step, and the additional bit of 0H is written in the second step, that is, at the end of a series of writing processes.

  As shown in FIG. 10, first, 1H + DATA_0 is written (S10-1). Next, 1H + DATA_1 is written (S10-2). Similarly, writing is performed from 1H + DATA_2 to 1H + DATA_n (S10-3 to S10-5).

  After writing DATA, 0H + ID is written. First, since only ID is written, 1H + ID is written (S10-6). Finally, in order to write an additional bit of 0H, writing of 0H + FFH is performed (S10-7). Thus, writing of one data group including the additional bits, DATA_0 to DATA_n, and ID is completed.

  As described above, according to the present embodiment, it is possible to confirm that no write error due to a momentary power interruption or the like has occurred by writing the additional bit of 0H last. That is, if the last 0H additional bit written can be read correctly, it can be determined that the previous writing of DATA_0 to DATA_n and ID has been executed normally.

  As mentioned above, although it demonstrated in detail based on embodiment of this invention, this invention is not limited to the above embodiment, A various deformation | transformation is possible. For example, the additional bits are not limited to 1-bit length and may be 2 bits or more. In the drawing, the additional bits are written to be arranged at the same address as the 8-bit data to be identified at the most significant bit position of the 9-bit data. However, the present invention is not limited to this. . Further, in FIG. 8, the additional bit areas and the data areas are alternately arranged, but they may be arranged in any way. In the description of the embodiment, the CPU 2 performs write / read commands for the memory control circuit 3, generation of write data, and determination of read values, but all or part of this function is stored in the memory. The control circuit 3 may execute it. Conversely, the CPU 2 may execute a direct access control function for the flash memory 4, which the memory control circuit 3 performs, without using the memory control circuit 3. Furthermore, the first embodiment and the second embodiment can be combined.

1 Microcomputer 2 CPU
3 Memory control circuit 4 Flash memory 5 and 6 Bus 7 Signal wiring 8 Emulation write unit (data group)
9 DATA
10 Data number (ID)
11, 12 Additional bits

Claims (15)

Flash memory,
A semiconductor device comprising a memory control circuit that accesses the flash memory in units of data groups,
The data group is:
A plurality of sets of data and additional bit data which is additional information associated with the data;
The flash memory is
A data area for storing a plurality of the data, and an additional bit area for storing a plurality of the additional bit data,
The memory control circuit includes:
When writing the data group to the flash memory,
When the data is first data that is identification information of the data group, the first additional bit data associated with the first data is written to the additional bit area,
For the second data the data is not identification information of the group of data, write the different second additional bit data to the additional bit region and said associated second data first added bit data ,
When reading the data group,
The address of the flash memory is changed in one of the first direction in ascending order or descending order or the second direction opposite to the first direction, and the address of the additional bit area is changed. Read the value stored at each address,
Extracting the first data associated with the additional bit data stored at an address whose read value is the same as the first value;
A semiconductor device which reads a data group which is identification information to be read by the extracted first data . The memory control circuit includes:
When writing the data group,
The address in the first direction, by changing the address of the flash memory, reads the values stored in each address of the additional bit region,
Detecting a first address whose read value is the value of the first additional bit data;
Wherein when viewed from a first address, before Symbol semiconductor device according to claim 1, characterized in that writing the data group the addresses changed in the second direction to the origin. The memory control circuit includes:
When writing the data group,
3. The semiconductor device according to claim 2, wherein the data group is written in the flash memory in units of sets, and the address is changed in the second direction for each set of writing. The memory control circuit includes:
When writing the data group,
4. The semiconductor device according to claim 3, wherein a set of the first data and the first additional bit data is performed at the end of writing of the data group. The memory control circuit includes:
When writing the data group,
5. The semiconductor device according to claim 3, wherein the additional bit data of the set is written after the set of data is written. First additional bit data, the semiconductor device according to any one of claims 1 to 5, characterized in that said a first value is a value opposite value indicating an erase state of the flash memory. The semiconductor device according to claim 6, wherein the first value is zero. The semiconductor device according to any one of claims 1 to 7, characterized in that said second additional bit data is 1. When the address of the data area where the data is stored and the address of the additional bit area where the additional bit data is stored are the same,
Said memory control circuit, the semiconductor device according to any one of claims 1 to 8, characterized in that associating the said data and said additional bit data. When a part of the address of the data area where the data is stored is the same as a part of the address of the additional bit area where the additional bit data is stored,
Said memory control circuit, the semiconductor device according to any one of claims 1 to 8, characterized in that associating the said data and said additional bit data. The bit length of the additional bit data, the semiconductor device according to any one of claims 1 to 10, characterized in that one bit. The semiconductor device according to any one of claims 1 to 10, wherein the bit width associated with one address of the additional bit area of the flash memory is one bit. The set of the first data and the first additional bit data, the set of the second data and the second additional bit data are:
The semiconductor device according to claim 1, wherein the data area and the additional bit area are stored at different addresses. The semiconductor device further includes a central processing unit,
The memory control circuit according to an instruction of said central processing unit, a semiconductor device according to any one of claims 1 to 11, characterized in that for executing access to the flash memory. Flash memory,
A central processing unit;
A microcomputer comprising a memory control circuit for accessing the flash memory in units of data groups according to instructions of the central processing unit,
The data group is:
A plurality of sets of data and additional bit data which is additional information associated with the data;
The flash memory is
A data area for storing a plurality of the data, and an additional bit area for storing a plurality of the additional bit data,
The memory control circuit includes:
When writing the data group to the flash memory,
When the data is first data that is identification information of the data group, the first additional bit data associated with the first data is written to the additional bit area,
For the second data the data is not identification information of the group of data, write the different second additional bit data to the additional bit region and said associated second data first added bit data ,
When reading the data group,
The address of the flash memory is changed in one of the first direction in ascending order or descending order or the second direction opposite to the first direction, and the address of the additional bit area is changed. Read the value stored at each address,
Extracting the first data associated with the additional bit data stored at an address whose read value is the same as the first value;
A microcomputer which reads a data group which is identification information to be read by the extracted first data .

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