JP5361658B2 - Resolver digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resolver digital converter which performs corrections, at all times during the operation of the resolver so as to follow the variations in the lag time of a signal input from a resolver. <P>SOLUTION: By a phase lag time measuring section 1, phase lag time is measured between an excitation signal RS output from an excitation signal generator 101 and outputs S1 and S2 from the resolver; a variable delay part 2 delays the exciting signal RS by a delay, corresponding to the phase lag time DT calculated by the phase lag time measuring section 1 and outputs it as a synchronization signal SS input to a synchronous detector 105. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a resolver digital converter.

  The resolver digital converter outputs an excitation signal to a resolver attached to the rotating device, calculates a rotation angle of the rotating device from an AC signal input from the resolver, and outputs the rotation angle as digital data.

  In calculating the rotation angle, synchronous detection using the excitation signal is performed in order to remove the excitation signal component included in the AC signal from the resolver. At this time, if there is a delay time between the excitation signal and the AC signal from the resolver, the phase of the synchronous detection is shifted and the sensitivity of the synchronous detection is lowered. As a result, an error occurs in the calculation of the rotation angle, and there arises a problem that the accuracy of the output rotation angle data is lowered.

  Conventionally, a method has been proposed in which the delay time of the AC signal input from the resolver is calculated and the rotation angle calculated based on the delay time is corrected with respect to the problem caused by the delay time described above (for example, , See Patent Document 1).

  However, in the proposed method described above, the delay time of the AC signal is calculated only when the resolver is stopped. Therefore, for example, when the delay time fluctuates due to temperature fluctuations during the operation of the resolver, the delay time is calculated. There was a problem that the rotation angle could not be corrected following the fluctuation.

JP 2005-147729 A (Page 3-6, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a resolver digital converter that can always perform corrections following changes in the delay time of a signal input from a resolver during the operation of the resolver.

  According to one aspect of the present invention, an excitation signal generating unit that generates an excitation signal to be supplied to a resolver, and an excitation signal component from two AC signals having different phases in which the excitation signal input from the resolver is amplitude-modulated. A resolver digital converter comprising synchronous detection means for removing, wherein the phase delay time measuring means for measuring the phase delay time from the excitation signal of the two AC signals, and the phase delay time measuring means calculated by the phase delay time measuring means Variable excitation means for delaying the excitation signal by a delay corresponding to the phase delay time and outputting the delayed signal as a synchronization signal to be input to the synchronous detection means, wherein the phase delay time measurement means is one of the two AC signals. The zero point detecting means for detecting the zero point of the level and outputting the zero point detection signal, and the zero point detection signal is output from the rising edge of the excitation signal. A resolver to digital converter is provided, characterized in that it comprises a measuring means for measuring to time is.

  According to the present invention, it is possible to always perform correction following the fluctuation of the delay time of the signal input from the resolver during the operation of the resolver.

The block diagram which shows the example of a structure of the resolver digital converter which concerns on the Example of this invention. The figure which shows the relationship between the excitation signal output from the resolver digital converter which concerns on the Example of this invention, and the alternating current signal output from a resolver. The block diagram which shows the example of the internal structure of the phase delay time measurement part of the Example of this invention. Operation | movement explanatory drawing of the phase delay time measurement part shown in FIG. Explanatory drawing regarding 0 point of the alternating current signal output from a resolver. The block diagram which shows the example of the internal structure of the variable delay part of the Example of this invention. The wave form diagram which shows the example of operation | movement of the resolver digital converter which concerns on the Example of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  FIG. 1 is a block diagram showing an example of the configuration of a resolver digital converter according to an embodiment of the present invention.

  The resolver digital converter of this embodiment has, as its basic configuration, an excitation signal generation unit 101 that generates an excitation signal RS to be supplied to the resolver, and AD converters 102A and 102B to which outputs S1 and S2 from the resolver are input, respectively. The multipliers 103A and 103B to which the output D1 of the AD converter 102A and the output D2 of the AD converter 102B are input, the subtractor 104 that subtracts the output of the multiplier 103B from the output of the multiplier 103A, and the excitation signal RS. Calculated by a synchronous detector 105 that synchronously detects the output of the subtractor 104 based on the synchronous signal SS, an angular velocity calculator 16 that integrates the output of the synchronous detector 105 to calculate the angular velocity v of the rotating device, and an angular velocity calculator 106. Rotation angle calculation unit 1 that calculates the rotation angle φ of the rotating device by integrating the angular velocity v 7, a COS table 108 that outputs a cosine function value cos φ corresponding to the rotation angle φ calculated by the rotation angle calculation unit 107 to the multiplication unit 103 A, and a sine corresponding to the rotation angle φ calculated by the rotation angle calculation unit 107. And a SIN table 109 that outputs the function value sinφ to the multiplication unit 103B.

  FIG. 2 shows examples of signal waveforms of the excitation signal RS generated by the excitation signal generation unit 101 and the outputs S1 and S2 from the resolver.

  As shown in FIG. 2A, the excitation signal RS generated by the excitation signal generation unit 101 is a rectangular group.

  This excitation signal RS is converted into a sine wave sin ωt as shown in FIG. 2B by an external filter (not shown), and used as an excitation wave supplied to the resolver.

  The resolver outputs two output signals, S1 (= sin θ · sin ωt) and S2 (= cos θ · sin ωt), which are amplitude-modulated from the excitation wave sin ωt according to the rotation angle θ of the rotating device.

  FIG. 2C shows a waveform example of the resolver output S1, and FIG. 2D shows a waveform example of the resolver output S2.

  At this time, a phase delay occurs between the excitation signal RS and the resolver outputs S1 and S2 due to the operation time of the resolver, the signal transmission time between the resolver and the resolver digital converter, and the like. The phase delay time at this time is represented as DT.

  Resolver outputs S1 and S2 are input to AD converters 102A and 102B, respectively, and converted to digital D1 and D2.

  The output D1 of the AD converter 102A is input to the multiplication unit 103A. The multiplier 103A multiplies the cosine function value cosφ with respect to the rotation angle φ of the previous calculation result fed back by the COS table 108, and outputs (sinθ · sinωt) · cosφ.

  On the other hand, the output of the AD converter 102B is input to the multiplication unit 103B. The multiplication unit 103B multiplies the sine function value sinφ with respect to the rotation angle φ of the previous calculation result fed back by the SIN table 109, and outputs (cosθ · sinωt) · sinφ.

The subtractor 104 subtracts the output of the multiplier 103B from the output of the multiplier 103A,
(Sinθ · sinωt) · cosφ− (cosθ · sinωt) · sinφ
= (Sinθ · cosφ−cosθ · sinφ) · sinωt
= Sin (θ−φ) · sinωt
Is output.

The synchronous detection unit 105 samples the output of the subtractor 104 based on the synchronous signal SS and performs synchronous detection synchronized with the excitation signal RS. Thereby, the component of the excitation signal RS is removed from the output of the subtractor 104, and the synchronous detection unit 105
sin (θ−φ)
Is output.

When the value of (θ−φ) is small, sin (θ−φ) ≈ (θ−φ). (Θ−φ) is a control deviation ε for setting φ = θ. Therefore, the output of the synchronous detection unit 105 is controlled by the control deviation ε = sin (θ−φ).
Can be considered.

  The angular velocity calculating unit 106 calculates the angular velocity v of the rotating device by integrating the control deviation ε, and the rotating angle calculating unit 107 integrates the angular velocity v calculated by the angular velocity calculating unit 106 to thereby calculate the rotation angle of the rotating device. Calculate φ.

  In this manner, the resolver digital converter having the configuration shown in FIG. 1 outputs the rotation angle φ corresponding to the rotation angle θ of the rotating device.

  As described above, synchronous detection by the synchronous detection unit 105 is performed in order to remove the excitation signal components included in the outputs S1 and S2 from the resolver. At this time, there is a phase difference of the phase delay time DT between the excitation signal RS and the outputs S1 and S2 from the resolver as shown in FIG. Therefore, if synchronous detection is performed as it is with the excitation signal RS, the phase of synchronous detection shifts, and the sensitivity of synchronous detection decreases. As a result, an error occurs in the calculation of the rotation angle, and the accuracy of the rotation angle data to be output decreases.

  Therefore, in this embodiment, the phase delay time measuring unit 1 that measures the phase delay time between the excitation signal RS and the outputs S1 and S2 from the resolver, and the phase delay time DT calculated by the phase delay time measuring unit 1 There is provided a variable delay unit 2 that delays the excitation signal RS with a delay according to the output and outputs it as a synchronization signal SS input to the synchronous detection unit 105.

  FIG. 3 shows an example of the internal configuration of the phase delay time measurement unit 1.

  In the example shown in FIG. 3, the phase delay time measurement unit 1 detects the zero point of the amplitude level of the resolver output S1 and outputs a zero point detection signal Z1, and the amplitude level of the resolver output S2 A zero point detection unit 11B that detects the zero point and outputs the zero point detection signal Z2, and an OR that outputs the zero point detection signal Z when either the zero point detection signal Z1 or the zero point detection signal Z2 is output. A gate 12 and a counter 13 that starts counting at the rising edge of the excitation signal RS, stops counting when the zero point detection signal Z is output, and outputs the count value at that time as the phase delay time DT. Has been. Here, it is assumed that the counter 13 counts with a high-frequency clock signal CK.

  FIG. 4 shows an example of operation waveforms of the phase delay time measuring unit 1 of the configuration example shown in FIG.

  The counter 13 starts counting at the rising edge of the excitation signal RS, and stops counting when, for example, the zero point of the amplitude level of the resolver output S1 is detected.

  Note that, here, the analog waveform of the resolver output S1 is shown so that it is easy to imagine the zero point detection, but in reality, the zero point detection is performed depending on whether or not the output D1 of the AD converter 102A is “0”. The zero point detection by the unit 11A is performed.

  By the way, since the phase delay time DT from the excitation signal RS is the same for both the resolver output S1 and the resolver output S2, it is basically possible to measure the phase delay time DT only by detecting either one of the zero points. is there.

  However, in this embodiment, zero point detection is performed by both the resolver output S1 and the resolver output S2. Hereinafter, the reason why the zero point detection is performed in both the resolver output S1 and the resolver output S2 will be described.

  As shown in FIG. 5, in the case of the resolver output S1, the signal level is very small near A where sin θ = 0, and in the case of the resolver output S2, around B where cos θ = 0. Therefore, in this vicinity, an error is likely to occur in the zero point detection.

  However, the signal output from the resolver has a phase difference of 90 ° between sin θ and cos θ. Therefore, sin θ = 0 and cos θ = 0 do not occur simultaneously.

  Therefore, in this embodiment, zero point detection is performed for both the resolver output S1 and the resolver output S2, thereby preventing an error in the zero point detection.

  FIG. 6 shows an example of the internal configuration of the variable delay unit 2.

  In the example shown in FIG. 6, the variable delay unit 2 includes a tapped multistage delay unit 21 that outputs an output obtained by sequentially delaying the excitation signal RS to the tap, and the phase delay time DT output from the phase delay time measurement unit 1. The tap switching unit 22 is configured to switch the output tap of the multistage delay unit 21 with taps according to the size and output the synchronization signal SS.

  By switching the output taps by the tap switching unit 22, it is possible to output the synchronization signal SS obtained by delaying the excitation signal RS in accordance with the phase delay time DT.

  Thus, even if the phase delay time DT of the resolver outputs S1 and S2 with respect to the excitation signal RS varies during the operation of the resolver, the phase of the synchronization signal SS can be corrected following the variation.

  FIG. 7 shows how the phase of the synchronization signal SS is corrected with respect to fluctuations in the phase delay time DT of the resolver outputs S1 and S2.

  As shown in FIG. 7, when the phase delay time of the resolver outputs S1 and S2 varies from DT1 to DT2, the phase of the synchronization signal SS with respect to the excitation signal RS is corrected following the variation.

  According to this embodiment, during the operation of the resolver, the phase delay time DT of the resolver outputs S1 and S2 with respect to the excitation signal RS is always measured, and input to the synchronous detection unit 105 according to the phase delay time DT. The phase of the synchronizing signal SS to be corrected can be corrected. Thereby, even if the phase delay time DT fluctuates during the operation of the resolver, the phase of the synchronization signal SS that follows the fluctuation can always be corrected. As a result, a decrease in the sensitivity of the synchronous detection in the synchronous detection unit 105 can be prevented, and a decrease in the accuracy of the rotation angle calculation in the rotation angle calculation unit 107 can be prevented.

DESCRIPTION OF SYMBOLS 1 Phase delay time measurement part 2 Variable delay part 11A, 11B 0 point detection part 12 OR gate 13 Counter 21 Multistage delay part 22 with a tap 22 Tap switching part 101 Excitation signal generation part 102A, 102B AD converter 103A, 103B Multiplication part 104 Subtractor 105 Synchronous detection unit 106 Angular velocity calculation unit 107 Rotation angle calculation unit 108 COS table 109 SIN table

Claims (3)

A resolver comprising excitation signal generation means for generating an excitation signal to be supplied to a resolver, and synchronous detection means for removing excitation signal components from two AC signals having different phases in which the excitation signal input from the resolver is amplitude-modulated. A digital converter,
Phase delay time measuring means for measuring a phase delay time of the two AC signals from the excitation signal;
Variable delay means for delaying the excitation signal by a delay corresponding to the phase delay time calculated by the phase delay time measuring means and outputting as a synchronization signal to be input to the synchronous detection means ;
The phase delay time measuring means is
A zero point detecting means for detecting a zero point of a level of either of the two AC signals and outputting a zero point detection signal;
A resolver digital converter, comprising: a measuring unit that measures a time from when the excitation signal rises until the zero point detection signal is output. The resolver digital converter according to claim 1, further comprising an AD converter that converts the AC signal into digital data. The resolver digital converter according to claim 2 , wherein an output of the AD converter is input to the zero-point detector.

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