JP5358520B2 - Solid-state imaging device, imaging apparatus, and solid-state imaging device driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacking type solid-state imaging device capable of suppressing afterimage, microfabrication, and low cost. <P>SOLUTION: A pixel G of a solid-state imaging device 100 has a photoelectric transducer P provided above a substrate 10. For each pixel G, a readout circuit 11 for reading out a signal corresponding to an electric charge generated in the photoelectric transducer P is provided in the substrate 10. Two readout circuits 11 corresponding to neighboring two photoelectric transducers P share a readout circuit 11c. When injecting electric charges from a reset drain RD of the readout circuit 11c to a connecting part C1 of a pixel 1, a potential of a transfer gate of a pixel 2 is made shallower than that of the reset drain RD, thereby preventing electric charges from being injected from the reset drain RD to a storage part SD2 of the pixel 2. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a solid-state imaging device, an imaging apparatus, and a driving method for a solid-state imaging device.

  A plurality of pixels each having a photoelectric conversion element including a pair of electrodes stacked above the semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes, and the charge generated in the photoelectric conversion element of each pixel corresponding to each pixel There is known a stacked solid-state imaging device having a configuration in which a readout circuit for reading a signal according to the above is provided (see Patent Document 1).

  Each pixel of the solid-state imaging device described in Patent Document 1 includes a connection portion that is electrically connected to the photoelectric conversion layer in the semiconductor substrate, a potential barrier portion provided next to the connection portion, and the potential barrier. And a MOS circuit that outputs a signal corresponding to the amount of charge stored in the charge storage unit.

  And in this solid-state image sensor, the afterimage is suppressed by performing the drive which injects an electric charge into a connection part.

JP 2010-16593 A

  The solid-state imaging device described in Patent Document 1 has a configuration in which a MOS circuit is provided for each pixel. However, if a MOS circuit is shared by a plurality of pixels, pixel miniaturization and cost reduction of the solid-state imaging device can be achieved. It becomes possible. However, Patent Document 1 does not consider a configuration in which a MOS circuit is shared by a plurality of pixels.

  An object of the present invention is to provide a stacked solid-state imaging device capable of realizing afterimage suppression, miniaturization, and low cost, an imaging apparatus including the same, and a driving method of the solid-state imaging device.

  A solid-state imaging device of the present invention is a solid-state imaging device having a plurality of photoelectric conversion elements including a pair of electrodes stacked above a semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes, corresponding to the photoelectric conversion elements A read circuit that reads a signal generated by the photoelectric conversion element and a drive unit that drives the read circuit, and the read circuit includes the photoelectric conversion layer and the semiconductor substrate of the corresponding photoelectric conversion element. A connection portion formed in the semiconductor substrate for electrical connection; and a potential barrier portion provided adjacent to the connection portion in the semiconductor substrate and serving as a potential barrier with respect to the potential of the connection portion; A first charge storage portion provided in the semiconductor substrate adjacent to the potential barrier portion, wherein the charge generated in the photoelectric conversion layer is stored through the connection portion and the potential barrier portion; and A signal output circuit that outputs a signal corresponding to the charge stored in the charge storage section, wherein the signal output circuit includes a charge injection section that injects charge into the connection section, and a plurality of adjacent photoelectric conversions The readout circuit corresponding to an element shares the charge injection unit, and the driving unit is one of the plurality of readout circuits sharing the charge injection unit. When charge is injected into the connection portion from the charge injection portion to bring the connection portion and the potential barrier portion of the first readout circuit into the same potential, the charge injection drive is performed when the charge injection drive is performed. Controlling the signal output circuit of the second readout circuit other than the first readout circuit among the plurality of readout circuits sharing the injection unit, and the first charge storage unit of the second readout circuit And the electric Injection potential barrier as a barrier against the potential of the charge injection portion between the injection portion and forms a.

  The imaging device of the present invention includes the solid-state imaging device.

  The solid-state imaging device driving method of the present invention is a solid-state imaging device driving method including a plurality of photoelectric conversion elements including a pair of electrodes stacked above a semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes. The image sensor is provided corresponding to the photoelectric conversion element, and includes a read circuit that reads a signal generated by the photoelectric conversion element, and the read circuit includes the photoelectric conversion layer and the semiconductor substrate of the corresponding photoelectric conversion element. A connection portion formed in the semiconductor substrate for electrically connecting the connection portion, and a potential barrier portion provided in the semiconductor substrate adjacent to the connection portion and serving as a potential barrier with respect to the potential of the connection portion And a first charge storage unit provided in the semiconductor substrate adjacent to the potential barrier unit, wherein the charge generated in the photoelectric conversion layer is stored through the connection unit and the potential barrier unit, and A signal output circuit that outputs a signal corresponding to the charge stored in one charge storage unit, wherein the signal output circuit includes a charge injection unit that injects charge into the connection unit, and a plurality of adjacent photoelectric transistors The readout circuit corresponding to the conversion element shares the charge injection part, and the connection part of the first readout circuit that is one of the plurality of readout circuits sharing the charge injection part Charge injection is performed by injecting charge from the charge injection section so that the connection section and the potential barrier section of the first readout circuit have the same potential. When performing the charge injection drive, the charge injection section is shared. Controlling the signal output circuit of the second readout circuit other than the first readout circuit among the plurality of readout circuits to perform the first charge accumulation unit and the charge injection of the second readout circuit With the department And it has a driving step for driving that forms an injection potential barrier as a barrier to the potential of the charge injection unit to.

  According to the present invention, it is possible to provide a stacked solid-state imaging device capable of realizing afterimage suppression, miniaturization, and low cost, an imaging apparatus including the same, and a driving method of the solid-state imaging device.

1 is a schematic plan view showing a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. 1 is a schematic cross-sectional view of a pixel G in the solid-state imaging device shown in FIG. The figure which showed the example of a structure of the read-out circuit corresponding to two pixels adjacent in the orthogonal | vertical direction among all the pixels of two adjacent rows in the row of pixels shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure which shows the modification of the read-out circuit of the solid-state image sensor shown in FIG. The figure for demonstrating an example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating an example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating an example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating an example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating an example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating an example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating another example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating another example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating another example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit. The figure for demonstrating another example of the drive method of the solid-state image sensor which has a circuit shown in FIG. 13 as a reading circuit.

  Below, the solid-state image sensor 100 which is one Embodiment of this invention is demonstrated with reference to drawings. The solid-state imaging device 100 is used by being mounted on an imaging module or the like mounted on an imaging device such as a digital camera or a digital video camera, an electronic endoscope, a mobile phone with a camera, or the like.

  FIG. 1 is a schematic plan view showing a schematic configuration of a solid-state imaging device 100 according to an embodiment of the present invention.

  The solid-state imaging device 100 includes a plurality of pixels G arranged two-dimensionally in a vertical direction Y and a horizontal direction X orthogonal thereto, a vertical driving unit 2, a signal processing unit 3, a horizontal driving unit 4, and a control. Part 5.

  As will be described in detail later, each pixel G includes a photoelectric conversion element provided above the semiconductor substrate, and a readout circuit that reads a signal corresponding to the charge generated in the photoelectric conversion element.

  The vertical driving unit 2 supplies a driving signal for driving the plurality of pixels G to a readout circuit described later corresponding to each pixel G, and performs exposure control and signal readout control for each pixel.

  The signal processing unit 3 includes a set of a CDS circuit and an AD conversion circuit provided corresponding to the column of pixels G arranged in the vertical direction Y. A set of a CDS circuit and an AD conversion circuit corresponding to a certain column performs correlated double sampling processing and digital conversion processing on a signal output from the readout circuit of the pixel G included in the column.

  The horizontal driving unit 4 performs driving to sequentially output signals processed by the set of the CDS circuit and the AD conversion circuit to the outside of the solid-state imaging device 100.

  The control unit 5 performs overall control of the solid-state imaging device 100 as a whole, and includes a circuit that generates a driving signal supplied from the vertical driving unit 2 to each pixel G, a power supply circuit for the solid-state imaging device 100, and the like.

  FIG. 2 is a schematic cross-sectional view of the pixel G in the solid-state imaging device 100 shown in FIG.

  As shown in FIG. 2, the pixel G includes a photoelectric conversion element P provided above the semiconductor substrate 10.

  The photoelectric conversion element P includes a pixel electrode 14 formed above the semiconductor substrate 10, a counter electrode 16 formed above the pixel electrode 14, and a photoelectric conversion layer 15 formed between the pixel electrode 14 and the counter electrode 16. Is provided. The photoelectric conversion element P is protected by the protective layer 17.

  The pixel electrode 14 is an electrode that collects charges generated in the photoelectric conversion layer 15, and is separated for each pixel G.

  The pixel electrode 14 is formed in the insulating layer 12 on the semiconductor substrate 10 and is electrically connected to the readout circuit 11 by a conductive plug 13 formed in the insulating layer 12 on the semiconductor substrate 10. .

  In the example of FIG. 2, the photoelectric conversion layer 15 is one layer common to all the pixels G formed on the pixel electrode 14, and is composed of a photoelectric conversion material that generates charges in response to received light. .

  The counter electrode 16 is one electrode common to all the pixels G formed on the photoelectric conversion layer 15 in the example of FIG. Since the counter electrode 16 needs to make light incident on the photoelectric conversion layer 15, the counter electrode 16 is made of a material (for example, ITO) having a high transmittance with respect to the incident light. The counter electrode 16 may be separated for each pixel G and supplied with a voltage.

  A predetermined counter voltage is supplied to the counter electrode 16 from a power source included in the control unit 5. This counter voltage is such that, among the charges generated in the photoelectric conversion layer 15, charges to be collected by the pixel electrode 14 move to the pixel electrode 14, and charges having the opposite polarity to the charge move to the counter electrode 16. Its polarity is determined.

  On the semiconductor substrate 10, readout circuits 11 are formed corresponding to the pixels G. Although details of the readout circuit 11 will be described later, it includes a signal output circuit that converts the charge generated and collected by the photoelectric conversion element P of the corresponding pixel G into a voltage signal corresponding to the amount of the charge and outputs the voltage signal. .

  In the solid-state imaging device 100, among all the pixels G in two rows adjacent in the vertical direction Y, each readout circuit 11 of a plurality of adjacent pixels G (for example, two pixels G adjacent in the vertical direction). Share a part of the signal output circuit, thereby realizing a reduction in component costs and miniaturization of the solid-state imaging device 100.

  FIG. 3 is a diagram illustrating a configuration example of a readout circuit corresponding to two pixels G adjacent in the vertical direction Y among all the pixels G in two adjacent rows in the row of pixels G illustrated in FIG. is there. In FIG. 3, one of the two adjacent pixels G (one closer to the signal processing unit 3) is denoted by reference numeral 1, and the other (one farther from the signal processing unit 3) is denoted by reference numeral 2.

  The readout circuit 11 of the pixel 1 includes a readout circuit 11 a provided in the pixel 1 and a readout circuit 11 c shared by the pixel 1 and the pixel 2.

  The readout circuit 11 of the pixel 2 includes a readout circuit 11 b provided in the pixel 2 and a readout circuit 11 c shared by the pixel 1 and the pixel 2.

  The read circuit 11c includes a floating diffusion FD that is a charge storage unit formed in the semiconductor substrate 10 and a MOS circuit 207 that is connected to the floating diffusion FD.

  The MOS circuit 207 includes a reset transistor 204 for resetting the potential of the floating diffusion FD to the reset potential RD, an output transistor 205 that converts the potential of the floating diffusion FD into a voltage signal, and outputs the voltage signal. And a selection transistor 206 that performs control to output a voltage signal to the signal line S.

  A reset pulse RS is supplied from the vertical drive unit 2 to the gate electrode of the reset transistor 204. A region of the semiconductor substrate 10 below the gate electrode of the reset transistor 204 is hereinafter referred to as a reset gate. A drain region (reset drain) of the reset transistor 204 is connected to a reset power source included in the control unit 5, and a variable voltage is supplied therefrom.

  A voltage for operating the output transistor 205 is supplied to the drain of the output transistor 205 like a power supply voltage Vdd from a power supply circuit included in the control unit 5.

  A selection pulse RW is supplied from the vertical driving unit 2 to the gate electrode of the selection transistor 206.

  The read circuit 11a includes, in the semiconductor substrate 10, a connection portion C1 made of an impurity layer and a storage portion SD1 made of an impurity layer.

  The connection portion C <b> 1 electrically connects the semiconductor substrate 10 and the photoelectric conversion layer 15 in the pixel 1, and is connected to the pixel electrode 14 in the pixel 1 by a conductive plug 13.

  The storage part SD <b> 1 is provided adjacent to the connection part C <b> 1, and stores the charge that has moved to the connection part C <b> 1 through the conductive plug 13. The storage unit SD1 has the same configuration as the charge storage unit of the embedded photodiode. That is, the storage part SD1 is formed at a predetermined depth from the surface of the semiconductor substrate 10, and an impurity layer having a conductivity type opposite to the conductivity type of the storage part SD1 is formed on the storage part SD1.

  Above the region (barrier gate) between the connection portion C1 and the storage portion SD1, the gate electrode BG1 of the transistor 201a having the connection portion C1 as a source and the storage portion SD1 as a drain is provided. A fixed voltage is applied from the control unit 5 to the gate electrode BG1.

  By applying the fixed voltage to the gate electrode BG1, the barrier gate below the gate electrode BG1 functions as a potential barrier portion that becomes a potential barrier with respect to the potential of the connection portion C1.

  A floating diffusion FD is provided adjacent to the storage unit SD1.

  Above the region (transfer gate) between the storage portion SD1 and the floating diffusion FD, the gate electrode Tx1 of the transistor 203a using the storage portion SD1 as a source and the floating diffusion FD as a drain is provided. The gate electrode Tx1 functions as a charge transfer unit that transfers charges accumulated in the accumulation unit SD1 to the floating diffusion FD. The voltage supplied to the gate electrode Tx1 is controlled by the vertical drive unit 2.

  When the transfer pulse is supplied to the gate electrode Tx1 and the transistor 203a is turned on, the charge stored in the storage part SD1 is transferred to the floating diffusion FD through the transfer gate. In order to make this transfer complete, it is preferable that the storage unit SD1 is completely depleted.

  In the example of FIG. 3, the transfer gate, the gate electrode Tx1, and the readout circuit 11c included in the readout circuit 11 of the pixel 1 function as a signal output circuit in the claims.

  In the readout circuit 11 of the pixel 1 configured as described above, the electric charge collected by the pixel electrode 14 is accumulated in the accumulation unit SD1 without being accumulated in the connection unit C1. That is, the amount of charge flowing from the pixel electrode 14 to the connection portion C1 matches the amount of charge flowing from the connection portion C1 to the storage portion SD1. The accumulation unit SD1 accumulates the electric charge flowing out from the connection unit C1.

  The potential of the connection portion C1 is a potential deeper by ΔV than the potential of the barrier gate. ΔV is uniquely determined according to the amount of current flowing from the connection portion C1 to the storage portion SD1 (= the amount of current flowing from the photoelectric conversion element P to the connection portion C1). When the amount of current flowing out from the connecting portion C1 is large, ΔV is small, and when the amount of current flowing out from the connecting portion C1 is small, ΔV is large. Thus, by taking an appropriate value of ΔV according to the amount of current, the amount of charge flowing into the connecting portion C1 and the amount of charge flowing out from the connecting portion C1 into the storage portion SD1 coincide.

  The potential of the storage part SD1 is determined by the impurity concentration of the storage part SD1. In the readout circuit 11, since charges move from the connection portion C1 to the storage portion SD1, the potential of the storage portion SD1 needs to be deeper than the potential of the connection portion C1. The potential of the barrier gate and the potential of the storage part SD1 are appropriately set so as to satisfy these relative potential orders.

  In addition, when excess charge is accumulated in the accumulation unit SD1, in order to prevent this excess charge from flowing back to the connection unit C1, the potential of the transfer gate when the transistor 203a is off is set deeper than the potential of the barrier gate. doing. In this way, excess charge is discharged to the floating diffusion FD beyond the potential of the transfer gate when the transistor 203a is off.

  Further, in order to prevent the excessive charge discharged to the floating diffusion FD from flowing back to the storage part SD1, the potential of the reset gate when the reset transistor 204 is off is set to the potential of the transfer gate when the transistor 203a is off. Is also deep. In this way, excess charge is discharged to the reset drain beyond the potential of the reset gate when the reset transistor 204 is off.

  In addition, the potential when the floating diffusion FD is reset is sufficiently deeper than the potential determined by the impurity concentration of the storage portion SD1 so that charges can be transferred smoothly from the storage portion SD1 to the floating diffusion FD. .

  The read circuit 11b includes, in the semiconductor substrate 10, a connection portion C2 made of an impurity layer and a storage portion SD2 made of an impurity layer.

  The connection portion C <b> 2 electrically connects the semiconductor substrate 10 and the photoelectric conversion layer 15 in the pixel 2, and is connected to the pixel electrode 14 in the pixel 2 by the conductive plug 13.

  The storage part SD2 is provided adjacent to the connection part C2, and stores the charge that has moved to the connection part C2 through the conductive plug 13. The storage unit SD2 has the same configuration as the charge storage unit of the embedded photodiode.

  Above the region (barrier gate) between the connection portion C2 and the storage portion SD2, the gate electrode BG2 of the transistor 201b having the connection portion C2 as a source and the storage portion SD2 as a drain is provided. The fixed voltage is applied to the gate electrode BG2 from the control unit 5.

  When the fixed voltage is applied to the gate electrode BG2, the barrier gate below the gate electrode BG2 functions as a potential barrier portion that becomes a potential barrier with respect to the potential of the connection portion C2.

  A floating diffusion FD is provided adjacent to the storage part SD2.

  Above the region (transfer gate) between the storage portion SD2 and the floating diffusion FD, the gate electrode Tx2 of the transistor 203b having the storage portion SD2 as a source and the floating diffusion FD as a drain is provided. The gate electrode Tx2 functions as a charge transfer unit that transfers charges accumulated in the accumulation unit SD2 to the floating diffusion FD. The voltage supplied to the gate electrode Tx2 is controlled by the vertical drive unit 2.

  When the transfer pulse is supplied to the gate electrode Tx2 and the transistor 203b is turned on, the charge stored in the storage part SD2 is transferred to the floating diffusion FD through the transfer gate. In order to make this transfer complete, it is preferable that the storage unit SD2 is completely depleted.

  The potential of the barrier gate of the pixel 2, the potential determined by the impurity concentration of the storage portion SD2, the potential of the transfer gate when the transistor 203b is off, and the potential of the transfer gate when the transistor 203b is on are respectively , The potential determined by the impurity concentration of the storage portion SD1, the potential of the transfer gate when the transistor 203a is off, and the potential of the transfer gate when the transistor 203a is on. Similarly to the potential of the connection portion C1, the potential of the connection portion C2 is uniquely determined according to the amount of current flowing from the connection portion C2 to the storage portion SD2.

  In the example of FIG. 3, the transfer gate, the gate electrode Tx2, and the readout circuit 11c included in the readout circuit 11 of the pixel 2 function as a signal output circuit in the claims.

  The solid-state imaging device 100 has a plurality of rows of pixels G, and has readout circuits corresponding to all the pixels in each row. That is, a group of readout circuits is provided for each row. The vertical drive unit 2 supplies a drive signal independently for each group of readout circuits included in the solid-state imaging device 100.

  Next, a method for driving the solid-state imaging device 100 will be described. Below, the case where the solid-state image sensor 100 collects electrons with the pixel electrode 14 is demonstrated. The solid-state imaging device 100 performs imaging by rolling shutter driving that reads signals while shifting the exposure period for each row of pixels G.

  4 to 11 are diagrams for explaining the imaging operation of the solid-state imaging device 100 shown in FIG. 4 to 11 illustrate changes in the cross-sectional potentials of the connection portion, the barrier gate, the storage portion, the transfer gate, the floating diffusion FD, the reset gate, and the reset drain included in the two adjacent pixels illustrated in FIG. 3. .

  4 to 11, “C1” and “C2” indicate the potentials of the connection portions C1 and C2, respectively. “BG1” and “BG2” indicate the potential of the barrier gate below the gate electrode BG1 and the barrier gate below the gate electrode BG2, respectively. “SD1” and “SD2” indicate the potentials of the storage units SD1 and SD2, respectively. “Tx1” and “Tx2” indicate the potentials of the transfer gate below the gate electrode Tx1 and the transfer gate below the gate electrode Tx2, respectively. “FD”, “RS”, and “RD” indicate the potentials of the floating diffusion FD, the reset gate, and the reset drain, respectively.

  FIG. 4A in FIG. 4 shows the potential of both the pixel 1 and the pixel 2 during the exposure period. During the exposure period of the pixels 1 and 2, no transfer pulse is supplied to the gate electrodes Tx1 and Tx2, and no reset pulse is supplied to the reset gate RS. In addition, a voltage is supplied to the reset drain from the reset power supply so that the potential becomes sufficiently deeper than the reset gate potential of the pixels 1 and 2.

  As described above, during the exposure period of the pixel 1 and the pixel 2, in both the pixel 1 and the pixel 2, the potentials of the barrier gate, the transfer gate, and the reset gate are increased in this order. Further, during this exposure period, electrons are accumulated in the accumulation units SD1 and SD2, so that the potential of the accumulation units SD1 and SD2 becomes shallow according to the amount of accumulated electrons. On the other hand, since no electrons are accumulated in the connection portions C1 and C2, the potentials of the connection portions C1 and C2 are kept constant.

  In the signal readout period of the pixel 1, the vertical driver 2 first supplies a reset pulse to the gate electrode of the reset transistor 204 and turns on the selection transistor 206. Thereby, the potential becomes as shown in FIG. 4B in FIG. 4, the potential of the floating diffusion FD becomes the same as the potential of the reset drain, and the potential of the floating diffusion FD is reset.

  Next, the vertical drive unit 2 stops the supply of the reset pulse and ends the reset of the floating diffusion FD. As a result, the potential is as shown in FIG. 5A in FIG.

  When the reset of the floating diffusion FD is completed, the potential of the floating diffusion FD becomes shallower than the potential during the reset due to the capacitance division of the reset gate and the floating diffusion FD. The potential of the floating diffusion FD immediately after resetting is converted into a voltage signal by the output transistor 205, and this voltage signal is output to the signal line S as a reset level signal (reset level signal).

  Next, the vertical drive unit 2 supplies a transfer pulse to the gate electrode Tx <b> 1 of the pixel 1. As a result, the potential of the transfer gate of the pixel 1 is deeper than the potential of the storage portion SD1 and shallower than the potential of the floating diffusion FD (see FIG. 5B), and the charge stored in the storage portion SD1 of the pixel 1 is floating. It is transferred to the diffusion FD.

  Next, the vertical driving unit 2 stops supplying the transfer pulse to the gate electrode Tx1 of the pixel 1. When the transfer pulse is stopped, the exposure period of the pixel 1 is completed. By stopping the transfer pulse, the potential becomes as shown in FIG. 6A in FIG.

  After the exposure period of the pixel 1 ends, a signal (imaging signal) corresponding to the potential of the floating diffusion FD is output to the signal line S. By obtaining the difference between the imaging signal and the reset level signal, a signal from which reset noise has been removed can be obtained.

  Next, the vertical drive unit 2 changes the voltage supplied to the gate electrode Tx2 of the pixel 2 during the exposure period so that the potential of the transfer gate of the pixel 2 becomes shallower than the potential of the barrier gate of the pixel 2 and is controlled. The unit 5 changes the voltage supplied to the reset drain of the reset transistor 204 so that the reset drain potential is shallower than the barrier gate potential of the pixels 1 and 2 and deeper than the transfer gate potential of the pixel 2.

  As a result, as shown in FIG. 6B in FIG. 6, electrons are injected from the reset drain into the connection portion C1, the storage portion SD1, and the floating diffusion FD. On the other hand, in the pixel 2, since the potential of the transfer gate becomes a barrier with respect to the potential of the reset drain, electrons are not injected into the connection portion C2 and the storage portion SD2.

  Next, the control unit 5 returns the voltage supplied to the reset drain to the value shown in FIG. 6A, and the vertical drive unit 2 returns the voltage supplied to the gate electrode Tx2 to the state shown in FIG. 6A. Thereafter, the vertical driving unit 2 supplies a transfer pulse to the gate electrode Tx1 and supplies a reset pulse to the gate electrode of the reset transistor 204.

  Thereby, as shown in FIG. 7A in FIG. 7, the electrons injected into the storage portion SD1 and the floating diffusion FD of the pixel 1 are discharged to the reset drain. At this time, the electrons 70 injected into the connection portion C1 remain as they are without being discharged to the reset drain. Thereby, the connection part C1 is initialized.

  Next, the vertical drive unit 2 stops supplying the transfer pulse to the gate electrode Tx1, stops supplying the reset pulse to the gate electrode of the reset transistor 204, and turns off the selection transistor 206. With the stop of the transfer pulse, the signal reading period of the pixel 1 is ended, and the exposure period of the next frame is started (FIG. 7B in FIG. 7).

  When the exposure period of the pixel 1 is started, the electrons injected into the connection part C1 move to the storage part SD1 with the passage of time, and the potential of the connection part C1 is the amount of current flowing into the connection part C1, During the elapsed time after the charge injection, the potential settles uniquely depending on the potential of the barrier gate and the like.

  Subsequently, the signal reading of the pixel 2 is performed. In the signal readout period of the pixel 2, the vertical driver 2 first supplies a reset pulse to the gate electrode of the reset transistor 204 and turns on the selection transistor 206. Thereby, the potential becomes as shown in FIG. 8A in FIG. 8, the potential of the floating diffusion FD becomes the same as the potential of the reset drain, and the potential of the floating diffusion FD is reset.

  Next, the vertical drive unit 2 stops the supply of the reset pulse and ends the reset of the floating diffusion FD. As a result, the potential is as shown in FIG. 8B in FIG.

  The potential of the floating diffusion FD immediately after resetting is converted into a voltage signal by the output transistor 205, and this voltage signal is output to the signal line S as a reset level signal (reset level signal).

  Next, the vertical drive unit 2 supplies a transfer pulse to the gate electrode Tx <b> 2 of the pixel 2. As a result, the potential of the transfer gate of the pixel 2 is deeper than the potential of the storage portion SD2 and shallower than the potential of the floating diffusion FD (see FIG. 9A), and the charge stored in the storage portion SD2 of the pixel 2 is floating. It is transferred to the diffusion FD.

  Next, the vertical drive unit 2 stops supplying the transfer pulse to the gate electrode Tx2 of the pixel 2. The exposure period of the pixel 2 ends with the stop of the transfer pulse. By stopping the transfer pulse, the potential becomes as shown in FIG. 9B in FIG.

  After the exposure period of the pixel 2 ends, a signal (imaging signal) corresponding to the potential of the floating diffusion FD is output to the signal line S. By obtaining the difference between the imaging signal and the reset level signal, a signal from which reset noise has been removed can be obtained.

  Next, the vertical drive unit 2 changes the voltage supplied to the gate electrode Tx1 of the pixel 1 during the exposure period so that the potential of the transfer gate of the pixel 1 becomes shallower than the potential of the barrier gate of the pixel 1 and is controlled. The unit 5 changes the reset voltage supplied to the reset drain of the reset transistor 204 so that the potential of the reset drain is shallower than the potential of the barrier gates of the pixels 1 and 2 and deeper than the potential of the transfer gate of the pixel 1.

  As a result, as shown in FIG. 10A in FIG. 10, electrons are injected from the reset drain into the connection portion C2, the storage portion SD2, and the floating diffusion FD. On the other hand, in the pixel 1, since the potential of the transfer gate becomes a barrier with respect to the potential of the reset drain, electrons are not injected into the connection portion C1 and the storage portion SD1.

  Next, the control unit 5 returns the voltage supplied to the reset drain to the value shown in FIG. 9B, and the vertical drive unit 2 returns the voltage supplied to the gate electrode Tx1 to the state shown in FIG. 9B. Thereafter, the vertical driving unit 2 supplies a transfer pulse to the gate electrode Tx2 and supplies a reset pulse to the gate electrode of the reset transistor 204.

  Thereby, as shown in FIG. 10B of FIG. 10, the electrons injected into the storage portion SD2 and the floating diffusion FD of the pixel 2 are discharged to the reset drain. At this time, the electrons 71 injected into the connection portion C2 remain as they are without being discharged to the reset drain. Thereby, the connection part C2 is initialized.

  Next, the vertical drive unit 2 stops supplying the transfer pulse to the gate electrode Tx2, stops supplying the reset pulse to the gate electrode of the reset transistor 204, and turns off the selection transistor 206. When the transfer pulse is stopped, the signal reading period of the pixel 2 is ended, and the exposure period of the next frame is started (FIG. 11).

  When the exposure period of the pixel 2 is started, electrons injected into the connection part C2 move to the storage part SD2 with the passage of time, and the potential of the connection part C2 is the amount of current flowing into the connection part C2, During the elapsed time after the charge injection, the potential settles uniquely depending on the potential of the barrier gate and the like.

  Thereafter, the state returns to the state of FIG. 4A. Such an operation is repeatedly performed during imaging.

  Since the pixel 1 and the pixel 2 are adjacent to each other, the time from the completion of the charge injection to the connection portion C1 in FIG. 7B of FIG. 7 until the completion of the charge injection to the connection portion C2 in FIG. Very short. For this reason, in FIGS. 7 to 11, it is illustrated that no charge is accumulated in the accumulation unit SD1 after the exposure of the pixel 1 is started.

  FIG. 12 shows the above operation in a timing chart. In FIG. 12, “C1”, “C2”, “SD1”, “SD2”, “FD”, and “RD” are a connection unit C1, a connection unit C2, a storage unit SD1, a storage unit SD2, and a floating diffusion FD, respectively. The reset drain potential is shown, and the lower the waveform is, the shallower the potential is. “BG1”, “BG2”, “Tx1”, “Tx2”, and “RW” are supplied to the gate electrode BG1, the gate electrode BG2, the gate electrode Tx1, the gate electrode Tx2, and the gate electrode of the selection transistor, respectively. A pulse waveform is shown.

  As described above, according to the solid-state imaging device 100, electrons are injected from the reset drain into the connection portion C1 (connection portion C2) of the pixel 1 (pixel 2) after the exposure is completed, so that the connection portion C1 (connection portion C2) Since the next exposure period of the pixel 1 (pixel 2) can be started after initialization, the occurrence of an afterimage can be suppressed.

  Further, according to the solid-state imaging device 100, since the readout circuit 11c is shared by the pixel 1 and the pixel 2, the device area can be reduced as compared with the configuration in which the readout circuit 11c is separately provided in the pixel 1 and the pixel 2. It becomes possible.

  Also, according to the solid-state imaging device 100, when electrons are injected into the connection portion of one of the two pixels sharing the readout circuit 11c, the potential of the transfer gate of the other pixel is set higher than the potential of the reset drain. Since it is shallow, electrons can be prevented from being injected into the connection portion and the storage portion of the other pixel, and afterimage of one pixel is suppressed without affecting the output signal of the other pixel. be able to.

  In the above description, only the operation for the pixels in the two adjacent rows is described. However, for example, when electrons are injected into the connection portion of the pixels in the first row, the readout circuit 11c is shared with the pixels in the first row. It is not necessary to change the potential of the transfer gate only for the pixels in the second row and change the potential of the transfer gate for the pixels in the other rows. In this case, since the pixels in the other rows are in the exposure period, there is no problem even if the potential of the transfer gate is made shallower than the potential of the reset drain. Since the number of times of OFF can be reduced, power consumption can be reduced.

  In addition, when electrons are injected into a connection portion of a pixel in a certain row, the potentials of the transfer gates of pixels in all rows other than this row may be changed. In this way, driving can be simplified.

  In the above description, when charge is injected into a pixel in a certain row, no pulse is supplied to the transfer gate Tx of the pixel to be injected, but a pulse having the same voltage as that during transfer may be supplied. In this case as well, charge injection can be performed similarly.

  In the above description, the operations shown in FIGS. 4 to 11 are continuously repeated. However, the exposure is performed between the start of exposure of pixel 2 in FIG. 11 and the readout of pixel 1 in FIG. 4 (signal accumulation period in FIG. 12). Electronic shutter drive (drive for discharging the charge in the storage portion) for period control may be performed.

  Next, a modification of the readout circuit of the solid-state image sensor 100 will be described.

(First modification)
FIG. 13 is a diagram showing a modification of the readout circuit 11 of the solid-state imaging device 100 shown in FIG. 1, and corresponds to FIG.

  In the example shown in FIG. 13, the readout circuit 11 of the pixel 1 includes a photoelectric conversion element P and readout circuit 11 a ′ provided in the pixel 1, and a drain D shared by the pixel 1 and the pixel 2. . Further, the readout circuit 11 of the pixel 2 includes a photoelectric conversion element P and readout circuit 11 b ′ provided in the pixel 2 and a drain D.

  The readout circuit 11a 'has the same configuration as that of FIG. 3 in which the transistor 203a of the readout circuit 11 of the pixel 1 is deleted and the drain of the transistor 201a is a floating diffusion FD.

  Specifically, the readout circuit 11a ′ includes the connection portion C1, the floating diffusion FD1 provided adjacent to the connection portion C1, and the gate electrode BG1 provided above the barrier gate between the connection portion C1 and the floating diffusion FD1. A reset transistor 302a that resets the potential of the floating diffusion FD1, an output transistor 303a that converts the potential of the floating diffusion FD1 into a voltage signal, and a control that outputs the converted voltage signal to the signal line S by the output transistor 303a. A selection transistor 304a.

  The connection portion C1, the floating diffusion FD1, and the gate electrode BG1 constitute a transistor 301a.

  A drain D is provided adjacent to the floating diffusion FD1, and a gate electrode RS1 of the reset transistor 302a is provided above the reset gate between the floating diffusion FD1 and the drain D.

  A voltage for operating the output transistor 303a, such as a power supply voltage Vdd, is supplied to the drain of the output transistor 303a from a power supply circuit included in the control unit 5.

  A selection pulse RW1 is supplied from the vertical drive unit 2 to the gate electrode of the selection transistor 304a.

  In the readout circuit 11 of the pixel 1 configured as described above, the electric charge collected by the pixel electrode 14 is accumulated in the floating diffusion FD1 without being accumulated in the connection portion C1.

  That is, the amount of charge that flows from the pixel electrode 14 to the connection portion C1 matches the amount of charge that flows from the connection portion C1 to the floating diffusion FD1. The floating diffusion FD1 accumulates the electric charge that has flowed out from the connection portion C1.

  The potential of the connection portion C1 is a potential deeper by ΔV than the potential of the barrier gate. ΔV is uniquely determined according to the amount of current flowing from the connection portion C1 to the storage portion SD1 (= the amount of current flowing from the photoelectric conversion element P to the connection portion C1). When the amount of current flowing out from the connecting portion C1 is large, ΔV is small, and when the amount of current flowing out from the connecting portion C1 is small, ΔV is large. Thus, by taking an appropriate value of ΔV according to the amount of current, the amount of charge flowing into the connection portion C1 and the amount of charge flowing out from the connection portion C1 to the floating diffusion FD1 coincide.

  The initial potential of the floating diffusion FD1 (the potential at the start of charge accumulation) is sufficiently deeper than the potential of the connection portion C1.

  In addition, when excessive charge is accumulated in the floating diffusion FD1, the potential of the reset gate when the reset transistor 302a is off is set to be higher than the potential of the barrier gate in order to prevent the excessive charge from flowing back to the connection portion C1. It ’s deep. In this way, excess charge is discharged to the drain D beyond the potential of the reset gate when the reset transistor 302a is off.

  In the example of FIG. 13, the transistors 302a, 303a, and 304a included in the readout circuit 11 of the pixel 1 function as a signal output circuit in the claims.

  The readout circuit 11b 'has the same configuration as that of FIG. 3 in which the transistor 203b of the readout circuit 11 of the pixel 2 is deleted and the drain of the transistor 201b is a floating diffusion FD.

  Specifically, the readout circuit 11b ′ includes the connection portion C2, the floating diffusion FD2 provided adjacent to the connection portion C2, and the gate electrode BG2 provided above the barrier gate between the connection portion C2 and the floating diffusion FD2. A reset transistor 302b that resets the potential of the floating diffusion FD2, an output transistor 303b that converts the potential of the floating diffusion FD2 into a voltage signal, and a control that outputs the converted voltage signal to the signal line S by the output transistor 303b. And a selection transistor 304b.

  The connection portion C2, the floating diffusion FD2, and the gate electrode BG2 constitute a transistor 301b.

  A drain D is provided adjacent to the floating diffusion FD2, and a gate electrode RS2 of the reset transistor 302b is provided above the reset gate between the floating diffusion FD2 and the drain D.

  A voltage for operating the output transistor 303b, such as a power supply voltage Vdd, is supplied to the drain of the output transistor 303b from the power supply circuit included in the control unit 5.

  A selection pulse RW2 is supplied from the vertical drive unit 2 to the gate electrode of the selection transistor 304b.

  The characteristics of the transistors 301b, 302b, 303b, and 304b are the same as the characteristics of the transistors 301a, 302a, 303a, and 304a.

  In the example of FIG. 13, the transistors 302b, 303b, and 304b included in the readout circuit 11 of the pixel 2 function as a signal output circuit in the claims.

  As described above, in the modification shown in FIG. 13, each of the pixel 1 and the pixel 2 includes a MOS circuit composed of four transistors, and the drain D of the reset transistor is composed of the MOS circuit of the pixel 1 and the MOS circuit of the pixel 2. Is configured to share.

  Next, a method for driving the solid-state imaging device 100 having the circuit shown in FIG. 13 as a readout circuit will be described. Below, the case where the solid-state image sensor 100 collects electrons with the pixel electrode 14 is demonstrated. The solid-state imaging device 100 performs imaging by rolling shutter driving that reads signals while shifting the exposure period for each row of pixels G.

  14 to 18 are diagrams for explaining an example of a method for driving the solid-state imaging device 100 having the circuit shown in FIG. 13 as a readout circuit. 14 to 18 illustrate changes in the cross-sectional potentials of the connection portions C1 and C2, the barrier gate, the floating diffusions FD1 and FD2, the reset gate, and the drain D included in the two adjacent pixels illustrated in FIG.

  14 to 18, “C1” and “C2” indicate the potentials of the connection portions C1 and C2, respectively. “BG1” and “BG2” indicate the potential of the barrier gate below the gate electrode BG1 and the barrier gate below the gate electrode BG2, respectively. “FD1” and “FD2” indicate the potentials of the floating diffusions FD1 and FD2, respectively. “RD” indicates the potential of the drain D.

  FIG. 14A in FIG. 14 shows the potential of both the pixel 1 and the pixel 2 during the exposure period. During the exposure period of the pixels 1 and 2, no reset pulse is supplied to the reset gates RS1 and RS2. In addition, a voltage is supplied to the drain D from a reset power supply so that the drain D has a potential sufficiently deeper than the potential of the reset gates of the pixels 1 and 2.

  As described above, during the exposure period of the pixel 1 and the pixel 2, the potentials of the barrier gate and the reset gate are deepened in this order in both the pixel 1 and the pixel 2. Further, since electrons are accumulated in the floating diffusions FD1, FD2 during this exposure period, the potentials of the floating diffusions FD1, FD2 become shallow according to the amount of accumulated electrons. On the other hand, since no electrons are accumulated in the connection portions C1 and C2, the potentials of the connection portions C1 and C2 are kept constant.

  During the signal readout period of the pixel 1, first, the vertical drive unit 2 supplies the selection pulse RW to the gate electrode of the selection transistor 304a, and turns on the selection transistor 304a. As a result, a voltage signal (imaging signal) corresponding to the potential of the floating diffusion FD1 is output to the signal line S (FIG 14B in FIG. 14).

  Next, the vertical drive unit 2 supplies a reset pulse to the gate electrode RS1 of the reset transistor 302a, and ends the exposure period of the pixel 1 with the start of supply of the reset pulse. As a result, the potential becomes as shown in FIG. 14C in FIG. 14, the potential of the floating diffusion FD1 becomes the same as the potential of the drain D, and the potential of the floating diffusion FD1 is reset.

  Next, the vertical drive unit 2 stops the supply of the reset pulse and ends the reset of the floating diffusion FD1. As a result, the potential becomes as shown in FIG. 15A in FIG.

  The potential of the floating diffusion FD1 immediately after reset is converted into a voltage signal by the output transistor 303a, and this voltage signal is output to the signal line S as a reset level signal. By obtaining the difference between the imaging signal and the reset level signal, a signal from which reset noise has been removed can be obtained.

  Next, the vertical drive unit 2 changes the voltage supplied to the gate electrode RS2 of the pixel 2 during the exposure period so that the potential of the reset gate of the pixel 2 is shallower than the potential of the barrier gate of the pixel 2. At the same time, the control unit 5 changes the reset voltage supplied to the drain D, and the potential of the drain D is shallower than the potential of the barrier gates of the pixels 1 and 2 and deeper than the potential of the reset gate of the pixel 2. To do.

  As a result, as shown in FIG. 15B in FIG. 15, electrons are injected from the drain D into the connection portion C1 and the floating diffusion FD1. On the other hand, in the pixel 2, since the potential of the reset gate becomes a barrier with respect to the potential of the drain D, electrons are not injected into the connection portion C2 and the floating diffusion FD2.

  Next, the control unit 5 returns the drain D potential to the value shown in FIG. 15A, and the vertical drive unit 2 returns the reset gate potential of the pixel 2 to the state shown in FIG. 15A. Thereafter, the vertical driving unit 2 supplies a reset pulse to the gate electrode RS1.

  Thereby, the electrons injected into the floating diffusion FD1 of the pixel 1 are discharged to the drain D as shown in FIG. 15C of FIG. At this time, the electrons 72 injected into the connection portion C1 remain as they are without being discharged to the drain D. Thereby, the connection part C1 is initialized.

  Next, the vertical drive unit 2 stops supplying the reset pulse to the gate electrode RS1 and turns off the selection transistor 304b. When the reset pulse is stopped, the signal readout period of the pixel 1 is ended, and the exposure period of the next frame is started (FIG. 16A in FIG. 16).

  When the exposure period of the pixel 1 is started, electrons injected into the connection portion C1 move to the floating diffusion FD1 as time passes, and the potential of the connection portion C1 is the amount of current flowing into the connection portion C1. During the elapsed time after the charge injection, the potential settles uniquely depending on the potential of the barrier gate and the like.

  Subsequently, signal reading of the pixel 2 is performed. In the signal readout period of the pixel 2, first, the vertical drive unit 2 supplies the selection pulse RW to the gate electrode of the selection transistor 304b to turn on the selection transistor 304b. Thereby, a voltage signal (imaging signal) corresponding to the potential of the floating diffusion FD2 is output to the signal line S (FIG. 16B in FIG. 16).

  Next, the vertical driving unit 2 supplies a reset pulse to the gate electrode RS2, and ends the exposure period of the pixel 2 with the start of supply of the reset pulse. Thereby, the potential becomes as shown in FIG. 16C in FIG. 16, the potential of the floating diffusion FD2 becomes the same as the potential of the drain D, and the potential of the floating diffusion FD2 is reset.

  Next, the vertical drive unit 2 stops the supply of the reset pulse and ends the reset of the floating diffusion FD2. As a result, the potential is as shown in FIG. 17A in FIG.

  The potential of the floating diffusion FD2 immediately after the reset is converted into a voltage signal by the output transistor 303b, and this voltage signal is output to the signal line S as a reset level signal. By obtaining the difference between the imaging signal and the reset level signal, a signal from which reset noise has been removed can be obtained.

  Next, the vertical drive unit 2 changes the voltage supplied to the gate electrode RS1 of the pixel 1 during the exposure period so that the potential of the reset gate of the pixel 1 is shallower than the potential of the barrier gate of the pixel 1. At the same time, the control unit 5 changes the reset voltage supplied to the drain D, so that the potential of the drain D is shallower than the potential of the barrier gates of the pixels 1 and 2 and deeper than the potential of the reset gate of the pixel 1. To do.

  As a result, as shown in FIG. 17B of FIG. 17, electrons are injected from the drain D into the connection portion C2 and the floating diffusion FD2. On the other hand, in the pixel 1, since the potential of the reset gate becomes a barrier with respect to the potential of the drain D, electrons are not injected into the connection portion C1 and the floating diffusion FD1.

  Next, the control unit 5 returns the drain D potential to the value shown in FIG. 17A, and the vertical drive unit 2 returns the reset gate potential of the pixel 1 to the state shown in FIG. 17A. Thereafter, the vertical drive unit 2 supplies a reset pulse to the gate electrode RS2.

  Thereby, the electrons injected into the floating diffusion FD2 of the pixel 2 are discharged to the drain D as shown in FIG. 17C of FIG. At this time, the electrons 73 injected into the connection portion C2 remain as they are without being discharged to the drain D. Thereby, the connection part C2 is initialized.

  Next, the vertical drive unit 2 stops supplying the reset pulse to the gate electrode RS2, and turns off the selection transistor 304b. When the reset pulse is stopped, the signal readout period of the pixel 2 is ended and the exposure period of the next frame is started (FIG. 18).

  When the exposure period of the pixel 2 is started, the electrons injected into the connection portion C2 move to the floating diffusion FD2 with the passage of time, and the potential of the connection portion C2 is the amount of current flowing into the connection portion C2. During the elapsed time after the charge injection, the potential settles uniquely depending on the potential of the barrier gate.

  Thereafter, the state returns to the state of FIG. 14A. Such an operation is repeatedly performed during imaging.

  Since the pixel 1 and the pixel 2 are adjacent to each other, the time from the completion of the charge injection to the connection portion C1 in FIG. 16A of FIG. 16 until the completion of the charge injection to the connection portion C2 in FIG. Very short. For this reason, in FIGS. 16 to 18, the charge is not accumulated in the floating diffusion FD <b> 1 after the exposure of the pixel 1 is started.

  FIG. 19 shows the above operation in a timing chart. In FIG. 19, “C1”, “C2”, “FD1”, “FD2”, and “RD” indicate the potentials of the connection portion C1, the connection portion C2, the floating diffusion FD1, the floating diffusion FD2, and the drain D, respectively. The lower the waveform is, the shallower the potential is. “BG1”, “BG2”, “RS1”, “RS2”, “RW1”, and “RW2” are the gate electrode BG1, the gate electrode BG2, the gate electrode RS1, the gate electrode RS2, and the gate of the selection transistor 304b, respectively. The pulse waveform supplied to the electrode and the gate electrode of the selection transistor 304a is shown.

  As described above, the afterimage can also be suppressed by using the circuit configuration shown in FIG.

  In the circuit configuration shown in FIG. 13, an overflow drain structure that discharges charges exceeding the saturation capacity of the floating diffusions FD1 and FD2 to the substrate side is realized by the reset gates and drains D of the reset transistors 304a and 304b. The overflow structure may be additionally provided as another structure other than the reset transistors 304a and 304b. As shown in FIG. 13, by realizing the overflow drain structure using the reset transistors 304a and 304b, it is not necessary to add a structure, and pixel miniaturization is facilitated.

  Further, when considering only the overflow structure, the deeper the reset gate potential (the potential when the reset transistor is off) of the reset transistors 304a and 304b, the better. However, since the saturation charge number of the floating diffusion is determined by the capacity and potential amplitude of the floating diffusion, if the potential of the reset gate is increased, the potential amplitude of the floating diffusion is decreased, and the saturation charge number is decreased. Accordingly, the potential of each reset gate when the reset transistors 304a and 304b are off should be set in a range (for example, 0.1 V to 0.3 V) in consideration of the number of saturated charges and the characteristics of the overflow structure. preferable.

  In the above description, the operations shown in FIGS. 14 to 18 are continuously repeated. However, the exposure is performed between the start of exposure of pixel 2 in FIG. 18 and the readout of pixel 1 in FIG. 14 (signal accumulation period in FIG. 19). Electronic shutter driving (driving for discharging the charges of the floating diffusion) for period control may be performed.

  Next, another example of a method for driving the solid-state imaging device 100 having the circuit shown in FIG. 13 as a readout circuit will be described. Below, the case where the solid-state image sensor 100 collects electrons with the pixel electrode 14 is demonstrated. The solid-state imaging device 100 performs imaging by rolling shutter driving that reads signals while shifting the exposure period for each row of pixels G.

  20 to 22 are diagrams for explaining another example of the driving method of the solid-state imaging device 100 having the circuit shown in FIG. 13 as a readout circuit. 20 to 22 illustrate changes in the cross-sectional potentials of the connection portions C1 and C2, the barrier gate, the floating diffusions FD1 and FD2, the reset gate, and the drain D included in the two adjacent pixels illustrated in FIG.

  The notations in FIGS. 20 to 22 are the same as the contents shown in FIG.

  FIG. 20A in FIG. 20 shows the potential of both the pixel 1 and the pixel 2 during the exposure period. During the exposure period of the pixels 1 and 2, no reset pulse is supplied to the reset gates RS1 and RS2. In addition, a voltage is supplied to the drain D from a reset power supply so that the drain D has a potential sufficiently deeper than the potential of the reset gates of the pixels 1 and 2.

  As described above, during the exposure period of the pixel 1 and the pixel 2, the potentials of the barrier gate and the reset gate are deepened in this order in both the pixel 1 and the pixel 2. Further, since electrons are accumulated in the floating diffusions FD1, FD2 during this exposure period, the potentials of the floating diffusions FD1, FD2 become shallow according to the amount of accumulated electrons. On the other hand, since no electrons are accumulated in the connection portions C1 and C2, the potentials of the connection portions C1 and C2 are kept constant.

  During the signal readout period of the pixel 1, first, the vertical drive unit 2 supplies the selection pulse RW to the gate electrode of the selection transistor 304a, and turns on the selection transistor 304a. As a result, a voltage signal (imaging signal) corresponding to the potential of the floating diffusion FD1 is output to the signal line S (FIG. 20B in FIG. 20).

  Next, the vertical drive unit 2 changes the voltage supplied to the gate electrode RS2 of the pixel 2 so that the potential of the reset gate of the pixel 2 is shallower than the potential of the barrier gate of the pixel 2. At the same time, the control unit 5 changes the reset voltage supplied to the drain D, and the drain D potential is shallower than the barrier gate potential of the pixels 1 and 2 and deeper than the reset gate potential of the pixel 2. To do. The exposure period of the pixel 1 ends with the start of changing the reset gate potential and the drain D potential of the pixel 2.

  As a result, as shown in FIG. 20C in FIG. 20, electrons are injected from the drain D into the connection portion C1 and the floating diffusion FD1. On the other hand, in the pixel 2, since the potential of the reset gate becomes a barrier with respect to the potential of the drain D, electrons are not injected into the connection portion C2 and the floating diffusion FD2.

  Next, the control unit 5 returns the drain D potential to the value shown in FIG. 20B, and the vertical drive unit 2 returns the reset gate potential of the pixel 2 to the state shown in FIG. 20B. Thereafter, the vertical driving unit 2 supplies a reset pulse to the gate electrode RS1.

  Thereby, as shown in FIG. 21A of FIG. 21, the electrons injected into the floating diffusion FD1 of the pixel 1 are discharged to the drain D. At this time, the electrons 74 injected into the connection portion C1 remain as they are without being discharged to the drain D. Thereby, the connection part C1 is initialized.

  Next, the vertical drive unit 2 stops the supply of the reset pulse to the gate electrode RS1, and ends the reset of the floating diffusion FD1. When the reset pulse supply is stopped, the signal reading period of the pixel 1 is ended, and the next exposure period is started. As a result, the potential is as shown in FIG. 21B of FIG.

  The potential of the floating diffusion FD1 immediately after reset is converted into a voltage signal by the output transistor 303a, and this voltage signal is output to the signal line S as a reset level signal. By obtaining the difference between the imaging signal and the reset level signal, a signal from which reset noise has been removed can be obtained.

  Next, the vertical drive unit 2 turns off the selection transistor 304a.

  Subsequently, signal reading of the pixel 2 is performed. In the signal readout period of the pixel 2, first, the vertical drive unit 2 supplies the selection pulse RW to the gate electrode of the selection transistor 304b to turn on the selection transistor 304b. As a result, a voltage signal (imaging signal) corresponding to the potential of the floating diffusion FD2 is output to the signal line S (FIG. 21C in FIG. 21).

  Next, the vertical drive unit 2 changes the voltage supplied to the gate electrode RS1 of the pixel 1 so that the potential of the reset gate of the pixel 1 is shallower than the potential of the barrier gate of the pixel 1. At the same time, the control unit 5 changes the reset voltage supplied to the drain D, so that the potential of the drain D is shallower than the potential of the barrier gates of the pixels 1 and 2 and deeper than the potential of the reset gate of the pixel 1. To do. The exposure period of the pixel 2 ends with the start of the change of the reset gate potential and the drain D potential of the pixel 1.

  As a result, as shown in FIG. 22A in FIG. 22, electrons are injected from the drain D into the connection portion C2 and the floating diffusion FD2. On the other hand, in the pixel 1, since the potential of the reset gate becomes a barrier with respect to the potential of the drain D, electrons are not injected into the connection portion C1 and the floating diffusion FD1.

  Next, the control unit 5 returns the drain D potential to the value shown in FIG. 21C, and the vertical drive unit 2 returns the reset gate potential of the pixel 1 to the state shown in FIG. 21C. Thereafter, the vertical drive unit 2 supplies a reset pulse to the gate electrode RS2.

  Thereby, the electrons injected into the floating diffusion FD2 of the pixel 2 are discharged to the drain D as shown in FIG. 22B of FIG. At this time, the electrons 75 injected into the connection portion C2 remain as they are without being discharged to the drain D. Thereby, the connection part C2 is initialized.

  Next, the vertical drive unit 2 stops supplying the reset pulse to the gate electrode RS2, and ends the reset of the floating diffusion FD2. With the stop of the supply of the reset pulse, the signal reading period of the pixel 2 is ended, and the next exposure period is started. As a result, the potential is as shown in FIG. 22C in FIG.

  The potential of the floating diffusion FD2 immediately after the reset is converted into a voltage signal by the output transistor 303b, and this voltage signal is output to the signal line S as a reset level signal. By obtaining the difference between the imaging signal and the reset level signal, a signal from which reset noise has been removed can be obtained.

  Next, the vertical drive unit 2 turns off the selection transistor 304b.

  Thereafter, the state returns to the state of FIG. Such an operation is repeatedly performed during imaging.

  FIG. 23 shows the above operation in a timing chart. The notation shown in FIG. 23 is the same as that shown in FIG.

  In the description so far, the barrier gate is configured by a transistor, but it is also possible to configure the barrier gate by using an impurity layer having a different concentration and conductivity type from the connection portions C1 and C2. In this case, the same effect as described above can be obtained.

  As described above, the following items are disclosed in this specification.

  The disclosed solid-state imaging device is a solid-state imaging device having a plurality of photoelectric conversion elements including a pair of electrodes stacked above a semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes, corresponding to the photoelectric conversion elements A read circuit that reads a signal generated by the photoelectric conversion element and a drive unit that drives the read circuit, and the read circuit includes the photoelectric conversion layer and the semiconductor substrate of the corresponding photoelectric conversion element. A connection portion formed in the semiconductor substrate for electrical connection; and a potential barrier portion provided adjacent to the connection portion in the semiconductor substrate and serving as a potential barrier with respect to the potential of the connection portion; A first charge storage portion provided in the semiconductor substrate adjacent to the potential barrier portion, wherein the charge generated in the photoelectric conversion layer is stored via the connection portion and the potential barrier portion; A signal output circuit that outputs a signal corresponding to the charge stored in one charge storage unit, wherein the signal output circuit includes a charge injection unit that injects charge into the connection unit, and a plurality of adjacent photoelectric transistors The read circuit corresponding to the conversion element shares the charge injection unit, and the drive unit includes a first read circuit that is one of the plurality of read circuits sharing the charge injection unit. When the charge injection driving is performed by injecting charges into the connection portion from the charge injection portion so that the connection portion and the potential barrier portion of the first readout circuit have the same potential. Controlling the signal output circuit of the second readout circuit other than the first readout circuit among the plurality of readout circuits sharing the charge injection unit, and the first charge accumulation of the second readout circuit Part and said And it forms an injection potential barrier as a barrier to the potential of the charge injection unit between the charge injection unit.

  In the disclosed solid-state imaging device, the signal output circuit includes the second charge accumulation unit, a transfer gate that transfers the charge accumulated in the first charge accumulation unit to the second charge accumulation unit, And a circuit that outputs a signal corresponding to the potential of the second charge storage unit, and the driving unit controls the potential of the transfer gate to form the injection potential barrier.

  In the disclosed solid-state imaging device, the signal output circuit includes a reset transistor for resetting the potential of the second charge storage unit, and the charge injection unit is a drain of the reset transistor.

  In the disclosed solid-state imaging device, the signal output circuit includes a reset transistor for resetting the potential of the first charge storage unit, the charge injection unit is a drain of the reset transistor, and the driving unit Controls the gate potential of the reset transistor to form the injection potential barrier.

  In the disclosed solid-state imaging device, the driving unit performs driving to form the injection potential barrier only for the readout circuit to be subjected to the charge injection driving.

  In the disclosed solid-state imaging device, the drive unit controls the signal output circuit for the read circuit other than the read circuit to be subjected to the charge injection drive, and the first charge accumulation of the read circuit is performed. And driving to form an injection potential barrier that becomes a barrier against the potential of the charge injection portion between the charge injection portion and the charge injection portion.

  The disclosed imaging device includes the solid-state imaging device.

  The disclosed method for driving a solid-state imaging device is a method for driving a solid-state imaging device having a plurality of photoelectric conversion elements including a pair of electrodes stacked above a semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes. The image sensor is provided corresponding to the photoelectric conversion element, and includes a read circuit that reads a signal generated by the photoelectric conversion element, and the read circuit includes the photoelectric conversion layer and the semiconductor substrate of the corresponding photoelectric conversion element. A connection portion formed in the semiconductor substrate for electrically connecting the connection portion, and a potential barrier portion provided in the semiconductor substrate adjacent to the connection portion and serving as a potential barrier with respect to the potential of the connection portion And a first charge storage unit provided in the semiconductor substrate adjacent to the potential barrier unit, in which charges generated in the photoelectric conversion layer are stored via the connection unit and the potential barrier unit, A signal output circuit that outputs a signal corresponding to the charge accumulated in the first charge accumulation unit, wherein the signal output circuit includes a charge injection unit that injects a charge into the connection unit, and a plurality of adjacent ones The readout circuit corresponding to the photoelectric conversion element shares the charge injection unit, and is connected to the connection unit of the first readout circuit which is one of the plurality of readout circuits sharing the charge injection unit. When charge injection is performed by injecting charge from the charge injection unit to bring the connection portion of the first readout circuit and the potential barrier unit to the same potential, and when performing the charge injection drive, the charge injection unit is Controlling the signal output circuit of the second readout circuit other than the first readout circuit among the plurality of readout circuits shared, and the charge storage unit and the charge of the second readout circuit With the injection part And it has a driving step for driving that forms an injection potential barrier as a barrier to the potential of the charge injection unit between.

  In the disclosed solid-state imaging device driving method, the signal output circuit transfers the second charge accumulation unit and the charge accumulated in the first charge accumulation unit to the second charge accumulation unit. A gate and a circuit for outputting a signal corresponding to the potential of the second charge storage unit, and in the driving step, the injection potential barrier is formed by controlling the potential of the transfer gate.

  In the disclosed solid-state imaging device driving method, the signal output circuit includes a reset transistor for resetting the potential of the second charge storage unit, and the charge injection unit is a drain of the reset transistor. It is.

  In the disclosed solid-state imaging device driving method, the signal output circuit includes a reset transistor for resetting a potential of the first charge storage unit, and the charge injection unit is a drain of the reset transistor, In the driving step, the injection potential barrier is formed by controlling the gate potential of the reset transistor.

  In the disclosed solid-state imaging device driving method, in the driving step, only the readout circuit to be subjected to the charge injection driving is driven to form the injection potential barrier.

  In the driving method of the disclosed solid-state imaging device, in the driving step, for the readout circuit other than the readout circuit to be subjected to the charge injection driving, the signal output circuit is controlled to control the first of the readout circuit. Drive is performed to form an injection potential barrier that becomes a barrier against the potential of the charge injection portion between the charge storage portion and the charge injection portion.

1, 2, G Pixel 10 Semiconductor substrate P Photoelectric conversion element C1, C2 Connection part FD1, FD2 Floating diffusion

Claims (13)

A solid-state imaging device having a plurality of photoelectric conversion elements including a pair of electrodes stacked above a semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes,
A readout circuit that is provided corresponding to the photoelectric conversion element and reads a signal generated by the photoelectric conversion element;
A drive unit for driving the readout circuit,
The readout circuit includes a connection portion formed in the semiconductor substrate for electrically connecting the photoelectric conversion layer of the corresponding photoelectric conversion element and the semiconductor substrate, and adjacent to the connection portion in the semiconductor substrate. And a potential barrier portion serving as a potential barrier with respect to the potential of the connection portion, and provided in the semiconductor substrate adjacent to the potential barrier portion, and the charge generated in the photoelectric conversion layer is the connection portion And a first charge storage section that is stored via the potential barrier section, and a signal output circuit that outputs a signal corresponding to the charge stored in the first charge storage section,
The signal output circuit includes a charge injection unit that injects a charge into the connection unit,
The readout circuits corresponding to the plurality of adjacent photoelectric conversion elements share the charge injection unit,
The drive unit injects charges from the charge injection unit into the connection unit of the first read circuit, which is one of the plurality of read circuits sharing the charge injection unit, and performs the first readout. The first readout circuit of the plurality of readout circuits sharing the charge injection portion when performing the charge injection drive to make the connection portion and the potential barrier portion of the circuit have the same potential. The signal output circuit of the second readout circuit other than the second readout circuit is controlled to provide a barrier against the potential of the charge injection unit between the first charge storage unit and the charge injection unit of the second readout circuit. A solid-state imaging device that forms an injection potential barrier. The solid-state imaging device according to claim 1,
The signal output circuit includes: the second charge storage unit; a transfer gate that transfers the charge stored in the first charge storage unit to the second charge storage unit; and the second charge storage unit. A circuit that outputs a signal corresponding to the potential,
The driving unit is a solid-state imaging device that controls the potential of the transfer gate to form the injection potential barrier. The solid-state imaging device according to claim 2,
The signal output circuit includes a reset transistor for resetting a potential of the second charge storage unit;
A solid-state imaging device in which the charge injection part is a drain of the reset transistor. The solid-state imaging device according to claim 1,
The signal output circuit includes a reset transistor for resetting a potential of the first charge storage unit;
The charge injection part is a drain of the reset transistor;
The driving unit is a solid-state imaging device that controls the gate potential of the reset transistor to form the injection potential barrier. The solid-state image sensor according to any one of claims 1 to 4,
A solid-state imaging device in which the driving unit performs driving to form the injection potential barrier only for the readout circuit to be subjected to the charge injection driving. The solid-state image sensor according to any one of claims 1 to 4,
For the readout circuit other than the readout circuit for which the drive unit performs the charge injection drive, the signal output circuit is controlled to control the first charge accumulation unit and the charge injection unit of the readout circuit. A solid-state imaging device that performs driving to form an injection potential barrier that acts as a barrier against the potential of the charge injection portion.   An imaging device provided with the solid-state image sensor of any one of Claims 1-6. A method for driving a solid-state imaging device having a plurality of photoelectric conversion elements including a pair of electrodes stacked above a semiconductor substrate and a photoelectric conversion layer sandwiched between the electrodes,
The solid-state image sensor is provided corresponding to the photoelectric conversion element, and includes a readout circuit that reads a signal generated by the photoelectric conversion element,
The readout circuit includes a connection portion formed in the semiconductor substrate for electrically connecting the photoelectric conversion layer of the corresponding photoelectric conversion element and the semiconductor substrate, and adjacent to the connection portion in the semiconductor substrate. And a potential barrier portion serving as a potential barrier with respect to the potential of the connection portion, and provided in the semiconductor substrate adjacent to the potential barrier portion, and the charge generated in the photoelectric conversion layer is the connection portion And a first charge storage section that is stored via the potential barrier section, and a signal output circuit that outputs a signal corresponding to the charge stored in the first charge storage section,
The signal output circuit includes a charge injection unit that injects a charge into the connection unit,
The readout circuits corresponding to the plurality of adjacent photoelectric conversion elements share the charge injection unit,
Injecting charge from the charge injection section into the connection section of the first read circuit, which is one of the plurality of read circuits sharing the charge injection section, and connecting the connection section of the first read circuit When the charge injection driving is performed so that the potential barrier unit has the same potential, a second of the plurality of read circuits sharing the charge injection unit other than the first read circuit is used. An injection potential barrier that controls the signal output circuit of the readout circuit and serves as a barrier against the potential of the charge injection section between the first charge storage section and the charge injection section of the second readout circuit. The solid-state image sensor drive method which has the drive step which performs the drive which forms A. A driving method of a solid-state imaging device according to claim 8,
The signal output circuit includes: the second charge storage unit; a transfer gate that transfers the charge stored in the first charge storage unit to the second charge storage unit; and the second charge storage unit. A circuit that outputs a signal corresponding to the potential,
In the driving step, the solid-state imaging device driving method for forming the injection potential barrier by controlling the potential of the transfer gate. A method for driving a solid-state imaging device according to claim 9,
The signal output circuit includes a reset transistor for resetting a potential of the second charge storage unit;
A method for driving a solid-state imaging device, wherein the charge injection unit is a drain of the reset transistor. A driving method of a solid-state imaging device according to claim 8,
The signal output circuit includes a reset transistor for resetting a potential of the first charge storage unit;
The charge injection part is a drain of the reset transistor;
In the driving step, a solid-state imaging device driving method for controlling the gate potential of the reset transistor to form the injection potential barrier. It is a drive method of the solid-state image sensing device according to any one of claims 8-11,
In the driving step, the solid-state imaging device driving method for driving to form the injection potential barrier only for the readout circuit to be subjected to the charge injection driving. It is a drive method of the solid-state image sensing device according to any one of claims 8-11,
In the driving step, also for a readout circuit other than the readout circuit to be subjected to the charge injection driving, the signal output circuit is controlled so that the first charge accumulation unit and the charge injection unit of the readout circuit A solid-state imaging device driving method for performing driving to form an injection potential barrier that is a barrier against the potential of the charge injection portion.

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