JP5358315B2 - Parallel computing device - Google Patents

Description

  The present invention relates to a parallel computing device.

Some electronic computing devices that perform large-capacity arithmetic processing are used for image processing. A system in which such an electronic computing device performs arithmetic processing in real time is shown as an example.
There is a system that assists safe driving by performing image processing based on video obtained by a video camera mounted on an automobile and presenting a detected result to a driver. An electronic computer (image processor) used in such a system is mounted on a car together with a video camera, and analyzes video (for example, 640 pixels × 480 pixels, 10 frames / second) from the video camera. For example, it is said that an image processor used for analysis of applications such as pedestrian detection needs to have a computing capacity of 100 GOPS (Giga (10 ⁹ ) operations per second) or more. In order to improve the detection accuracy of pedestrians or to detect pedestrians far away, it is necessary to detect and determine the detailed situation indicated from the video signal output by the video camera. Based on the resolution that can determine the details of the situation, it is necessary to increase the resolution of the video camera and increase the number of pixels constituting the video signal. Accordingly, the amount of calculation required for image analysis increases in proportion to the number of pixels handled. Therefore, a faster image processor is required.
Moreover, in order to improve safety, a pedestrian must be detected in a shorter time, which requires a shorter detection cycle and an increased number of frames to be processed per second. When the number of frames is increased, the amount of computation required for image analysis increases in proportion to the number of frames to be handled, and thus further speeding up of the image processor is required.

On the other hand, since there is a limit to the power that can be supplied in an in-vehicle environment, it is essential to operate with low power consumption (several watts or less), and the speed of the processor cannot be increased by ignoring the increase in power consumption.
In recent years, the performance of general-purpose processors (general-purpose CPUs) used in personal computers (PCs) has improved dramatically (about 10 Gflops). Still, compared with the performance required for the above applications, the performance is insufficient and the power consumption is several tens of watts (watts), so it cannot be used for in-vehicle applications.
As a processor dedicated to high-performance image processing for a PC, for example, a semiconductor device called GPGPU (General Purpose Computing on Graphics Processing Unit) is commercially available from nVIDIA, USA. Although the nominal computing performance of the processor mounted on this semiconductor device is estimated to be several hundreds Gflos, it is estimated to be sufficient, but the power consumption is large (several tens of watts), and it is a processor dedicated to image processing, but video data It is suitable for use and is not suitable for uses such as pedestrian detection.

As a processor with low power consumption of several watts, for example, there is an embedded processor SH4 series of Renesas Technology Corp., but the calculation performance is too low at less than 2 Gflops.
Under these circumstances, an image processor having a computer architecture that achieves extremely high arithmetic processing performance with low power consumption has been developed. One example is an image processor intended for in-vehicle image processing. The image processor has a configuration in which a large number of element processor elements (element PEs) with a very low power consumption with a low operating frequency are integrated and processed in one LSI. For example, IMAPCAR developed by NEC Corporation (for example, Non-Patent Document 1).

Okazaki, Akinori, Koga, Hidano, “In-vehicle embedded image recognition processor IMAPCAR”, NEC Technical Report Vol. 60 No. 2/2007 p17-20,2007. Kyo, S .; Okazaki, S .; Arai, T., "An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems", Computer Architecture, 2005. ISCA apos; 05. Proceedings. 32nd International Symposium on Volume, Issue, 4 -8 June 2005 p134-145,2005.

  By the way, in general, the effective performance obtained when a parallel processor is actually operated is the nominal value obtained by multiplying the total number of arithmetic units (ALU) incorporated therein and their operating frequencies. It is considerably low compared. The main cause of the decrease in effective performance is that data required by the arithmetic unit cannot be supplied at an appropriate timing, or the arithmetic result cannot be stored immediately and play occurs in the arithmetic unit. In order to increase the effective performance obtained when the parallel processing processor is actually operated, it is necessary to supply data to the computing unit without interruption, and at the same time to store the result of the operation quickly in an appropriate location. .

There are SIMD (Single Instruction Multi Data) type, MIMD (Multi Instruction Multi Data) type and VLIW (Very Long Instruction Word) type architectures for parallel operation of multiple element PEs. Since it is necessary to have both low cost and high performance, the above-mentioned IMAPCAR method combining the VLIW type with the SIMD type is superior.
A configuration example of the SIMD type image processor is shown in FIG. In the SIMD type parallel computing device, all the element PEs simultaneously read data or output data all at once because of the structure that all the elements PE operate simultaneously with the same instruction. For example, if there are 128 element PEs in one LSI, and these operate on a 100 MHz (megahertz) clock and request one 8-bit data at a time, the instantaneous data transfer rate required Is 100 MHz × 1B × 128 = 12.8 GB (gigabytes) / second. This is not a difficult data transfer speed, but it also increases costs and power consumption including external circuits. Therefore, in the configuration shown in the figure, a local memory is provided for each element PE, and these and the element PE are connected by a dedicated bus. With this configuration, the required data transfer rate between each element PE and local memory is a maximum of 100 MB (megabytes) / second.

  On the other hand, data to be processed must first be supplied from an element outside the LSI, and the processing result must be extracted outside the LSI. Assuming that the input image is 8 bits / pixel in black and white in the example (640 pixels x 480 pixels, 10 frames / second), the data transfer rate of the input data is 640 x 480 x 10 / s x 1B = 3.1MB / Sec. If you use 8 input data lines, you can input with 3.1MHz clock. This level of data input speed can be easily achieved. In general, in image processing, the amount of output data is almost the same as that of input data, so that it can be easily output.

Further, according to the technique of Non-Patent Document 1, the element PE of IMAPCAR is a VLIW type having four sub-processors (hereinafter referred to as SPE) (see FIG. 13). The four sub-PEs are functionally differentiated. That is, a sub PE (MEM / Add in the figure) in charge of data input / output or addition with the local memory, a sub PE (same logic) in charge of logical operation, a sub PE (same ALU) in charge of arithmetic logic operation, and A sub-PE (multiplier) responsible for multiplication. 28 general registers (GR) are provided in common to the four sub-PEs. This configuration has the following three problems.
The first problem is that data input / output to / from local memory can only be done by one sub-PE, so if memory access is concentrated, data input / output may not be in time (insufficient memory data bus bandwidth), and conversely When there is almost no memory access or addition, this sub-PE is idle.
The second problem is that one sub-PE is fixed to multiplication, but the frequency of multiplication in image processing is not so high, and there is a high possibility that this sub-PE (same Multiplier) will be idle. . Due to these problems, it is difficult to always keep the four sub-PEs active (no play).
The third problem is in 28 GRs.
According to Section 5.3 in Non-Patent Document 2, the operands of the instruction executed in the sub-PE are three operands of source 2 and destination 1. Since there are 28 GRs, 5 bits are required for each operand specification, and the total is 15 bits. Therefore, when the four sub-PEs are combined for the VLIW configuration, 60 bits are required, which increases the capacity of the memory for storing the instruction code, which increases the cost.

  The present invention has been made to solve the above problems, and an object of the invention is to provide a parallel computing device with high effective efficiency.

In order to solve the above problem, the invention described in claim 1 is directed to a plurality of arithmetic processors (for example, arithmetic processor PE2 in the embodiment) that perform arithmetic processing in parallel, and control signals to each of the arithmetic processors. An instruction execution control unit (for example, instruction execution control processor PE-I3 in the embodiment) to be supplied, and the arithmetic processor holds a plurality of data or a plurality of operation results (for example, the embodiment) And the arithmetic units (for example, ALUs 12A to 12C and 12DA in the embodiment) that perform arithmetic processing on the data read from the storage unit and supply the result to the storage unit. sub processor (e.g., sub-processor (SPE) 2A-2D in the embodiment) of With few, are those least two sub-processors among the plurality of sub-processors have the same structure, constituting the sub-processor identical structure sub processor group (e.g., sub-processor groups SPE2G in the embodiment) having the same configuration The instruction execution control unit includes an exchange unit (for example, exchange units 33A to 33C in the embodiment) that exchanges and supplies a control signal to be supplied to a sub-processor included in the same-structured sub-processor group. a parallel computing apparatus characterized.

According to a second aspect of the present invention, the subprocessor includes a register unit (for example, Acc13A to 13D in the embodiment) that is connected to one input of the arithmetic unit and stores information to be written. Normally stores the calculation result of the calculation unit, and outputs the stored calculation result. The sub- processor group having the same structure includes a register reference unit (for example, the register reference units 15A to 15C in the embodiment). The register reference unit supplies an output from each of the register units included in each sub-processor included in the same-structured sub-processor group to input data to the other input of the arithmetic unit of the sub-processor. When handling as input from at least some of the registers, the register And the register for supplying the input data can be changed. When the instruction execution control unit exchanges the control signal to be supplied to each sub processor of the same structure sub processor group, Is replaced with each of the register units associated with each of the registers that supply the input data before replacement, and the control signal supplied before replacement to the sub-processor to which the register unit belongs The register reference unit is controlled so as to newly associate the register unit included in the sub processor to be supplied after replacement with the register that supplies the input data. it is a parallel computing system according to claim 1.

According to the first and second aspects of the invention, the parallel computing device includes a plurality of arithmetic processors that perform arithmetic processing in parallel. In the arithmetic processor, the instruction execution control unit supplies a control instruction to each. In the sub processor, the storage unit holds a plurality of data or a plurality of calculation results. The arithmetic unit performs arithmetic processing on the data read from the storage unit and supplies the result to the storage unit.
In addition, at least two of the plurality of sub processors have the same structure. Those sub-processors having the same structure form an identical structure processor group. The instruction execution control unit exchanges and supplies control signals supplied from the exchange unit to the sub processors included in the same structure sub processor group.
This allows you to exchange combinations of data and processing without exchanging data stored in the storage unit or preparing similar programs with different operands to switch referenced data and perform similar processing. can do.

1 is a schematic block diagram showing a first embodiment of the present invention. It is a block diagram which shows the structure of PE2 in 1st Embodiment. It is a timing chart in the case of inputting image data in a 1st embodiment. It is a timing chart in the case of outputting data outside from PE2 in a 1st embodiment. It is a figure which shows the example of the video signal input into the arithmetic processing in 1st Embodiment. It is a figure which shows the structure of the address register in 1st Embodiment. It is a figure which shows the mapping of the image data to the local memory in 1st Embodiment. It is a schematic block diagram which shows PE-I3 in 1st Embodiment. It is a figure which shows the command selection state in the exchange part 31 in 1st Embodiment. It is a figure which shows operation | movement of the register reference part in 1st Embodiment. It is a block diagram which shows the structure of PE2 in 2nd Embodiment. It is a block diagram of the structural example of the SIMD type image processor by a prior art. The structural example of the element arithmetic processor by a prior art is shown.

(First embodiment)
An embodiment of a parallel computing device will be described with reference to the drawings.
FIG. 1 is a schematic block diagram showing an embodiment of the present invention.
The parallel computing device 1 shown in this figure performs parallel arithmetic processing by a plurality of arithmetic processors (also referred to as “element PEs”). Prior to detailed description of the present embodiment, an outline of the configuration of the parallel computing device 1 will be described.
Operation processors (PE) 2-0 to 2-106 (collectively referred to as “operation processors (PE) 2”) in the parallel computing device 1 and an instruction execution control processor (PE-I) that supplies control instructions to each of the PEs 2. ) 3 is included.
The parallel computing device 1 includes an input / output processor (IOP) 4, an instruction memory 5, a data input shift register 6, a data output shift register 7, and an external memory 9.

Each of the arithmetic processors 2 includes four sub processors (SPE) 2A to 2D.
Each of the SPEs 2A to 2D has a VLIW (Very Long Instruction Word) type configuration that executes different instructions. Each PE2 is formed with the same configuration in which SPE2A to 2D are combined. Moreover, 107 SPE2A which all PE2 has are comprised by SIMD (Single Instruction Multi Data) type, and execute the same instruction in all SPE2A. Similarly, SPE2B, SPE2C, and SPE2D are each configured as a SIMD type.
These SPEs 2A to 2D are configured by combining SPEs having different configurations. A description will be given by taking, as an example, a combination of SPE2A to SPE2C for performing arithmetic processing in the arithmetic processor 2 and SPE2D having a configuration such as external input / output in addition to arithmetic processing. A combination of SPE2A to SPE2C having the same configuration is referred to as a sub processor group 2G.

The PE-I3 controls the execution order of the instructions of the PE2.
The PE-I 3 controls processing that requires conditional branching such as loop processing and subroutine calls in the PE 2 program. When the PE-I3 and PE2 instructions are described in an assembler program, they are described as VLIW-type instructions that execute five instructions SPE2A to SPE2D and PE-I3 in parallel.

The IOP4 performs input / output with the outside of the PE2.
The program code executed by the SIMD + VLIW type parallel computing device 1 is read in advance from the external memory 9 by the IOP 4 before the calculation is started, and is written in the instruction memory 5 attached to the PE-I 3. Thereafter, when the IOP4 sends a calculation start signal to the PE-I3, the PE-I3 reads out the instruction to be executed by itself from the instruction memory and the four instructions to be executed by the SPE2D from the SPE2A, and starts the operation. Data to be calculated is fetched from the outside by the IOP 4 and transferred through the data input shift register 6 to the processors PE2-0 to PE2-106. The calculation result is read from each PE 2 by the IOP 4 via the data output shift register 7, transferred to the external memory 9, and output outside the PE 2.

The data input shift register 6 and the data output shift register 7 input and output data to be operated by the PE 2 of the parallel computing device 1. The data input shift register 6 shifts the data input via the IOP 4 to a position where the PE 2 corresponding to the serially input data is arranged by the function of the shift register. Further, the data output shift register 7 shifts the result of the arithmetic processing in each PE2 from the position where the PE2 is arranged to the IOP4 and outputs the result via the IOP4.
In this way, the plurality of PEs 2 can perform arithmetic processing and input / output processing in parallel.

FIG. 2 is a block diagram showing the configuration of the PE 2 in the parallel computing device 1 of the present invention.
The parallel computing device 1 shown in this figure includes PE2-k, PE2- (k-1) and PE2- (k + 1), PE-I3, IOP4, instruction memory 5, and data arranged with PE2-k in between. An input shift register 6 and a data output shift register 7 are shown. The same components as those in FIG.

Since PE2-k has the same configuration as adjacent PE2- (k-1) and PE2- (k + 1), see PE2-k (hereinafter referred to as "PE2" unless otherwise indicated). To show the configuration.
The PE 2 includes a register 2M in addition to the four sub processors (SPEs) 2A to 2D. Also, SPE2A to SPE2C have the same configuration and form a sub processor group SPE2G.

  The register 2M is a storage area for temporary storage of data necessary for calculation. The register 2M includes 12 registers (R4 to R15) inside. The register 2M is referred to from each SPE and is written.

  The SPE 2A includes a local memory (LM) 11A, an ALU 12A, an Acc 13A, a selector (Sel) 14A, and a register reference unit (Sel) 15A. Similarly, the SPE 2B includes a local memory (LM) 11B, an ALU 12B, an Acc 13B, a selector (Sel) 14B, and a register reference unit (Sel) 15B. The SPE 2C includes a local memory (LM) 11C, an ALU 12C, an Acc 13C, a selector (Sel) 14C, and a register reference unit (Sel) 15C.

First, the structure of SPE2A-2C is demonstrated on behalf of SPE2A.
In the SPE 2A, the local memory 11A is, for example, a memory having a 512 × 8b (bit) configuration, and records input data and calculation results of calculation processing.
The Acc 13A is an accumulator in which the calculation result of the ALU 12A is written and is referenced from the ALUs 12A to 12D.
The selector 14A selects an input to the ALU 12A.
The ALU 12A performs predetermined arithmetic processing based on the input data. One input of the ALU 12A is supplied with data from the Acc 13A. The other input of the ALU 12A is supplied with the data selected by the selector 14A.
The data selected by the selector 14A is any one of the register 2M, Acc13A, Acc13B, Acc13C, Acc13D, and data stored in the local memory 11A.

The calculation result by the ALU 12A is normally written in the Acc 13A. However, the calculation result is written by selecting one of the registers R4 to R15 in the register 2M using an instruction for transferring the data of the Acc 13A to the register 2M. Further, using a command for transferring the data of Acc13A to the memory 11A, one of the storage areas in the memory 11A is selected and written.
The register reference unit 15A selects data to be output to the selector 14A based on a control signal from the PE-I3. The data that can be selected is data of Acc13A to Acc13C. By changing the selection of the register selection unit 15A without changing the selection condition in the selector 14A, the data of Acc13A to Acc13C can be referred to.
SPE2B to SPE2C have a configuration corresponding to the configuration of SPE2A.

Subsequently, SPE2D having a configuration different from SPE2A to SPE2C will be described.
The SPE2D includes a local memory 11D, an arithmetic unit 12, an Acc13D and a selector 14D, a data input buffer (SIN_reg) 16, a data output buffer (SOUT_reg) 17, a PE output register L (PE-out-L) 18, and a PE output register R ( PE-out-R) 19. As described above, the SPE2D has a unique configuration different from the other SPE2A to SPE2C and does not include a register reference unit, which is a difference from the above-described SPE2A to SPE2C.

The configuration of SPE2D is shown in comparison with SPE2A.
The local memory 11D in the SPE2D corresponds to the local memory 11A.
The arithmetic unit 12D includes an ALU 12DA, a multiplier 12DM, and a selector 12DS. The ALU 12DA corresponds to the ALU 12A, and the output is input to the ACC 13D via the selector 12DS. The multiplier 12DM sets the same input signal as that of the ALU 12DA and performs multiplication of input data. The selector 12DS selectively outputs the calculation result of the ALU 12DA or the multiplier 12DM to the Acc 13D. Acc13D corresponds to Acc13A.
The selector 14D has the same register 2M as the selector 14A, Acc13A, Acc13B, Acc13C and Acc13D, data stored in the local memory 11D, and input data from the data input shift register 6 input via the data input buffer 16. , There is input data from adjacent PE2- (k-1) and PE2- (k + 1).

The data input buffer 16 temporarily holds the input from the data input shift register 6 that sets the data input to the PE2 in each PE2. The data output buffer 17 temporarily stores data to be output to the data output shift register 7 when the calculated result is output from the PE 2, and reading is performed by the data output shift register 7.
The PE output register L18 and the PE output register R19 temporarily store data to be output to the adjacent PE2.
The data stored in the PE output register L18 and the PE output register R19 is referred to from the SPE2D in the adjacent PE2.
The PE output register L18 outputs data to the adjacent PE2- (k-1) on the left side of the drawing. The PE output register R19 outputs data to the adjacent PE2- (k + 1) on the right side of the drawing.
In this way, the SPE2D can selectively process the arithmetic processing including multiplication and the data exchange processing outside the PE2.

  With the SPEs 2A to 2D described above, the local memories 11A to 11D are divided and arranged in each SPE. In the example shown in this figure, it is assumed that the capacity is divided into four in units of 512 × 8b (bits). The total capacity of the local memories 11A to 11D is the same storage capacity as 2k x 8b (bits) that are arranged together without being divided, but by being arranged separately, each SPE can be accessed simultaneously. Thus, the data transfer capability for the local memory in PE2 is quadrupled. With this configuration, all SPEs can access the memory without waiting time, and further, it is possible to avoid an access collision problem that occurs when using a multi-port memory. However, in exchange for these advantages, the area required for the arrangement of the local memories 11A to 11D is slightly increased as compared with the case where one 2k × 8b (bit) memory is arranged.

  Each of the local memories 11A to 11D includes an address register therein. In the SPEs 2A to 2D, when accessing the local memories 11A to 11D, address information is first set in an address register (not shown), and then writing to the memory or reading from the memory is performed. If the address register is reset every time the local memories 11A to 11D are accessed, the efficiency is deteriorated. Therefore, in addition to the normal memory access instruction, an instruction that automatically increments the address set in the address register after access and an instruction that decrements by 1 are prepared. By using such an address register, the number of instructions necessary for memory access can be reduced, and the efficiency of memory access can be improved in a process in which memory access increases, such as image processing.

  In addition, since all SPEs are respectively provided with ALUs 12A to 12DA, arithmetic logic operation processing can be performed in any SPE. Further, the SPE2D is provided with a multiplier (Mul) 12DM and can perform multiplication processing. With this configuration, each SPE can perform arithmetic logic operation processing in parallel, which greatly improves the degree of freedom of instruction assignment by the compiler.

Each SPE 2 is not a general register system but an accumulator system. That is, one input of each of the ALUs 12A to ALU12DA is fixed to the accumulator (Acc), and the output destinations of the ALUs 12A to ALU12DA are the respective Accs 13A to 13D. Only the other input of the ALU 12A to ALU 12DA can specify the data reference destination according to the instruction.
The PE 2 includes a register 2M used for temporary storage of data necessary for calculation. Normally, data is supplied from the register 2M to the ALUs 12A to 12DA. With this architecture, the number of operands required for an instruction referring to this register can be reduced to 4 bits, and even when the four SPEs 2A to 2D are controlled independently, a total of 16 bits can be configured, resulting in a very compact size.

Next, accumulator (Acc) selection control processing in each SPE will be described.
Acc13A to Acc13D are four registers (registers R0 to R3) that can be referenced from each ALU. Although Acc13A to Acc13D are distributed and arranged in each SPE, they can be read by referring to other SPEs.
However, in SPE2A to 2C, Acc13A to Acc13C and Acc13D have different reference methods.
Acc13A to Acc13C are selected by the register reference units 15A to 15C, and then selected by the selectors 14A to 14D together with the Acc13D, the register 2M, etc., and input to one side of the ALUs 12A to ALU12DA.
Acc13D is different in that it is selected by the selectors 14A to 14D together with the register 2M and the like and input to one side of the ALUs 12A to 12DA.

The register R3 referenced from each ALU always corresponds to Acc13D by the selection of the selectors 14A to 14D, but the registers R0 to R2 can change the reference destination depending on the state in which the register reference units 15A to 15C are set. It becomes like this. Therefore, the registers R0 to R2 change to any one of Acc13A to Acc13C depending on the setting of the register reference units 15A to 15C.
Data writing to the registers R4 to R15 is performed by a data transfer command from Acc13A to Acc13D. Simultaneous writing to the same register can be easily avoided by the compiler. In addition, since data writing to the registers R4 to R15 can be executed only by the above-mentioned instruction, even when reading and writing from the same register occur simultaneously, a timing problem can be easily avoided by providing a data bypass.
For the input to the arithmetic unit 12D and the multiplier 12DM, refer to the description of the ALU 12DA described above.

A process for inputting and outputting image data will be described with reference to the drawings.
FIG. 3 is a timing chart of image data input processing.
The SPE2D has a configuration for inputting / outputting data to / from the outside of the PE2.
Input image data is captured by the IOP 4 and set while being shifted to the data input shift register (Serial-in) 6. Immediately after PE2 is reset (initialized) (time t _i 0), the flag Sin-emty indicating that the data input shift register 6 is empty is set to 1, and the data input shift register 6 is ready for data. The flag Sin-rdy indicating this is 0. When calculation is started, the IOP 4 waits for Sin-emty to become 1 before writing data to the data input shift register 6 (time t _i 1), but since Sin-emty is already 1, data transfer is immediately started (time t _i 2).

On the other hand, PE-I3 waits for Sin-rdy to become 1 (time t _i 2). As soon as PE-I3 enters the wait state, all SPEs enter the wait state. The IOP 4 sets Sin-rdy to 1 when the data transfer for one line to the data input shift register 6 is completed (time t _i 4). Then, PE-I 3 exits from the wait state (time t _i 5), and at the same time, transfers data from the data input shift register 6 to the data input register (SIN-reg) 16 in one clock, and simultaneously clears Sin-rdy. -emty is set to 1 to inform IOP4 that the data input shift register 6 has become empty (time t _i 8). When data is prepared in the data input buffer (SIN-reg) 16, it can be read out by the processing of the SPE2D and stored in the local memory or used immediately for calculation processing.

On the other hand, IOP4 enters the wait state when there is no other processing after transferring the data for one line, and waits for Sin-emty to become 1 to transfer the data for the next line ( Time t _i 7). When Sin-emty becomes 1, the IOP 4 starts data transfer to the data input shift register 6 again.

Sin-emty is cleared by IOP4 at an appropriate timing (time t _i 3). By this procedure, the data writing from the IOP 4 and the calculation process in the PE 2 are synchronized, and the calculation process in the PE 2 and the image data input work can be executed in parallel.

FIG. 4 is a timing chart of a process for outputting data to the outside via the IOP4.
Immediately after PE2 is reset, the flag SOUT-emty indicating that the data output buffer (SOUT-reg) 17 is empty is set to 1, and the flag SOUT-rdy indicating that data is ready in SOUT-reg is set. 0 (time to0). When the calculation is started, the IOP 4 waits until SOUT-rdy becomes 1 (time to 1).
On the other hand, PE-I3 tries to enter a wait state waiting for SOUT-emty to become 1, but does not enter the wait because SOUT-emty is already 1 (time to1). Then, at the same time as PE-I3 clears SOUT-emty, SPE2D starts to accumulate output data in SOUT-reg (time to3).
When the data to be output is prepared, PE-I3 sets SOUT-rdy to 1 (time to4). Then, IOP4 exits the wait state (time to7), transfers data from SOUT-reg to Serial-out in one clock, clears SOUT-rdy at the same time, sets SOUT-emty to 1, and sets SOUT-em to PE-I3. Notify that reg is empty (time to8). Thereafter, the IOP 4 reads the data while shifting the Serial-out and transfers it to the outside of the LSI (time to 8). By this procedure, the data processing in PE2 and the data output to the outside of the LSI by IOP4 can be synchronized, and these processes can be executed in parallel.

In addition, there are a PE output register L register 18 and a PE output register R register 19 for transferring data between adjacent PEs 2. When the SPE2D writes it to the PE output register L register 18 on the left side, that is, the PE2 with the smaller PE2 number, the SPE2D adjacent to the left can be read after the next instruction. Similarly, when the SPE2D writes data to the PE output register R register 19 on the right side, that is, the PE2 having a larger PE2 number, the SPE2D adjacent to the right can be read after the next instruction.
As described above, the use of the configuration shown in FIG. 2 is effective in lacking bandwidth in accessing the local memory and keeping each SPE in the instruction execution state.

Furthermore, a technique for solving the problem of insufficient bandwidth in access to a local memory that occurs when applied to an image processing application will be described.
FIG. 5 shows an example of a video signal input to the arithmetic processing in the embodiment of the present invention.
As shown in the figure, the input video signal represents a black and white image displayed by a screen composed of pixels in which 640 pixels × 480 pixels are two-dimensionally arranged. One pixel is composed of 8 bits, and a gradation corresponding to the brightness of each pixel is indicated.

Next, problems and countermeasures regarding processing unique to image processing will be described.
Data is input to the parallel computing device 1 by dividing the video signal into 480 times for each line in units of 640 pixels for one line from the video camera. The input data is divided and stored in 107 PEs 2 from PE 2-0 to PE 2-106, and each PE 2 shares the arithmetic processing.
By the way, in image processing, a specific pixel is defined, and data of pixels in the vertical and horizontal directions adjacent to the pixel in the coordinate axis direction indicated by a two-dimensional plane is often referred to.
If the data of the upper, lower, left, and right pixels that are frequently referred to cannot be accessed efficiently, the processing becomes complicated and the processing speed decreases.
First, a method for efficiently handling the left and right pixels arranged in the horizontal direction will be described.
Each PE 2 is in charge of the data of 6 pixels divided among the input data (107 × 6 = 642). However, if only 6 pixels in charge are stored in the local memory, data is frequently exchanged between the adjacent PEs 2 and the efficiency is deteriorated. Therefore, each PE 2 stores data that should be stored by both neighbors one pixel at a time. Each local memory will store 8 pixels per line.

Next, a method for efficiently handling the upper and lower pixels arranged in the vertical direction will be described. Since the pixels in the vertical direction are handled in units of lines, they will be described as a reference between lines.
Since the capacity of the local memories 11A to 11D arranged in each SPE is 512 × 8b (bits), one local memory included in each SPE has data for 64 lines (= 512 ÷ 8 (pixels)) at a time. Can be stored. Since there are four local memories in PE2, a maximum of 256 lines of data can be stored at the same time, but since one screen is 480 lines, it is not possible to store up to one screen of data.
In image processing, an image is often divided into narrow areas to be subject to calculation. Therefore, if input data is stored in order, for example, only in the local memory 11A of the SPE2A, only the local memory 11A of the SPE2A is frequently read when performing calculations. The data transfer capability obtained by distributing the memory is not used.

Further, if data for 65 lines or more is to be stored at a time, the data for the first 64 lines and the data for the next 64 lines must be stored in separate memories, and only a program for storing the data is required. In addition, the program that uses the data becomes complicated because the condition determination process is performed.
In this way, the bandwidth of memory access cannot be expanded simply by dividing and arranging the local memory, and the processing program becomes complicated when trying to store and process data for 65 lines or more. A new problem arises.

Here, an address register for accessing the local memory will be described.
FIG. 6 is a diagram showing the configuration of the address register. In the address register shown in this figure, three modes that can be selected as mode 0 to mode 2 can be set.
In mode 0, a memory address to be referred to is determined by the base pointer BP and the four pointers AP0 to AP3. The memory access instruction can designate one pointer AP0 to AP3 as its operand. For example, when the pointer AP0 is designated, the lower 3 bits of the pointer AP0 become bits 2-0 of the memory address, the bits 4-3 are fixed to 0, and the value of BP becomes bits 8-5.

  When an instruction for automatically incrementing the memory address by 1 is executed, the pointer AP0 is incremented by 1 after accessing the local memory. When the value of the pointer AP0 is changed from 7 to 8, the lower 3 bits are all 0, so that it eventually returns to the first address. This mode is convenient when processing line by line in image processing. When the line is moved by 1, the value of the base pointer BP is increased or decreased by 1. Instructions for increasing / decreasing the base pointer BP and the pointers AP0 to AP3 by 1 are prepared. In this mode, for example, the pointer AP0 holds the data read address, the pointer AP1 holds the storage address to which data is temporarily written, and the pointer AP0 and the pointer AP1 are designated by the operand by the read / write instruction to switch the respective addresses. Can be accessed.

The operation in mode 1 is the same, but since the lower 4 bits of the pointers AP0 and AP2 are allocated, it is useful when data is accessed two lines at a time.
In mode 2, since the value of the pointer AP0 can be directly converted into a 9-bit address, the 512B (byte) memory space can be accessed linearly.

FIG. 7 shows an example of mapping of image data to the local memory according to the present embodiment.
In order to make the processing program the same when storing data for 65 lines or more, as shown in the figure, the image data is stored for each line in the local memory 11A of the SPE2A, the local memory 11B of the SPE2B, and the local memory 11C of the SPE2C. Are stored in order.

  First, the procedure for storing the data of line 0 in the image signal in the local memory is shown.

  The image signal captured by the IOP 4 is set in the data input buffer 16 in the SPE 2D by the data input shift register 6. When the ALU 12DA in the SPE 2D reads the set image signal data from the data input buffer 16, the data is written to the Acc 13D and can be referred to as the register R3. The ALU 12A in the SPE 2A refers to the data written in the register R3, transfers it to the Acc 13A, and then writes it in the local memory 11A.

Next, a procedure for writing the next line 1 data to the local memory 11B of the SPE2B using a program for writing the data of the line 0 to the local memory 11A of the SPE2A will be described.
FIG. 8 is a schematic block diagram showing the PE-I 3 in the embodiment of the present invention. PE-I3 shown by this figure is provided with the exchange part 31 inside.
The PE-I 3 disassembles the instructions described in the program registered in the instruction memory 5 and extracts instructions for SPE2A, SPE2B, and SPE2C (OP codes) and rotation instructions for exchanging the instructions. The rotation instruction is executed by PE-I3. The instructions (OP codes) for SPE2A, SPE2B, and SPE2C are indicated as spe-a code, spe-b code, and spe-c code, respectively, and the rotation instruction is indicated as a ROT instruction.
The exchange unit 31 in the PE-I 3 rotates (exchanges) these OP codes as necessary.

The exchange unit 31 includes an instruction selection unit 32, instruction selection units 33A to 33C, and instruction decoding units 34A to 34C.
The instruction selection unit 32 in the exchange unit 31 controls input selection of the instruction selection units 33A to 33C according to the input ROT instruction. The instruction selection unit 32 includes a 2-bit counter inside, and increments the counter value by one when the ROT instruction is executed. The instruction selector 32 returns the value to 0 when the ROT instruction is executed when the counter value is 2, and changes the value in the range of 0-2. The instruction selector 32 outputs a select signal for switching the inputs of the instruction selectors 33A to 33C according to the counter value.
The instruction selection units 33A to 33C switch the input spe-a code, the spe-b code, and the spe-c code in accordance with a select signal output from the instruction selection unit 32.
The instruction decoder units 34A to 34C generate and output control signals for the SPEs 2A to 2C according to the input instruction code.

In the exchanging unit 31, the instruction selecting unit 33A receives the code for spe-a at the I0 input, the code for spe-b at the I2 input, and the code for spe-c at the I1 input. In the instruction selector 33B, the code for spe-a is input to the I1 input, the code for spe-b is input to the I0 input, and the code for spe-c is input to the I2 input. In the instruction selecting unit 33C, the code for spe-a is input to the I2 input, the code for spe-b is input to the I1 input, and the code for spe-c is input to the I0 input.
The instruction selection units 33A to 33C output codes input to the corresponding input terminals of the I0 input, the I1 input, and the I2 input in accordance with the values 0 to 2 of the input select signal.

A process of exchanging control signals supplied to each SPE by the exchanging unit 31 shown in FIG. 8 will be described with reference to the drawings.
FIG. 9 is a diagram illustrating an instruction selection state in the exchange unit 31.
When the select signal output from the instruction select unit 32 is 0, the spe-a code is used for the SPE2A control signal, the spe-b code is used for the SPE2B control signal, and the spe-c code is used for the SPE2C control signal. Code is output. When the ROT instruction is executed and the select signal becomes 1, the SPE2A control signal has a spe-c code, the SPE2B control signal has a spe-a code, and the SPE2C control signal has a spe-b code. Is output. When the ROT instruction is executed and the select signal becomes 2, the SPE2A control signal is Spe-b code, the SPE2B control signal is Spe-c code, and the SPE2C control signal is Spe-a code. Code is output. Next, when the ROT instruction is executed, the value of the select signal returns to zero.

When the ROT instruction is executed in PE-I3 after the SPE 2A reads line 0 in accordance with the code for spe-a while the select signal in the instruction select unit 32 is 0, the select signal becomes 1. Therefore, even an OP code of a program described for spe-a is executed by SPE2B. That is, it is possible to write the data of line 1 in the local memory 11B of the SPE 2B by executing the same program as the program that has read line 0. Similarly, when the ROT instruction is executed after the reading of the line 1 is completed, the data of the line 2 can be written into the local memory 11C of the SPE 2C.
Next, when data is read by executing the ROT instruction, the data on line 0 is overwritten with the data on line 3 in SPE2A. If this is inconvenient, the ROT instruction is executed at PE-I3 and at the same time, the instruction to increase the base pointer BP (FIG. 6) by 1 is executed at SPE2A. In this way, data can be stored as shown in FIG. 7 by a program that simply loops while executing the ROT instruction.

  Note that the instructions of SPE2D and PE-I3 are always code for spe-d and code for pe-i and do not change. Moreover, in order to rotate (exchange) SPE2A-SPE2C, these must have the completely same structure. Accordingly, the configuration necessary for data input / output with the outside of PE2 and the multipliers are all concentrated on SPE2D.

Next, it will be described how image processing can be performed efficiently using image data stored as shown in FIG. For example, a case where a digital filter having a window of 3 pixels × 3 pixels is applied to an image is shown.
In the first process, data of 3 pixels (9 pixels in total) is read and processed from line 0 (upper stage), line 1 (middle stage), and line 2 (lower stage). It is assumed that the data of line 0 is stored in SPE2A, the data of line 1 is stored in SPE2B, and the data of line 2 is stored in each local memory 11A to 11C of SPE2C.
In the SPEs 2A to 2C, three pixels can be distributed and read from the data of each line. That is, the expanded memory bandwidth can be used effectively. When the processing for one line is completed and the processing for the next line is started, line 1 becomes the upper stage, line 2 becomes the middle stage, and line 3 becomes the lower stage. If the ROT instruction is executed at the end of processing for one line, the code for spe-a is executed by SPE2B, the code for spe-b is executed by SPE2C, and the code for spe-c is executed by SPE2A. It is easy to move to a line that can be switched sequentially.

  That is, the instruction to access the upper data is described as a code for spe-a, but the local memory in which the data is stored is the local memory 11B in the SPE 2B. This is because the code for spe-a is executed by the SPE 2B including the local memory 11B, so that the data on the line 1 is eventually processed as the upper data. However, it is necessary to pay attention to the code for spe-c, which is executed by SPE2A, but if it is left as it is, line 0 is accessed. Therefore, an instruction for incrementing the base pointer BP by 1 is executed in SPE2A simultaneously with the ROT instruction. In this way, image processing using data stored as shown in FIG. 7 can be performed with a program that simply loops by adding an ROT instruction and an instruction to increase the base pointer BP.

Finally, the functions of the three register reference units 15A to 15C in FIG. 2 will be described with reference to the drawings.
FIG. 10 is a diagram illustrating the operation of the register reference unit.
In order for the program to operate correctly even when the SPE is rotated, it is necessary that the Acc of the SPE in which the code for spe-a is executed can be read from another SPE as the register R0. Similarly, it is necessary that the Acc of the SPE in which the code for spe-b is executed is read as register R1, and the Acc of the SPE in which the code for spe-c is executed is read as register R2.
Therefore, the register reference units 15A to 15C select Acc 13A to 13C as registers R0 to R2 according to the value of the select signal output from the instruction select unit 32, as shown in the figure.
When the select signal output from the instruction select unit 32 is 0, Acc13A is referred to in the register R0, Acc13B is referred to in the register R1, and Acc13C is referred to in the register R2. When the select signal is 1, Acc13B is referred to in the register R0, Acc13C is referred to in the register R1, and Acc13A is referred to in the register R2. When the select signal is 2, the register R0 refers to Acc13C, the register R1 refers to Acc13A, and the register R2 refers to Acc13B.

(Second Embodiment)
An embodiment of a parallel computing device will be described with reference to the drawings.
FIG. 11 is a block diagram showing a configuration of PE2 in the second embodiment. The same components as those in FIG.
The parallel computing device 1a shown in this figure includes PE2a, PE-I3a, IOP4, instruction memory 5, data input shift register 6, and data output shift register 7. The same components as those in FIG. PE2a represents a plurality of PE2a-0 to PE2a-106 having the same configuration. Further, IOP4 and instruction memory 5 are not shown.

PE2a corresponds to PE2 in FIG. 2, and has a partially different configuration. The PE 2a includes SPE2Aa to SPE2Da and a register 2M.
SPE2Aa to SPE2Da in PE2a correspond to SPE2A to SPE2D in FIG. 2, but include selectors 14XA to 14XD instead of selectors 14A to 14D and register reference units 15A to 15C.
The selectors 14XA to 14XC select signals to be input according to the configuration in which the selectors 14A to 14C and the register reference units 15A to 15C are integrated according to the selection control signal. Signals input to the selector 14XA are Acc13A to Acc13D, the local memory 11A, and the register 2M. The signals input according to the selection control signal from the PE-I 3a are switched. The selectors 14XB to 14XC are the same as the selector 14XA.
In addition, the selector 14XD receives the signals from the Acc 13A to Acc 13D, the local memory 11D, the register 2M and the data input buffer (SIN_reg) 16 and the input signal from the adjacent PE 2a, and is selected from the PE-I 3a. The input signal is switched according to the control signal.

The PE-I 3a corresponds to the PE-I 3 in FIG. 2 and includes an exchange unit 31a. The exchanging unit 31a includes an instruction selecting unit 32 and selection control units 35A to 35D.
The instruction selection decoding units 35A to 35D have a configuration in which the instruction selection units 33A to 33D and the instruction decoding units 34A to 34D in FIG. 8 are respectively combined, and input spe-a code, spe-b code, spe- The c code is switched according to the select signal output from the instruction select unit 32, and a control signal for controlling each of the SPEs 2A to 2C is generated and output according to the input instruction code.

With the above configuration, the selection of the registers R0 to R3 in the SPEs 2A to 2C is simplified, and the selectors 14XA to 14XC in the SPE are switched in one stage.
By using the ROT instruction shown in the first embodiment, the selection process (OP code) for SPE2A, SPE2B, and SPE2C can be exchanged and supplied to the ALUs 12A to 12C of each SPE in the same manner.

  According to the embodiment described above, in a parallel computer adopting a VLIW type architecture having a plurality of sub-PEs, the problem of multiple access to the local memory can be avoided by dividing and arranging the local memory for each sub-PE. However, the data transfer capability between the memory and the sub-PE can be increased. In addition, all the data stored in the local memory was exchanged in a short time (1 clock) by making the configuration of two or more sub-PEs exactly the same and exchanging control signals for controlling the operation of the sub-PEs. The same effect can be achieved. With these features, the data transfer capability between the sub-PE and the local memory is greatly improved, and a parallel processing processor with high effective computing performance can be provided.

According to the embodiment of the present invention, the parallel computing device 1 includes a plurality of arithmetic processors (PE) 2 that perform arithmetic processing in parallel. In the arithmetic processor 2, the instruction execution control unit 3 supplies a control instruction to each. In the sub processor SPE2A, the storage unit 11A holds a plurality of data or a plurality of calculation results. The ALU 12A performs arithmetic processing on the data read from the storage unit 11A and supplies the result to the storage unit.
Further, in the sub processor, at least two sub processors among the plurality of sub processors have the same structure. Those sub-processors having the same structure form an identical structure processor group. In addition, the instruction execution control unit exchanges and supplies a control signal supplied from the exchange unit to the sub processors included in the same structure sub processor group.
As a result, it is possible to exchange data stored in the storage unit, or to change the data to be referred to and perform similar processing without preparing a similar program with different operands. And processing combinations can be exchanged.

The present invention is not limited to the above embodiments, and can be modified without departing from the spirit of the present invention.
For example, in the description of the present invention, the number of arithmetic processors 2 incorporated in one parallel computing device 1 (LSI) is 107, but the present invention is not limited to this, and one or more arithmetic processors 2 are used. Applicable to computers with built-in Further, although the number of sub-PEs to be parallelized in the VLIW type is set to 4 for each arithmetic processor 2, the present invention is not limited to this and can be applied to a system having a plurality of SPEs. Further, although the number of sub-PEs whose OP codes are exchanged by the ROT instruction is 3, the present invention is not limited to this, and can be applied to a system in which OP codes of a plurality of sub-PEs are exchanged.

  In the description of the present invention, it is assumed that all the arithmetic processors 2 form a SIMD type and are controlled by one instruction control processor. However, the present invention is not limited to this, and a plurality of arithmetic processors 2 are provided. It can be applied to an intermediate architecture between SIMD type and MIMD type. In the configuration of the second embodiment shown in FIG. 11, the OP code is decoded after exchanging the OP code of each SPE. However, when the number of control signals is smaller than the number of bits of the OP code. If the OP code is decoded and then exchanged, the same effect as that of the present invention can be obtained.

  Further, in the configuration shown in FIG. 2, the selection of Acc13A to Acc13C is made in two stages for easy understanding, but in order to reduce the number of necessary circuit elements and at the same time increase the operation speed of the circuit, It is desirable to configure in one stage as shown in FIG. In this case, as shown in FIG. 11, the data selection signals themselves of the selectors 14XA to 14XD are exchanged using the same instruction select signal as in FIG.

2 Operation processor (PE)
2A, 2B, 2C, 2C, 2D Sub operation processor (SPE, Sub processor)
2G sub-processor group (same processor group)
3 Instruction execution control processor (PE-I, instruction execution control unit)
11A, 11B, 11C, 11D Local memory (LM, storage unit)
12A, 12B, 12C, 12DA ALU (arithmetic unit)
13A, 13B, 13C, 13D Acc (register part)
31 Exchange Department

Claims (2)

A plurality of arithmetic processors that perform arithmetic processing in parallel;
An instruction execution control unit for supplying a control signal to each of the arithmetic processors;
With
The arithmetic processor is
A storage unit for holding a plurality of data or a plurality of calculation results;
An arithmetic unit that performs arithmetic processing on the data read from the storage unit and supplies the result to the storage unit;
With multiple sub-processors with
Is at least two sub-processors among the plurality of sub-processors having the same structure, the sub-processor having the same configuration and form the same structure sub processor group,
The instruction execution control unit
A parallel computing device comprising: an exchange unit that exchanges and supplies control signals to be supplied to sub-processors included in the same-structure sub-processor group. The sub-processor is
A register unit connected to one input of the arithmetic unit and storing information to be written;
The register unit is
Usually, the calculation result by the calculation unit is stored, the stored calculation result is output,
The same structure sub- processor group includes a register reference unit,
The register reference unit is a register that supplies an output from each of the register units included in each of the sub-processors included in the same-structured sub-processor group to input data to the other input of the arithmetic unit of the sub-processor. Among them, when handling as input from at least some of the registers, it is possible to change the association between the register unit and the register that supplies the input data,
The instruction execution control unit, when exchanging the control signal to be supplied to each sub processor of the same structure sub processor group, was associated with each of the registers that supply the input data before the exchange, In place of each of the register units, the input unit includes the register unit included in the sub processor to be supplied after the replacement of the control signal supplied to the sub processor to which the register unit belongs. 2. The parallel computing apparatus according to claim 1 , wherein the register reference unit is controlled so as to be newly associated with a register that supplies the data.

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