JP5356895B2 - Bias amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bias amplifier which prevents a malfunction caused by influences of power supply voltage variation or noise. <P>SOLUTION: A bias amplifier includes: an amplifier circuit 10A, of which the non-inverted input terminal is connected to a first reference voltage Vref1 and of which the inverted input terminal is connected to an output terminal 1, including a phase compensating capacitor C1 which is connected between a gate of an internal output transistor MN3 and the output terminal 1, and a shutoff transistor MN4 for turning off the output transistor MN3; a stabilizing capacitor C2 connected between the output terminal 1 and a ground GND; a malfunction detecting circuit 20 which outputs a detecting signal when a voltage Vout of the output terminal 1 becomes below a second reference voltage Vref2; and a current source circuit 30 for charging the stabilizing capacitor C2. The malfunction detecting circuit 20 outputs the detecting signal, so that the shutoff transistor MN4 turns off the output transistor MN3 and the current source circuit 30 charges the stabilizing capacitor C2. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a bias amplifier for an LCD drive, and more particularly to a bias amplifier that detects a malfunction when receiving power supply fluctuation or external noise and stops the operation.

  As a conventional amplifier used for general purposes, for example, a configuration as shown in FIG. 10A is known. In FIG. 10A, an amplifier circuit 10 serving as a voltage follower is configured by connecting a non-inverting input terminal (+) to a first reference voltage Vref1 and connecting an inverting input terminal (−) to an output terminal 1. The A stabilizing capacitor C2 is connected between the output terminal 1 and the ground GND. Therefore, in this amplifier circuit 10, the reference voltage Vref 1 is impedance-converted by the amplifier circuit 10 and is output to the output terminal 1. That is, the amplifier circuit 10 performs the impedance conversion of the reference voltage Vref1 and plays a role of outputting a constant voltage according to the load connected to the output terminal 1. The stabilizing capacitor C2 is for stabilizing the voltage at the output terminal 1 against a sudden load fluctuation.

  As shown in FIG. 11, the amplifier circuit 10 constitutes an output circuit with a current source I1 and PMOS transistors MP1 and MP2 constituting a differential input circuit, and NMOS transistors MN1 and MN2 connected as current mirrors as active loads. An NMOS transistor MN3, a current source I2, and a phase compensation capacitor C1 are provided. VDD is a high potential power supply voltage, and VSS is a low potential power supply voltage.

  Incidentally, there is COG (Chip On Glass) as a mounting form of the LCD driver. In this mounting mode, wiring resistance is increased because wiring is performed on the glass substrate. For this reason, ITO (Indium Tin Oxide) wiring resistance exists at the power supply terminal of the LCD driver. FIG. 10B is a circuit diagram in which an ITO wiring resistance R0 made of a transparent electrode film is inserted by applying this mounting form to the amplifier having the configuration shown in FIG. Due to the presence of the ITO wiring resistance R0, the power line of the amplifier circuit 10 is in a high impedance state, and noise is easily superimposed. However, the amplifier circuit configuration takes no measures against fluctuations in power supply voltage and noise.

  Conventionally, a voltage deviation occurs in the output voltage of the bias amplifier, and an auxiliary function that compensates for driving capability when an error voltage occurs, or a patent document 1 aimed at shortening the rise time of a circuit immediately after power-on. Has been proposed.

  As shown in FIG. 7, in this patent document 1, an NMOS transistor MN5 is added to the circuit shown in FIG. 10A, the source of the transistor MN5 is connected to the output terminal 1 of the amplifier circuit 10, and the gate is connected to the first circuit. 1 is connected to the reference voltage Vref1, and the drain is connected to the high potential power supply voltage VDD. In Patent Document 1, before the amplifier circuit 10 operates, the stabilization capacitor C2 is charged by the transistor MN5, and the rise time of the output voltage Vout can be shortened. In Patent Document 1, when the output voltage Vout decreases, the stabilization capacitor C2 is charged by the transistor MN5, and the driving capability of the amplifier circuit 10 can be supplemented.

Japanese Patent Application No. 2001-117648

  However, the circuit described in Patent Document 1 aims to improve the characteristics of the amplifier circuit 10 and does not have a preventive function against noise.

  The LCD driver has a built-in bias amplifier that generates a constant voltage necessary for driving the liquid crystal, and many of them are amplifiers with low current consumption. An amplifier with low current consumption has a problem in that the circuit operation is slow because the slew rate is small, and the nodes in the circuit cannot follow the noise speed.

  Here, in order to explain in detail, the cause of noise and the mechanism of malfunction will be described with reference to FIGS. In the LCD driver mounting form, since wiring is performed on the glass substrate, the ITO wiring resistance R0 exists as described above, and the power supply line of the amplifier circuit 10 has high impedance, so that noise is easily superimposed thereon.

  There are a frame inversion driving method and a line inversion driving method as LCD panel driving methods. In either case, the polarity of the applied voltage is inverted to drive the LCD panel. When the polarity is switched, all the charges on the panel are discharged and driven to the opposite polarity. Due to the current at the time of switching, a voltage drop occurs in the ITO wiring resistance R0 in FIG. 10B and appears as noise in the line of the low potential power supply voltage VSS in the LCD driver. When all the power supply terminals in the LCD driver are common, the same noise is generated in the power supply line in the bias amplifier built in the LCD driver, resulting in malfunction.

  The malfunction mechanism will be described below. In the basic configuration of the amplifier circuit 10 used conventionally, it is necessary to provide a phase compensation capacitor C1 as shown in FIG. In particular, since the role of the bias amplifier is a voltage buffer, the configuration is often used in a voltage follower. In such a case, the amplifier circuit 10 is most likely to oscillate, and it is necessary to insert a capacitor C1 for performing phase compensation. This phase compensation capacitor C1 functions as a mirror capacitor in the region where the output stage gain exists, and appears to be twice as large as the voltage gain from the internal node A. Due to the presence of this capacitor C1, the pole is shifted to the low frequency side. Stable operation is possible. Although the amplifier operation is stable due to the presence of the capacitor C1, the influence of noise on the circuit will be described below.

  In FIG. 11, the speed of the potential change of the node A, which is the output node of the differential pair, is largely limited by the presence of the capacitor C1 and the current source I1 of the differential pair that is reducing the current consumption. End up. Therefore, this node A follows the speed of the voltage fluctuation when a large voltage fluctuation occurs in the low-potential power supply voltage VSS due to a current flowing through the wiring resistance R0 in FIG. 11 or by instantaneous noise superposition. It becomes impossible to control the gate voltage of the output transistor MN3.

  Assuming that the low potential power supply voltage VSS rises momentarily (when it swings to the VDD side), the transistor MN1 of the current mirror circuit, which is an active load, functions as a diode due to the rise of the low potential power supply voltage VSS. A current is supplied to A. At this time, the charge of the phase compensation capacitor C1 is discharged, and the potential of the node A is raised. After that, when the low-potential power supply voltage VSS returns to the original voltage, the phase compensation capacitor C1 is charged by the current source I1, so that the charging becomes a constant current operation, and the node A returns to the original bias point. It takes a long time. Meanwhile, since a gate voltage higher than necessary is applied to the output transistor MN3, a drain current is caused to flow, and as a result, the potential of the output terminal 1 is lowered.

  It is an object of the present invention to provide a bias amplifier that solves such problems and prevents malfunction due to influences of fluctuations in power supply voltage and noise.

  To achieve the above object, a bias amplifier according to a first aspect of the present invention has a non-inverting input terminal connected to a first reference voltage, an inverting input terminal connected to an output terminal, and a gate of an internal output transistor, An amplifier circuit having a phase compensation capacitor connected between the output terminal and a cutoff transistor for turning off the output transistor; a stabilization capacitor connected between the output terminal and ground; and A malfunction detection circuit that outputs a detection signal when the voltage falls below a second reference voltage; and a current source circuit that charges the stabilization capacitor, and the malfunction detection circuit outputs the detection signal, thereby A cutoff transistor turns off the output transistor, and the current source circuit charges the stabilization capacitor.

According to a second aspect of the present invention, in the bias amplifier according to the first aspect, the malfunction detection circuit includes a first comparator that inputs the voltage of the output terminal and the second reference voltage and compares them with each other. The detection signal is output from the first comparator.

According to a third aspect of the present invention, in the bias amplifier according to the first aspect, the malfunction detection circuit inputs the voltage of the output terminal and the first reference voltage, and presets the first reference voltage. A second comparator that converts the input reference voltage into the second reference voltage and compares it with the voltage at the output terminal is provided, and the detection signal is output from the second comparator.

  According to a fourth aspect of the present invention, the non-inverting input terminal is connected to the first reference voltage, the inverting input terminal is connected to the output terminal, and is connected between the gate of the internal output transistor and the output terminal. An amplifier circuit having a phase compensation capacitor and a cutoff transistor for turning off the output transistor, a stabilization capacitor connected between the output terminal and ground, a voltage of the output terminal, and the first reference voltage A comparison transistor that inputs a differential voltage of the gate-source voltage as a gate-source voltage, and a malfunction detection circuit that outputs a detection signal when the current flowing through the comparison transistor reaches a predetermined value. By outputting the current, the cutoff transistor turns off the output transistor and flows through the comparison transistor. Characterized by being adapted to charge the stabilizing capacitor.

  According to the present invention, even when the amplifier circuit malfunctions due to noise, the malfunction detection circuit detects the malfunction and outputs a detection signal, so that the circuit operation of the amplifier circuit can be stopped. It is possible to prevent the bias amplifier from malfunctioning due to the influence of power supply voltage fluctuations and noise. Also, it is instantaneous from when the malfunction detection circuit outputs a detection signal to when the output transistor is turned off by the cutoff transistor, even if malfunctions occur frequently (when noise frequently occurs) It is possible to minimize the change in the voltage at the output terminal, and the current consumption can be greatly reduced.

It is a circuit diagram of the basic circuit of the bias amplifier in this invention. 1 is a circuit diagram of a bias amplifier according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the transistor level of the bias amplifier of a 1st Example. It is a circuit diagram of the bias amplifier of 2nd Example in this invention. It is a circuit diagram which shows the transistor level structure of the comparator in the bias amplifier of a 2nd Example. It is a circuit diagram of the bias amplifier of 3rd Example in this invention. 10 is a circuit diagram of a conventional bias amplifier described in Patent Document 1. FIG. FIG. 8 is a waveform diagram of a simulation result when noise is applied to the bias amplifier of FIG. 7. It is a wave form diagram of the simulation result at the time of the noise application of the bias amplifier of this invention. (A) is a circuit diagram of a conventional bias amplifier, and (b) is a circuit diagram in which an ITO wiring resistance is inserted into the configuration of the conventional bias amplifier. It is a transistor level circuit diagram of a conventional bias amplifier.

<Principle of the present invention>
FIG. 1 shows a bias amplifier with a malfunction detection function according to the present invention. In the bias amplifier of the present invention, a non-inverting input terminal (+) is connected to the first reference voltage Vref1, an inverting input terminal (−) is connected to the output terminal 1, and an output terminal of the amplifier circuit 10A. 1 is connected between the output terminal 1 and the high-potential power supply voltage VDD, the stabilization capacitor C2 connected between the ground terminal 1 and the ground GND, the malfunction detection circuit 20 that detects the occurrence of malfunction by inputting the output voltage Vout of the output terminal 1. Current source circuit 30.

  In the present invention, when the output voltage Vout of the amplifier circuit 10A decreases due to a malfunction of the amplifier circuit 10A due to noise, this is detected by the malfunction detection circuit 20 as a malfunction. As a result, the malfunction detection circuit 20 immediately outputs a detection signal to the amplifier circuit 10A and stops outputting the output voltage Vout from the amplifier circuit 10A. At the same time, the current source circuit 30 is operated to charge the stabilization capacitor C2, and the output voltage Vout is restored to a predetermined voltage. Thereafter, when the output voltage Vout returns to a predetermined voltage, the malfunction detection circuit 20 does not detect malfunction, the amplifier circuit 10A starts the normal voltage follower operation, and the stabilization capacitor C2 by the current source circuit 30 Charging stops. As a result, it is possible to prevent the bias amplifier from malfunctioning due to the influence of power supply voltage fluctuations and noise.

<First embodiment>
FIG. 2 shows a bias amplifier according to a first embodiment of the present invention, and FIG. 3 shows a transistor level circuit of the bias amplifier. In FIG. 3, the line of the low potential power supply voltage VSS and the ground GND are connected via the ITO wiring resistance R0, and the line of the low potential power supply voltage VSS is a power supply node having a relatively high impedance.

  The amplifier circuit 10A is obtained by additionally connecting a blocking NMOS transistor MN4 between the node A and the low-potential power supply voltage VSS in the configuration of the amplifier circuit 10 described in FIG. The malfunction detection circuit 20 includes a comparator 21, a second reference voltage Vref2 connected to the inverting input terminal (−) of the comparator 21, and an inverter INV that transmits the output of the comparator 21 to the transistor MN4 of the amplifier circuit 10A. The non-inverting input terminal (+) of the comparator 21 is connected to the output terminal 1. The current source circuit 30 includes a PMOS transistor MP3 and a current limiting resistor R1, and the gate of the transistor MP3 is connected to the output side of the comparator 21.

  In the driving operation of the LCD panel, since the discharge current of the panel instantaneously flows in the low potential power supply voltage VSS when the frame is switched, a voltage drop due to the ITO wiring resistance R0 occurs, and the power supply noise in the form of whiskers in the low potential power supply voltage VSS. Occurs. When the low-potential power supply voltage VSS rises momentarily due to the power supply noise and exceeds the potential of the node A, the transistor MN1 operates as a diode. At this time, a current path is generated between the node A and the low potential power supply voltage VSS via the transistor MN1, and as a result, the charge of the phase compensation capacitor C1 is discharged to the low potential power supply voltage VSS, and the terminal of the phase compensation capacitor C1 The inter-potential difference is reduced. Thereafter, with the passage of time, the potential of the low potential power supply voltage VSS returns (decreases) to near the potential of the ground GND. However, since the charge of the phase compensation capacitor C1 is discharged, the phase compensation capacitor C1 It is charged via the node A by I1 and cannot follow the recovery speed of the low potential power supply voltage VSS. In the meantime, the potential difference between the node A and the low-potential power supply voltage VSS increases, and as a result, the gate-source voltage Vgs of the output transistor MN3 increases, so that the drain current of the output transistor MN3 increases, and the output of the output terminal 1 Press down the voltage Vout.

  When the output voltage Vout becomes lower than the potential of the second reference voltage Vref2, the comparator 21 inverts the output from “H” to “L” and turns on the transistor MP3 of the current source circuit 30. As a result, a current is supplied from the high-potential power supply voltage VDD to the output terminal 1 via the current limiting resistor R1, and the stabilization capacitor C2 is charged. Further, the “L” output of the comparator 21 is inverted to “H” by the inverter INV and applied to the gate of the cutoff transistor MN4. As a result, the cutoff transistor MN4 is turned on, the node A is connected to the line of the low potential power supply voltage VSS, and the output transistor MN3 is turned off.

  When the output voltage Vout of the output terminal 1 exceeds the second reference voltage Vref2 due to the current supplied from the current source circuit 30, the comparator 21 is inverted again to change the output from “L” to “H”, and the output transistor MN4. Is turned off, and the current source transistor MP3 is turned off. This operation restores the bias amplifier to normal operation. Thus, a stop circuit is not necessary for stopping the operation.

  In the bias amplifier of this embodiment, the output stage configuration is a class A output, and the output transistor MN3 to be controlled is an NMOS type, but the circuit configuration of the output stage has a reverse polarity, and the output transistor to be controlled is a PMOS transistor. In such a case, the operation can be performed by reversing the circuit configuration function.

<Second embodiment>
FIG. 4 shows a bias amplifier according to a second embodiment of the present invention. In the present embodiment, the inverting input terminal (−) of the comparator 21A of the malfunction detection circuit 20A is connected to the first reference voltage Vref1, and the second reference voltage Vref2 is deleted. However, if the configuration of the comparator 21A is the same as that of the first embodiment described with reference to FIG. 3, malfunction detection becomes frequent. Therefore, a comparator 21A having an input offset voltage is used. The malfunction detection circuit 20A is configured.

  FIG. 5 shows the configuration of the comparator 21A. In this comparator 21A, the differential pair transistors are constituted by PMOS transistors MP11 to MP13, but the non-inverting input terminal (+) side is constituted by a series circuit of the transistors MP12 and MP13, so that a substantial PMOS transistor can be realized. By extending the L length (gate length), an offset voltage is generated in the input voltage of the comparator 21A, and the reference voltage Vref1 is converted to the reference voltage Vref2 by the offset voltage. As described above, the second reference voltage Vref2 can be omitted by generating the offset voltage in the comparator 21A. MN11 and MN12 are NMOS transistors constituting a current mirror circuit as an active load, MN13 is an NMOS output transistor, and MP14 and MP15 are PMOS transistors that function as current sources.

<Third embodiment>
FIG. 6 shows a bias amplifier according to a third embodiment of the present invention. In the bias amplifier of this embodiment, the malfunction detection circuit 20B is configured by an enhancement type comparison NMOS transistor MN21, current mirror-connected PMOS transistors MP21 and MP22, and a current source I3. The comparison transistor MN21 has a gate ground configuration in which the source is connected to the output terminal 1 of the amplifier circuit 10A and the gate is connected to the first reference voltage Vref1. The drain current of the comparison transistor MN21 is copied by the transistors MP21 and MP22. The inverter function is realized by the copy current and the current of the current source I3.

  In this embodiment, since the comparison transistor MN21 has a grounded gate configuration, when the output voltage Vout decreases due to malfunction of the amplifier circuit 10A due to noise, and the gate-source voltage Vgs of the comparison transistor MN21 exceeds the threshold value, The comparison transistor MN21 is turned on, and current is supplied from the output terminal 1 to the stabilization capacitor C2. At this time, since a current also flows through the current mirror circuit including the transistors MP21 and MP22, when the current flowing through the transistor MP22 becomes equal to or higher than the current of the current source I3, the inverter function is activated and the cutoff transistor MN4 of the amplifier circuit 10A is operated. Is turned on, the output transistor MN3 is turned off, and the operation of the amplifier circuit 10A is stopped.

<Simulation results>
Here, FIG. 8 shows the simulation result waveform of the conventional bias amplifier shown in FIG. 7 when the noise waveform is applied to the line of the low potential power supply voltage VSS, and the bias of the first embodiment of the present invention. The waveform of the simulation result of the amplifier is shown in FIG.

  In the simulation result of the conventional circuit in FIG. 8, the potential of the node A rises due to the rise of the low potential power supply voltage VSS (noise waveform), and the output transistor MN3 malfunctions, so that the output voltage Vout of the output terminal 1 is It is confirmed that it has decreased. Further, since the voltage change speed of the node A is limited by the current source I1, the operation is slow, and the output transistor MN3 continues to pass current while the potential of the node A is lowered to the potential of the low potential power supply voltage VSS. .

  On the other hand, in the simulation result of the circuit of the present invention in FIG. 9, the malfunction detection circuit 20 detects the malfunction from the decrease of the output voltage Vout due to the rise (noise waveform) of the low potential power supply voltage VSS, and the amplifier is shortened in a short time. By outputting a stop signal to the circuit 10A, the potential of the node A is immediately fixed to the original low potential power supply voltage VSS potential, and it is confirmed that the output transistor MN3 is not malfunctioning.

10, 10A: amplifier circuit 20, 20A, 20B: malfunction detection circuit, 21: (first) comparator, 21A: (second) comparator 30: current source circuit C1: phase compensation capacitor, C2: stabilization capacitor MN3 : Output transistor, MN4: cutoff transistor, MN21: comparison transistor

Claims (4)

A non-inverting input terminal connected to the first reference voltage, an inverting input terminal connected to the output terminal, and a phase compensation capacitor connected between the gate of the internal output transistor and the output terminal, and the output transistor. An amplifier circuit having a cutoff transistor to be turned off, a stabilization capacitor connected between the output terminal and the ground, and a malfunction detection circuit that outputs a detection signal when the voltage of the output terminal falls below a second reference voltage; A current source circuit for charging the stabilizing capacitor,
The bias amplifier, wherein the malfunction detection circuit outputs the detection signal so that the cutoff transistor turns off the output transistor and the current source circuit charges the stabilization capacitor. The bias amplifier of claim 1, wherein
The malfunction detection circuit includes a first comparator that inputs and compares the voltage of the output terminal and the second reference voltage, and the detection signal is output from the first comparator. amplifier. The bias amplifier of claim 1, wherein
The malfunction detection circuit receives the voltage of the output terminal and the first reference voltage, converts the first reference voltage into the second reference voltage by a preset input offset voltage, and converts the first reference voltage to the output terminal. A bias amplifier, comprising: a second comparator for comparing with a voltage, wherein the detection signal is output from the second comparator. A non-inverting input terminal connected to the first reference voltage, an inverting input terminal connected to the output terminal, and a phase compensation capacitor connected between the gate of the internal output transistor and the output terminal, and the output transistor. An amplifier circuit having a cutoff transistor to be turned off, a stabilization capacitor connected between the output terminal and the ground, and a differential voltage between the voltage of the output terminal and the first reference voltage is input as a gate-source voltage. A malfunction detection circuit that outputs a detection signal when the current flowing through the comparison transistor reaches a predetermined value.
The bias amplifier, wherein the malfunction detection circuit outputs the detection signal so that the cutoff transistor turns off the output transistor and a current flowing through the comparison transistor charges the stabilization capacitor.

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