JP5355921B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify number of processes and also improve integration required, when forming a multilayer integrated circuit comprised of multilayer structure single crystal semiconductor layers on a support substrate. <P>SOLUTION: The semiconductor device, formed by allowing a plurality of semiconductor elements to be laminated via insulating layers has a structure, such that semiconductor layers comprising the semiconductor elements are laminated via the insulating layers and a region which a semiconductor layer is in contact with a wiring is superimposed with other semiconductor layer disposed via the insulating layer. The contact region is formed by a silicide layer which extends from a conductive impurity region disposed on the semiconductor layer. In other words, the semiconductor device has a structure, such that the region in contact with the semiconductor element and wiring is formed by the silicide and is also disposed at a position superimposed with an upper layer semiconductor element, thereby a portion between the conductive impurity region that comprises the semiconductor element and a region in contact with the wiring is coupled by the silicide. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to a semiconductor device having a plurality of semiconductor layers and a manufacturing method thereof.

In the technical field of semiconductor devices, higher performance and lower power consumption of semiconductor devices have been attempted with the aim of further miniaturization and higher integration. In order to improve the degree of integration of a semiconductor integrated circuit, a multilayer integrated circuit in which an integrated circuit (semiconductor element layer) has a multilayer structure has been proposed.

As an example of manufacturing such a multilayer integrated circuit, an organic material interlayer insulator is formed on a first semiconductor element layer provided on a substrate, and a second semiconductor element layer is stacked on the interlayer insulator. Have been reported (see, for example, Patent Document 1).

On the other hand, instead of a silicon wafer produced by thinly cutting a single crystal semiconductor ingot, a semiconductor substrate (SOI substrate) called a silicon-on-insulator in which a thin single crystal semiconductor layer is provided on an insulating layer ) Have been developed and are becoming popular as substrates for manufacturing microprocessors and the like. This is because integrated circuits using an SOI substrate are attracting attention as reducing parasitic capacitance between the drain of the transistor and the substrate, improving the performance of the semiconductor integrated circuit, and reducing power consumption.

As a method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (see, for example, Patent Document 2). In the hydrogen ion implantation separation method, a microbubble layer is formed at a predetermined depth from the surface by injecting hydrogen ions into a silicon wafer, and the microbubble layer is used as a cleavage plane, so that a thin silicon film is formed on another silicon wafer. Bond layers (SOI layers). In addition to performing heat treatment for peeling the SOI layer, an oxide film is formed on the SOI layer by heat treatment in an oxidizing atmosphere, and then the oxide film is removed, and then heat treatment is performed in a reducing atmosphere at 1000 to 1300 ° C. It is said that it is necessary to increase the bonding strength by performing the above.

Attempts have also been made to form an SOI layer on an insulating substrate such as glass. As an example of an SOI substrate in which an SOI layer is formed on a glass substrate, a thin single crystal silicon layer is formed on a glass substrate having a coating film by using a hydrogen ion implantation separation method (Patent Document 3). And Patent Document 4). Also in this case, a microbubble layer is formed at a predetermined depth from the surface by implanting hydrogen ions into the single crystal silicon piece, and after bonding the glass substrate and the single crystal silicon piece, the microbubble layer is used as a cleavage plane to form silicon. A thin silicon layer (SOI layer) is formed on the glass substrate by peeling the piece.

As a structure of a thin film transistor (TFT) on an insulating substrate such as a glass substrate, a structure in which a base insulating film, an active layer, a gate insulating film, a gate electrode, an interlayer insulating film, and a wiring are formed on a glass substrate. Can be mentioned. As one of the purposes for increasing the response speed of the TFT, the design rule of the entire TFT is reduced.
JP-A-5-335482 US Pat. No. 6,372,609 JP 11-163363 A US Pat. No. 7,119,365

When a multilayer integrated circuit having a multilayer structure of the above integrated circuit is formed on a supporting substrate that is not superior in heat resistance compared to a silicon wafer, such as a glass substrate, if the semiconductor layer has good crystallinity, the performance is improved. Low power consumption can be achieved. For this purpose, it is effective to form a thin single crystal semiconductor layer (SOI layer) on a supporting substrate by a hydrogen ion implantation separation method using a single crystal semiconductor.

Further, as the integrated circuit has a multi-layer structure, the number of manufacturing steps becomes more complicated. Therefore, it is desirable to simplify the number of steps.

An object of the present invention is to provide a semiconductor device which is a more integrated multilayer integrated circuit.

An object of the present invention is to manufacture a semiconductor device which is a multilayer integrated circuit with high productivity.

The present invention has a structure in which semiconductor layers constituting a semiconductor element are stacked through an insulating layer, and a region where one semiconductor layer is in contact with a wiring overlaps with another semiconductor layer provided through the insulating layer This is a semiconductor device having a configuration arranged as described above. In this configuration, the contact region is formed by a silicide layer extending from one conductivity type impurity region provided in the one semiconductor layer. That is, in a semiconductor device in which a plurality of semiconductor elements are stacked via an insulating layer, a contact region between the semiconductor element and a wiring is formed of silicide and arranged at a position overlapping with an upper semiconductor element, thereby configuring the semiconductor element This is a semiconductor device having a configuration in which the one conductivity type impurity region and the contact region of the wiring are connected by silicide.

Since silicide is formed on the surface side of the semiconductor layer, it can be electrically connected to one conductivity type impurity region formed in the semiconductor layer, and a contact region between the one conductivity type impurity region and the wiring, Acts to reduce the resistance between.

According to a method for manufacturing a semiconductor device of the present invention, a first island-shaped semiconductor layer partially including silicide is formed on an insulating surface, a second island-shaped semiconductor layer is formed thereon, and the first island-shaped semiconductor layer is formed. A layer located above a partial region of the island-shaped semiconductor layer is removed, and one conductivity is applied to a portion of the first island-shaped semiconductor layer and a portion of the second island-shaped semiconductor layer. An impurity to be added is added to form a high concentration impurity region in the first island-shaped semiconductor layer and the second island-shaped semiconductor layer. In particular, when a transistor is provided in the first semiconductor element layer, a first gate insulating film is formed on the first island-shaped single crystal semiconductor layer, and a first gate electrode is formed thereon, A sidewall in contact with the first gate electrode is formed, and after the sidewall is formed, silicide is formed in part of the first island-shaped single crystal semiconductor layer.

A semiconductor device formed by the above manufacturing method includes a first island-shaped semiconductor layer on an insulating surface, a conductive layer thereon, and a second island-shaped semiconductor layer thereon. In particular, the first island-shaped semiconductor layer includes a first region to which an impurity imparting one conductivity is added, and a second region that is electrically connected to the first region and in which silicide is formed. The second region is disposed so as to overlap with either the conductive layer or the second island-shaped semiconductor layer on a plane, and the second island-shaped semiconductor layer imparts the one conductivity. And a third region to which impurities to be added are added at a concentration substantially equal to that of the first region.

With such a configuration, the first region becomes a high concentration impurity region, and the second region becomes a silicide formation region. A semiconductor element including the first island-shaped semiconductor layer is formed by the first region and the second region. In particular, when a transistor is provided in the first semiconductor element layer, the first region and the second region become a source region or a drain region.

At this time, the region where silicide is formed is provided apart from the semiconductor junction interface region. For example, a transistor is an interface between a channel region and a source region, an interface between a channel region and a drain region, an interface between a channel region and an LDD region, an interface between an LDD region and a source region, and an LDD region. And the interface between the drain region and the like. That is, the semiconductor junction interface region is a region where the amount of impurities imparting one conductivity added to the semiconductor changes, and refers to a region that determines semiconductor element characteristics.

In the present invention, the transistor is preferably a top gate type. This is because an impurity imparting one conductivity can be added from above the substrate by self-alignment using the gate electrode on the island-like semiconductor layer as a mask. At this time, a structure in which the gate electrode has a stacked structure of metal materials and a part of the source region and the drain region are formed between the gate electrode and the substrate can be formed.

In the semiconductor device of the present invention, the source region or the drain region of the transistor in the substrate plane including the first region is removed by removing a stacked structure such as an interlayer film on the upper layer, thereby performing ion doping or ion implantation. According to the method, an impurity imparting one conductivity can be added. However, as described above, in the transistor of the first semiconductor element layer, silicide is formed, and in the portion separated from the semiconductor junction interface region, the laminated structure such as the interlayer film on the upper layer is removed to give one conductivity. It is not necessary to add impurities to be added. This is because by providing silicide in the source region and the drain region, the resistance of a portion where no impurity is added can be sufficiently reduced.

By forming silicide in this way, another effect can be obtained for integration. That is, the semiconductor layer region in which silicide is formed has a much lower resistance than the semiconductor layer region to which an impurity imparting one conductivity is added and no silicide is formed, and thus can be used as a wiring. If the degree of freedom of wiring formation increases, it can contribute to high integration.

The method for manufacturing a semiconductor element of the present invention is effective for an element to which an impurity imparting one conductivity type in a semiconductor is added, such as a memory element, a diode, a resistor, a coil, a capacitor, and an inductor, in addition to a transistor. In any case, silicide is formed in the low-resistance semiconductor layer, and in the portion separated from the semiconductor junction interface region, the laminated structure such as an interlayer film on the upper layer is removed during the step of adding an impurity imparting one conductivity type. It is not necessary.

Since the semiconductor element of the present invention is intended for integration, it is preferable to use a single crystal semiconductor layer using SOI technology in order to form a semiconductor layer with high mobility and small size.

In the present invention, after adding an impurity imparting one conductivity, activation by laser irradiation or heat treatment by a diffusion furnace is performed.

A contact region between the semiconductor element and the wiring is formed of silicide and disposed at a position overlapping with the upper semiconductor element, and the contact region between the one conductivity type impurity region constituting the semiconductor element and the wiring is connected with silicide. As a result, in the three-dimensional integrated circuit, the process can be simplified and the degree of integration can be improved.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment mode, a semiconductor device and a manufacturing method of the semiconductor device which are aimed at higher integration and downsizing will be described in detail with reference to FIGS. For such a purpose, an example in which a single crystal semiconductor layer using SOI technology is used in the following semiconductor device is shown.

The semiconductor device in this embodiment has a structure in which a single crystal semiconductor element layer is stacked in multiple layers over a supporting substrate. In this embodiment, a semiconductor device including two single crystal semiconductor element layers is described as an example. The upper and lower single crystal semiconductor element layers to be stacked are electrically connected by a wiring layer penetrating the stacked structure.

Hereinafter, a method for manufacturing a semiconductor device in this embodiment will be described.

First, as illustrated in FIG. 1A, the insulating layer 111 is formed over the single crystal semiconductor substrate 110. The insulating layer 111 can have a single-layer structure or a multilayer structure of two or more layers. The thickness can be 5 nm or more and 400 nm or less. In this embodiment, the insulating layer 111 has a two-layer structure including the insulating film 111a and the insulating film 111b. The combination of the insulating film 111a and the insulating film 111b that causes the insulating layer 111 to function as a blocking film is, for example, a silicon oxide film and a silicon nitride film, a silicon oxynitride film and a silicon nitride film, a silicon oxide film and a silicon nitride oxide film, or an oxynitride film. There are a silicon film, a silicon nitride oxide film, and the like.

For example, as the lower insulating film 111a, the single crystal semiconductor substrate 110 can be oxidized to form an oxide film. The thermal oxidation treatment for forming the oxide film may be dry oxidation using oxygen gas for growing the oxide film, but it is preferable to add a gas containing halogen to the oxidizing atmosphere. An oxide film containing halogen can be formed as the insulating film 111a. As the gas containing halogen, one or more kinds of gases selected from HCl, HF, NF ₃ , HBr, Cl, ClF, BCl ₃ , F, Br _{2 and the} like can be used. By performing the heat treatment in such a temperature range, it is possible to obtain a gettering effect of metal impurities in the structure by halogen.

Next, as illustrated in FIG. 1B, the single crystal semiconductor substrate 110 is irradiated with an ion beam 121 including ions accelerated by an electric field through the insulating layer 111, so that the surface of the single crystal semiconductor substrate 110 is irradiated. An embrittled region 116 is formed in a region having a predetermined depth. The ion beam 121 is generated by exciting the source gas to generate a plasma of the source gas, and extracting ions contained in the plasma by the action of an electric field from the plasma. The thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 110 is determined by the depth to which ions are added. The depth at which the embrittlement region 116 is formed is adjusted so that the thickness of the single crystal semiconductor layer is 20 nm to 500 nm, preferably 20 nm to 200 nm.

After the embrittlement region 116 is formed over the single crystal semiconductor substrate 110, the bonding layer 114 is formed over the upper surface of the insulating layer 111 as illustrated in FIG. In the step of forming the bonding layer 114, the heating temperature of the single crystal semiconductor substrate 110 is set to a temperature at which an element or molecule added to the embrittlement region 116 is not precipitated, and the heating temperature is preferably 350 ° C. or lower. In other words, this heating temperature is a temperature at which gas does not escape from the embrittled region 116. Note that the bonding layer 114 can also be formed before the ion addition step. In this case, the process temperature when forming the bonding layer 114 can be 350 ° C. or higher.

The bonding layer 114 is a layer for forming a smooth and hydrophilic bonding surface on the surface of the single crystal semiconductor substrate 110. Therefore, the average roughness Ra of the bonding layer 114 is 0.7 nm or less, and more preferably 0.4 nm or less. The thickness of the bonding layer 114 can be greater than or equal to 10 nm and less than or equal to 200 nm. The preferred thickness is 5 nm or more and 500 nm or less, and more preferably 10 nm or more and 200 nm or less.

On the other hand, the support substrate 100 is a light transmissive substrate such as an aluminosilicate glass, an aluminoborosilicate glass, or a barium borosilicate glass that is used for the electronic industry. In addition to the above example, a substrate using a material having a softening point temperature higher than that of the glass substrate may be used. For example, a quartz substrate, a ceramic substrate, a sapphire substrate, or the like may be used.

Then, the single crystal semiconductor substrate 110 over which the insulating layer 111, the embrittled region 116, and the bonding layer 114 are formed and the supporting substrate 100 are washed. This cleaning step can be performed by ultrasonic cleaning with pure water. In addition, the surface of the bonding layer 114 and the support substrate 100 can be activated by cleaning with ozone water, irradiation with an atomic beam or an ion beam, plasma treatment, or radical treatment. When an atomic beam or an ion beam is used, a rare gas neutral atom beam or a rare gas ion beam such as argon can be used.

FIG. 1D is a cross-sectional view illustrating a bonding process. The supporting substrate 100 and the single crystal semiconductor substrate 110 are brought into close contact with each other through the bonding layer 114. A pressure of about 300 to 15000 N / cm ² is applied to one end of the single crystal semiconductor substrate 110. This pressure is preferably 1000 to 5000 N / cm ² . The bonding layer 114 and the support substrate 100 start to be bonded from the portion where the pressure is applied, and the bonding portion reaches the entire surface of the bonding layer 114. As a result, the single crystal semiconductor substrate 110 is in close contact with the support substrate 100. Since this bonding step can be performed at normal temperature without heat treatment, a low heat resistant substrate having a heat resistant temperature of 700 ° C. or lower such as a glass substrate can be used as the supporting substrate 100.

After the single crystal semiconductor substrate 110 is attached to the supporting substrate 100, heat treatment for increasing the bonding force at the bonding interface between the supporting substrate 100 and the bonding layer 114 is preferably performed. This treatment temperature is set to a temperature that does not cause cracks in the embrittled region 116, and the treatment can be performed in a temperature range of 200 ° C. or higher and 450 ° C. or lower. In addition, by bonding the single crystal semiconductor substrate 110 to the supporting substrate 100 while heating in this temperature range, the bonding force at the bonding interface between the supporting substrate 100 and the bonding layer 114 can be strengthened.

Next, heat treatment is performed to cause separation in the embrittled region 116, so that the single crystal semiconductor layer 112 is separated from the single crystal semiconductor substrate 110. FIG. 1E illustrates a separation process for separating the single crystal semiconductor layer 112 from the single crystal semiconductor substrate 110. The element with the embrittlement region 116 indicates the single crystal semiconductor substrate 110 from which the single crystal semiconductor layer 112 is separated.

For this heat treatment, a rapid thermal annealing (RTA) device, a resistance heating furnace, or a microwave heating device can be used. As the RTA apparatus, a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. Through this heat treatment, the temperature of the supporting substrate 100 to which the single crystal semiconductor layer 112 is attached is preferably increased to a range of 550 ° C. to 650 ° C.

The single crystal semiconductor layer 112 is preferably planarized and thinned using CMP or the like after the above steps. For example, hydrogen, an inert gas typified by helium, or a halogen ion typified by fluorine is implanted into a predetermined depth of the single crystal semiconductor substrate, and then a heat treatment is performed to separate the surface single crystal silicon layer. It can be formed by an ion implantation separation method. Alternatively, a method may be applied in which single crystal silicon is epitaxially grown on porous silicon, and the porous silicon layer is cleaved with a water jet and peeled off. The thickness of the single crystal semiconductor layer 112 is 5 nm to 500 nm, preferably 10 nm to 200 nm. Note that the present invention is not limited to this, and the single crystal semiconductor layer 112 may be planarized and thinned by a reverse sputtering method. Further, planarization and thinning may be performed by using CMP and reverse sputtering together.

FIG. 2A illustrates a region where an element is formed in an SOI substrate including the single crystal semiconductor layer 112a in which the single crystal semiconductor layer 112 is planarized and thinned in this manner. First, a pattern is formed so that the single crystal semiconductor layer 112a of the SOI substrate has a desired shape (see FIG. 2B). A resist mask is used for pattern formation. In a state where a resist mask having a desired pattern is formed, the single crystal semiconductor layer 112a is etched, so that an island-shaped single crystal semiconductor layer 113 is formed. The etching condition at this time may be a condition in which the etching rate for the island-shaped single crystal semiconductor layer 113 is high and the etching rate for the insulating layer 111 is low, and either dry etching or wet etching is selected.

Next, a first gate insulating film 115 and a first gate electrode layer 122 are sequentially formed, and an LDD region 113c is formed in the island-shaped single crystal semiconductor layer 113 (see FIG. 2C). Next, a sidewall 124 is formed, and a silicide 125 is formed in a portion to be a source region or a drain region 113b.

The first gate insulating film 115 is formed using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. For the formation, a CVD method, a sputtering method, a plasma CVD method, or the like may be used. The film thickness is 5 nm to 200 nm. Note that the first gate insulating film 115 is not limited to the illustrated structure, and may be formed over the entire surface.

The first gate electrode layer 122 can be formed by a CVD method, a sputtering method, a droplet discharge method, or the like. The first gate electrode layer 122 may be formed using an element selected from tantalum, tungsten, titanium, and molybdenum, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor layer typified by polycrystalline silicon doped with an impurity element such as phosphorus may be used. Further, it may be a single layer or a stacked layer. For example, a two-layer structure including a titanium nitride film and a molybdenum film, or a three-layer structure in which a tungsten film with a thickness of 50 nm, an alloy film of aluminum and silicon with a thickness of 500 nm, and a titanium nitride film with a thickness of 30 nm are stacked. It is good also as a structure.

The LDD region 113c is formed by adding an impurity element of one conductivity type so that ions can pass through the first gate electrode layer by an ion doping method or an ion implantation method. The LDD region 113c is an impurity region into which an impurity of one conductivity type is introduced at a low concentration. Note that the LDD region is a region formed for the purpose of improving reliability in a TFT in which a semiconductor layer is formed of a polycrystalline silicon film. It is important to suppress the off current in a TFT whose semiconductor layer is polycrystalline silicon, and a sufficiently low off current is required particularly when used as an analog switch such as a pixel circuit. However, due to the reverse bias strong electric field at the drain junction, there is a leakage current through the defect even at the off time. Since the electric field in the vicinity of the drain end is relaxed by the LDD region, the off-current can be reduced. In addition, the reverse bias electric field at the drain junction can be distributed to the junction between the channel formation region and the LDD region, and the junction between the LDD region and the drain region, and the electric field is relaxed, thereby reducing leakage current. .

Next, sidewalls 124 are provided on side surfaces of the first gate electrode layer 122. The sidewall 124 is formed by forming an insulating film over the entire surface and selectively etching the insulating film. Note that the insulating film type is the same as that of the first gate insulating film 115.

Next, a silicide 125 is formed in a portion that becomes a source region or a drain region. First, a conductive film is formed over the gate electrode layer. As a material of the conductive film, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), hafnium (Hf), tantalum (Ta), vanadium (V ), Neodymium (Nd), chromium (Cr), platinum (Pt), palladium (Pd), and the like are formed by a technique such as sputtering. Next, silicide 125 is formed by reacting the conductive film with silicon in the exposed semiconductor layers of the source and drain regions by heat treatment, GRTA method, LRTA method, or the like.

The source region or the drain region is a semiconductor layer with a low resistance, and is usually a high concentration impurity region formed by introducing one conductivity type impurity at a high concentration. At this time, the impurity imparting one conductivity to the source region or the drain region does not reach the final concentration. That is, it is added in a later step.

Next, the insulating film 130 is formed, and an opening for connecting the first wiring layer 120 formed over the insulating layer and the source region or the drain region of the island-shaped single crystal semiconductor layer 113 is formed. . The first wiring layer 120 is formed through the opening. The first wiring layer 120 is made of a heat-resistant material, and is formed of an element selected from tantalum, tungsten, titanium, and molybdenum, or an alloy material or a compound material containing the element as a main component, like the first gate electrode layer. do it.

As described above, the first gate electrode layer 122 and the first wiring layer 120 are preferably formed using a material that can withstand heat treatment in the range of 550 ° C. to 650 ° C.

Through the above steps, the first single crystal semiconductor element layer 140 is formed. Next, a second single crystal semiconductor element layer is formed over the supporting substrate.

After the first wiring layer 120 is formed, an insulating film 134 is formed (see FIG. 2D). The insulating film 134 has a smooth surface and forms a hydrophilic surface. As the insulating layer, a silicon oxide film can be used. As the silicon oxide film, a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas is preferable. In addition, a silicon oxide film manufactured by a chemical vapor deposition method using silane gas can be used.

Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), trimethylsilane (TMS: (CH ₃ ) ₃ SiH), tetramethylsilane (chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclo Tetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) and other silicon-containing compounds can be used. Note that in the case where a silicon oxide layer is formed by a chemical vapor deposition method using organosilane as a source gas, it is preferable to mix an oxygen-providing gas. As a gas for imparting oxygen, oxygen, nitrous oxide, nitrogen dioxide, or the like can be used. Further, an inert gas such as argon, helium, nitrogen or hydrogen may be mixed.

The insulating film 134 may be planarized. As the planarization process, a polishing process or an etching process may be performed. Of course, both the polishing process and the etching process may be performed. As the polishing treatment, a chemical mechanical polishing (CMP) method or a liquid jet polishing method can be used. As the etching treatment, wet etching, dry etching, or both can be used as appropriate.

Then, another single crystal semiconductor substrate in which the embrittlement region is formed as described above is attached to the insulating film 134, and heat treatment is performed to cause separation in the embrittlement region. The single crystal semiconductor layer is separated. Thus, the embrittlement region 135, the insulating film 136 formed thereon, and the second single crystal semiconductor layer 137 formed thereon are formed over the supporting substrate (see FIG. 3A).

Further, a second single crystal semiconductor element layer 141 is formed in the same manner as described above. In FIG. 3B, similarly to the first single crystal semiconductor element layer 140, a transistor which is an element is provided with a sidewall to form an LDD region.

A transistor formed in each single crystal semiconductor element layer may have a single drain shape without forming sidewalls and LDD regions. In this case, a single crystal semiconductor layer formation, a gate insulating film formation, a gate electrode layer formation, and an impurity addition formation may be performed. The transistor has a structure in which a desired function is considered. For example, in the first single crystal semiconductor element layer 140, an analog arithmetic element having a small leakage current even when the process is long is formed using a sidewall and an LDD region. The single crystal semiconductor element layer 141 may have a structure in consideration of the purpose and productivity so that a single drain structure is formed in a process in which a digital arithmetic element is shortened. Although the single crystal semiconductor element layer has two layers, the process is optimized as described above when three or more layers are formed.

The source and drain regions of the transistor in the substrate surface are arranged so that an impurity imparting one conductivity can be added by ion doping or ion implantation by removing a laminated structure such as an interlayer film above the transistor. To do. However, a part of the source region and the drain region formed in the first single crystal semiconductor element layer 140 has a structure and a structure of the elements in the first wiring layer 120 and the second single crystal semiconductor element layer 141 on a plane. An overlapping region 143 may occur. At this time, at least a semiconductor junction interface of the transistor in the first single crystal semiconductor element layer 141 is disposed so as not to overlap with the transistor and the wiring in the first single crystal semiconductor element layer 140.

Next, the interlayer film is etched so that the upper portion of the element portion of the first single crystal semiconductor element layer 140 is exposed (see FIG. 3C). Then, introduction of an impurity 123 imparting one conductivity type to the transistors in the first single crystal semiconductor element layer 140 and the second single crystal semiconductor element layer 141 is performed, so that a source region or a drain region is formed. These regions are doped with low-concentration impurities when the LDD region is formed. Here, high-concentration impurities are further introduced by bare doping. Since an n-channel transistor is formed in this embodiment mode, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into a semiconductor layer. In the case of forming a p-channel transistor, an impurity element imparting p-type conductivity such as boron (B) may be introduced into the semiconductor layer.

In this way, high-concentration impurities are added to the source region or the drain region. When attention is paid to the first single crystal semiconductor element layer 140, an element is formed in an upper layer in this step, that is, in the region 143 overlapping on the plane. Impurities are not added to the source region or the drain region. In this embodiment mode, a silicide 125 is formed in the transistor in the first single crystal semiconductor element layer 140, so that the resistance of the source region or the drain region of the region 143 can be sufficiently low.

Next, after forming a first interlayer insulating film (not shown) including a silicon oxide film by CVD with a thickness of 50 nm, a step of activating the impurity element added to each island-like semiconductor region is performed. This activation process is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods. By this activation treatment, the LDD region, the source region, and the drain region function in the transistor.

Next, as shown in FIG. 4, an interlayer film 144 is formed. The interlayer film 144 is formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. Further, an organic resin film may be laminated on the organic resin film or the protective film instead of the silicon nitride film or the like. As the organic resin material, polyimide, polyamide, acrylic, benzocyclobutene (BCB), or the like can be used.
Advantages of using the organic resin film include a point that the film formation method is simple, a point that parasitic capacitance can be reduced because the relative dielectric constant is low, and a point that it is suitable for flattening. Of course, organic resin films other than those described above may be used.

Thereafter, contact holes reaching the source region and the drain region for forming a desired wiring are formed in the interlayer film 144, and then a wiring layer 145 is formed. The wiring layer 145 may be made of a material having low heat resistance, such as aluminum or an aluminum alloy, depending on the upper limit of the processing temperature in a later step. That is, a conductive film can be formed by a PVD method, a CVD method, a vapor deposition method, or the like, and then etched into a desired shape. Further, the wiring layer 145 can be selectively formed at a predetermined place by a printing method, an electrolytic plating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the wiring layer 145 is formed using a metal such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, or Ba. do it. A light-transmitting material can also be used.

By the wiring layer 145, the first single crystal semiconductor element layer 140 and the second single crystal semiconductor element layer 141 are electrically connected. Although not illustrated, in the case where a part of the lower single crystal semiconductor layer and the upper single crystal semiconductor layer are overlapped and stacked, the wiring layer 145 passes through the upper single crystal semiconductor layer and passes through the lower single crystal semiconductor layer or the second single crystal semiconductor layer. It may be formed in contact with one wiring layer 120. When the layers that can be stacked as described above are stacked densely so as to overlap with each other, a highly integrated semiconductor device can be obtained.

Although FIG. 3 illustrates a structure in which two single crystal semiconductor element layers are stacked, a stacked structure including three or more layers may be used. The plurality of single crystal semiconductor elements can be stacked by bonding an insulating layer provided over a substrate and a single crystal semiconductor layer. In this case, stacked single crystal semiconductor element layers are formed by repeating exposure of a desired transistor and introduction of an impurity imparting one conductivity several times.

In such a configuration, the step of introducing an impurity imparting one conductivity of a plurality of source regions and drain regions is not performed for each layer, but a plurality of layers are performed at a time, which is different from the conventional technique. There is. One of the functions and effects of the present invention is that since the impurity introduction process can be reduced, defects due to incomplete process treatment can be reduced, and a semiconductor device can be manufactured with high productivity.

The semiconductor device of the present invention has a structure in which single crystal semiconductor elements are three-dimensionally stacked and highly integrated. As a single crystal semiconductor element, not only a field effect transistor but also a memory element using a single crystal semiconductor layer can be applied, and a semiconductor device satisfying functions required for various purposes can be manufactured and provided. .

(Embodiment 2)
In this embodiment mode, an example of element arrangement in which an impurity imparting one conductivity can be added from the substrate surface, which can be manufactured with reference to Embodiment Mode 1, is shown.

In this embodiment, an example in which booster circuits are stacked will be described. The booster circuit is used for many purposes such as CCD, organic EL, low-temperature polysilicon liquid crystal, white light emitting diode, RF circuit, and multi-power supply system. For example, with a decrease in voltage in a semiconductor device such as a flash memory, the power supply voltage is boosted in order to obtain a high voltage necessary for writing and erasing data. 2. Description of the Related Art In recent years, boosting circuits that generate a high voltage with a small area and high efficiency are expected in many fields as the integrated circuits of semiconductor devices become highly integrated.

The booster circuit in the semiconductor device described in this embodiment includes a capacitor (bipolar), here, a first input end 151, a second input end 152, an output end 153, Capacitive elements 205_1 to n-th capacitive element 205_n, first diode 154_1 to n-th diode 154_n, and an inverter 156. The first diode 154_1 to the n-th diode 154_n are rectifying elements that are connected in series and have a rectifying action from the first input end 151 to the output end 153. Here, the first input end 151 is connected to one electrode of the first diode 154_1, and the other electrode of the first diode 154_1 is one electrode of the second diode 154_2 and the first capacitor element. It is connected to one electrode of 205_1 (see FIG. 5).

The second input end 152 is connected to the first wiring 157a and the second wiring 157b. The first wiring 157a is connected to the other electrode of the odd-numbered capacitor such as the first capacitor 205_1 or the third capacitor 205_3. The second wiring 157b is connected to the other electrode of the even-numbered capacitor such as the second capacitor 205_2 or the fourth capacitor 205_4.

A predetermined voltage (for example, power supply voltage) is input to the first input end 151, and a boosted voltage is output from the output end 153. In addition, a clock signal is input to the second input end portion 152, and a signal (“High” or “Low” inverted by the inverter 156 to the first wiring 157 a and the second wiring 157 b, respectively. )) Is entered. Therefore, at regular intervals, the other electrode of the odd-numbered capacitor element (the first capacitor element 205_1, the third capacitor element 205_3, etc.) connected to the first wiring 157a and the second wiring 157b are connected. High and low are applied to the other electrodes of the even-numbered capacitor elements (second capacitor element 205_2, fourth capacitor element 205_4, etc.), respectively.

The operation of the booster circuit of the semiconductor device of this embodiment will be briefly described with reference to FIG.

The booster circuit shown here includes n diodes 154_1 to 154_n, capacitive elements 205_1 to 205_n, and an inverter 156. When a clock signal is input, the input voltage is VIN and the forward voltage of the diode is VF. The output is that a voltage of (VIN−VF) × n can be obtained. The clock signal is input to one end of 205_1 and 205_3 through the second input end 152, and the signal inverted by the inverter 156 is input to one end of 205_2. The anode viewed from the diode 154_2 is A, and the cathode is B. Charges are supplied to the anode A and the cathode B by the clock signal and its inverted signal, respectively. When the potential difference between the anode A and the cathode B exceeds the forward voltage VF of the diode, a current flows and boosts the cathode side. The voltage that rises at this time is (VIN-VF). When a plurality of circuits are connected in series, the output voltage increases by (VIN−VF) each time one stage is advanced. In the case of FIG. 5, since n stages are connected in series, the output increases by (VIN−VF) × n. In this way, the circuit of FIG. 5 functions as a booster circuit.

Since the diode in the element group 190 shown in FIG. 5 is required to have a rectifying function, it is necessary to reduce the off current and the cut current. That is, it is effective to form a sidewall and an LDD region in the diode 154 of the element group 190. If the sidewalls are formed, the number of steps for forming silicide in the source region and the drain region is not significantly increased as in the first embodiment. Therefore, in this embodiment, the diode 154 includes the sidewalls and , LDD regions and silicide are formed.

Next, a specific configuration of the booster circuit of the semiconductor device of this embodiment will be described with reference to FIGS. 6 is a schematic diagram of a top view of the element group 190 in FIG. 5, and FIG. 7 is a schematic diagram of a cross-sectional view between A1 and A2 in FIG.

In FIG. 6, n diodes 154_1 to 154_n are shown, and the island-shaped single crystal semiconductor layers 163_1 to 163_n, the gate electrode layers 167_1 to 167_n, the wirings 168_1 to 168_n, the conductive films 170_1 to 170_n, which are configured or connected to the diodes 154_1 to 154_n. have.

In FIG. 7, island-shaped single crystal semiconductor layers 163 </ b> _ <b> 1 to 163 </ b> _n provided over the supporting substrate 150 through the bonding layer 161 and the insulating layer 162, and gates provided above the gate insulating films 165 </ b> _ <b> 1 through 165 </ b> _n. A part of the structure including the electrode layers 167_1 to 167_n, the insulating film 169 above the electrode layers, and the conductive films 170_1 to 170_n above the electrode layers is shown. In addition, LDD regions 171_1 to 171_n, source or drain regions 172_1 to 172_n, silicide layers 173_1 to 173_n, and sidewalls 174_1 to 174_n are formed in each island-shaped single crystal semiconductor layer.

Although not illustrated in FIG. 7, the gate electrode layers 167_1 to 167_n and the wirings 168_1 to 168_n connected to the capacitor have the same structure. 5A to 5C are formed with a plurality of electrode layers. The first wiring 157a and the second wiring 157b can be formed in a manner similar to that of the conductive films 170_1 to 170_n.

In the thin film transistor including the island-shaped single crystal semiconductor layer 163, the gate insulating film 165, and the gate electrode layer 167 functioning as a gate electrode, the gate electrode layer 167 and the conductive film 170_1 functioning as a source electrode or a drain electrode are electrically connected. Connected and functions as a diode. The conductive film 170_1 corresponds to one electrode of the first diode 154_1 in FIG. 5, and the conductive film 170_2 corresponds to the other electrode of the first diode 154_1.

When formed in this manner, among the regions where the island-shaped single crystal semiconductor layers 163_1 to 163_n are formed on a plane, a region 195 where the conductive films 170_1 to 170_n overlap and a region 196 where they do not overlap can be distinguished.

An example in which the diode of the booster circuit having the above structure is provided in the first single crystal semiconductor element layer 194 and the diode of the booster circuit having the same structure is provided in the second single crystal semiconductor element layer 194 is shown in FIGS. 9 and FIG.

As illustrated in FIG. 8, the first diode 155 </ b> _ <b> 1 to the n-th diode 155 </ b> _n and the first diode 154 </ b> _ <b> 1 to n-th diode in the first single-crystal semiconductor element layer 193 are provided in the second single crystal semiconductor element layer 194. It is formed in the same manner as 154_n. At this time, the n diodes 155_1 to 155_n include island-shaped single crystal semiconductor layers 164_1 to 164_n. 9 and 10 illustrate the element group 191 including the first diode 155_1 to the n-th diode 155_n in FIG.

An arrangement example of the second single crystal semiconductor element layer 194 at this time is shown in FIG. Note that in FIG. 9, only the island-shaped single crystal semiconductor layers 164 </ b> _ <b> 1 to 164 </ b> _n of the single crystal semiconductor element layer 194 are illustrated for description. The island-shaped single crystal semiconductor layers 164_1 to 164_n and the island-shaped single crystal semiconductor layers 163_1 to 163_n partially overlap with each other in the region 195. On the other hand, in the region 196, it is shown that there is no overlap.

FIG. 10 is a schematic diagram of a cross-sectional view taken along A1-A2 in FIG. However, in accordance with Embodiment 1, the stacked structure of the first single crystal semiconductor element layer 193 such as an interlayer film over the first diode 154_1 to the nth diode 154_n is removed at least in the region 196. It shows how it is. As described above, the source region and the drain region of the first single crystal semiconductor element layer 193 and the second single crystal semiconductor element layer 194 are ion-doped or ion-doped so that the semiconductor element operates favorably. An impurity imparting one conductivity can be added by an implantation method.

Thereafter, as in the first embodiment, an interlayer film is formed, wiring is formed, and a desired element is completed.

The effect of the embodiment of the present invention can be improved in productivity by reducing the impurity addition step. At this time, integration can be performed by overlapping a source region or a drain region on a plane in the region 195.

(Embodiment 3)
In this embodiment, an example of a semiconductor device intended to provide higher integration and miniaturization will be described. Specifically, as an example of a semiconductor device, an example of a semiconductor device provided with a microprocessor and an arithmetic function capable of transmitting and receiving data without contact will be described.

FIG. 11 illustrates an example of a microprocessor 500 as an example of a semiconductor device. The microprocessor 500 is manufactured by the semiconductor device according to the above embodiment. The microprocessor 500 includes an arithmetic circuit 501 (also referred to as Arithmetic logic unit. ALU), an arithmetic circuit control unit 502 (ALU Controller), an instruction analysis unit 503 (Instruction Decoder), an interrupt control unit 504 (Interrupt Controller), and timing control. Unit 505 (Timing Controller), register 506 (Register), register control unit 507 (Register Controller), bus interface 508 (Bus I / F), read-only memory (ROM) 509, and memory interface 510 (ROM I / F) have.

An instruction input to the microprocessor 500 via the bus interface 508 is input to the instruction analysis unit 503 and decoded, and then to the arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505. Entered. The arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505 perform various controls based on the decoded instruction. Specifically, the arithmetic circuit control unit 502 generates a signal for controlling the operation of the arithmetic circuit 501. The interrupt control unit 504 processes an interrupt request from an external input / output device or a peripheral circuit based on its priority or mask state while the microprocessor 500 executes a program. The register control unit 507 generates an address of the register 506 and reads and writes the register 506 in accordance with the state of the microprocessor 500. The timing control unit 505 generates a signal for controlling the operation timing of the arithmetic circuit 501, the arithmetic circuit control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507. For example, the timing control unit 505 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits. Note that the microprocessor 500 illustrated in FIG. 11 is only an example in which the configuration is simplified, and actually, the microprocessor 500 may have various configurations depending on the application.

In the microprocessor 500, the arithmetic circuit 501 and the arithmetic circuit control unit 502 are formed in the single crystal semiconductor element layer 551, and the register 506 and the register control unit 507 are formed in the single crystal semiconductor element layer 552. The unit 503, the interrupt control unit 504, the timing control unit 505, and the bus interface 508 are formed in the single crystal semiconductor element layer 553, and the ROM 509 and the ROM interface 510 are formed in the single crystal semiconductor element layer 554. The single crystal semiconductor element layer 551, the single crystal semiconductor element layer 552, the single crystal semiconductor element layer 553, and the single crystal semiconductor element layer 554 that are formed using the present invention are stacked in a multilayer structure, and a wiring layer that penetrates the stack Are electrically connected.

Since single crystal semiconductor element layers manufactured in separate processes are stacked on each other substrate and integrated, optimized conditions (materials, films) are not affected by the manufacturing conditions of other single crystal semiconductor element layers. A single crystal semiconductor element layer having high characteristics in terms of thickness and element structure can be formed. Accordingly, a semiconductor device having a multilayer structure of a plurality of single crystal semiconductor elements can also have high performance.

Next, an example of a semiconductor device having an arithmetic function capable of transmitting and receiving data without contact will be described with reference to FIGS. FIG. 12 shows an example of a computer (hereinafter referred to as “RFCPU”) that operates by transmitting and receiving signals to and from an external device by wireless communication. The RFCPU 511 includes an analog circuit portion 512 and a digital circuit portion 513. The analog circuit portion 512 includes a resonance circuit 514 having a resonance capacity, a rectifier circuit 515, a constant voltage circuit 516, a reset circuit 517, an oscillation circuit 518, a demodulation circuit 519, and a modulation circuit 520. The digital circuit unit 513 includes an RF interface 521, a control register 522, a clock controller 523, an interface 524, a central processing unit 525, a random access memory 526, and a read only memory 527.

The operation of the RFCPU 511 having such a configuration is as follows. A signal received by the antenna 528 generates an induced electromotive force by the resonance circuit 514. The induced electromotive force is charged in the capacitor unit 529 through the rectifier circuit 515. Capacitance portion 529 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitor portion 529 is not necessarily formed integrally with the RFCPU 511, and may be attached to a substrate having an insulating surface constituting the RFCPU 511 as a separate component.

The reset circuit 517 generates a signal that resets and initializes the digital circuit portion 513. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 518 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 516. A demodulation circuit 519 formed by a low-pass filter binarizes fluctuations in the amplitude of an amplitude modulation (ASK) received signal, for example. The modulation circuit 520 transmits transmission data by changing the amplitude of an amplitude modulation (ASK) transmission signal. The modulation circuit 520 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 514. The clock controller 523 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the central processing unit 525. The power supply management circuit 530 monitors the power supply voltage.

A signal input from the antenna 528 to the RFCPU 511 is demodulated by the demodulation circuit 519 and then decomposed into a control command and data by the RF interface 521. The control command is stored in the control register 522. The control command includes reading of data stored in the read-only memory 527, writing of data to the random access memory 526, an arithmetic instruction to the central processing unit 525, and the like. The central processing unit 525 accesses the read-only memory 527, the random access memory 526, and the control register 522 via the interface 524. The interface 524 has a function of generating an access signal for any of the read-only memory 527, the random access memory 526, and the control register 522 from the address requested by the central processing unit 525.

As a calculation method of the central processing unit 525, a method in which an OS (operating system) is stored in the read-only memory 527 and a program is read and executed together with activation can be employed. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the method using both hardware and software, a method in which a part of processing is performed by a dedicated arithmetic circuit and the central processing unit 525 executes the remaining operations using a program can be applied.

In the RFCPU 511, the resonance circuit 514, the constant voltage circuit 516, the rectification circuit 515, the demodulation circuit 519, the modulation circuit 520, the reset circuit 517, the oscillation circuit 518, the power management circuit 530, the capacitor portion 529, and the antenna 528 are single crystal semiconductor element layers. The RF interface 521, the control register 522, the clock controller 523, the CPU interface 524, the CPU 525, the RAM 526, and the ROM 527 are formed in the single crystal semiconductor element layer 562. By using the present invention, the single crystal semiconductor element layer 561 and the single crystal semiconductor element layer 562 are stacked in a multilayer structure, and are electrically connected by a wiring layer penetrating the stack.

The above circuit can be reduced in size by stacking two or more single crystal semiconductor element layers having the structure of the present invention by using SOI technology. The operational effect shown in this embodiment is to reduce the number of steps of impurity addition, thereby reducing the number of steps and manufacturing the semiconductor device with high productivity.

(Embodiment 4)
According to the present invention, a semiconductor device that functions as a chip having a processor circuit (hereinafter also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The application of the semiconductor device of the present invention is wide-ranging, and can be applied to any product that can be used for production and management by clarifying information such as the history of an object without contact. For example, banknotes, coins, securities, certificate documents, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles, foods, clothing, health supplies, daily necessities, chemicals, etc. It can be provided and used in an electronic device or the like. These examples will be described with reference to FIG.

Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a chip 1190 having a processor circuit (see FIG. 13A). The certificate refers to a driver's license, a resident's card, or the like, and can be provided with a chip 1191 having a processor circuit (see FIG. 13B). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 1197 including a processor circuit (see FIG. 13C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a chip 1193 including a processor circuit (see FIG. 13D). Books refer to books, books, and the like, and can be provided with a chip 1194 including a processor circuit (see FIG. 13E). A recording medium refers to DVD software, a video tape, or the like, and can be provided with a chip 1195 including a processor circuit (see FIG. 13F). A vehicle refers to a vehicle such as a bicycle, a ship, or the like, and can be provided with a chip 1196 including a processor circuit (see FIG. 13G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

Such a semiconductor device is provided by being attached to the surface of an article or embedded in an article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in an organic resin.

In this way, by providing semiconductor devices in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. it can. Further, forgery or theft can be prevented by providing a semiconductor device in the vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by embedding or attaching a semiconductor device equipped with a sensor to a living creature such as livestock, it is possible to easily manage the health state such as body temperature as well as the year of birth, gender or type.

Note that this embodiment can be implemented in combination with any of Embodiments 1 to 3 as appropriate.

8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a circuit of a semiconductor device. 10A to 10D are plan views illustrating a method for manufacturing a semiconductor device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a circuit of a semiconductor device. 10A to 10D are plan views illustrating a method for manufacturing a semiconductor device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention. FIG. 11 is a block diagram illustrating a structure of a microprocessor obtained by the semiconductor device of the invention. FIG. 6 is a block diagram illustrating a configuration of an RFCPU obtained by the semiconductor device of the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention.

Claims (7)

A first island-like semiconductor layer ;
Silicide formed in a part of the first island-shaped semiconductor layer;
A first insulating film provided to cover a portion of the silicide;
A conductive layer electrically connected to the silicide through the opening of the first insulating film;
A second insulating film on the first insulating film and the conductive layer;
A second island-like semiconductor layer on the second insulating film,
A portion of the second island-shaped semiconductor layer overlaps with the opening;
The first island-shaped semiconductor layer has a source region and a drain region,
The source region or the drain region has a region to which an impurity imparting one conductivity is added ,
The semiconductor device is characterized in that the region to which the impurity imparting one conductivity is added does not overlap with the first insulating film. A first island-like semiconductor layer;
A gate insulating film over the first island-shaped semiconductor layer,
A gate electrode on the gate insulating film,
A sidewall provided on a sidewall of the gate electrode;
Silicide formed in a part of the first island-shaped semiconductor layer;
A first insulating film provided to cover a portion of the silicide;
A conductive layer electrically connected to the silicide through the opening of the first insulating film;
A second insulating film on the first insulating film and the conductive layer;
A second island-like semiconductor layer on the second insulating film,
A portion of the second island-shaped semiconductor layer overlaps with the opening;
The first island-shaped semiconductor layer has a source region and a drain region,
The source region or the drain region has a region to which an impurity imparting one conductivity is added ,
The region to which the impurity imparting one conductivity is added does not overlap with the first insulating film,
An LDD region is provided in the first island-shaped semiconductor layer overlapping the sidewall. In claim 1 or 2,
The semiconductor device, wherein the first island-shaped semiconductor layer is made of a single crystal semiconductor. Over an insulating surface, it forms the shape of the first island-shaped semiconductor layer,
Forming silicide on a part of the first island-shaped semiconductor layer;
Forming an insulating film on the first island-shaped semiconductor layer and the silicide;
Forming a second island-shaped semiconductor layer on the insulating film;
Removing the insulating film on a partial region of the silicide and a partial region of the first island-like semiconductor layer ;
A method for manufacturing a semiconductor device, wherein an impurity imparting one conductivity is added to part of the first island-shaped semiconductor layer and part of the second island-shaped semiconductor layer. Forming a first island-like semiconductor layer on the insulating surface;
Forming a gate insulating film on the first island-shaped semiconductor layer;
Form forms a gate electrode on the gate insulating film,
Forming a sidewall on the side wall of the gate electrode;
Forming silicide on a part of the first island-shaped semiconductor layer;
Forming a first insulating film on the gate electrode;
Forming an opening in the first insulating film;
Forming a conductive layer in the first insulating film and the opening;
Forming a second insulating film on the first insulating film and the conductive layer;
Forming a second island-shaped semiconductor film on the second insulating film;
Removing the first insulating film and the second insulating film on a partial region of the silicide and a partial region of the first island-like semiconductor layer ;
A method for manufacturing a semiconductor device, wherein an impurity imparting one conductivity is added to part of the first island-shaped semiconductor layer and part of the second island-shaped semiconductor layer. In claim 4 or 5,
The method for manufacturing a semiconductor device, wherein the first island-shaped semiconductor layer is formed of a single crystal semiconductor. In any one of Claims 4 thru | or 6,
The method for manufacturing a semiconductor device, wherein the first island-shaped semiconductor layer is separated from a silicon wafer by a hydrogen ion implantation separation method and attached to a glass substrate.

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