JP5339576B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Manufacturing method of semiconductor integrated circuit device Download PDF

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JP5339576B2
JP5339576B2 JP2008052895A JP2008052895A JP5339576B2 JP 5339576 B2 JP5339576 B2 JP 5339576B2 JP 2008052895 A JP2008052895 A JP 2008052895A JP 2008052895 A JP2008052895 A JP 2008052895A JP 5339576 B2 JP5339576 B2 JP 5339576B2
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opening
resist
resist pattern
insulating film
interlayer insulating
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JP2008270747A (en
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智弘 西脇
一重 兼子
哲也 山田
洋治 野村
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Semiconductor Components Industries LLC
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Priority to JP2008052895A priority Critical patent/JP5339576B2/en
Priority to US12/076,822 priority patent/US7943054B2/en
Priority to CN2008100876119A priority patent/CN101276783B/en
Priority to KR1020080028219A priority patent/KR20080087757A/en
Priority to TW097111209A priority patent/TWI375332B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking

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  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)

Description

本発明は、受光部を含む半導体基板上に集積回路を形成する半導体集積回路装置に関し、特に、基板上に積層した層間絶縁膜をエッチングして開口部を形成する半導体集積回路装置の製造方法に関する。   The present invention relates to a semiconductor integrated circuit device that forms an integrated circuit on a semiconductor substrate including a light receiving portion, and more particularly to a method for manufacturing a semiconductor integrated circuit device that forms an opening by etching an interlayer insulating film stacked on the substrate. .

近年、情報記録媒体として、ＣＤ（Ｃｏｍｐａｃｔ Ｄｉｓｋ）やＤＶＤ（Ｄｉｇｉｔａｌ Ｖｅｒｓａｔｉｌｅ Ｄｉｓｋ）といった光ディスクが大きな位置を占めるようになってきた。これら光ディスクの再生装置は、光ディスクのトラックに沿って照射したレーザ光の反射光強度の変化を光検出器での検出に基づいて、記録データを再生する。   In recent years, optical disks such as CDs (Compact Disks) and DVDs (Digital Versatile Disks) have come to occupy a large position as information recording media. These optical disk playback devices play back recorded data based on detection by a photodetector of a change in reflected light intensity of laser light irradiated along the track of the optical disk.

図９は従来の光検出器１０の概略の平面図である。   FIG. 9 is a schematic plan view of a conventional photodetector 10.

図１０は、図９に示す直線Ａ−Ａ’を通り半導体基板に垂直な断面での受光部１１及び配線構造１２を示す概略の断面図である。   FIG. 10 is a schematic cross-sectional view showing the light receiving unit 11 and the wiring structure 12 in a cross section passing through the straight line A-A ′ shown in FIG. 9 and perpendicular to the semiconductor substrate.

光検出器１０は、反射光を検知するために、半導体基板１４Ａの表面に、２×２の４つの区画に分割されたＰＩＮフォトダイオード（ＰＤ）拡散層３４を含む受光部１１を有する。受光部１１にレーザ光の反射光が入射することで微弱な光電変換信号が発生し、この信号は周辺領域に形成された増幅器にて増幅され、後段の信号処理回路へ出力される。   The photodetector 10 includes a light receiving unit 11 including a PIN photodiode (PD) diffusion layer 34 divided into four 2 × 2 sections on the surface of the semiconductor substrate 14A in order to detect reflected light. A weak photoelectric conversion signal is generated when the reflected light of the laser beam is incident on the light receiving unit 11, and this signal is amplified by an amplifier formed in the peripheral region and is output to a signal processing circuit at a subsequent stage.

また、各ＰＤ拡散層３４は分離拡散層３３により分離される。   Each PD diffusion layer 34 is separated by the separation diffusion layer 33.

ここで、光検出器１０は、半導体基板１４Ａ上に、ゲート酸化膜１４Ｂを成膜し、第１層間絶縁膜１６、第１金属層１７、第２層間絶縁膜１８、第２金属層１９、第３層間絶縁膜２０が順次積層される。第１金属層１７及び第２金属層１９はそれぞれアルミニウム（Ａｌ）等により形成され、フォトリソグラフィ技術を用いてパターニングされる。第１金属層１７には、パターニングにより、配線構造１２及び配線構造１２に接続される信号線１３Ａと電圧印加線１３Ｂとが形成される。   Here, the photodetector 10 forms a gate oxide film 14B on a semiconductor substrate 14A, a first interlayer insulating film 16, a first metal layer 17, a second interlayer insulating film 18, a second metal layer 19, The third interlayer insulating film 20 is sequentially stacked. The first metal layer 17 and the second metal layer 19 are each formed of aluminum (Al) or the like, and are patterned using a photolithography technique. In the first metal layer 17, the wiring structure 12 and the signal line 13A and the voltage application line 13B connected to the wiring structure 12 are formed by patterning.

これにより、分離拡散層３３は配線構造１２を介して電圧印加線１３Ｂにより電位固定される。一方、各ＰＤ拡散層３４で発生した光電変換信号も配線構造１２を介して信号線１３Ａにより取り出される。   Thereby, the potential of the isolation diffusion layer 33 is fixed by the voltage application line 13B via the wiring structure 12. On the other hand, the photoelectric conversion signal generated in each PD diffusion layer 34 is also taken out by the signal line 13 </ b> A through the wiring structure 12.

上記において、光電変換信号の周波数特性の確保やノイズの重畳を抑制するために、各ＰＤ拡散層３４と信号線１３Ａ、並びに、分離拡散層３３と電圧印加線１３Ｂとは、いずれも低抵抗となるように電気的に接続される必要がある。このため、配線構造１２は、それぞれの拡散層とできるだけ多くのコンタクトを取る必要がある。したがって、図９に示したように、配線構造１２は、受光部１１を取り囲み、平面形状において角部を有するように配置される。   In the above, in order to ensure the frequency characteristics of the photoelectric conversion signal and to suppress noise superposition, each PD diffusion layer 34 and the signal line 13A, and the separation diffusion layer 33 and the voltage application line 13B are both low resistance. It is necessary to be electrically connected. For this reason, the wiring structure 12 needs to make as many contacts as possible with each diffusion layer. Therefore, as illustrated in FIG. 9, the wiring structure 12 surrounds the light receiving unit 11 and is disposed so as to have a corner in a planar shape.

金属層と層間絶縁膜とを積層した後、受光部１１への光の入射効率を高めるために、受光部１１上に積層された層間絶縁膜等をエッチングし、開口部１５が形成される。開口部１５は、配線構造１２が成す形状を一回り小さくした相似形に開口され、受光部上のみ開口される。
特開２００１-６０７１３号公報 After the metal layer and the interlayer insulating film are stacked, the interlayer insulating film and the like stacked on the light receiving unit 11 are etched to increase the light incident efficiency on the light receiving unit 11 to form the opening 15. The opening 15 is opened in a similar shape that is slightly smaller than the shape formed by the wiring structure 12 and is opened only on the light receiving portion.
Japanese Patent Laid-Open No. 2001-60713

入射効率を高めるには、開口部１５はできるだけ深くエッチングする必要がある。この開口部１５を形成するために層間絶縁膜等をエッチングする際、第３層間絶縁膜２０上に形成されるレジストパターン２５も、その表面よりエッチングされる。このため、レジストの膜厚が十分でない場合、エッチングにより第３層間絶縁膜２０の上面が露出され、開口部でないところまで削られてしまう。   In order to increase the incidence efficiency, it is necessary to etch the opening 15 as deeply as possible. When the interlayer insulating film or the like is etched to form the opening 15, the resist pattern 25 formed on the third interlayer insulating film 20 is also etched from the surface. For this reason, when the film thickness of the resist is not sufficient, the upper surface of the third interlayer insulating film 20 is exposed by etching, and the resist is scraped to a place that is not an opening.

これに対し、レジストの膜厚を厚くすることが考えられるが、それでも、配線構造１２上の一部の層間絶縁膜等がエッチングされてしまうという不具合が生じる。   On the other hand, it is conceivable to increase the thickness of the resist, but there is still a problem that a part of the interlayer insulating film on the wiring structure 12 is etched.

本発明の半導体集積回路装置の製造方法は、受光部を含む半導体基板上に層間絶縁膜を形成する工程と、前記層間絶縁膜上にレジストを塗布する工程と、前記レジストをレジストパターンに形成する工程と、前記レジストパターンを硬化する工程と、前記レジストパターンをマスクとして、前記層間絶縁膜をエッチングする工程と、を具備し、レジストパターンは、平面形状で角を有さない形状にて、受光部上が開口することを特徴とするものである。   The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming an interlayer insulating film on a semiconductor substrate including a light receiving portion, a step of applying a resist on the interlayer insulating film, and forming the resist in a resist pattern. And a step of curing the resist pattern, and a step of etching the interlayer insulating film using the resist pattern as a mask. The resist pattern has a planar shape with no corners and receives light. The upper part is open.

本発明によれば、受光部を有する半導体集積回路装置の製造方法において、開口部を形成する際に、開口部以外の部分がエッチングされることを抑制することができる。   According to the present invention, in the method of manufacturing a semiconductor integrated circuit device having a light receiving portion, it is possible to suppress etching of portions other than the opening when the opening is formed.

以下、本発明の実施形態について、図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は本実施の形態における光検出器５０の概略の平面図である。   FIG. 1 is a schematic plan view of a photodetector 50 in the present embodiment.

図２は、図１に示す直線Ｂ−Ｂ’を通り半導体基板５４Ａに垂直な断面での受光部５１及び配線構造５２を示す概略の断面図である。   FIG. 2 is a schematic cross-sectional view showing the light receiving portion 51 and the wiring structure 52 in a cross section passing through the straight line B-B ′ shown in FIG. 1 and perpendicular to the semiconductor substrate 54A.

反射光を検知する光検出器５０は、半導体基板５４Ａの表面に受光部５１を有する。受光部５１は、２×２の４つの区画に分割されたＰＩＮフォトダイオード（ＰＤ）拡散層７４を含む。ＰＤ拡散層７４は、例えば、高濃度のｎ型不純物を拡散されたカソード領域として形成される。また、各ＰＤ拡散層７４は分離拡散層７３により分離される。分離拡散層７３は、半導体基板５４Ａ表面に、例えば、高濃度のｐ型不純物を拡散したアノード領域として形成される。ＰＤ拡散層７４をカソード領域として形成することで、レーザ光の反射光が受光部５１に入射することで生成する電荷のうち、電子のみを集めることができる。   The photodetector 50 that detects the reflected light has a light receiving portion 51 on the surface of the semiconductor substrate 54A. The light receiving unit 51 includes a PIN photodiode (PD) diffusion layer 74 divided into four 2 × 2 sections. The PD diffusion layer 74 is formed, for example, as a cathode region in which a high concentration n-type impurity is diffused. Each PD diffusion layer 74 is separated by the separation diffusion layer 73. The isolation diffusion layer 73 is formed on the surface of the semiconductor substrate 54A, for example, as an anode region in which a high concentration p-type impurity is diffused. By forming the PD diffusion layer 74 as a cathode region, it is possible to collect only electrons among the charges generated when the reflected light of the laser light enters the light receiving unit 51.

光検出器５０は、半導体基板５４Ａ上に、ゲート酸化膜５４Ｂを成膜し、第１層間絶縁膜５６、第１金属層５７、第２層間絶縁膜５８、第２金属層５９、第３層間絶縁膜６０が順次積層される。第１金属層５７及び第２金属層５９は、アルミニウム（Ａｌ）等により形成され、フォトリソグラフィ技術を用いてパターニングされる。第１金属層５７には、パターニングにより、配線構造５２と、配線構造５２に接続される信号線５３Ａと電圧印加線５３Ｂとが形成される。   In the photodetector 50, a gate oxide film 54B is formed on a semiconductor substrate 54A, and a first interlayer insulating film 56, a first metal layer 57, a second interlayer insulating film 58, a second metal layer 59, a third interlayer are formed. Insulating films 60 are sequentially stacked. The first metal layer 57 and the second metal layer 59 are formed of aluminum (Al) or the like, and are patterned using a photolithography technique. In the first metal layer 57, a wiring structure 52, a signal line 53A connected to the wiring structure 52, and a voltage application line 53B are formed by patterning.

ここで、図１に示すように、本実施形態では、配線構造５２は半導体基板５４Ａ上に形成され、平面形状で受光部５１を四角形の領域で囲むように配置される。したがって、配線構造５２が配置されることで形成される四隅には、角部が形成される。   Here, as shown in FIG. 1, in the present embodiment, the wiring structure 52 is formed on the semiconductor substrate 54 </ b> A, and is arranged so as to surround the light receiving portion 51 with a rectangular region in a planar shape. Accordingly, corners are formed at the four corners formed by the wiring structure 52 being arranged.

さらに、配線構造５２は、各ＰＤ拡散層７４及び分離拡散層７３と複数のコンタクトにより電気的に接続される。これにより、分離拡散層７３は配線構造５２を介して電圧印加線５３Ｂにより電位固定される。例えば、分離拡散層７３には接地電位が印加される。また、各ＰＤ拡散層７４で発生した光電変換信号は配線構造５２を介して信号線５３Ａにより取り出される。   Furthermore, the wiring structure 52 is electrically connected to each PD diffusion layer 74 and the isolation diffusion layer 73 by a plurality of contacts. Thereby, the potential of the isolation diffusion layer 73 is fixed by the voltage application line 53B through the wiring structure 52. For example, the ground potential is applied to the separation diffusion layer 73. Further, the photoelectric conversion signal generated in each PD diffusion layer 74 is taken out by the signal line 53A through the wiring structure 52.

各ＰＤ拡散層７４及び分離拡散層７３と配線構造５２とが接続された後、第２層間絶縁膜５８を形成する。なお、本実施形態では、各層間絶縁膜は、例えば、ＴＥＯＳ（Tetra-ethoxy-silane）やＢＰＳＧ（Borophosphosilicate Glass）、ＳＯＧ（Spin on Glass）によって形成される。   After each PD diffusion layer 74 and isolation diffusion layer 73 and the wiring structure 52 are connected, a second interlayer insulating film 58 is formed. In the present embodiment, each interlayer insulating film is formed of, for example, TEOS (Tetra-ethoxy-silane), BPSG (Borophosphosilicate Glass), or SOG (Spin on Glass).

各金属層と層間絶縁膜とが積層された後、エッチングにより、受光部５１上に開口部５５を形成する。開口部５５は、受光部５１に対する反射光の入射効率を高めるために形成する。   After each metal layer and the interlayer insulating film are stacked, an opening 55 is formed on the light receiving portion 51 by etching. The opening 55 is formed to increase the incident efficiency of reflected light with respect to the light receiving unit 51.

開口部５５を形成するために、まず、第３層間絶縁膜６０上にレジストを塗布する。レジストは、開口部形成時にエッチングされても、第３層間絶縁膜６０が露出されない程度の厚みを有するように積層される。レジストを露光、現像して、受光部５１上が開口されたレジストパターン６５が形成される。その後、レジストにポストベークが施され、硬化される。硬化されたレジストをエッチングマスクとして用い、受光部５１上に開口部５５が形成される。   In order to form the opening 55, first, a resist is applied on the third interlayer insulating film 60. The resist is laminated so as to have such a thickness that the third interlayer insulating film 60 is not exposed even if the resist is etched when the opening is formed. The resist is exposed and developed, and a resist pattern 65 having an opening on the light receiving portion 51 is formed. Thereafter, the resist is post-baked and cured. An opening 55 is formed on the light receiving portion 51 using the cured resist as an etching mask.

図３は、従来の開口部の形状、すなわちレジストパターン２５の形状を表した斜視図である。図３に示されるように、従来では、開口部１５は角部を有する形状、例えば四角形となるように形成されていた。これについて、以下に説明を加える。なお、図中の番号は、従来の光検出器１０を表した図９及び図１０と共通となるように付されている。   FIG. 3 is a perspective view showing the shape of the conventional opening, that is, the shape of the resist pattern 25. As shown in FIG. 3, conventionally, the opening 15 is formed to have a shape having a corner, for example, a quadrangle. This will be described below. Note that the numbers in the figure are assigned in common with FIGS. 9 and 10 showing the conventional photodetector 10.

レジストパターン２５は、第３絶縁膜２０上にレジストを塗布し、露光し、現像して形成される。図４は、図３のレジストにポストベークを施した後の、レジストパターン２５の平面図である。図中の矢印は、応力を表す。   The resist pattern 25 is formed by applying a resist on the third insulating film 20, exposing, and developing. FIG. 4 is a plan view of the resist pattern 25 after post-baking the resist of FIG. The arrows in the figure represent stress.

図４に示すように、ポストベーク後のレジストパターン２５にはクラックが生じる。このようなクラックは、厚い膜厚のレジストを硬化したことで、レジストパターン２５の開口部１５の角部に集中する応力が過多となり、レジストに応力破壊が起こることで生じる。図１１は、この応力破壊を説明するための、レジスト膜４０の境界部分の模式的な断面図である。同図には基板４２の上に積層したレジスト膜４０に形成されたパターンの境界部分が示されている。図１１に示すように、レジストによっては、レジスト膜４０のエッジ４４が尖頂形状となるものがある。尖頂形状のエッジ４４では先端の厚さ（レジスト膜４０の上面４６と側面４８とに挟まれるレジスト膜４０の厚さ）が、例えば、丸まった形状のエッジなどと比べるとエッジの先端から遠い位置まで薄い状態となる。このため、開口部１５の角部に対応するエッジ４４から、応力破壊が生じやすい。例えば、現像後にレジストをポストベークする際に生じる応力によって、開口部１５に位置するエッジ４４に亀裂（クラック）が生じる。   As shown in FIG. 4, a crack occurs in the resist pattern 25 after post-baking. Such a crack is generated when a resist having a large film thickness is cured, so that stress concentrated on the corner portion of the opening 15 of the resist pattern 25 becomes excessive, and stress breakdown occurs in the resist. FIG. 11 is a schematic cross-sectional view of the boundary portion of the resist film 40 for explaining this stress fracture. The figure shows a boundary portion of a pattern formed on the resist film 40 laminated on the substrate 42. As shown in FIG. 11, depending on the resist, the edge 44 of the resist film 40 has a peak shape. In the apex-shaped edge 44, the thickness of the tip (the thickness of the resist film 40 sandwiched between the upper surface 46 and the side surface 48 of the resist film 40) is, for example, a position farther from the tip of the edge than a rounded edge or the like. Until it becomes thin. For this reason, stress fracture tends to occur from the edge 44 corresponding to the corner of the opening 15. For example, the stress generated when the resist is post-baked after development causes a crack at the edge 44 located in the opening 15.

クラックが生じたレジストパターン２５をエッチングマスクとして用いてエッチングを行うと、クラック下の第３層間絶縁膜２０もエッチングされる。これにより、開口部１５の形状に、クラックの形状が反映されてしまう。   When etching is performed using the resist pattern 25 in which the crack has occurred as an etching mask, the third interlayer insulating film 20 under the crack is also etched. As a result, the shape of the crack is reflected in the shape of the opening 15.

図５は、従来の形状の開口部１５を隣接して形成した場合の、レジストパターン２５のクラックの発生の状況を示したものである。図５に示すように、クラックは、開口部１５が隣接して配置される側（隣接開口部側）の開口部１５の角部よりも、開口部１５が隣接して配置されない側（非隣接開口部側）の開口部１５の角部に発生しやすい。これは、隣接開口部側では（ｄ，ｅ）、（ｃ、ｆ）で応力が分散されるのに対し、非隣接開口部側ではａ、ｂ、ｇ、ｈの各点に応力が集中するためである。   FIG. 5 shows the state of occurrence of cracks in the resist pattern 25 in the case where the openings 15 having a conventional shape are formed adjacent to each other. As shown in FIG. 5, the crack is not adjacent to the corner of the opening 15 on the side where the opening 15 is adjacent (adjacent opening side) (the non-adjacent side). It tends to occur at the corner of the opening 15 on the opening side. This is because stress is distributed at (d, e) and (c, f) on the adjacent opening side, whereas stress is concentrated on each point of a, b, g, and h on the non-adjacent opening side. Because.

図６は、本実施形態におけるレジストパターン２５の平面図である。図中の矢印は応力を表す。なお、図中の番号は、本実施形態の光検出器５０を表した図１及び図２と共通となるように付されている。   FIG. 6 is a plan view of the resist pattern 25 in the present embodiment. The arrow in the figure represents stress. The numbers in the figure are assigned in common with those in FIGS. 1 and 2 showing the photodetector 50 of the present embodiment.

図１に示すように、本実施形態では、開口部５５は平面形状で角を有さない形状となるように開口される。このため、開口部５５を形成するためのレジストパターン６５も開口部５５と同形状に形成される。したがって、図６に示すように、レジストパターン６５も平面形状で角を有さない形状に形成されるため、レジストの硬化による応力が分散される。これにより、レジストパターン６５に発生するクラックを抑制できる。   As shown in FIG. 1, in this embodiment, the opening 55 is opened so as to have a planar shape and no corners. Therefore, the resist pattern 65 for forming the opening 55 is also formed in the same shape as the opening 55. Therefore, as shown in FIG. 6, since the resist pattern 65 is also formed in a planar shape having no corners, stress due to the curing of the resist is dispersed. Thereby, the crack which generate | occur | produces in the resist pattern 65 can be suppressed.

なお、本発明は、上記実施形態に記載された、開口部５５の平面形状が配線構造５２の角部に対応する部分が円弧となるように、レジストパターン６５が形成されるものに限定されない。配線構造５２の角部に対応する部分が面取りされた開口部５５の平面形状となるようにレジストパターンを形成することによっても応力を分散させることができ、レジストパターンの応力破壊を抑制できる。したがって、例えば、図７に示されるように、開口部５５の平面形状が８角形となるようなレジストパターンであってもよい。また、８角形以上の多角形であってもよい。   Note that the present invention is not limited to the one in which the resist pattern 65 is formed such that the planar shape of the opening 55 described in the above embodiment corresponds to a corner of the wiring structure 52 is an arc. The stress can also be dispersed by forming a resist pattern so that the portion corresponding to the corner of the wiring structure 52 has a chamfered opening 55, and the stress breakdown of the resist pattern can be suppressed. Therefore, for example, as shown in FIG. 7, a resist pattern in which the planar shape of the opening 55 is an octagon may be used. Further, it may be an octagon or more.

さらに、図８に示されるように、隣接して開口部５５が形成される場合、開口部５５の平面形状は、隣接開口部側は下層の配線構造５２と相似形状に形成され、非隣接開口部側は円弧となるように、レジストパターン６５を形成することもできる。これは、隣接開口部側の角部は隣接する開口部の角部によって応力が分散されるためクラックが生じにくく、したがって、非隣接開口部側にのみ応力集中が緩和される形状が採用される。   Furthermore, as shown in FIG. 8, when the opening 55 is formed adjacently, the planar shape of the opening 55 is similar to the lower wiring structure 52 on the adjacent opening side, and the non-adjacent opening is formed. The resist pattern 65 can also be formed so that the part side becomes an arc. This is because the corner portion on the adjacent opening side is less susceptible to cracking because the stress is dispersed by the corner portion of the adjacent opening portion, and therefore, the shape in which stress concentration is eased only on the non-adjacent opening portion side is adopted. .

また、以上のように、本発明は、開口部を形成する際のマスクの変更以外に、新たな装置や工程を導入する必要が無い。   Further, as described above, the present invention does not require introduction of a new apparatus or process other than changing the mask when forming the opening.

本発明の光検出器の概略の平面図である。It is a schematic plan view of the photodetector of the present invention. 本発明の光検出器の概略の断面図である。It is sectional drawing of the outline of the photodetector of this invention. 従来のポストベーク前のレジストパターンの斜視図である。It is a perspective view of the resist pattern before the conventional post-baking. 従来のポストベーク後のレジストパターンの平面図である。It is a top view of the resist pattern after the conventional post-baking. 従来において開口部が隣接して形成される場合の平面図である。It is a top view in case an opening part is formed adjacently conventionally. 本発明のポストベーク後のレジストパターンの平面図である。It is a top view of the resist pattern after the post-baking of this invention. 本発明の光検出器の概略の平面図である。It is a schematic plan view of the photodetector of the present invention. 本発明において開口部が隣接して形成される場合の平面図である。It is a top view in case an opening part is formed adjacently in this invention. 従来の光検出器の概略の平面図である。It is a schematic plan view of a conventional photodetector. 従来の光検出器の概略の断面図である。It is sectional drawing of the outline of the conventional photodetector. レジスト膜の境界部分の模式的な断面図である。It is typical sectional drawing of the boundary part of a resist film.

符号の説明Explanation of symbols

１０，５０ 光検出器、１１，５１ 受光部、１２，５２ 配線構造、１３Ａ，５３Ａ 信号線、１３Ｂ，５３Ｂ 電圧印加線、１４Ａ，５４Ａ 半導体基板、１４Ｂ，５４Ｂ ゲート酸化膜、１５，５５ 開口部、１６，５６ 第１層間絶縁膜、１７，５７ 第１金属層、１８，５８ 第２層間絶縁膜、１９，５９ 第２金属層、２０，６０ 第３層間絶縁膜、２１ ウェハ、２５，６５ レジストパターン、３３，７３ 分離拡散層、３４，７４ ＰＤ拡散層、４０ レジスト膜、４４ エッジ。   DESCRIPTION OF SYMBOLS 10,50 Photodetector, 11,51 Light-receiving part, 12,52 Wiring structure, 13A, 53A Signal line, 13B, 53B Voltage application line, 14A, 54A Semiconductor substrate, 14B, 54B Gate oxide film, 15, 55 Opening 16, 56 First interlayer insulating film, 17, 57 First metal layer, 18, 58 Second interlayer insulating film, 19, 59 Second metal layer, 20, 60 Third interlayer insulating film, 21 Wafer, 25, 65 Resist pattern, 33, 73 separation diffusion layer, 34, 74 PD diffusion layer, 40 resist film, 44 edge.

Claims (3)

受光部を含む半導体基板において、
前記半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜上にレジストを塗布する工程と、
前記レジストをレジストパターンに形成する工程と、
前記レジストパターンを硬化する工程と、
前記レジストパターンをマスクとして、前記層間絶縁膜をエッチングし前記受光部上に開口部を形成する工程と、
を具備する半導体集積回路装置の製造方法において、
前記レジストパターンは、前記開口部を形成するための開口を複数隣接して形成され、
前記各開口の平面形状は、他の前記開口が隣接して配置されない部分のみにて角を有さない形状であること、を特徴とする半導体集積回路装置の製造方法。 In the semiconductor substrate including the light receiving part,
Forming an interlayer insulating film on the semiconductor substrate;
Applying a resist on the interlayer insulating film;
Forming the resist into a resist pattern;
Curing the resist pattern;
Etching the interlayer insulating film using the resist pattern as a mask to form an opening on the light receiving portion;
In a method for manufacturing a semiconductor integrated circuit device comprising:
The resist pattern is formed adjacent to a plurality of openings for forming the opening,
The planar shape of each opening, a method of manufacturing a semiconductor integrated circuit device according to claim, that other of said opening has a shape having no corners at only the portion that is not disposed adjacent. 受光部を含む半導体基板において、
前記半導体基板上に、平面形状で角部を成すように前記受光部を取り囲む配線構造を形成する工程と、
前記半導体基板及び前記配線構造上に層間絶縁膜を形成する工程と、
前記層間絶縁膜上にレジストを塗布する工程と、
前記レジストをレジストパターンに形成する工程と、
前記レジストパターンを硬化する工程と、
前記レジストパターンをマスクとして、前記層間絶縁膜をエッチングし前記受光部上に開口部を形成する工程と、
を具備する半導体集積回路装置の製造方法において、
前記レジストパターンは、前記開口部を形成するための開口を複数隣接して形成され、
前記各開口の平面形状は、他の前記開口に隣接しない部分のみにて前記角部に対応する部分が面取りされた形状であること、を特徴とする半導体集積回路装置の製造方法。 In the semiconductor substrate including the light receiving part,
Forming a wiring structure that surrounds the light receiving portion so as to form a corner portion in a planar shape on the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate and the wiring structure;
Applying a resist on the interlayer insulating film;
Forming the resist into a resist pattern;
Curing the resist pattern;
Etching the interlayer insulating film using the resist pattern as a mask to form an opening on the light receiving portion;
In a method for manufacturing a semiconductor integrated circuit device comprising:
The resist pattern is formed adjacent to a plurality of openings for forming the opening,
The planar shape of each opening, a method of manufacturing a semiconductor integrated circuit device according to claim, that portion corresponding to the corner portion only at the portion which is not adjacent to the other of said opening has a shape which is chamfered. 請求項２に記載の半導体集積回路装置の製造方法において、前記角部に対応する部分の前記面取りされた形状を円弧とすることを特徴とする半導体集積回路装置の製造方法。
3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the chamfered shape of a portion corresponding to the corner portion is an arc.
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