JP5338236B2 - NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING SAME, NONVOLATILE MEMORY DEVICE USING THE NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING SAME - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a nonvolatile memory element, wherein the shape shift of upper and lower electrodes is made small; a nonvolatile memory device provided with the nonvolatile memory element; and methods for manufacturing them. <P>SOLUTION: The method for manufacturing a nonvolatile memory element includes: a step of stacking a lower electrode layer 3, a resistance change layer 2, an upper electrode layer 1, and a mask layer in sequence; a step of forming the mask layer into a specified shape; and an etching step of forming the upper electrode layer 1, the resistance change layer 2 and the lower electrode layer 3 into the specified shape by the same mask while the mask layer with the specified shape is used as a mask. In the method, the etching rate of the lower electrode layer is larger than that of the upper electrode layer 1 when etching the lower electrode layer 3. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a nonvolatile memory element that stores data using a material whose resistance value reversibly changes when an electric pulse is applied, a nonvolatile memory device, and a method for manufacturing the same.

  In recent years, with the advancement of digital technology in electronic devices, there has been an increasing demand for even larger capacity and non-volatile storage elements in order to store data such as music, images and information. As one measure for meeting these demands, attention has been focused on a memory element using a material whose resistance value is changed by a given electric pulse and keeps the state.

  FIG. 5 is a cross-sectional view of an essential part showing the configuration of a conventional example of such a nonvolatile memory element (see Patent Document 1). As shown in FIG. 5, this nonvolatile memory element is a memory element (nonvolatile memory element) including one resistor 232 and one switching structure (transistor). A drain 221 b is formed, a gate insulating layer 222 and a gate electrode 223 are formed on the semiconductor substrate 220 in contact with the source 221 a and the drain 221 b, a contact plug 225 is formed in the interlayer insulating film 224, and the contact plug 225 is a lower electrode 231. A resistor 232 and an upper electrode 233 are sequentially formed on the lower electrode 231.

Examples of substances constituting the resistor 232 include nickel oxide (NiO), titanium oxide (TiO ₂ ), hafnium oxide (HfO), niobium oxide (NbO ₂ ), zinc oxide (ZnO), and zirconium oxide. (ZrO ₂ ), tungsten oxide (WO ₃ ), cobalt oxide (CoO), GST (Ge ₂ Sb ₂ Te ₅ ), PCMO (Pr _x Ca _1-x MnO ₃ ) and the like are used. Such a transition metal oxide exhibits a specific resistance value when a specific voltage is applied or by applying a specific voltage by a specific application method, and the resistance value is newly applied to a voltage or current. It is known to maintain its resistance value until is applied.
JP 2006-135335 A

Although the electrode material used as the lower electrode or the upper electrode is not specifically described in the nonvolatile memory element of the above-described conventional example, there is a certain limitation as an electrode that reversibly changes the resistor. Limited to materials. For example, platinum (Pt) is preferable as the electrode to be reversibly changed. When Pt or the like is used for the lower electrode and the upper electrode and a nonvolatile memory element as in the above-mentioned conventional example is manufactured, Pt is generally a difficult-to-etch material, so the upper electrode and the lower electrode have different shapes after etching. Occurs. That is, a conventional resist as a mask, the use of Pt to the upper and lower electrodes, since Pt is hardly etched material, as shown in FIG. 7, the upper electrode 301 and lower electrode 303 longer etching time, etching In the meantime, the mask 304 itself is also significantly etched to reduce the dimension in the width direction, and the upper electrode 301 and the lower electrode 303 are tapered. Therefore, the size difference between the upper electrode region and the lower electrode region in contact with the resistance change layer 302 is increased, the shape shift of the nonvolatile memory element is increased, and the variation in characteristics tends to increase.

For the nonvolatile memory element, upper and lower electrodes for reversibly changing the resistor are indispensable. When the electrodes are, for example, Pt which is representative of a difficult-to-etch material, the nonvolatile memory is required unless the shape shift is reduced. There was a problem that the characteristic variation of the element would occur.

  The present invention solves the above-described conventional problems, and a nonvolatile memory element that reduces a shape difference between a lower electrode and an upper electrode even when a difficult-to-etch material is used as an electrode, and a nonvolatile memory including the nonvolatile memory element It is an object of the present invention to provide a sexual memory device and a manufacturing method thereof.

  In order to solve the above-described problems, a method of manufacturing a nonvolatile memory element according to the present invention includes a lower electrode, an upper electrode formed above the lower electrode, and an intervening between the lower electrode and the upper electrode. And a resistance change layer whose resistance value reversibly changes based on an electrical signal applied between the lower electrode and the upper electrode. A step of depositing the upper electrode layer and the mask layer in this order; a step of forming the mask layer in a predetermined shape; and the upper electrode layer and the resistance change using the mask layer formed in the predetermined shape as a mask. And etching the lower electrode layer to form a nonvolatile memory element comprising an upper electrode having a predetermined shape, a resistance change layer, and a lower electrode, and the lower electrode layer is etched. The etching rate of the lower electrode layer at the time of packaging has a greater than the etching rate for the upper electrode layer.

  Furthermore, it is preferable that the lower electrode layer and the upper electrode layer use different materials, and the material of the lower electrode layer has a higher etching rate than the material of the upper electrode layer, and the upper electrode is platinum or iridium. It is preferable. Furthermore, it is preferable that the lower electrode is any one of tantalum nitride, tantalum, titanium nitride, and titanium aluminum nitride.

  By using such a manufacturing method, the etching rate of the lower electrode layer when etching the lower electrode layer is larger than the etching rate of the upper electrode layer. Therefore, when etching the lower electrode layer, not only the mask layer The upper electrode also functions as a mask, and the lower electrode layer can be etched. Therefore, the shape of the lower electrode can be formed substantially the same as the shape of the resistance change layer, and the dimensional difference between the upper electrode connection surface in contact with the resistance change layer and the lower electrode connection surface in contact with the resistance change layer is reduced. can do. Thereby, for example, even when platinum or iridium, which is a difficult-to-etch material, is used as an electrode that reversibly changes the resistance change layer, stable characteristics with small characteristic variations can be obtained.

A method for manufacturing a nonvolatile memory device according to the present invention includes a semiconductor substrate, a plurality of word lines and a plurality of bit lines formed on the semiconductor substrate and arranged to cross each other, the plurality of word lines, and the plurality of word lines. And a plurality of transistors provided corresponding to the intersections of the bit lines, and a plurality of nonvolatile memory elements provided in a one-to-one correspondence with the plurality of transistors. Each of the nonvolatile memory elements is interposed between a lower electrode, an upper electrode formed above the lower electrode, and the lower electrode and the upper electrode, and between the lower electrode and the upper electrode. A step of forming a transistor and a semiconductor circuit on the substrate, the resistance change layer having a resistance value that reversibly changes based on an applied electrical signal, Forming a first insulating layer on the substrate and covering the transistor; forming a first contact on the first insulating layer formed on the substrate; and Covering, depositing the lower electrode layer, the variable resistance layer, the upper electrode layer, and the mask layer in this order; forming the mask layer in a predetermined shape; and the mask formed in the predetermined shape Etching the upper electrode layer, the resistance change layer, and the lower electrode using a layer as a mask to form an upper electrode having a predetermined shape, and a nonvolatile memory element including the resistance change layer and the lower electrode. The non-volatile memory element has an etching rate of the lower electrode layer when etching the lower electrode layer larger than an etching rate with respect to the upper electrode layer. As described above, a step of forming a second insulating layer on the first interlayer insulating layer, a second contact connected to the upper electrode layer, and a third connected to the transistor or the semiconductor circuit Forming the contacts at the same time.

  Furthermore, it is preferable that the lower electrode layer and the upper electrode layer use different materials, and the material of the lower electrode layer has a higher etching rate than the material of the upper electrode layer, and the upper electrode layer is made of platinum or iridium. Preferably there is. Furthermore, it is preferable that the lower electrode layer is any one of tantalum nitride, tantalum, titanium nitride, and titanium aluminum nitride.

  By using such a manufacturing method, the etching rate of the lower electrode layer when etching the lower electrode layer is larger than the etching rate of the upper electrode layer. Therefore, when etching the lower electrode layer, not only the mask layer The upper electrode also functions as a mask, and the lower electrode layer can be etched. Therefore, the shape of the lower electrode can be formed substantially the same as the shape of the resistance change layer, and the dimensional difference between the upper electrode connection surface in contact with the resistance change layer and the lower electrode connection surface in contact with the resistance change layer is reduced. can do. Thereby, for example, even when platinum or iridium, which is a difficult-to-etch material, is used as an electrode that reversibly changes the resistance change layer, stable characteristics with small characteristic variations can be obtained.

  Furthermore, since the upper electrode is made of a difficult-to-etch material, the etching rate of the upper electrode is lower than the etching rate of the insulating layer when forming the second contact and the third contact, and the second electrode that connects the wiring layer and the upper electrode Even if the third contact and the third contact connecting the transistor and the wiring layer deeper than the second contact are formed simultaneously, the etching amount of the upper electrode is very small. Therefore, the second contact and the third contact can be formed at the same time, and the process can be simplified.

  The nonvolatile memory element according to the present invention includes a lower electrode, an upper electrode formed above the lower electrode, and interposed between the lower electrode and the upper electrode, and is provided between the lower electrode and the upper electrode. A resistance change layer whose resistance value reversibly changes based on an electrical signal generated, the upper electrode and the lower electrode are made of different materials, and the etching rate of the lower electrode is the etching rate of the upper electrode. Having a larger material.

  Furthermore, the upper electrode is preferably made of platinum or iridium, and the lower electrode is preferably any one of tantalum nitride, tantalum, titanium nitride, and titanium aluminum nitride.

  With such a configuration, the dimensional difference between the upper electrode connection surface in contact with the resistance change layer and the lower electrode connection surface in contact with the resistance change layer is small, and a stable shape with a small shape shift of the resistance change layer can be reliably obtained. Can do. Furthermore, a nonvolatile memory element having stable characteristics using, for example, platinum or iridium which is a difficult-to-etch material as an electrode can be obtained.

A non-volatile memory device according to the present invention includes a semiconductor substrate, a plurality of word lines and a plurality of bit lines formed on the semiconductor substrate and arranged to cross each other, the plurality of word lines and the plurality of bit lines. And a plurality of non-volatile memory elements provided in one-to-one correspondence with the plurality of transistors, and each of the non-volatile memory elements includes a lower electrode. And an upper electrode formed above the lower electrode, and interposed between the lower electrode and the upper electrode, and reversibly resistance based on an electrical signal applied between the lower electrode and the upper electrode A resistance change layer whose value changes, wherein the upper electrode layer and the lower electrode layer are made of different materials, and the etching rate of the lower electrode is an etching rate of the upper electrode. Made larger material than Chin Great, the transistors and semiconductor integrated circuits are connected the lower electrode layer and the upper electrode layer and the electrically have to be provided on the substrate.

  Further, the upper electrode is preferably made of platinum or iridium, and the lower electrode is preferably any one of tantalum nitride, tantalum, titanium nitride, and titanium aluminum nitride.

  According to the nonvolatile memory element, the nonvolatile memory device, and the manufacturing method thereof of the present invention, it is possible to simplify the process, and even if a difficult-to-etch material is used as an electrode, the dimensional difference between the upper electrode and the lower electrode And a stable shape with a small shape shift can be obtained with certainty and stable characteristics can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same component and description may be abbreviate | omitted. In addition, for the sake of convenience, a part thereof may be enlarged and illustrated.

  FIG. 1A is a perspective view schematically showing a configuration of a main part of the storage unit of the nonvolatile memory element 1A according to the embodiment of the present invention, and FIG. It is sectional drawing which looked at the cross section along the -I 'line in the arrow direction.

  As shown in FIGS. 1A and 1B, the nonvolatile memory element 1A of the present invention includes a lower electrode 3, a resistance change layer 2 formed on the lower electrode 3, and a resistance change layer 2. The upper electrode 1 formed on the upper side is provided. As the resistance change layer 2, when an electrical pulse is applied between the upper electrode and the lower electrode, the applied pulse is made different (for example, voltage value, current value, pulse length, etc.) to change the resistance value reversibly. In order to show, a transition metal oxide is used. For example, hafnium oxide, zircon oxide, tantalum oxide, or the like can be used. The lower electrode layer 3 is made of a material having a high etching rate such as tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), or titanium aluminum nitride (TiAlN), while the upper electrode layer 1 is made of platinum (Pt ), Iridium (Ir), or the like is used.

  FIG. 2 is a cross-sectional view of a nonvolatile memory device 10A equipped with the nonvolatile memory element 1A according to the embodiment of the present invention. In a normal case, a large number of memory elements are formed on the substrate, but only one memory element is shown here for the sake of simplification of the drawing. In addition, in order to facilitate understanding, a part is enlarged.

  As shown in FIG. 2, in the nonvolatile memory device 10A of the present embodiment, a gate layer (gate electrode) 13 connected to a word line and a source layer or drain layer 12 are formed on a substrate 11, A first contact 15 connected to the source or drain layer 12 is formed so as to penetrate the first insulating layer 14. The first contact 15 is formed so as to be connected to the lower electrode 3 of the nonvolatile memory element 1A. That is, the nonvolatile memory element 1A in which the lower electrode 3, the resistance change layer 2, and the upper electrode 1 are formed on the first contact 15 is formed. A second insulating layer 19 is formed so as to cover the nonvolatile memory element 1A.

In addition, wiring patterns 18 and 20 are formed on the upper surface of the second insulating layer 19. Then, a second contact 16 is formed so as to penetrate the second insulating layer 19, and the second insulating layer 1
A third contact 17 is formed so as to penetrate 9 and the first insulating layer 14. The upper electrode 1 of the nonvolatile memory element 1 A is connected to the wiring pattern 18 by the second contact 16, and the source layer or the drain layer 12 is connected to the wiring pattern 20 by the third contact 17. A third insulating layer 21 is formed on the second insulating layer 19 so as to cover the wiring patterns 18 and 20, and a fourth contact 22 connected to the wiring pattern 20 so as to penetrate the third insulating layer 21 is provided. Is formed. A wiring pattern 23 serving as a bit line is formed on the third insulating layer 21 so as to be connected to the fourth contact 22.

  Operations of the nonvolatile memory element 1A and the nonvolatile memory device 10A configured as described above will be described below.

  In the nonvolatile memory element 1 </ b> A, a first predetermined electrical pulse (current pulse or voltage pulse) is applied between the lower electrode 3 and the upper electrode 1. In this case, this electric pulse is applied to the resistance change layer 2 disposed between the lower electrode 3 and the upper electrode 1. As a result, the resistance change layer 2 has the first predetermined resistance value and maintains that state. In this state, when a second predetermined electric pulse is applied between the lower electrode 3 and the upper electrode 1, the resistance value of the resistance change layer 2 becomes the second predetermined resistance value, and this state is maintained. To do.

  Here, the first predetermined resistance value and the second predetermined resistance value are associated with two values of binary data, for example. As a result, binary data can be written to the nonvolatile memory element 1A by applying the first or second predetermined electrical pulse to the resistance change layer 2. Also, by supplying a voltage or current that does not change the resistance value of the resistance change layer 2 to the nonvolatile memory element 1A and detecting the resistance value, the binary value written in the nonvolatile memory element 1A is detected. Data can be read out.

  Thus, the resistance change layer 2 disposed between the lower electrode 3 and the upper electrode 1 functions as a storage unit.

  In the nonvolatile memory device 10A, a nonvolatile memory element 1A is connected to a transistor (voltage or current supply switch) including a gate layer 13, a source layer, or a drain layer 12. By applying a voltage or current controlled by this transistor to the nonvolatile memory element 1A, binary data can be written to the nonvolatile memory element 1A as described above. Further, the written binary data can be read by applying a predetermined voltage or current to the nonvolatile memory element 1A. Hereinafter, a method for manufacturing the nonvolatile memory element 1A and the nonvolatile memory device 10A according to the above-described embodiment of the present invention will be described.

  3 (a) to 3 (c) and FIGS. 4 (a) and 4 (b) are cross-sectional views showing the steps of the method for manufacturing the nonvolatile memory element 1A and the nonvolatile memory device 10A according to the embodiment of the present invention. .

  First, in the step shown in FIG. 3A, a gate layer 13, a source layer, and a drain layer 12 are formed on a substrate 11 using a conventional semiconductor process, and then a first insulating layer 14 is formed thereon. . Then, a first contact 15 that penetrates through the first insulating layer 14 and is connected to the source or drain layer 12 is formed.

Next, in the step shown in FIG. 3B, the lower electrode layer 3, the resistance change layer 2, and the upper portion constituting the nonvolatile memory element 1 </ b> A are formed on the first insulating layer 14 so as to cover the first contact 15. The electrode layer 1 is formed in this order. Here, not only the state of being etched into a predetermined pattern shape but also the state of film formation is referred to as the lower electrode layer 3, the resistance change layer 2, and the upper electrode layer 1. As the resistance change layer 2, when an electrical pulse is applied between the upper electrode and the lower electrode, the applied pulse is made different (for example, voltage value, current value, pulse length, etc.) to change the resistance value reversibly. In order to show, a transition metal oxide is used. For example, hafnium oxide, zircon oxide, tantalum oxide, or the like can be used. The lower electrode layer 3 uses a material with a high etching rate such as TaN, Ta, TiN, TiAlN, while the upper electrode layer 1 uses a material with a low etching rate such as Pt or Ir. Specifically, TaN is deposited to 50 nm as the lower electrode layer 3, TaO _x (0.8 ≦ x ≦ 1.9) is deposited to 30 nm as the resistance change layer 2, and Pt is deposited as 80 nm as the upper electrode layer 1.

  Next, in the step shown in FIG. 3C, a resist film 24 is formed in a predetermined shape pattern above the first contact 15 by a normal exposure process and development process.

Next, in the step shown in FIG. 4A, the upper electrode layer 1, the resistance change layer 2 and the lower electrode layer 3 are formed into a predetermined shape pattern by etching by a dry etching process. At this time, as described in the process of FIG. 3B, the lower electrode layer 3 uses a material having a high etching rate such as TaN, Ta, TiN, TiAlN, and the upper electrode layer 1 has an etching rate such as Pt, Ir. However, since the lower electrode layer 3 and the resistance change layer 2 are etched almost perpendicularly, the upper electrode layer 1 is difficult to be etched, so that the upper electrode 1 is etched into a tapered shape. Therefore, the contact area of the upper electrode 1 in contact with the upper surface side of the resistance change layer 2 and the contact area of the lower electrode 3 in contact with the lower surface side of the resistance change layer 2 are substantially the same. In this way, the upper electrode layer 1 and the lower electrode layer 3 are made of different electrode materials so that the etching rate of the lower electrode layer is made larger and the etching rate of the upper electrode layer is made smaller. It is a feature of the present invention that the upper and lower electrode layers and the resistance change layer are etched. As a specific example in this step, Pt of the upper electrode layer 1 and TaO _x of the resistance change layer 2 are etched using a mixed gas of Ar, Cl, and O ₂ , and further a mixed gas of Ar, Cl, and CHF ₃ Is used to etch TaN of the lower electrode layer 3. At this time, the etching rate of TaN is about 6 times or more of the etching rate of Pt. For this reason, Pt of the upper electrode layer 1 is a step of etching Pt of the upper electrode layer 1 and TaO _x of the resistance change layer 2, and Pt of the upper electrode 1 is slightly trapezoidal as shown in FIG. However, TaN of the lower electrode layer 3 can be etched almost vertically, and the size of the contact region where Pt of the upper electrode 1 and TaO _{x of the} resistance change layer 2 are in contact with the TaN of the lower electrode 3 It is possible to reduce the dimensional difference in the contact region where the TaO _{x of the} resistance change layer 2 is in contact.

  Next, in the step shown in FIG. 4B, the second insulating layer 19 is formed so as to cover the nonvolatile memory element 1A. The second insulating layer 19 passes through the second contact 16 connected to the upper electrode layer 1 of the nonvolatile memory element 1A, the second insulating layer 19 and the first insulating layer 14, and the source. A third contact 17 connected to the layer or drain layer 12 is formed at the same time. Next, a wiring pattern 18 and a wiring pattern 20 connected to the second contact 16 and the third contact 17 are formed on the upper surface of the second insulating layer 19. As a specific example in this step, even if the second contact 16 having a height of 600 nm and the third contact 17 having a height of 1080 nm are simultaneously formed, the Pt of the upper electrode layer 1 to which the second contact 16 is connected is formed. Since the etching amount is 10 nm or less, the second contact 16 and the third contact 17 can be formed simultaneously.

  Next, in the step shown in FIG. 5, a third insulating layer 21 is formed so as to cover the wiring patterns 18 and 20. Then, a fourth contact 22 is formed so as to penetrate the third insulating layer 21 and connect to the wiring pattern 20, and the wiring pattern 23 is connected to the fourth contact 22 on the third insulating layer 21. Is formed.

In this way, the nonvolatile memory device 10A on which the nonvolatile memory element 1A is mounted is manufactured. Using this nonvolatile memory element 1A, a nonvolatile memory device having a configuration of, for example, one transistor / 1 nonvolatile memory element can be manufactured.

  By manufacturing the nonvolatile memory element of this embodiment by such a manufacturing method, the size of the contact region (contact area) of the upper electrode 1 in contact with the resistance change layer 2 and the lower electrode 3 in contact with the resistance change layer 2 are obtained. Since the dimensional difference of the contact region (contact area) is small, it is possible to obtain the nonvolatile memory element 1A that can stably apply the voltage and current necessary for resistance change. Therefore, the nonvolatile memory device 10A having stable characteristics with respect to resistance change can be obtained.

  In the case of the present embodiment, it is possible to apply a process for manufacturing a memory portion of a conventional nonvolatile memory element with almost no change, so that the nonvolatile memory element has higher performance and is less expensive. In addition, a nonvolatile memory device can be obtained stably.

  When Ta is used for the lower electrode layer 3, the etching rate of Ta when the lower electrode layer 3 is etched is substantially equal to the etching rate when TaN is used for the lower electrode layer 3. Further, when TiN or TiAlN is used for the lower electrode layer 3, the etching rate of TiN or TiAlN when etching the lower electrode layer 3 is about three times or more of the etching rate of Pt.

  Further, even when Ir is used for the upper electrode layer 1, an etching rate substantially the same as that when Pt is used for the upper electrode layer 1 can be obtained with respect to the lower electrode layer 3 as described above. Therefore, the same effect can be obtained even if Ir is used for the upper electrode layer 1, and the same effect can be obtained even if Ta, TiN, TiAlN is used for the lower electrode layer 3.

  The nonvolatile memory element and the nonvolatile memory device of the present invention are capable of high-speed operation and have stable rewriting characteristics, and various electronic devices such as digital home appliances, memory cards, portable telephones, and personal computers. It is useful as a nonvolatile memory element and a nonvolatile memory device used in

(A) is a perspective view which shows typically the structure of the principal part of the memory | storage part of the non-volatile memory element which concerns on embodiment of this invention, (b) followed the II 'line of the same figure (a). Sectional view of the section viewed in the direction of the arrow Sectional drawing which shows the specific structure of the non-volatile memory device carrying the non-volatile memory element which concerns on embodiment of this invention FIGS. 3A to 3C are cross-sectional views illustrating steps of a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. FIGS. (A), (b) is sectional drawing which shows the process of the manufacturing method of the non-volatile memory device which concerns on embodiment of this invention FIG. 4 is a cross-sectional view showing a process of a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. Sectional drawing of the principal part showing the configuration of the nonvolatile memory element in the conventional example Sectional drawing which shows the structure of the non-volatile memory element in the manufacturing method of a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1A Nonvolatile memory element 1 Upper electrode layer 2 Resistance change layer 3 Lower electrode layer 10A Nonvolatile memory device 11 Substrate 12 Source and drain layer 13 Gate layer 14 First insulating layer 15 First contact 16 Second contact 17 Second contact 3 contacts 18 wiring pattern 19 second insulating layer 20 wiring pattern 21 third insulating layer 22 fourth contact 23 wiring pattern 24 resist mask

Claims (8)

A lower electrode, an upper electrode formed above the lower electrode, and interposed between the lower electrode and the upper electrode, and reversibly based on an electrical signal applied between the lower electrode and the upper electrode In a method of manufacturing a nonvolatile memory element including a resistance change layer whose resistance value changes in
Depositing a lower electrode layer, a resistance change layer, an upper electrode layer, and a mask layer in this order;
Forming the mask layer in a predetermined shape;
The upper electrode layer, the resistance change layer, and the lower electrode layer are etched using the mask layer formed in the predetermined shape as a mask, and a nonvolatile memory composed of the upper electrode, the resistance change layer, and the lower electrode having a predetermined shape. And an etching process for forming a volatile memory element,
The etching rate of the lower electrode layer when etching the lower electrode layer is greater than the etching rate for the upper electrode layer ,
The upper electrode is a difficult-to-etch material,
A method for manufacturing a nonvolatile memory element, wherein the lower electrode is any one of tantalum nitride, titanium nitride, and titanium aluminum nitride . Method of manufacturing a nonvolatile memory element according to claim 1 wherein the upper electrode is platinum or iridium. A semiconductor substrate, a plurality of word lines and a plurality of bit lines arranged on the semiconductor substrate and arranged so as to intersect with each other, are provided corresponding to intersections of the plurality of word lines and the plurality of bit lines, respectively. A plurality of transistors, and a plurality of nonvolatile memory elements provided in one-to-one correspondence with the plurality of transistors, and a method for manufacturing a nonvolatile memory device,
Each of the nonvolatile memory elements includes a lower electrode, an upper electrode formed above the lower electrode, and interposed between the lower electrode and the upper electrode, and is provided between the lower electrode and the upper electrode. A resistance change layer whose resistance value reversibly changes based on an electrical signal generated,
Forming a transistor and a semiconductor circuit on the substrate;
Forming a first insulating layer on the substrate and covering the transistor;
Forming a first contact on the first insulating layer formed on the substrate;
Covering the first contact and depositing the lower electrode layer, the resistance change layer, the upper electrode layer, and a mask layer in this order;
Forming the mask layer in a predetermined shape;
Using the mask layer formed in the predetermined shape as a mask, the upper electrode layer, the resistance change layer, and the lower electrode are etched, and a nonvolatile memory including the upper electrode, the resistance change layer, and the lower electrode having a predetermined shape is etched. an etching step of forming an element,
So as to cover the non-volatile memory element, forming a second insulating layer on the first insulation layer,
Simultaneously forming a second contact connected to the upper electrode layer and a third contact connected to the transistor or the semiconductor circuit ;
The etching rate of the lower electrode layer when etching the lower electrode layer is greater than the etching rate for the upper electrode layer ,
The upper electrode is a difficult-to-etch material,
A method for manufacturing a nonvolatile memory device, wherein the lower electrode is any one of tantalum nitride, titanium nitride, and titanium aluminum nitride . Method for manufacturing a nonvolatile memory device according to claim 3 wherein the upper electrode layer is platinum or iridium. A lower electrode;
An upper electrode formed above the lower electrode;
A resistance change layer that is interposed between the lower electrode and the upper electrode and reversibly changes its resistance value based on an electrical signal applied between the lower electrode and the upper electrode;
Wherein Ri etching rate of the lower electrode Do from larger material than the etching rate of the upper electrode,
The upper electrode is a difficult-to-etch material,
A nonvolatile memory element in which the lower electrode is any one of tantalum nitride, titanium nitride, and titanium aluminum nitride . The nonvolatile memory element according to claim 5, wherein the upper electrode is made of platinum or iridium. A semiconductor substrate, a plurality of word lines and a plurality of bit lines arranged on the semiconductor substrate and arranged so as to intersect with each other, are provided corresponding to intersections of the plurality of word lines and the plurality of bit lines, respectively. A plurality of transistors, and a plurality of nonvolatile memory elements provided in one-to-one correspondence with the plurality of transistors,
Each of the nonvolatile memory elements includes a lower electrode, an upper electrode formed above the lower electrode, and interposed between the lower electrode and the upper electrode, and is provided between the lower electrode and the upper electrode. A resistance change layer whose resistance value reversibly changes based on an electrical signal generated,
The etching rate of the lower electrode is made of material having a large than the etching rate of the upper electrode,
The upper electrode is a difficult-to-etch material,
The lower electrode is one of tantalum nitride, titanium nitride, titanium aluminum nitride,
A nonvolatile memory device comprising the substrate and the transistor and a semiconductor integrated circuit electrically connected to the lower electrode layer and the upper electrode layer. Non-volatile memory device according to claim 7, wherein the upper electrode is made of platinum or iridium.

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