JP5337177B2 - Memory control device and memory control method - Google Patents

Description

  Embodiments described herein relate generally to a memory control device and a memory control method for controlling a memory of a video server.

  The memory control unit of the video server performs MXF (Material eXchange Format) material data input via a broadband transmission path from the file processing unit and outputs it to the memory unit via SERDES (Serializer / Deserializer). There is a function and a function of buffering MXF material data input from the memory unit and outputting it to the file processing unit or the decoder unit via a broadband transmission path.

Japanese Patent Laid-Open No. 2003-87710

  However, since the playback and file output buffers are shared memory to reduce hardware constraints and costs, realization of simultaneous playback and file output processing becomes more complex in design as the number of playback channels increases. Was increasing.

  An object of the present embodiment is to provide a memory control device and a memory control method capable of efficiently realizing simultaneous processing of reproduction and file output from the memory of a video server.

  The memory control device according to the present embodiment is a memory control device of a video server that transmits file output data and reproduction data by buffering them in a common memory, and the file output data and the reproduction data are transmitted from the memory. Reading means for switching between, a first buffer for temporarily storing the file output data read by the reading means before transmission, and the reproduction data read by the reading means before transmission A second buffer for temporarily storing; and a control unit for controlling the reading unit to read the reproduction data during a period in which a back pressure signal is received from the first buffer.

The memory control method according to the present embodiment is a method used in a memory control device of a video server for buffering and transmitting file output data and reproduction data to a common memory, and the file output data from the memory the reproduced data and the read switches the previous first accumulated in the buffer Ki読 the file output data Desa viewed temporarily before transmission, temporarily before transmitting the reproduced data before been Desa see Ki読 In other words, the reproduction data is stored in a second buffer, and the reproduction data is controlled to be read during a period in which a back pressure signal is received from the first buffer.

1 is a block diagram illustrating a configuration of a memory control device according to an embodiment. The figure which shows the allocation image of the process in 1 frame. The figure which shows the read / write timing of a buffer memory. The figure which shows the read-out timing of the buffer memory when there is no write-in operation.

  Hereinafter, a memory control device and a memory control method according to the present embodiment will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration example of a memory control device according to the present embodiment. In FIG. 1, the memory control device 1 includes a memory controller 11 that is a control interface of the buffer memory 2, a first FPGA (Field Programmable Gate Array) 12, and a second FPGA 13. Since the buffer memory 2 is commonly used for reproduction and file output, the memory controller 11 cannot simultaneously read the reproduction data and file output data from the buffer memory 2.

  The first FPGA 12 includes an input buffer 21, a write control unit 22, a read control unit 23, and a read / write switching control unit 24. Data (file processing data and reproduction data) received from the memory unit 3 is temporarily stored in the input buffer 21. The write control unit 22 takes out data from the input buffer 21 according to control by the read / write switching control unit 24, passes it to the memory controller 11, and writes data in the buffer memory 2. The read control unit 23 reads data from the buffer memory 2 via the memory controller 11, identifies the read data as file output / reproduction, the file output data to the file output speed conversion buffer 31, and the reproduction data for reproduction. Each is sent to the speed conversion buffer 33. As will be described later, the read / write switching control unit 24 controls switching between the writing process of the write control unit 22 and the reading process of the read control unit 23.

  The second FPGA 13 includes a file output speed conversion buffer 31 that temporarily stores file output data before transmission, a first transmission control unit 32 that transmits file output data, and temporary reproduction data before transmission. And a second transmission control unit 34 for transmitting reproduction data. The file output speed conversion buffer 31 and the reproduction speed conversion buffer 33 are composed of a FIFO (First In First Out) memory. Usually, since the I / O speed of the buffer memory 2 and the bit width of the external interface (Reed-Solomon decoder 4 and file processing unit 5) are different, the operating frequencies are different. The file output speed conversion buffer 31 and the reproduction speed conversion buffer 33 are provided as buffer buffers for absorbing this speed difference. The file output data transmitted from the first transmission control unit 32 is decoded by the Reed-Solomon decoder 4 and then sent to the file processing unit 5. The reproduction data transmitted from the second transmission control unit 34 is decoded by the decoder unit 6 and then transmitted to the baseband as on-air data.

  Next, the operation of the memory control device configured as described above will be described.

  FIG. 2 shows an allocation image of read / write processing within one frame.

  For example, if 40 channels of output channels per frame (33.3 ms) are to be secured for playback, just outputting 40 channels of playback from the buffer memory 2 requires 32.1 ms, which is approximately one frame time. . On the other hand, file output does not need to be output in frame synchronization, but requires Reed-Solomon decoding, so 5.7 ms per channel is required. For this reason, when 40 channels are played back, file output cannot be processed for one channel in the same frame, and playback and file output cannot be processed simultaneously. In addition, since idle time is generated due to back pressure from the file output speed conversion buffer 31 and the reproduction speed conversion buffer 33, the processing efficiency is poor.

  Therefore, in the present embodiment, as shown in FIG. 2, in order to transmit 40 channels of playback and 5 channels of file output within one frame, 45 channels are written, 40 channels are read, and file output 5 is transmitted. Provided is a method for performing channel reading in parallel.

  A memory control method for realizing the processing of FIG. 2 will be described with reference to FIG. FIG. 3 is a diagram showing the read / write timing of the buffer memory.

  At t1 in FIG. 3, the read / write switching control unit 24 switches to reading the file output data after the writing of the data for one channel by the write control unit 22 is completed.

  At t2, when the back pressure signal is received from the file output speed conversion buffer 31, the read / write switching control unit 24 causes the read control unit 23 to stop reading the file output data.

  At t3, the read / write switching control unit 24 causes the read control unit 23 to read the reproduction data during the period in which the back pressure signal is received from the file output speed conversion buffer 31.

  When reproduction data or file output data is stored in the input buffer 21 from the memory unit 3 at t4, the write control unit 22 switches to writing processing.

  FIG. 4 shows the read timing of the buffer memory when there is no write operation.

  At time t1 in FIG. 4, the read / write switching control unit 24 causes the read control unit 23 to stop reading the file output data at the time when the back pressure signal is received from the file output speed conversion buffer.

  At t2, the read / write switching control unit 24 causes the read control unit 23 to read the reproduction data during the period in which the back pressure signal is received from the file output speed conversion buffer 31.

  At t3, when the back pressure from the file output speed conversion buffer 31 is released, the read / write switching control unit 24 starts reading the file output data again.

  As described above, in this embodiment, the back pressure from the file output speed conversion buffer is utilized to efficiently switch between reading the file output data in the buffer memory, reading the reproduction data, and reproducing / writing the file output data. As a result, it is possible to allocate the idle time of the file output process to the reproduction process. Further, by providing a speed conversion buffer separately for reproduction and file output at the subsequent stage of the buffer memory, it becomes possible to transmit reproduction data and file output data simultaneously.

  Although several embodiments have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Memory control apparatus, 2 ... Buffer memory, 3 ... Memory unit, 4 ... Reed-Solomon decoder, 5 ... File processing unit, 6 ... Decoder unit, 11 ... Memory controller, 12 ... 1st FPGA, 13 ... 2nd FPGA, 21 ... input buffer, 22 ... write control unit, 23 ... read control unit, 24 ... read / write switching control unit, 31 ... file output speed conversion buffer, 32 ... first transmission control unit, 33 ... reproduction speed conversion Buffer 34... Second transmission control unit.

Claims (4)

A memory control device for a video server for buffering and transmitting file output data and reproduction data to a common memory,
Read means for switching and reading the file output data and the reproduction data from the memory;
A first buffer for temporarily storing the file output data read by the reading means before transmission;
A second buffer for temporarily storing the reproduction data read by the reading means before transmission;
And a control means for controlling the reading means so that the reproduction data is read during a period in which a back pressure signal is received from the first buffer. A writing means for writing the file output data and the reproduction data into the memory;
The memory control device according to claim 1, wherein the control unit prioritizes a writing process by the writing unit during the period. A method used in a memory control device of a video server for buffering and transmitting file output data and reproduction data in a common memory,
Switching and reading the file output data and the reproduction data from the memory;
The file output data before Desa see Ki読 accumulated temporarily first buffer before transmission,
Temporarily stored in the second buffer before transmitting the reproduced data before Desa see Ki読,
A memory control method comprising: controlling the reproduction data to be read during a period in which a back pressure signal is received from the first buffer. Writing the file output data and the reproduction data to the memory;
The memory control method according to claim 3, wherein the control further prioritizes the writing process in the period.

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