JP5326643B2 - Method of manufacturing nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method which can control a variation of a film thickness in a wafer surface and can efficiently manufacture a nitride semiconductor element with stable quality. <P>SOLUTION: The manufacturing method includes a laminating process to form a nitride semiconductor layer of on a grown substrate to obtain a wafer, a groove forming process to remove a part of the wafer from a nitride semiconductor layer side in a thickness direction to form a plurality of grooves, a process to form burying layers in a plurality of grooves, and removing process composed of a first process to make a bottom surface of some burying layer exposed from the grown substrate side and in a state of being covered with the grown substrate or the nitride semiconductor layer and a second process to expose a bottom surface different from the bottom surface exposed in the first process. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a nitride semiconductor device.

Conventionally, In _x Al _y Ga as element using a nitride semiconductor of _{1-xy N (0 ≦ x} , 0 ≦ y, 0 ≦ x + y ≦ 1), the nitride semiconductor light emitting device (LED), laser diode (LD ), Vertical cavity surface emitting lasers (VCSEL), photodetectors (PD), etc. are being researched.
As a method for manufacturing a nitride semiconductor device, a nitride semiconductor layer and electrodes are usually formed on a growth substrate, and the resulting wafer is divided into a plurality of chips to obtain the device.
In addition, after forming a nitride semiconductor layer and electrodes on the growth substrate, another support substrate is provided on the semiconductor layer side, and the growth substrate may be removed (for example, Patent Documents 1 to 4).
In some vertical cavity surface emitting lasers, a Bragg reflector is formed on the exposed semiconductor layer surface after the growth substrate is removed (for example, Patent Document 5).

JP 2006196669 A JP 2004-95959 A JP-A-2005-333130 JP 2006-135321 A JP 2003-234542 A

As described above, since most of the processes of the nitride semiconductor device are manufactured in a wafer state, it is important to suppress variations in the wafer surface in order to manufacture the device efficiently. Usually, the growth substrate is often removed as in Patent Documents 1 to 5, or thinned by polishing or the like. At this time, the processed film thickness tends to vary within the wafer surface. In order to improve the mass productivity of the nitride semiconductor element, it is effective to use a large wafer. However, such a tendency tends to appear as the wafer becomes larger. Variations in the thickness within the wafer surface cause problems such as variations in device characteristics and a decrease in yield.
In addition, in a vertical cavity surface emitting laser, it is difficult to obtain a Bragg reflector having a high reflectance with a nitride semiconductor, and therefore, a Bragg reflector made of a dielectric material is used as in Patent Document 5. . In that case, the Bragg reflector is formed after removing the growth substrate. In the vertical cavity surface emitting laser, the cavity length shift greatly affects the laser characteristics, so that it is important to determine the cavity length by controlling the film thickness after removing the growth substrate. That is, in the vertical cavity surface emitting laser, it is required to control the in-plane distribution of the film thickness in the wafer plane as described above with higher accuracy.
The present invention has been made in view of the above problems, and provides a manufacturing method capable of efficiently manufacturing a stable quality nitride semiconductor element while suppressing variations in film thickness within the wafer surface. Objective. It is another object of the present invention to provide a manufacturing method capable of manufacturing a highly efficient vertical cavity surface emitting laser by suitably controlling the cavity length in the vertical cavity surface emitting laser.

The method of manufacturing a nitride semiconductor laser device according to the present invention includes a groove portion in which a wafer having a nitride semiconductor layer formed on a growth substrate is partially removed from the nitride semiconductor layer side in the film thickness direction to form a plurality of groove portions. Forming a buried layer in a plurality of grooves, removing a portion of the wafer on the growth substrate side, exposing a bottom surface of a portion of the buried layer, and After the removal step, the wafer comprises a first step in which the bottom surface is covered with the growth substrate or the nitride semiconductor layer, and a second step in which the bottom surface covered in the first step is exposed. And a step of obtaining a nitride semiconductor device .
Another method of manufacturing a nitride semiconductor laser device according to the present invention includes a stacking step of forming a nitride semiconductor layer on a growth substrate to obtain a wafer, and a part of the wafer in the film thickness direction from the nitride semiconductor layer side. A groove forming step of removing and forming a plurality of grooves, a step of forming a buried layer in the plurality of grooves, and exposing a bottom surface of a part of the buried layer from the growth substrate side. A removal step comprising: a first step in which the bottom surface is covered with a growth substrate or a nitride semiconductor layer; and a second step in which a bottom surface different from the bottom surface exposed in the first step is exposed. It is characterized by that.
The removal step is preferably performed by chemical mechanical polishing.
The buried layer is preferably formed of a material containing any one of silicon nitride, niobium oxide, and silicon oxide, and the removing step is preferably performed using an alkaline solvent.
The growth substrate is preferably made of a nitride semiconductor or silicon.
In the first step, polishing may be performed so that the thickness at the outer peripheral portion of the wafer is thinner than the thickness at the central portion.
In the second step, the wafer may be polished so that the difference in film thickness between the central portion and the outer peripheral portion of the wafer is reduced while maintaining the thickness at the outer peripheral portion of the wafer.
In the stacking step, a nitride semiconductor layer is stacked in this order on the growth substrate in the order of the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer, and the first conductive semiconductor layer is exposed in the groove forming step. In addition, the nitride semiconductor layer can be removed.
The nitride semiconductor device may be a vertical cavity surface emitting laser in which the surface exposed by the removing step and the surface of the nitride semiconductor layer are the cavity surfaces.
After the removing process, an etching process for removing the surface exposed in the removing process may be provided.
The first conductivity type semiconductor layer has an Al-containing layer, and the growth substrate and the first conductivity type semiconductor layer closer to the growth substrate than the Al-containing layer contain Al having a lower mixed crystal than the Al-containing layer. It is also possible to form a groove part deeper than the Al-containing layer in the groove part forming step and expose the Al-containing layer in the etching process.
The nitride semiconductor device may be a vertical cavity surface emitting laser in which the surface exposed by the etching process and the surface of the nitride semiconductor layer are the cavity surfaces.

  According to the method for manufacturing a nitride semiconductor device of the present invention, it is possible to efficiently produce a nitride semiconductor device having a stable quality by suppressing variations in film thickness within the wafer surface after the wafer thinning or growth substrate removal step. The manufacturing method which can be performed can be provided. In addition, in the vertical cavity surface emitting laser, it is possible to provide a manufacturing method capable of accurately controlling the cavity length and manufacturing a highly efficient vertical cavity surface emitting laser.

Schematic sectional view of a vertical cavity surface emitting laser according to an embodiment of the present invention Schematic diagram illustrating a manufacturing process of a vertical cavity surface emitting laser according to an embodiment of the present invention. Schematic diagram illustrating a manufacturing process of a vertical cavity surface emitting laser according to an embodiment of the present invention. Schematic diagram illustrating a manufacturing process of a vertical cavity surface emitting laser according to an embodiment of the present invention. Schematic sectional view of a nitride semiconductor light emitting device according to another embodiment of the present invention The schematic diagram explaining the manufacturing process of the nitride semiconductor light-emitting device concerning another embodiment of this invention. The schematic diagram explaining the manufacturing process of the nitride semiconductor light-emitting device concerning another embodiment of this invention. Schematic sectional view of a vertical cavity surface emitting laser according to an embodiment of the present invention Schematic diagram illustrating a manufacturing process of a vertical cavity surface emitting laser according to an embodiment of the present invention. Schematic diagram illustrating a manufacturing process of a vertical cavity surface emitting laser according to an embodiment of the present invention. Schematic diagram illustrating a manufacturing process of a vertical cavity surface emitting laser according to an embodiment of the present invention. Schematic sectional view of a vertical cavity surface emitting laser according to an embodiment of the present invention

First, each process which comprises this invention is demonstrated using FIG. 2 thru | or 4. FIG.
<Lamination process>
As shown in FIG. 2A, a nitride semiconductor layer 20 is stacked on the growth substrate 10 to obtain a wafer 15. The growth method of the nitride semiconductor layer is not particularly limited, and MOVPE (metal organic chemical vapor deposition), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy). Or the like, a method known as a nitride semiconductor growth method can be used.
<Groove formation process>
As shown in FIG. 2B, a plurality of grooves 30 are formed by partially removing the wafer 15 obtained in the stacking step from the nitride semiconductor layer side in the film thickness direction. In the present invention, the final wafer thickness can be determined in accordance with the depth of the groove. Therefore, it is preferable that the plurality of groove portions are formed with substantially the same depth, and the other groove portions are formed with substantially the same depth in the wafer surface. This makes it possible to suppress the film thickness distribution in the wafer plane. Also, the resonator length of the vertical cavity surface emitting laser can be determined by this process. That is, the thickness from the nitride semiconductor layer surface to the groove bottom surface corresponding to the depth of the formed groove portion can be set as the resonator length. Therefore, the resonator length can be suitably controlled by controlling the depth of the groove.
The bottom surface of the groove portion 30 is formed so that the nitride semiconductor layer 20 or the growth substrate 10 is exposed, but it is preferable that the first conductivity type semiconductor layer is exposed. Thereby, regardless of the conductivity of the growth substrate, a counter electrode structure can be obtained, and the device can be downsized and the light extraction efficiency can be improved.

  Further, by providing the groove, the element region on the surface of the nitride semiconductor layer can be defined. That is, each element can be obtained by dividing the wafer in the groove region by using the region where the nitride semiconductor layer is left in the groove forming step as the device region. At this time, the wafer is not necessarily divided in each groove region, and the wafer can be arbitrarily divided in a region other than the element region. For example, a vertical cavity surface emitting laser array having a plurality of element regions may be used.

  The groove can be formed by a method known in the art, and examples thereof include etching (dry etching, wet etching), blasting, scribe (cutter scribe, laser scribe, etc.), dicing and the like. Of these, etching is preferable.

  For example, wet etching is performed by exposing the nitride semiconductor layer to an etchant by immersing the nitride semiconductor layer in an alkaline solution such as potassium hydroxide or sodium hydroxide, or an acidic solution such as phosphoric acid, sulfuric acid, or aqua regia for a predetermined time. It can be carried out.

The dry etching can be performed using, for example, reactive ion etching (RIE), reactive ion beam etching (RIBE), electron cyclotron resonance (ECR) etching, ion beam etching, or the like. In any case, an etching gas (for example, a fluorine gas such as CF ₄ , a chlorine gas such as Cl ₂ , CCl ₄ , or SiCl ₄ , or an iodine gas such as HI alone or a mixed gas) may be appropriately selected. When performing dry etching, the etching conditions including the type of etching gas (gas flow rate, RF power, pressure, temperature, etching time, etc.) can be determined by appropriately adjusting.

More preferable is RIE (reactive ion etching) using a mask because the groove formation region and the element region can be freely determined by the mask pattern, and the depth of the groove is also a desired depth. This is because it is relatively easy to control. A specific etching method is not particularly limited, and examples thereof include a method in which a predetermined mask pattern is formed on the surface of the nitride semiconductor layer, and etching is performed using this mask pattern as a mask. The mask pattern can be formed by patterning a resist, an insulator such as SiO ₂ or the like into an appropriate shape by a known method such as photolithography and an etching process. The shape of the mask pattern is not particularly limited. When the mask pattern is associated with the element region, a circle, an ellipse, a rectangle, or the like can be selected to obtain desired characteristics.

<Embedding process>
As shown in FIG. 2C, the buried layer 40 is formed in the plurality of grooves 30 provided in the wafer 15. The thickness of the buried layer can be determined in consideration of the in-plane distribution at the time of polishing, the selectivity between the buried layer and the nitride semiconductor layer, etc., but is buried so as to cover at least the bottom surface of the groove. It is preferable to form a layer and form a film having a thickness of 100 nm or more from the bottom of the groove. Thereby, the function as a stop layer at the time of grinding | polishing can be fulfill | performed. Moreover, although the film thickness of a buried layer is based also on the depth of a groove part, about 100-6000 nm is mentioned. Further, in the case of bonding to the support substrate, the buried layer is preferably formed so as to fill the entire groove portion, and specifically, is formed to have the same height as the surface of the nitride semiconductor layer. Alternatively, it is preferably formed at the same height as the surface of the electrode formed on the surface of the nitride semiconductor layer. By forming the surface of the buried layer and the nitride semiconductor layer and the electrode without any step, the subsequent device process can be easily performed. In addition, an unintentionally provided gap due to a step makes it possible to prevent deterioration of element characteristics due to a change in refractive index distribution or the like, but this can be prevented.

  The method for forming the buried layer is not particularly limited, and the buried layer can be formed using a method known in the art. For example, evaporation method, sputtering method, reactive sputtering method, ECR plasma sputtering method, magnetron sputtering method, ion beam assisted evaporation method, ion plating method, laser ablation method, CVD method, spray method, spin coating method, dip method, etc. Is mentioned. Or a combination of two or more of these methods, or these methods and whole or partial pretreatment, irradiation of inert gas (Ar, He, Xe, etc.) or plasma, irradiation of oxygen or ozone gas or plasma, Various methods such as a method of combining any one or more of oxidation treatment (heat treatment) and exposure treatment can be used.

<Removal process>
As shown in FIGS. 2D to 3G, a removing process of exposing the bottom surface of the buried layer 40 from the obtained wafer 15 is performed. When the bottom surface of the formed buried layer 40 is in the nitride semiconductor layer, a part of the growth substrate 10 and the nitride semiconductor layer 20 is removed, and when the bottom surface of the buried layer 40 is in the growth substrate, A part of the growth substrate 10 is removed. After this step, processing is performed with the growth substrate side facing upward.
In the present specification, the term “upper” includes not only directly above but also the meaning / content of upper.
In exposing the bottom surface of the buried layer 40, the growth substrate 10 is first roughly removed as shown in FIG. The removal of the growth substrate here is not particularly limited, and can be performed by a method known in the art. For example, a laser lift-off method, grinding, polishing, etching, or the like can be used, and these methods may be combined.

<First step>
Subsequently, as shown in FIG. 3F, the bottom surface of the part of the buried layer 40 is exposed from the growth substrate side, and the bottom surface of the part of the buried layer 40 is formed by the growth substrate 10 or the nitride semiconductor layer 20. The 1st process which makes it the coat | covered state is performed. By the previously formed buried layer, polishing is stopped in the exposed region when the bottom surface of the buried layer is exposed, and the nitride semiconductor layer in the exposed region is held on substantially the same surface as the bottom surface of the buried layer. Here, the nitride semiconductor layer in the vicinity of the exposed buried layer and the nitride semiconductor layer in a region sandwiched between the exposed buried layers are defined as an exposed region.

  The position and region in the wafer of the bottom surface of the buried layer exposed in the first step are not particularly limited. It can be set as appropriate in consideration of the wafer mounting state and wafer warpage during the removal step. Polishing may be performed so that only the vicinity of the wafer center is exposed, polishing may be performed so that only the outer periphery of the wafer is exposed, or an arbitrary region may be exposed between the center and the outer periphery, or these May be combined.

Further, the position and region within the wafer are not particularly limited with respect to the bottom surface of the buried layer to be coated. Similar to the exposed region, it may be covered only near the wafer center, or may be covered only at the outer periphery of the wafer, or an arbitrary region from the center to the periphery may be covered, These may be combined. Further, there is no particular limitation on the coating thickness of the growth substrate or nitride semiconductor layer that forms the coating region. The region to be removed in the second step thereafter is preferably within 6 μm for the vertical cavity surface emitting laser and within 10 μm for the nitride semiconductor light emitting device. Within this range, it is preferable that the growth substrate and the nitride semiconductor layer can be easily removed to expose the bottom surface of the buried layer without adjusting the polishing conditions during the polishing in the second step.
Further, there may be a distribution in the film thickness coated in the coating region. Specifically, in a form in which the film thickness increases gradually or stepwise toward the outer periphery of the wafer, in a form in which the film thickness increases gradually or stepwise toward the center of the wafer, in any region in the wafer It is good also as a form which has distribution of a film thickness gradually or in steps.
Further, the ratio between the exposed area and the covered area is not particularly limited. Preferably, about 1 to 50% of the wafer area is exposed in the first step.

In the present invention, an exposed region is formed in the vicinity of the outer periphery of the wafer as shown in FIG. 3 (f) in a wafer having a thinner thickness at the outer periphery of the wafer as shown in FIG. An example of the polishing is such that the thickness at the outer peripheral portion of the wafer is thinner than the thickness at the central portion so that the inner region becomes the coating region. At this time, it is preferable to polish the coating region so that the coating film thickness increases as it approaches the center of the wafer. This is because the slurry as the polishing liquid is efficiently supplied to the entire surface. At this time, it is preferable that the exposed region is formed about 1 to 5 mm from the outer periphery of the wafer (about 10% or less of the wafer area), and is about 10 μm or less even at the thickest portion of the coating region. In such a form, the bottom surface of the buried layer other than that exposed in the first step can be exposed only by proceeding with the polishing in the second step described later, and a wafer having a uniform thickness can be obtained by a simple method. be able to.
As another example, as shown in FIG. 7F, one side of the wafer is used as an exposed region and the other side is used as a covered region. Further, it is preferable to polish the coating region so that the coating film thickness increases as the distance from the exposed region increases. Such a configuration is preferable because the bottom surface of the buried layer of the entire wafer can be exposed by polishing the other side in the second step, and a wafer having a uniform thickness can be obtained by a simple method.
In general, the shape of the wafer is often formed in a circular shape. However, when the wafer is cut into a rectangular shape or an amorphous wafer is used, the nitride is removed from the corner when performing the removal process. As the semiconductor is removed, the in-plane distribution tends to appear more remarkably. Even in such a case, the production method of the present invention is effective.

Polishing or etching can be used as the removal method in the first step. A specific method includes, for example, chemical mechanical polishing (CMP). The wafer is held by a holding member and pressed against a polishing cloth, and polishing is performed while flowing a slurry which is a polishing liquid containing hard fine abrasive grains.
The CMP apparatus and conditions are not particularly limited, and the material of the polishing cloth, hardness, slurry composition, pH, liquid temperature, particle concentration of abrasive grains contained in the slurry, particle diameter, particle hardness, and pressure applied during polishing Further, CMP can be performed by appropriately adjusting conditions such as the polishing rate.
Preferably, the slurry contains an alkaline solvent, whereby the nitride semiconductor layer can be suitably polished. Examples of the slurry include phosphoric acid, potassium hydroxide, tetramethylammonium hydroxide (TMAH) and the like. When the slurry contains an alkaline solvent, the buried layer is preferably made of a material that is less soluble in an alkaline solvent than the nitride semiconductor layer, and is made of a material that can function as a CMP stop layer. Furthermore, since the growth substrate or nitride semiconductor layer to be polished is the -C plane, it can be suitably polished by CMP using a slurry containing an alkaline solvent, and a flat polished surface can be obtained in the exposed region. preferable. By combining these conditions as appropriate, CMP can be performed to determine the final wafer thickness.

<Second step>
Subsequently, as shown in FIG. 3G, a second step of exposing a bottom surface different from the bottom surface exposed in the first step is performed. That is, the bottom surface of the buried layer 40 different from the bottom surface exposed in the first step is exposed in a state where the exposed region formed in the first step is held. By performing the second step, the nitride semiconductor layer between the buried layers exposed in the first step and / or the second step is held on substantially the same surface as the exposed buried layer. At this time, as the exposed bottom surface, at least the bottom surface of the buried layer other than that exposed in the first step is exposed, but all the bottom surfaces of the buried layer covered in the first step are exposed. There is no need. Preferably, the bottom surfaces of all formed buried layers are exposed.

  The position and region in the wafer of the bottom surface of the buried layer exposed in the second step are not particularly limited. The vicinity of the center of the wafer may be exposed, the outer periphery of the wafer may be exposed, an arbitrary region from the center to the outer periphery may be exposed, or a combination thereof may be used. Preferably, as described above, in the wafer polished such that the thickness at the outer peripheral portion of the wafer as shown in FIG. 3F is thinner than the thickness at the central portion, the wafer is maintained while maintaining the thickness at the outer peripheral portion. Polishing is performed so that the difference in film thickness between the central portion and the outer peripheral portion becomes small. Thereby, substantially the same thickness can be obtained on the entire wafer surface.

  The position and region in the wafer of the bottom surface of the buried layer exposed after the second step are not particularly limited. Only the vicinity of the wafer center may be exposed, only the outer periphery of the wafer may be exposed, an arbitrary region between the center and the periphery may be exposed, or a combination thereof may be used. . In order to increase the effective diameter of the wafer, it is preferable that the finally exposed area is large, but the ratio between the exposed area and the covered area is not particularly limited. Preferably, the second step is preferably performed such that about 50 to 100% of the wafer area is finally polished to a desired thickness.

  Further, the position and region of the bottom surface of the buried layer that is covered when the second step is completed are not particularly limited. Similar to the exposed one, only the vicinity of the wafer center may be exposed, only the outer periphery of the wafer may be exposed, or an arbitrary region may be exposed between the center and the outer periphery. These may be combined. Further, the coating thickness of the growth substrate or nitride semiconductor layer coated at this time is not particularly limited. Further, the coating film thickness may be distributed. Specifically, in a form in which the film thickness increases gradually or stepwise toward the outer periphery of the wafer, in a form in which the film thickness increases gradually or stepwise toward the center of the wafer, in any region in the wafer It is good also as a form which has distribution of a film thickness gradually or in steps.

  In the present invention, an exposed region is formed in the vicinity of the outer peripheral portion of the wafer as described above, and the inner region is polished in the second step even in the wafer polished so that the inner region becomes a coating region. In-plane distribution can be suppressed by exposing the bottom surface of the buried layer. Finally, it is preferable to polish in the second step so that about 80% of the wafer area maintains the reference wafer thickness. Further, after the second step, it is preferable that the wafer film thickness difference in the plane is 2 μm or less at maximum. This is preferable because variations in device characteristics and a decrease in yield due to the variation can be suppressed.

  A specific removal method in the second step can be performed in the same manner as in the first step. Further, the polishing conditions may be the same or changed in the first step and the second step. When polishing a wafer having warpage, if the hardness of the polishing cloth is reduced, the distribution of the film thickness within the wafer surface can be suppressed, and the polishing conditions in the first and second steps can be reduced. Even if polishing is continued without changing, it is preferable to make the film thickness of the wafer uniform in the surface. In the second step, the surface of the nitride semiconductor layer that has already been exposed in the first step needs to be retained, but dishing can be suppressed by increasing the hardness of the polishing pad compared to the first step. This is preferable. Further, it is preferable that processing can be performed quickly by increasing the pressure and / or increasing the number of rotations.

  In addition, when a heterogeneous substrate made of a material different from the nitride semiconductor layer is used as the growth substrate, it is only necessary to remove the growth substrate by laser lift-off and polish only the nitride semiconductor layer. Variation in thickness can be suppressed to a relatively small value depending on polishing conditions and the like. However, when a nitride semiconductor substrate is used, the nitride semiconductor substrate and the nitride semiconductor layer are removed by grinding and polishing, so that the in-plane distribution increases as the polishing process proceeds. Therefore, by forming the buried layer as described above, it is possible to maintain the wafer thickness without further polishing with the bottom surface of the buried layer exposed in the polishing step.

  As described above, in the present invention, polishing is stopped at a desired position during polishing like a nitride semiconductor layer formed on a nitride semiconductor substrate, and wafer thickness control is performed like a vertical cavity surface emitting laser. Even when required, control with high accuracy becomes possible. In addition, the final film thickness distribution can be eliminated even within the wafer surface, and a large number of regions having a desired thickness can be secured within the wafer surface.

Hereinafter, embodiments of the present invention will be described.
Embodiment 1
As shown in FIG. 1, the vertical cavity surface emitting laser obtained by the manufacturing method of the present invention includes a first Bragg reflector 71 and a nitride semiconductor layer formed on a support substrate 50 with an adhesive layer 60 interposed therebetween. 20 and the second Bragg reflector 72, and laser light is emitted from the second Bragg reflector side. In the nitride semiconductor layer 20, a p-type semiconductor layer, an active layer, and an n-type semiconductor layer are sequentially stacked from the support substrate 50 side. A p-side electrode 91 is formed on the surface of the p-type semiconductor layer between the first Bragg reflector 71 and the nitride semiconductor layer 20, and an n-side electrode 92 is formed on the surface of the n-type semiconductor layer. A connection electrode 93 is provided on the side surface of the first Bragg reflector 71 so as to connect to the p-side electrode 91 and the adhesive layer 60. A buried layer 40 is formed on the side surface of the nitride semiconductor layer 20. Although details will be described later, the nitride semiconductor layer 20 is stacked on a growth substrate 10 different from the support substrate 50.
Each configuration will be described below.

(Growth substrate 10)
The growth substrate may be any substrate that can grow a nitride semiconductor. Specifically, a nitride semiconductor such as GaN or AlN having any one of the C-plane, M-plane, A-plane and R-plane as a main surface, and any one of the C-plane, M-plane, A-plane and R-plane as the main plane. And sapphire, spinel (MgA1 ₂ O ₄ ), silicon carbide, silicon, ZnS, ZnO, GaAs, diamond, lithium niobate, neodymium gallate and the like. The growth substrate may have an off angle of about 0 ° to 10 ° on the first main surface and / or the second main surface. Among these, a nitride semiconductor substrate is preferable from the viewpoint of growing a nitride semiconductor layer with good crystallinity. Moreover, it is preferable if the substrate to be polished in the polishing step is a -C plane because desired processing is easily performed in the polishing step.

(Nitride semiconductor layer 20)
As the nitride semiconductor laminated on a growth substrate, those represented by _{In x Al y Ga 1-xy} N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) are preferred. In addition to this, an element in which B is partially substituted as a group III element may be used, or an element in which a part of N is substituted with P or As may be used as a group V element. Increasing the In content of the active layer enables light emission in the long wavelength region, and increasing the Al content enables light emission in the ultraviolet region, allowing light emission in the wavelength region of about 300 nm to 650 nm. .

  Depending on the growth substrate to be used, a crystal nucleation layer, a low temperature growth buffer layer, a high temperature growth layer, a mask layer, an intermediate layer, or the like may be arbitrarily formed as a base layer.

One of the first conductivity type layer and the second conductivity type layer means that one is n-type and the other is p-type. The n-type layer contains at least one group IV element or group VI element such as Si, Ge, Sn, S, O, Ti, Zr, and Cd as an n-type impurity. The p-type layer contains Mg, Zn, Be, Mn, Ca, Sr, etc. as p-type impurities.
The impurities are preferably contained in a concentration range of, for example, about 5 × 10 ¹⁶ / cm ³ to 1 × 10 ²¹ / cm ³ . However, all of the semiconductor layers constituting the first and second conductivity type semiconductor layers do not necessarily contain impurities.

For example, the first conductivity type layer, the active layer, and the second conductivity type layer may have a single film structure, a multilayer film structure, or a superlattice structure including two layers having different composition ratios. These layers may include a composition gradient layer and a concentration gradient layer.
The active layer preferably has a quantum well structure such as a single quantum well structure or a multiple quantum well structure.

  The film thickness of the nitride semiconductor layer is not particularly limited. For example, the first conductivity type layer is about 0.2 to 12 μm, the active layer is about 15 to 300 nm, and the second conductivity type layer is 20 to 500 nm. It can be formed with a degree.

  In addition, as shown to Fig.9 (a), you may form the Al content layer 24 in a 1st conductivity type semiconductor layer. This layer can function as an etching stop layer for suitably controlling the film thickness when the resonator length is finally determined by etching the nitride semiconductor layer. Therefore, when the Al-containing layer is made to function as an etching stop layer, the first conductive semiconductor layer on the growth substrate side of the growth substrate or the Al-containing layer does not contain Al or contains Al even more than the Al-containing layer. A low mixed crystal is preferable. The composition and material of the Al-containing layer are not particularly limited, and may be any material that is less likely to be etched by an etchant used for etching or the like than the first conductivity type semiconductor layer. Specifically, an AlGaN layer having an Al composition ratio of about 0.1 to 0.3 can be used. The film thickness of the Al-containing layer is not particularly limited, and for example, about 10 to 50 nm is exemplified, and a plurality of layers may be provided.

(Bragg reflectors 71 and 72)
The Bragg reflector is formed from a dielectric multilayer film. Examples of the dielectric used here include oxides and nitrides such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, and Ti (for example, AlN, AlGaN, GaN, BN, etc.) or fluoride. _{Specifically, SiO 2, Nb 2 O 5} , TiO 2, ZrO 2, Ta 2 O 5, HfO 2 , and the like. Among these dielectrics, a dielectric multilayer film can be obtained by alternately laminating two or more material layers having different refractive indexes. For example, a multilayer film such as SiO ₂ / Nb ₂ O ₅ , SiO ₂ / ZrO ₂ , or SiO ₂ / AlN is preferable.

In order to obtain a desired reflectance, the material, film thickness, number of pairs of multilayer films, and the like can be adjusted as appropriate. The thickness of each layer can be adjusted as appropriate depending on the material used, and is determined by the desired oscillation wavelength (λ) and the refractive index (n) at λ of the material used. Specifically, it is preferably an odd multiple of λ / (4n), and is preferably adjusted as appropriate in consideration of reflectivity and heat dissipation. For example, when an element having an oscillation wavelength of 410 nm is formed of SiO ₂ / Nb ₂ O ₅ , the thickness of each layer is exemplified by about 40 to 70 nm. Repeated lamination is exemplified twice or more, preferably about 5 to 15 times. The film thickness of the dielectric multilayer film is, for example, about 0.6 to 1.7 μm.

  The uppermost layer (the layer farthest from the nitride semiconductor layer) of the first Bragg reflector is preferably made of a material having a low refractive index among the multilayer films constituting the first Bragg reflector. Thereby, the reflectance in the interface with the member formed on a Bragg reflector can be raised.

The first Bragg reflector is not particularly limited in size and shape as long as it covers the element region. Specifically, it can be formed of a circle, ellipse, rectangle or the like having a predetermined size. In the case of a circle, the diameter is preferably about 5 to 70 μm. Further, the size of the first Bragg reflector can be made smaller than that of the support substrate and the nitride semiconductor layer, and heat radiation can be suitably performed by forming a connection electrode described later on the side surface of the first Bragg reflector.
In this specification, the element region means a region sandwiched between opposing Bragg reflectors in a nitride semiconductor layer into which a current is injected, as indicated by M in FIGS.

  The first Bragg reflector and the second Bragg reflector can be formed with the same material, shape, and size. However, the first Bragg reflector and the second Bragg reflector do not necessarily have the same material and the same configuration. In order to obtain a desired reflectance, the material, film thickness, number of pairs of multilayer films, order, and the like can be adjusted as appropriate.

(Supporting substrate 50)
The support substrate is selected in consideration of mechanical properties, elasticity, plasticity, heat dissipation and the like. Specifically, a substrate made of an insulator such as AlN, a substrate made of a semiconductor such as Si, SiC, or Ge, a metal substrate made of a single metal or a composite of two or more metals can be used. Among these, the Si substrate is preferable because it has conductivity, is inexpensive, and can be easily processed. The film thickness of the support substrate is suitably about 50 to 500 μm, for example.

(Embedded layer 40)
In the present invention, since the buried layer is exposed to the polishing process, it is preferably formed of a material having mechanical strength that can withstand the polishing process. In addition, since the grooves provided in the nitride semiconductor layer and the growth substrate are filled, the occurrence of cracks and the like can be suppressed by making the difference in thermal expansion coefficient from the nitride semiconductor layer and the growth substrate small. it can. Furthermore, when covering the vicinity of the active layer, it is preferably formed of an insulating material. Specifically, oxides such as Nb ₂ O ₅ , SiO ₂ , Ga ₂ O ₃ , Al ₂ O ₃ , and ZrO ₂ , nitrides such as SiN, AlN, and AlGaN, diamond-like carbon (DLC), SiC, etc. Can be mentioned. Moreover, it is preferable to form with the material which can function as a stop layer at the time of chemical mechanical polishing (CMP). From this viewpoint, the material is preferably a material that is mechanically and resistant to an alkaline solvent, and is preferably at least less soluble in an alkaline solvent than the nitride semiconductor layer and / or the growth substrate. Considering the above, preferable materials include silicon nitride, niobium oxide, silicon oxide, DLC, SiC, and the like. Also, ProTEK manufactured by Brewer Science can be used as the buried layer.
Further, a buried layer having a multilayer structure may be used. In this case, any one of the buried layers constituting the multilayer structure may function as a CMP stop layer. For example, select an insulating material for the first layer and cover the vicinity of the active layer, and select a material resistant to an alkaline solvent so that the second layer formed thereon functions as a CMP stop layer. It can also be formed. Specifically, such a structure can be realized by using an arbitrary insulating material as described above as the first layer and using Pt, W, or Mo as the second layer.
The buried layer is preferably made of a material having a refractive index smaller than that of the nitride semiconductor from the viewpoint of light confinement, and is preferably made of a material having good thermal conductivity from the viewpoint of heat dissipation.
Further, when the buried layer is formed of an insulating material, it can function as an insulating layer for injecting current into a desired region. However, as shown in FIG. 12, a nitride semiconductor is provided separately from the buried layer. An insulating layer 42 may be provided on the surface of the layer. The nitride semiconductor layer may have a structure in which current is injected into a desired region using a method known in the art such as ion implantation or selective oxidation (thermal oxidation, anodization, etc.). It may be used in combination with a buried layer and / or an insulating layer.

(P-side electrode 91)
As shown in FIG. 1, since the p-side electrode is disposed between the second conductive semiconductor layer and the first Bragg reflector, it is preferable to transmit light having a wavelength generated in the active layer. For example, it can be formed of a single-layer film or a stacked film including at least one element selected from the group consisting of zinc (Zn), indium (In), tin (Sn), and magnesium (Mg). Moreover, it is preferable to form with a conductive oxide, specifically, ZnO, In ₂ O ₃ , SnO ₂ , ATO, ITO, MgO, and the like can be given. Of these, ITO is preferable. The film thickness of the p-side electrode can be appropriately adjusted in consideration of optical loss due to light absorption of the electrode material, electrical resistance, and the like, and for example, about 30 to 100 nm is exemplified.

(N-side electrode 92)
The n-side electrode is made of a material known in the art and includes at least one selected from the group consisting of metals, alloy oxides or nitrides, and transparent conductive oxides such as ITO, ZnO, and In ₂ O _3. It can be formed of a single layer film or a laminated film. Specifically, Ti—Pt—Au, Ti—Al—Au, and the like can be given.

(Connection electrode 93)
The connection electrode is provided to electrically connect the p-side electrode and an adhesive layer described later. The connection electrode is preferably disposed on the side surface of the first Bragg reflector or formed so as to penetrate the first Bragg reflector. However, the connection electrode may be omitted when current can be supplied to the p-side electrode, or another layer may be formed between the p-side electrode and the adhesive layer.

  Further, the thickness of the connection electrode is not particularly limited, but the upper surface of the connection electrode (here, the surface on the support substrate side shown in FIG. 1) is approximately the same height as the upper surface of the first Bragg reflector. It is preferable to form as follows. Thus, the laminate and the support substrate can be firmly bonded, and the support substrate can be prevented from being peeled off during the subsequent steps.

The connection electrode can be selected from materials known in the art in consideration of electric resistance and heat dissipation. For example, it can be formed of a single layer film or a laminated film including at least one selected from the group consisting of transparent conductive oxides such as metals, alloy oxides or nitrides, ITO, ZnO, and In ₂ O _3. . Specifically, Ti—Rh—Au, Ti—Pt—Au, Cr—Rh—Au, Cr—Pt—Au, Ni—Au, Ni—Au—Pt, Pd—Pt, Ni—Pt, and the like can be given. .

(Adhesive layer 60)
The adhesive layer is preferably formed on the entire surface of the first Bragg reflector and the connection electrode in order to securely bond the support substrate and the nitride semiconductor wafer. The adhesive layer can be formed using a material similar to that of the connection electrode described above. Specifically, (Ti / Si) -Pt-Pd, Ti-Pt-Au- (Au / Sn), Ti-Pt-Au- (Au / Si), Ti-Pt-Au- (Au / Ge) Ti—Pt—Au—In, Au—Sn, In, Au—Si, Au—Ge, Al—Rh—Au— (Au / Sn), and the like. In order to prevent cracking and peeling of the nitride semiconductor layer, it is preferable to form the same on the surface of the support substrate. However, the nitride semiconductor layer may be formed only on either the nitride semiconductor wafer or the support substrate, and the other may be omitted. Good.

Hereinafter, a method of manufacturing the vertical cavity surface emitting laser according to this embodiment will be described with reference to FIGS. 1 to 4 and 9 to 11.
First, as described above, the stacking step (FIG. 2A) and the groove forming step (FIG. 2B) are performed.
When the Al-containing layer 24 described above is included in the first conductivity type semiconductor layer, the bottom surface of the groove is preferably formed on the growth substrate side in the Al-containing layer or in the Al-containing layer 24. . When the bottom surface of the groove portion is provided in the Al-containing layer, the depth of the groove portion can be controlled with high accuracy in the groove portion forming step, which is preferable. Also, as shown in FIG. 9B, when the bottom surface of the groove 30 is formed on the growth substrate side with respect to the Al-containing layer 24, the resonator length is adjusted again in an etching process to be described later to make the length more accurate. This is preferable.
Two or more Al-containing layers may be formed. For example, when the first Al-containing layer and the second Al-containing layer are formed in order from the growth substrate side, they are preferably formed so as to be separated from each other, and in the groove portion forming step, the process is preferably performed until the bottom surface of the groove portion reaches the first Al-containing layer. . As a result, the depth of the groove can be controlled with high accuracy, and the depth of the groove can be formed uniformly within the wafer surface. At this time, the thickness of the second Al-containing layer is preferably thicker than that of the first Al-containing layer. This makes it easy to adjust the resonator length again in an etching process described later. In addition, the Al mixed crystal ratio of the first Al-containing layer is smaller than that of the second Al-containing layer, and the film thickness is preferably thin.
Shortening the resonator length can reduce optical loss and improve longitudinal mode stability, but resistance and heat generation increase from the viewpoint of current injection. It is preferable to adjust. Specifically, the resonator length is suitably about 0.3 to 5.0 μm.

Subsequently, as shown in FIG. 2C, an embedding process is performed.
After the embedding process, electrodes and the like are formed and the support substrate 50 is bonded as shown in FIG.
First, in order to inject a current into a desired region, an insulating layer is preferably formed on the surface of the nitride semiconductor layer (see 42 in FIG. 12). The insulating layer is preferably formed in a region facing an n-side electrode provided later.
Subsequently, it is preferable to form the p-side electrode 91. The p-side electrode is formed so as to be in contact with a part or the entire surface of the second conductivity type layer. Further, in the formed part, as shown in FIG. 2D, it may be disposed on the previously formed buried layer 40.

  Subsequently, the connection electrode 93 is preferably formed on the p-side electrode. The connection electrode is preferably provided so as to be in contact with the p-side electrode formed on the buried layer. When the connection electrode is disposed in a region (element region) where the p-side electrode is in contact with the second conductivity type semiconductor layer, a current flows only directly below the connection electrode, and the current hardly spreads over the entire element region. This can be prevented.

Subsequently, it is preferable to form the first Bragg reflector 71 in the element region. The formation region is not particularly limited, and it is preferable that the p-side electrode and the connection electrode ensure an appropriate contact area and be adjusted to a position where current can be supplied uniformly to the element region. For example, as shown in FIG. 1, the first Bragg reflector is disposed near (above) the portion where the second conductivity type semiconductor layer and the p-side electrode are in direct contact, and the connection electrode is disposed so as to surround the periphery thereof. Furthermore, the form which forms the Bragg reflector 71b in the outer periphery is illustrated. As shown in FIG. 2D, when the connection electrode 93 penetrates the first Bragg reflector, the penetration position is not particularly limited. However, as described above, the connection electrode is disposed outside the element region. As a result, the current can be easily spread over the entire element region.
The dielectric multilayer film constituting the first Bragg reflector can be formed by a method known in the art. For example, evaporation method, sputtering method, reactive sputtering method, ECR plasma sputtering method, magnetron sputtering method, ion beam assisted evaporation method, ion plating method, laser ablation method, CVD method, spray method, spin coating method, dip method or A method of combining two or more of these methods, or these methods and whole or partial pretreatment, irradiation of inert gas (Ar, He, Xe, etc.) or plasma, irradiation of oxygen or ozone gas or plasma, oxidation Various methods such as a method of combining one or more of treatment (heat treatment) and exposure treatment can be used. Note that in the combination method, the film formation and / or treatment may not necessarily be performed simultaneously or continuously, and the treatment may be performed after the film formation, or vice versa.

Thereafter, an adhesive layer 60 is formed on the obtained wafer. As described above, the uppermost layer of the first Bragg reflector is made of a low refractive index material among the multilayer films constituting the first Bragg reflector, so that the reflectance at the interface with the adhesive layer can be increased. it can.
Subsequently, the obtained wafer is bonded to the support substrate 50. At this time, the adhesive layer 60 may also be formed on the support substrate.
As a joining method, a method usually used in the field such as a method of joining by joining the joining surfaces and holding them under a predetermined temperature and pressure can be used. Specific examples include a thermocompression bonding method and a direct bonding method.

Subsequently, as described above, the removing step including the first step and the second step is performed (FIGS. 3E to 3G).
When removal of the growth substrate is started, a distribution occurs in the thickness of the growth substrate 10 as shown in FIG. In the case of FIG. 3, the wafer is preferentially polished from the outer peripheral portion of the wafer, and the film thickness of the growth substrate is increased in the vicinity of the central portion. Further, polishing is performed to expose the nitride semiconductor layer 20, and the first step is performed so that the bottom surface of a part of the buried layer is exposed as shown in FIG. Then, the polishing is advanced, and as shown in FIG. 3G, the second step is performed so that the bottom surface of the buried layer different from the bottom surface of the buried layer exposed in the first step is exposed. At this time, in the vicinity of the exposed buried layer and the nitride semiconductor layer sandwiched between the buried layers, the nitride semiconductor layer is not polished any more and the film thickness is maintained. When the polishing is proceeded as it is, the polishing is proceeded in the region where the nitride semiconductor layer remains as in the central portion of the wafer in FIG. Polishing is appropriately performed until the bottom surface of the buried layer in a desired region is exposed, or until a wafer having a uniform thickness reaches a desired area, and the removal step is completed.
In the present embodiment, the surface of the nitride semiconductor layer exposed in this removal step can be used as the cavity surface of the vertical cavity surface emitting laser, and in this case, the processed surface is required to be flat. It is done. In addition, a vertical cavity surface emitting laser has a shorter cavity length than an edge emitting laser element. Therefore, in order to oscillate the vertical cavity surface emitting laser efficiently, it is required to form the cavity length with an accurate thickness, that is, to process it to an accurate thickness.

<Etching process>
As described above, when the first conductivity type semiconductor layer has the Al-containing layer 24, an etching process is performed after the polishing process, thereby forming a flatter resonator surface and more accurate resonator length. can do.
According to the manufacturing method of the present invention, the resonator length can be approximately the same as the depth of the groove 30 formed in the groove forming step, but depending on the polishing conditions and the area of the nitride semiconductor layer to be polished, 10 (f) and 10 (g), the nitride semiconductor layer may form a recess called dishing. The larger the area of the nitride semiconductor layer exposed in the removal step, the easier it is to process, while the larger the area, the easier dishing occurs. In addition, when the hardness of the polishing cloth at the time of CMP processing is increased, dishing of the nitride semiconductor can be suppressed, while film thickness distribution in the wafer surface is likely to occur. Therefore, even if dishing occurs in the polishing process, the dishing portion is removed by the etching process, a flat resonator surface is formed, a more accurate resonator length can be obtained, and vertical resonance that can oscillate efficiently A surface-emitting laser can be provided. Specifically, as shown in FIG. 9B, the groove 30 is formed deeper than the Al-containing layer 24 in the groove forming process. As shown in FIG. 10H, when the growth substrate 10 and the first conductivity type semiconductor layer closer to the growth substrate than the Al-containing layer 24 contain lower mixed crystal Al or no Al than the Al-containing layer. In addition, the nitride semiconductor layer is etched until the Al-containing layer is exposed after the polishing step.

As the etching at this time, dry etching or wet etching can be selected. For example, wet etching is performed by exposing the nitride semiconductor layer to an etchant by immersing the nitride semiconductor layer in an alkaline solution such as potassium hydroxide or sodium hydroxide, or an acidic solution such as phosphoric acid, sulfuric acid, or aqua regia for a predetermined time. It can be carried out.
The dry etching can be performed using, for example, reactive ion etching (RIE), reactive ion beam etching (RIBE), electron cyclotron resonance (ECR) etching, ion beam etching, or the like. In any case, an etching gas (for example, a fluorine gas such as CF ₄ , a chlorine gas such as Cl ₂ , CCl ₄ , or SiCl ₄ , or an iodine gas such as HI alone or a mixed gas) may be appropriately selected. When performing dry etching, the etching conditions including the type of etching gas (gas flow rate, RF power, pressure, temperature, etching time, etc.) can be determined by appropriately adjusting.

Preferably, RIE using a mask is preferable. That is, a predetermined mask pattern selected from a circle, an ellipse, a rectangle, and the like is formed in the element region, and etching is performed using this mask pattern as a mask. The mask pattern can be formed by patterning a resist, an insulator such as SiO ₂ or the like into an appropriate shape by a known method such as photolithography and an etching process.

Subsequently, as shown in FIG. 3H, an electrode or the like is formed on the exposed polished surface.
First, it is preferable to form the n-side electrode 92. The n-side electrode may be formed at any position and contact area as long as it can supply current to the nitride semiconductor layer, and can be appropriately adjusted depending on the material used, the size of the element, and the like. For example, a configuration in which the second conductive semiconductor layer and the p-side electrode are arranged in an annular shape so as to surround a region facing the portion in direct contact is preferable. In addition, an n-side electrode is disposed on the surface of the first conductive type semiconductor layer on the surface of the first conductive type semiconductor layer in a longitudinal sectional view with respect to a region where the p-side electrode and the second conductive type semiconductor layer are in contact with each other. May be. When arranged diagonally, the current can be spread in the lateral direction, so that the current that can be supplied to the element region is increased and a highly efficient light-emitting element can be obtained.

  Subsequently, a second Bragg reflector 72 is formed in the element region. The order of forming the n-side electrode and the second Bragg reflector is not limited. The second Bragg reflector can be formed in the same manner as the first Bragg reflector described above. It is not always necessary to select the same method, and it can be formed by appropriately selecting from the methods described above. The second Bragg reflector may be formed so as to cover a part of the n-side electrode.

  A transparent electrode may be formed between the first conductivity type semiconductor layer and the second Bragg reflector before forming the second Bragg reflector. The transparent electrode is provided so as to be electrically connected to the n-side electrode, and can also be formed on the buried layer exposed in the removing step. Thereby, the current distribution in the first conductive type semiconductor layer can be improved. The transparent electrode can be formed in the same manner using the same material as the p-side electrode. However, the p-side electrode and the transparent electrode do not necessarily have the same material, the same configuration, and shape.

Finally, as shown in FIG. 3H, an adhesive member 94 is formed on the back surface of the support substrate of the obtained element, and then the wafer obtained as shown in FIG. 4I is separated into an element state. Examples of the adhesive member include those formed of TiSi ₂ / Pt / Au from the support substrate side. For dividing the wafer, methods known in the art such as a dicer, a scriber, and etching can be used. Grooves may be formed between the elements by these methods, and divided by pressing along the groove with a breaker or the like.
Further, a laser device can be obtained by mounting the obtained element on various packages formed of metal, resin, or the like.

  According to the above manufacturing method, in the vertical cavity surface emitting laser in which the growth substrate is removed to form the Bragg reflector, the cavity length can be controlled with high accuracy. In addition, since the in-plane distribution in the wafer surface can be suppressed, even in a vertical cavity surface emitting laser in which the deviation of the resonator length directly affects the element characteristics, the number of wafers taken from one wafer can be increased. A high-quality vertical cavity surface emitting laser can be manufactured stably and efficiently.

[Embodiment 2]
As shown in FIG. 5, the nitride semiconductor light emitting device obtained by the manufacturing method of the present invention includes a p-side electrode 91, a nitride semiconductor layer 20, and an n-side electrode formed on a support substrate 50 through an adhesive layer 60. The nitride semiconductor layer has a p-type semiconductor layer, an active layer, and an n-type semiconductor layer stacked in that order from the support substrate side. A buried layer 40 is formed on the side surface of the nitride semiconductor layer. About the member common to Embodiment 1, it is possible to use similarly.
A method for manufacturing the nitride semiconductor light emitting device of this embodiment will be described with reference to FIGS. Description of the steps performed in the same manner as in Embodiment 1 is omitted.
First, as described above, the stacking step (FIG. 6A) and the groove forming step are performed (FIG. 6B).
Subsequently, as shown in FIG. 6C, a p-side electrode 91 is formed on the surface of the nitride semiconductor layer. As the p-side electrode, a light-transmitting p-side electrode as described above may be combined with a multilayer film such as SiO ₂ / Nb ₂ O ₅ , SiO ₂ / ZrO ₂ , or SiO ₂ / AlN. It is good also as a reflective electrode which consists of Ag, Al, Rh, etc., and may combine both.
Subsequently, as shown in FIG. 6D, an embedding process is performed. At this time, the upper surface of the buried layer 40 is formed so as to be the same height as the surface of the p-side electrode 91 previously formed.
After that, an adhesive layer 60 is formed on the obtained wafer and the support substrate 50, and the wafer is bonded to the support substrate (FIG. 7E), and the removal step including the first step and the second step is performed as in the first embodiment. (FIGS. 7 (f) to (g)). Thereafter, an n-side electrode 92 is formed on the surface of the nitride semiconductor layer and an adhesive member 94 is formed on the back surface of the support substrate, and then the obtained wafer is divided to obtain a light emitting device as shown in FIG.
Since the nitride semiconductor light emitting device is expected to be downsized and improve the light extraction efficiency by adopting a counter electrode structure, a method for manufacturing a nitride semiconductor light emitting device using the support substrate as described above has been proposed. . However, in a silicon substrate or a nitride semiconductor substrate, the in-plane distribution at the time of polishing processing is remarkably easy to cause variations in element characteristics. In particular, when a silicon substrate is used, the silicon substrate may remain partially even if polishing is stopped at a desired position. Since silicon absorbs light having a wavelength emitted by the nitride semiconductor, the output of the element on which the silicon substrate remains is inferior. In other words, even if the elements are obtained from the same wafer, the output is distributed. However, by forming the buried layer and performing the removal process in two steps as in the present invention, the bottom surface of the buried layer is reduced. It is held on the exposed surface and is not polished further, and the wafer thickness can be maintained. Thus, polishing can be stopped at a desired position, the final film thickness distribution can be eliminated even within the wafer surface, and a large number of regions having the desired thickness can be secured within the wafer surface. In addition, when a silicon substrate is used, a step of doping impurities into the substrate is required. However, in this embodiment, since the growth substrate is removed, a light emitting element can be obtained without providing a step of doping impurities.

Example 1
In this example, a method for manufacturing a vertical cavity surface emitting laser according to Embodiment 1 as shown in FIG. 1 will be described with reference to FIGS.
First, as shown in FIG. 2A, a nitride semiconductor substrate 10 having a diameter of 2 inches and a dislocation density of 1 × 10 ⁶ cm ² is prepared as a growth substrate. On the C surface of the nitride semiconductor substrate 10, Si-doped GaN is grown as an n-side semiconductor layer with a film thickness of 2 μm. Next, a barrier layer made of Si-doped In _0.02 Ga _0.98 N is grown to a thickness of 13 nm, and a well layer made of undoped In _0.10 Ga _0.90 N is grown to a thickness of 9 nm. A barrier layer and a well layer are alternately stacked twice, and finally an active layer having a multi-quantum well structure (MQW) with a total thickness of 57 nm is grown with a 13 nm barrier layer made of undoped In _0.02 Ga _0.98 N. Let Next, a p-type Al _0.33 Ga _0.67 N layer doped with Mg is grown to a thickness of 7.5 nm as a p-side semiconductor layer, and a contact layer made of p-type GaN doped with Mg is grown to a thickness of 63 nm. Let
The wafer 15 obtained by forming the nitride semiconductor layer 20 as described above is taken out of the reaction vessel, and as shown in FIG. 2B, a groove 30 for defining the resonator length and the element region is formed. After forming the SiO ₂ film on substantially the entire surface of the wafer surface, SiO ₂ is formed in a circular mask pattern diameter 15μm by photolithography and etching, it as a mask, the nitride semiconductor layer by chlorine-based gas using RIE 20 is etched by 1 μm to form a groove 30 having the n-side semiconductor layer as a bottom surface.
As shown in FIG. 2C, a buried layer 40 made of SiN is formed to 1 μm in the formed groove 30.
As shown in FIG. 2D, an insulating layer made of SiO ₂ (not shown, see 42 in FIG. 12) is formed on the obtained wafer, and a circular opening having a diameter of 8 μm is formed on the p-type semiconductor layer. Pattern into shape. A p-side electrode 91 made of ITO is formed with a film thickness of 50 nm on the insulating layer made of SiO _2, and heat treatment is performed to obtain ohmic contact. A connection electrode 93 made of Ti / Rh / Au is formed to a thickness of 1.3 μm, and a region (element region) in which the p-type semiconductor layer and the p-side electrode are in direct contact is opened by a lift-off process. A first Bragg reflector 71 having a diameter of 25 μm is formed on the opening of the connection electrode, which is the element region, and the buried layer. In the first Bragg reflector 71, 12 pairs of Nb ₂ O ₅ (film thickness: 40 nm) and SiO ₂ (film thickness: 70 nm) are stacked from the nitride semiconductor layer side, and the first dielectric layer (Nb ₂ O ₅ ) is formed with a film thickness of 20 nm. On the first Bragg reflector 71 and the connection electrode 93, the adhesive layer 60 made of Ti / Pt / Au / Sn / Au (film thickness: 100 nm / 300 nm / 300 nm / 3000 nm / 100 nm) in this order from the nitride semiconductor layer side. Form.
An adhesive layer 60 made of TiSi ₂ / Pt / Pd (film thickness: 3 nm / 250 nm / 350 nm) is formed on the surface of the silicon substrate to be the support substrate 50, and the adhesive layer on the silicon substrate and the adhesive layer on the wafer side are pasted Match.
As shown in FIG. 3E, grinding and polishing are performed. At this time, the maximum film thickness difference in the wafer is about 6 μm.
Subsequently, as shown in FIG. 3F, CMP is performed using a slurry containing KOH so as to expose the bottom surface of the buried layer 40 on the outer peripheral portion of the wafer. Subsequently, CMP is performed to expose the bottom surface of the buried layer 40 at the center of the wafer, as shown in FIG.
As shown in FIG. 3H, an n-side electrode 92 is formed on the n-type semiconductor layer in a shape having a circular opening having a diameter of 10 μm with the element region as the center. A second Bragg reflector 72 is formed in a circular shape with a diameter of 20 μm in the opening of the n-side electrode. In the second Bragg reflector, 7 pairs of SiO ₂ (film thickness: 70 nm) and Nb ₂ O ₅ (film thickness: 40 nm) are laminated from the support substrate 50 side.
Finally, as shown in FIG. 4I, the wafer is separated into chips by dicing to obtain a vertical cavity surface emitting laser.
In the vertical cavity surface emitting laser manufactured by such a method, the cavity length is adjusted by performing CMP until the buried layer formed in the groove is exposed. Control becomes possible and a highly efficient vertical cavity surface emitting laser can be obtained.

(Example 2)
As shown in FIGS. 8 to 11, the vertical cavity surface emitting laser according to the present example has an Al-containing layer 24 as an etching stop layer in the first conductivity type semiconductor layer. Except for this configuration, the second embodiment is substantially the same as the first embodiment.
Specifically, as shown in FIG. 9A, after the first conductive type semiconductor layer is formed to have a thickness of 1.5 μm, an Al-containing layer 24 made of Al _0.2 Ga _0.8 N is formed to a thickness of 50 nm. Thereafter, a first conductive semiconductor layer having a thickness of 0.5 μm is formed. The active layer and the second conductivity type semiconductor layer are formed in the same manner as in Example 1.
As shown in FIG. 9B, in the groove forming step, the nitride semiconductor layer 20 is etched by 1 μm to form a groove 30 having the bottom surface of the nitride semiconductor layer 20 on the growth substrate side relative to the Al-containing layer 24.
Thereafter, similarly to Example 1, a buried layer 40 is formed (FIG. 9C), a p-side electrode and the like are formed (FIG. 9D), and a polishing step is performed (FIG. 10E). ~ (G)). The polishing step is performed in the same manner except that a soft polishing cloth is used as compared with Example 1. At the end of the polishing process, dishing is formed as shown in FIG.
Subsequently, as shown in FIG. 10H, a mask pattern is formed with a resist in a region other than the device region, and the nitride semiconductor layer 20 in the device region is etched until the Al-containing layer is exposed.
Thereafter, in the same manner as in Example 1, an n-side electrode or the like is formed (FIG. 11 (i)), and a chip is formed (FIG. 11 (j)).
In the present embodiment, the resonator length can be controlled more accurately by performing the etching process after the polishing process of the first embodiment. As a result, a highly efficient vertical cavity surface emitting laser can be obtained, and improvement in device characteristics is expected.

(Example 3)
The vertical cavity surface emitting laser according to this example is substantially the same as Example 2 except that a plurality of Al-containing layers functioning as etching stop layers are provided in the first conductivity type semiconductor layer.
Specifically, after the first conductive semiconductor layer is formed to 1.5 μm, a first Al-containing layer made of Al _0.2 Ga _0.8 N is formed to 20 nm. Thereafter, a 1 μm first conductive semiconductor layer is formed, a second Al-containing layer made of Al _0.2 Ga _0.8 N is formed to 30 nm, and a 1 μm first conductive semiconductor layer is formed. The active layer and the second conductivity type semiconductor layer are formed in the same manner as in Example 2.
In the groove forming step, the nitride semiconductor layer 20 is etched to form a groove having the first Al-containing layer as a bottom surface.
Thereafter, as in Example 2, the polishing process is performed. At the end of the polishing process, dishing is formed as shown in FIG.
Subsequently, a mask pattern is formed with a resist in a region other than the device region, and the nitride semiconductor layer in the device region is etched until the second Al-containing layer is exposed.
Thereafter, in the same manner as in Example 2, an n-side electrode or the like is formed to form a chip.
In the present embodiment, as compared with the second embodiment, the in-plane distribution in the groove forming process is suppressed, and the resonator length can be controlled with higher accuracy.

Example 4
The vertical cavity surface emitting laser according to this example is substantially the same as Example 1 except that the buried layer 40 is formed of niobium oxide, and is manufactured substantially as in Example 1. Can do.
In the present embodiment, the same effect as in the first embodiment can be obtained.

(Example 5)
The vertical cavity surface emitting laser according to this example is substantially the same as that of Example 1 except that the buried layer 40 is formed of a laminated structure made of SiO ₂ / Ti / Pt.
0.5 μm of SiO ₂ is formed on the side and bottom surfaces of the formed groove 30. Subsequently, 0.1 μm of Ti and 0.5 μm of Pt are formed.
In the removing step, CMP is performed with a slurry using KOH, and SiO ₂ is exposed in a part of the wafer surface. Subsequently, CMP is performed under the same conditions to polish the nitride semiconductor layer in other regions to expose the SiO ₂ , and in the previously exposed regions, the SiO ₂ and Ti are polished to expose the Pt layer. The
Except this, it can be manufactured in substantially the same manner as in Example 1.
In this embodiment, the buried layer of the insulating material can be made thinner as compared with the first embodiment, damage to the nitride semiconductor layer can be reduced, and Vf can be reduced.

(Example 6)
In this example, a method for manufacturing the nitride semiconductor light emitting device according to the second embodiment as shown in FIG. 5 will be described with reference to FIGS.
Using the silicon substrate 10, a nitride semiconductor layer 20 was grown in the same manner as in Example 1 except that the film thickness of the first conductivity type semiconductor layer was changed to 5 μm (FIG. 6A). A groove 30 having a depth of 4 μm is formed (FIG. 6B).
Subsequently, as shown in FIG. 6C, in the element region on the p-type semiconductor layer, ITO is formed as a p-side electrode 91 by 0.05 μm, SiO ₂ (film thickness: 5000 mm), and Nb ₂ O ₅ (film) Three pairs of thickness: 483 Å) / SiO ₂ (film thickness: 845 ３) are formed.
As shown in FIG. 6D, a buried layer 40 made of SiN is formed in a thickness of 4 μm in the groove. At this time, the upper surface of the buried layer is formed to be the same height as the surface of the p-side electrode 91 formed earlier. Subsequently, an adhesive layer 60 is formed and bonded to the wafer obtained in the same manner as in Example 1 (FIG. 7E).
The silicon substrate 10 is ground and polished so that the thinnest portion of the wafer is about 5 μm from the bottom surface of the buried layer 40 (FIG. 7F). At this time, a film thickness distribution occurs in the wafer surface. Subsequently, CMP is performed using a slurry containing TMAH so as to expose the bottom surface of the buried layer 40. Subsequently, CMP is performed to expose the bottom surface of the desired buried layer 40 (FIG. 7G).
An n-side electrode 92 is formed (FIG. 7H), and dicing is performed on the buried layer 40 to separate it into chips to obtain a nitride semiconductor light emitting device as shown in FIG.
The nitride semiconductor light emitting device manufactured by such a method can stop polishing at a desired position, can suppress the distribution of the film thickness within the wafer surface, and can provide a region of the desired thickness within the wafer surface. It is possible to secure a large number of chips and increase the number of chips collected from one wafer.

DESCRIPTION OF SYMBOLS 10: Growth substrate 15: Wafer 20: Nitride semiconductor layer 21: 1st conductivity type semiconductor layer 22: Active layer 23: 2nd conductivity type semiconductor layer 24: Al content layer 30: Groove part 40: Buried layer 50: Support substrate 60: Adhesive layer 71: First Bragg reflector 72: Second Bragg reflector 91: p-side electrode 92: n-side electrode 93: connection electrode 94: adhesive member

Claims (11)

To growth substrate to form a nitride semiconductor layer wafer, then partially removed in a thickness direction from the nitride semiconductor layer side, a groove forming step of forming a plurality of grooves,
Forming buried layers in the plurality of grooves,
Removing a portion of the growth substrate side of the wafer to expose the bottom surface of a portion of the buried layer, the bottom surface of the other portion of the buried layer covered by the growth substrate or the nitride semiconductor layer a first step of the state, and a second step of exposing the bottom that was covered by the first step, a removal step consisting of,
Dividing the wafer after the removing step to obtain a nitride semiconductor element;
A method for manufacturing a nitride semiconductor device comprising:   The method for manufacturing a nitride semiconductor device according to claim 1, wherein the removing step is performed by chemical mechanical polishing.   3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the removing step is performed using an alkaline solvent, and the buried layer is formed of a material that is less soluble in an alkaline solvent than the nitride semiconductor layer. .   The method for manufacturing a nitride semiconductor device according to claim 3, wherein the buried layer is formed of a material including any one of silicon nitride, niobium oxide, and silicon oxide.   5. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 4, wherein, in the first step, polishing is performed so that a thickness at an outer peripheral portion of the wafer is thinner than a thickness at a central portion.   The nitride semiconductor device manufacturing method according to claim 5, wherein in the second step, polishing is performed so that a difference in film thickness between the central portion and the outer peripheral portion of the wafer is reduced while maintaining the thickness at the outer peripheral portion of the wafer. Method. The nitride semiconductor layer is formed by laminating a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer in this order on the growth substrate. In the groove forming step, the nitride semiconductor layer is formed on the bottom surface of the groove. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the nitride semiconductor layer is removed so that the first conductivity type semiconductor layer is exposed.   The method for manufacturing a nitride semiconductor device according to claim 1, further comprising an etching step of removing a surface exposed in the removing step after the removing step. The nitride semiconductor layer is formed by laminating a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer in this order on the growth substrate, and the first conductive type semiconductor layer is an Al-containing layer. The first conductive type semiconductor layer on the growth substrate side of the growth substrate and the Al-containing layer contains lower mixed crystal Al than the Al-containing layer or does not contain Al, and in the groove forming step, The method for manufacturing a nitride semiconductor device according to claim 8, wherein a groove is formed deeper than the Al-containing layer, and the Al-containing layer is exposed in the etching step. The nitride semiconductor device, nitride according to claim 1 to 9 is a vertical cavity surface emitting laser that the surface side and the nitride semiconductor layer of the growth substrate has been removed side and the resonator surfaces A method for manufacturing a semiconductor device.   The method for manufacturing a nitride semiconductor device according to claim 1, wherein the growth substrate is made of a nitride semiconductor or silicon.

Images