JP5324056B2 - Solid-state imaging device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly multiply a signal charge caused by feeble incident light in a pixel even in a low drive voltage which is equal to a power voltage used for a usual CMOS image sensor, and to obtain a superior S/N ratio compared to that in a conventional device. <P>SOLUTION: In a solid-state image pickup element 1, a PD impurity region 33, a charge multiplication region 35 and an output impurity region 37 are arranged in parallel on the lower side of a gate oxide film 39 along the lower face thereof, and a multiplication gate electrode 41 and a transfer gate electrode 43 are arranged in parallel on the upper side of the gate oxide film 39 along the upper face thereof. In particular, the charge multiplication region 35 is formed immediately below the multiplication gate electrode 41 across the gate oxide film 39. Namely, a structure (multiplication structure 45) with which the multiplication gate electrode 41 and the charge multiplication region 35 are closely confronted is disposed adjacently to the PD impurity region 33 and the transfer gate electrode 43 between the PD impurity region 33 and the transfer gate electrode 43. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a solid-state imaging device capable of amplifying current generated by incident light by utilizing an avalanche multiplication phenomenon in a pixel (solid-state imaging device) and improving sensitivity and S / N, and a driving method thereof.

In a solid-state imaging device typified by a CCD or a CMOS image sensor, the area of a photodiode (PD), which is a light receiving area, decreases as the number of pixels increases, and sensitivity decreases.
Therefore, in the conventional solid-state imaging device, sensitivity reduction has been compensated by methods such as improving the efficiency of the microlens formed in the pixel, improving the efficiency of the output amplifier arranged at the end of the CCD, and the efficiency of the intra-pixel amplifier in the CMOS.

  However, when shooting in an environment where the illumination light is weak, the noise generated in the pixel is larger than the incident light compared to the light incident on the pixel, so the conventional method alone amplifies the noise. There arises a problem that the optical signal cannot be identified.

  In order to solve such a problem, in the conventional solid-state imaging device, dark current caused by surface defects is reduced by embedding impurities having a polarity different from that of the impurities forming PD in the surface of the PD, or the defect density of the Si substrate. The method of improving has been taken.

  However, in an environment where the illuminance is only 0.1 lx or less, such as at night when there is no illumination, an image that can withstand practical use cannot be obtained. As a cause of this, in such a conventional technique, since the quantum efficiency for converting incident light into electric charge is theoretically 1 or less, there is a principle background that S / N deteriorates due to generation of slight noise. .

  On the other hand, in recent years, as an imaging tube for high-vision photography, an amorphous selenium (a-Se) thin film is formed, and a high voltage such as 1500 V to 3500 V is applied to the HARP imaging tube to multiply the charge. It is known (refer to NHK Giken R & D No. 78 (2003) etc.). Further, a technique has been proposed in which an a-Se thin film is formed on a solid-state imaging device to obtain high sensitivity (see NHK Giken R & D No. 67 (2001)).

  However, in this method, in order to realize charge multiplication, a material different from silicon (Si) suitable for manufacturing an inexpensive solid-state imaging device must be laminated as a thin film, and only conventional Si is used. There is a problem that it is more expensive than a solid-state imaging device manufactured in this way. In addition, according to this method, a voltage of about 60 V must be applied to the solid-state imaging device, and a power source that is higher than a power source voltage that normally uses the solid-state imaging device is required, resulting in an increase in power consumption. There is.

  On the other hand, the following a) to d) are representative methods for increasing the sensitivity by multiplying the charge with respect to incident light by using a conventional solid-state imaging device that is inexpensive and has a proven track record as a basic configuration. There is.

  a) Hatori devised a method of multiplying charges by generating a high electric field when transferring charges from a CCD terminal portion to a floating diffusion, which is a charge readout region, using a CCD as a basic configuration (Patent Document 1). reference).

  However, according to this method, the multiplication of the charge is limited to one time of reading the charge to the floating diffusion, so that the multiplication factor is also limited to a constant value. In order to generate a high electric field, it is necessary to apply a voltage of 15 V or higher, which is higher than a power supply voltage for driving a normal CMOS image sensor.

  b) A p-type and n-type impurity layer is stacked directly under the PD, an NPN structure or a PNPN is formed by controlling the concentration peak interval between the impurity diffusion regions, a reverse bias is applied, and a high electric field is applied. A method of multiplying the charge by generating it was devised (see Patent Document 2).

However, even in this method, it is necessary to apply a voltage of about 40 V, which is higher than the driving voltage of a normal CMOS image sensor, in order to generate a high electric field.
c) Hynesem proposed a method of performing charge multiplication in a horizontal transfer CCD stage using a CCD as a basic configuration (see Patent Document 3).

  According to this method, the charge multiplication factor can be arbitrarily set according to the number of stages of the horizontal transfer CCD or according to the number of horizontal transfers. FIG. 26 shows a cross-sectional view of a horizontal transfer CCD portion by this method. Here, charge multiplication is performed by applying a voltage that generates a high electric field between the CCD transfer gates (P1).

  However, since this method is based on a CCD, the driving voltage is as high as about 12 to 20 V, and the power consumption is higher than that of a normal CMOS image sensor. Further, since the charge multiplication operation is performed only after passing through the vertical transfer CCD from the pixel, there is a problem that noise superimposed on the charge signal between these paths is multiplied together at the time of charge multiplication.

d) Hynecek has proposed a pixel structure that can be applied to a CMOS image sensor separately from the above-mentioned patent document (see Patent Document 4).
In this pixel structure, a high electric field is generated by alternately applying a voltage to electrodes provided adjacent to each other in the pixel, thereby multiplying the charge. This principle can be regarded as a method in which charge multiplication by the horizontal transfer CCD of the above-mentioned patent document is built in a pixel. Therefore, as in the above patent documents, the drive voltage required for charge multiplication is about 22V, which is higher than the power supply voltage of a normal CMOS image sensor. As a result, the same problem as in each of the above patent documents occurs.
JP-A-5-211180 JP-A-5-335549 JP-A-7-176721 JP 2001-127277 A

  The present invention has a problem common to the above-described conventional techniques, that is, a drive voltage required for charge multiplication is higher than a voltage normally used for a power supply voltage of a CMOS image sensor, and power consumption is also increased. It was made in view of this.

  That is, the present invention suitably multiplies the signal charge generated by weak incident light in the pixel even at a driving voltage as low as the power supply voltage used in a normal CMOS image sensor, and is superior to the conventional S. The purpose is to realize / N.

First, the principle of the present invention made to solve the above problems will be described.
Here, a typical MOS (Metal Oxide Semiconductor) structure is assumed as a structure using the vicinity of the surface of the Si substrate, and a mechanism in which avalanche charge multiplication occurs due to an electric field generated inside the depletion layer will be described.

A cross-sectional view of the MOS structure is shown in FIG. In FIG. 1, the Si substrate is p-type and the impurity (acceptor) concentration is NA. When a sufficiently large positive voltage is applied to the gate electrode (Poly Si electrode) to form a strong inversion state, a depletion layer spreads from the insulating film SiO ₂ toward the Si substrate, and near the interface between the SiO ₂ and the Si substrate In this case, an inversion layer in which electrons are accumulated (inversion layer in a strong inversion state) is generated.

Next, let us consider the transient state up to the inversion state of FIG. 1 in the MOS structure. When a sufficiently large voltage for applying an inversion state is applied to the Poly Si electrode, electrons move from the Si substrate side to the SiO ₂ side, and a depletion layer is generated first. At this time, if a single electron is externally injected into the depletion layer while a sufficiently large electric field is applied to the depletion layer, the electrons traveling in the depletion layer collide with the crystal lattice and cause electrons and holes to flow. The generated “impact ionization” occurs. Since the charge is apparently increased by impact ionization, it can be considered that “charge multiplication” occurred avalanche. That is, electric charges (electrons in this case) injected into the depletion layer cause avalanche charge multiplication by impact ionization. The electrons and holes generated by the charge multiplication further cause charge multiplication while moving in opposite directions.

In general, charge multiplication is said to occur when the electric field strength becomes stronger than about 2 × 10 ⁵ [V / cm]. This phenomenon should occur in the time until the inversion state, which is a steady state. Further, when the applied electric field strength is further increased beyond the condition for causing avalanche charge multiplication, the depletion layer becomes thin and the tunnel current becomes dominant. In this case, avalanche charge multiplication no longer occurs.

The transient state in which one electron is injected into the depletion layer of the MOS structure has been considered above. However, it is assumed that this MOS structure is provided in the pixel of the image sensor (solid-state imaging device).
Considering that light is applied to a photodiode (PD) to generate electrons and the electrons injected from the PD into the MOS structure are multiplied as described above, avalanche charge multiplication is a charge injected into the depletion layer. Since the number of charges to be multiplied varies depending on the number of light, it is suitable for weak light multiplication. On the other hand, the tunnel current cannot directly multiply the weak light because the injected charge directly penetrates the depletion layer. The breakdown due to the tunnel current is generally considered to occur when it becomes stronger than about 1 × 10 ⁶ [V / cm].

  Therefore, when the present inventors performed a desktop calculation, an electric field of an avalanche charge multiplication occurs in the structure of FIG. 1 and a tunnel breakdown does not occur even with an impurity concentration that can be realized by a normal CMOS fabrication process. I found that the condition was met.

Therefore, the present invention has been made based on this finding. Hereinafter, each claim will be described.
(1) In the solid-state imaging device according to the first aspect of the present invention, a gate oxide film, a PD impurity region for forming a photodiode (PD) that generates a charge by incident light, and a charge are multiplied on a semiconductor substrate. A multiplication gate electrode, a charge multiplication region that is provided opposite to the multiplication gate electrode and that multiplies the charge generated in the PD impurity region by the multiplication gate electrode, and the multiplied charge. A solid-state imaging device having a pixel configuration including a transfer gate electrode for transferring and an output impurity region for outputting the transferred charge, wherein the gate oxide film is opposite to a semiconductor substrate side (hereinafter referred to as an upper surface side). The charge multiplication region is formed directly below the multiplication gate electrode with the gate oxide film interposed therebetween, and on the upper surface side of the gate oxide film. The above The double gate electrode and the transfer gate electrode are disposed, and the PD impurity region, the charge multiplying region, and the output impurity region are provided on the semiconductor substrate side (hereinafter referred to as a lower surface side) of the gate oxide film. The charge multiplication region is disposed directly below the multiplication gate electrode with the gate oxide film interposed therebetween, and has an impurity concentration set independently of the surrounding impurity concentration. The impurity diffusion region is formed as the impurity diffusion region having an impurity concentration suitable for multiplying charges, and the PD impurity region is at least in the charge multiplication region when viewed from above. It has the part which adjoins.

In the present invention, the drive voltage of a normal CMOS image sensor is set by setting the impurity concentration in the charge multiplication region to an appropriate value (for example, 1.6 × 10 ^{17 to} 4.8 × 10 ¹⁷ [cm ⁻³ ]). Is applied to the multiplication gate electrode (for example, 2.6 to 5.0 [V]), and the electric field strength sufficient for avalanche multiplication (for example, 2.0 × 10 ^{5 to} 3.6 × 10 6). ⁵ [V / cm]) can be generated, and as a result, an excellent S / N can be realized even for weak incident light.

  That is, according to the present invention, the charge can be avalanche-multiplied by using a depletion layer whose thickness and internal electric field strength are adjusted by the impurity concentration of the charge-multiplier region. The avalanche multiplication, which could not be realized without applying a relatively high voltage due to restrictions on the arrangement accuracy between them, can be realized with a low voltage about the power supply voltage of the CMOS image sensor. As a result, a special power supply system is not required, and it is possible to obtain an improved S / N ratio by realizing a multiplication operation in the most adjacent region of the PD with lower power consumption than in the prior art.

In the present invention, the multiplication gate electrode and the transfer gate electrode are arranged on the opposite side (hereinafter referred to as the upper surface side) of the gate oxide film to the semiconductor substrate side, and the semiconductor substrate side (hereinafter referred to as the lower surface side) of the gate oxide film. A PD impurity region, a charge multiplication region, and an output impurity region, and the charge multiplication region is formed immediately below the multiplication gate electrode with the gate oxide film interposed therebetween. Has been. Here, the term “directly below” indicates that it is on the lower surface side (projection region) when viewed from the upper surface side.
Furthermore, in the present invention, the PD impurity region has at least a portion adjacent to the charge multiplication region as viewed from above.
Thereby, charges generated in the PD impurity region can be efficiently injected into the charge multiplication region. Here, the term “adjacent” means that at least a part of the PD impurity region reaching the surface of the semiconductor substrate and the charge multiplication region may be adjacent to each other, and may partially overlap in the projection region when viewed from the upper surface side. .
The present invention is characterized by the above-described pixel configuration (solid-state imaging device), a solid-state imaging device having the pixel configuration, a pixel array in which a plurality of the solid-state imaging devices are arranged, and an apparatus using the pixel array Etc. are also within the scope of the present invention.

Further, in the present invention, the charge multiplication region is an impurity diffusion region having an impurity concentration set independently of the surrounding impurity concentration, and the impurity concentration is an impurity concentration suitable for multiplying the charge. It is formed as an impurity diffusion region.
Therefore, it is possible to form a charge multiplication region optimum for avalanche charge multiplication without affecting other circuit elements formed in the solid-state imaging device.

( 2 ) In the invention of claim 2 , a portion of the PD impurity region reaching the surface of the semiconductor substrate is an n-gon when viewed from above, and the multiplication gate electrode, the charge multiplication region, and the transfer gate The electrode and the output impurity region leave one side to (n−1) sides when the periphery of the portion of the PD impurity region of the n-gonal portion reaching the surface of the semiconductor substrate is viewed from above. It is formed so as to surround it.

  In the present invention, by adopting the above-described configuration, the charge multiplication effect can be estimated in proportion to the area of the multiplication gate electrode and the charge multiplication region as viewed from above, so that it matches the weak light to be detected. Easy design.

( 3 ) In the invention of claim 3 , at least the multiplication gate electrode and the charge multiplication region surround the entire periphery of the portion of the PD impurity region reaching the semiconductor substrate surface as viewed from above. It is formed.

  In the present invention, since the area of the multiplication gate electrode and the charge multiplication region as viewed from above is maximized, the charge multiplication effect can also be maximized. In addition, it is desirable to arrange other configurations (transfer gate electrode and output impurity region) so as to capture the periphery as much as possible.

( 4 ) The invention of claim 4 is characterized in that a part of the PD impurity region is extended to a position directly below the multiplication gate electrode and the charge multiplication region.
In the present invention, the area where the PD impurity region and the charge multiplication region are in contact with each other can be set relatively wide, so that charge can be efficiently injected into the charge multiplication region.

( 5 ) In the invention of claim 5 , a portion of the PD impurity region reaching the surface of the semiconductor substrate is an n-gon when viewed from above, and the multiplication gate electrode, the charge multiplication region, and the transfer gate The electrode, the output impurity region, and the portion of the PD impurity region that extends to the region immediately below the charge multiplication region are the upper surface around the portion of the PD impurity region of the n-gonal portion that reaches the semiconductor substrate surface. As viewed from the side, the first side to the (n-1) side are left and surrounded.

  In the present invention, the area where the PD impurity region and the charge multiplication region are in contact with each other is set wide to efficiently inject charges into the charge multiplication region, while the multiplication gate electrode and the charge multiplication region are viewed from above. Since the charge multiplication effect can be estimated in proportion to the area, the design according to the weak light to be detected can be easily performed.

( 6 ) In the invention of claim 6 , at least the multiplication gate electrode, the charge multiplication region, and a portion of the PD impurity region that extends to a position immediately below the charge multiplication region is the PD impurity. The region is formed so as to surround the entire periphery of the region reaching the surface of the semiconductor substrate when viewed from above.

  In the present invention, the area where the PD impurity region and the charge multiplication region are in contact with each other is set wide to efficiently inject charges into the charge multiplication region, while the multiplication gate electrode and the charge multiplication region are viewed from above. Since the area can be maximized, the charge multiplication effect can also be maximized. In addition, it is desirable to arrange other configurations (transfer gate electrode and output impurity region) so as to capture the periphery as much as possible.

( 7 ) In the invention of claim 7 , a part of the PD impurity region passes immediately below the charge multiplication region immediately below the multiplication gate electrode, and a gap between the multiplication gate electrode and the transfer gate electrode. Is characterized by being formed so as to extend to the surface of the semiconductor substrate.

  In the present invention, the area where the PD impurity region and the charge multiplication region are in contact with each other can be set relatively wide, and the injection of charges into the charge multiplication region can be performed efficiently. Since the portion is formed up to the vicinity of the transfer gate, the multiplied charge is efficiently transferred to the output impurity region.

( 8 ) In the invention of claim 8 , a portion of the PD impurity region that reaches the surface of the semiconductor substrate excluding a portion that extends to the surface of the semiconductor substrate in the gap between the multiplication gate electrode and the transfer gate electrode, It is n-gonal when viewed from above, passing through the multiplication gate electrode, the charge multiplication region, the transfer gate electrode, the output impurity region, and the PD impurity region directly below the charge multiplication region. The portion of the gap between the multiplication gate electrode and the transfer gate electrode extending to the surface of the semiconductor substrate is the gap between the multiplication gate electrode and the transfer gate electrode in the PD impurity region of the n-gonal portion. It is formed so as to surround any one of sides 1 to (n-1) when viewed from the upper surface around the portion reaching the surface of the semiconductor substrate excluding the portion extending to the surface of the semiconductor substrate. To.

  In the present invention, the area where the PD impurity region and the charge multiplication region are in contact with each other can be set relatively wide, and the injection of charges into the charge multiplication region can be performed efficiently. Since the portion is formed up to the vicinity of the transfer gate, the multiplied charge is efficiently transferred to the output impurity region. Further, since the charge multiplication effect can be estimated in proportion to the area of the multiplication gate electrode and the charge multiplication region as viewed from above, the design according to the weak light to be detected can be facilitated.

( 9 ) In the invention of claim 9 , in the PD impurity region, the upper surface side and a lower surface direction (depth direction) of a peripheral portion not adjacent to the charge multiplication region as viewed from the upper surface. An impurity region having a polarity opposite to that of the PD impurity region is provided on a side surface.

  In the present invention, the effect of dark current caused by surface states existing on the surface is reduced by the impurity regions formed on the surface and side surfaces of the PD impurity region, and the charge injected from the PD impurity region into the charge multiplication region. By extracting the charge having a reverse polarity and being a noise component from the charge multiplication region, fluctuations in the number of charges due to charge multiplication can be reduced, and noise can be reduced.

( 10 ) According to the invention of claim 10 , in the PD impurity region, the upper surface side and the central portion of the PD impurity region as viewed from the upper surface are deeper than the depth of the PD impurity region toward the lower surface. And an impurity region having a polarity opposite to that of the PD impurity region.

  In the present invention, the charge that becomes a noise component up to a region deeper than the PD impurity region without forming an impurity region having a polarity opposite to that of the PD impurity region in the lower surface direction (depth direction) around the PD impurity region as viewed from the upper surface. Therefore, fluctuation in the number of charges due to charge multiplication can be reduced and noise can be reduced while maintaining a relatively high degree of design freedom around the PD impurity region as viewed from above.

( 11 ) In the invention of claim 11, the surface of the region reaching the semiconductor substrate surface excluding the portion of the PD impurity region extending to the semiconductor substrate surface in the gap between the multiplication gate electrode and the transfer gate electrode And an impurity region having a polarity opposite to that of the PD impurity region on a side surface along a lower surface direction of a peripheral portion of the region that is not adjacent to the charge multiplication region when viewed from the upper surface. To do.

  In the present invention, the area where the PD impurity region and the charge multiplication region are in contact with each other can be set relatively wide, and the injection of charges into the charge multiplication region can be performed efficiently. Since the portion is formed up to the vicinity of the transfer gate, the multiplied charge is efficiently transferred to the output impurity region.

In addition, since the charge multiplication effect can be estimated in proportion to the area of the multiplication gate electrode and the charge multiplication region as viewed from above, the design according to the weak light to be detected can be facilitated.
Furthermore, the influence of the dark current due to the surface level existing on the surface is reduced, and the charge that has the opposite polarity to the charge injected from the PD impurity region into the charge multiplication region and becomes a noise component is charged in the charge multiplication region. By pulling out from, fluctuations in the number of charges accompanying charge multiplication can be reduced, and noise can be reduced.

( 12 ) In the invention of claim 12, the multiplication gate electrode, the charge multiplication region, the transfer gate electrode, the output impurity region, and the PD impurity region immediately below the charge multiplication region. The portion extending through the gap between the multiplication gate electrode and the transfer gate electrode to the surface of the semiconductor substrate is the semiconductor substrate in the gap between the multiplication gate electrode and the transfer gate electrode in the PD impurity region. A semiconductor substrate formed so as to surround a region reaching the surface of the semiconductor substrate excluding a portion extending to the surface when viewed from above, and in a gap between the multiplication gate electrode and the transfer gate electrode in the PD impurity region When viewed from the surface and upper surface of the region other than the portion extending to the surface, the depth is larger than the depth of the PD impurity region from the center of the region toward the lower surface. As such, characterized by comprising an impurity region having a polarity opposite to that of the PD impurity region.

  In the present invention, the area where the PD impurity region and the charge multiplication region are in contact with each other can be set relatively wide, and the injection of charges into the charge multiplication region can be performed efficiently. Since the portion is formed up to the vicinity of the transfer gate, the multiplied charge is efficiently transferred to the output impurity region.

In addition, since the area of the multiplication gate electrode and the charge multiplication region as viewed from above can be maximized, the charge multiplication effect can also be maximized.
Furthermore, the influence of the dark current due to the surface level existing on the surface is reduced, and the charge that has the opposite polarity to the charge injected from the PD impurity region into the charge multiplication region and becomes a noise component is charged in the charge multiplication region. By pulling out from, fluctuations in the number of charges accompanying charge multiplication can be reduced, and noise can be reduced.

( 13 ) In the invention of claim 13 , an epitaxial layer is laminated on the semiconductor substrate, and at least the PD impurity region and the charge multiplication region are provided on the upper surface side (opposite side of the semiconductor substrate) of the epitaxial layer. And the output impurity region.

  In the present invention, the impurity concentration of the epitaxial layer is controlled to be relatively low compared to the semiconductor substrate, so that the depletion formed from the PD impurity region toward the semiconductor substrate when the solid-state imaging device of the present invention is operated. The thickness of the layer can be made sufficient.

  If the wavelength of the input light including the desired signal is relatively long, such as in the near-infrared light band, the penetration depth of light into the semiconductor will be long, so make the depletion layer thick enough in this way. Therefore, the sensitivity in a desired wavelength band can be increased.

  Conversely, if the wavelength of the input light containing the desired signal is relatively short, the epitaxial layer is thinned to make the depletion layer thinner, reducing the sensitivity of unwanted long-wavelength signals while reducing the required short wavelength. Side sensitivity can be ensured.

  At the same time, the thickness of the epitaxial layer is made to be the same as the thickness of the depletion layer, and the impurity concentration of the semiconductor substrate is made relatively high to reduce the resistance value so that the response to high frequency input light is not impaired. There is an effect to.

Note that the multiplication gate electrode and the transfer gate electrode can be formed on the upper surface side (opposite to the epitaxial layer) of the semiconductor substrate via a gate oxide film.
( 14 ) The invention according to claim 14 is the method of driving a solid-state imaging device according to any one of claims 1 to 13 , wherein the charge generated in the PD impurity region by the incident light is increased in the charge. A step of applying a voltage to the multiplication gate electrode to cause avalanche multiplication in the charge multiplication region when injected into the multiplication region; and a step of returning the voltage applied to the multiplication gate electrode to an initial value. And a step of applying a voltage to the transfer gate electrode to transfer the multiplied charge to the output impurity region.

  In the present invention, a depletion layer is first formed in a region immediately below the multiplication gate electrode (a region where an electric field is generated by the multiplication gate electrode) by applying a voltage equivalent to the power supply voltage of the CMOS image sensor to the multiplication gate electrode. Arise. That is, according to the present invention, the charge can be avalanche-multiplied by using a depletion layer whose thickness and internal electric field strength are adjusted by the impurity concentration of the charge-multiplier region. Charge multiplication, which could not be realized unless a relatively high voltage is applied due to restrictions on the arrangement accuracy between them, can be realized with a low voltage about the power supply voltage of the CMOS image sensor.

  The charge generated by the incident light is injected from the PD impurity region into the charge multiplication region in accordance with the electric field generated by the multiplication gate electrode, and the charge multiplication region causes charge multiplication by the avalanche multiplication phenomenon described above. Note that after an appropriate time, the applied voltage of the multiplication gate voltage is lowered.

  Next, a voltage is applied to the transfer gate voltage to transfer the multiplied charge to the output impurity region. A signal in the output impurity region reflecting the multiplied charge amount can be output to the outside of the pixel by a method such as reading it out as a voltage by a source follower amplifier or the like.

As described above, in the present invention, an improved S / N can be obtained by multiplying the signal charge caused by the weak light in the pixel without using an amplifier based on an electronic circuit.
( 15 ) In the invention of claim 15 , the step of applying a voltage to the multiplication gate electrode and the step of applying a voltage to the transfer gate electrode are performed at a timing such that a part of each step overlaps. It is set and driven.

According to the present invention, it is possible to increase the ratio of reading the multiplied charge before recombination, and to obtain an improved S / N.
( 16 ) In the invention of claim 16, the step of returning the applied voltage after applying the voltage to the multiplication gate electrode to the initial value, and the step of applying the voltage to the transfer gate electrode, It is characterized by being driven at a timing at which a part of them overlaps.

According to the present invention, it is possible to increase the ratio of reading the multiplied charge before recombination, and to obtain an improved S / N.
( 17 ) In the invention of claim 17 , the step of applying a voltage to the multiplication gate electrode and the step of returning the voltage applied to the multiplication gate electrode to an initial value so that a predetermined signal intensity can be obtained. The charge multiplication factor is controlled repeatedly until it becomes.

  In the present invention, the above-mentioned multiplication gate drive is repeated until the signal intensity becomes appropriate, thereby multiplying the charge. Next, a voltage is applied to the transfer gate to transfer the multiplied charge to the output impurity region. The output impurity region signal reflecting the multiplied charge amount is output as a voltage to the outside of the pixel by a method such as reading by a source follower amplifier.

  Thus, even if the multiplication factor per time becomes a relatively small value by making the driving condition of the solid-state imaging device in one multiplication the condition for obtaining the optimum S / N, the multiplication is repeated repeatedly. The result obtained is the desired multiplication factor and an improved S / N can be obtained.

Next, the best mode (embodiment) of the present invention will be described.
[First Embodiment]
a) First, the solid-state imaging device according to the first embodiment having the pixel configuration of the present invention will be described.

  FIG. 2 is a block diagram showing a schematic configuration of the solid-state imaging device. As shown in FIG. 2, the solid-state imaging device according to the first embodiment is a CMOS image sensor, and includes a solid-state imaging device 1 having a pixel configuration, which will be described in detail later, and a pixel array 3 in which a large number of the solid-state imaging devices 1 are arranged vertically and horizontally. , A row selector 5, a column selector 7, a CDS (Correlation Double Sampling) array 9, an amplifier circuit 11, an ADC 13, a bias unit 15, a control register 17, a timing generator 19, and I A known configuration such as / O21 is provided.

b) Next, the solid-state imaging device 1 which is a main part of the present invention will be described.
FIG. 3 is a cross-sectional view schematically showing the solid-state imaging device 1. In the figure, the upper side is the upper surface side of the solid-state image sensor 1, and the lower side is the lower surface side of the solid-state image sensor 1.

  As shown in FIG. 3, the solid-state imaging device 1 includes a PD impurity region 33, a charge multiplication region 35, an output impurity region 37, a gate oxide film 39, and a multiplication gate electrode 41 on a semiconductor substrate 31. And a transfer gate electrode 43.

  Specifically, in the solid-state imaging device 1, the PD impurity region 33, the charge multiplication region 35, and the output impurity region 37 are arranged in parallel on the lower surface side (semiconductor substrate 31 side) of the gate oxide film 39 along the lower surface. In addition, the multiplication gate electrode 41 and the transfer gate electrode 43 are arranged in parallel along the upper surface side of the gate oxide film 39 (on the side opposite to the semiconductor substrate 31).

  In particular, in this embodiment, the charge multiplication region 35 is formed immediately below the multiplication gate electrode 41 with the gate oxide film 39 interposed therebetween. That is, the structure in which the multiplication gate electrode 41 and the charge multiplication region 35 are closely opposed to each other (multiplication structure 45) is formed between the PD impurity region 33 and the transfer gate electrode 43. It is disposed adjacent to the electrode 43.

  Of these, the semiconductor substrate 31 may be a Si substrate that is generally used for CCDs and CMOS image sensors. However, even if the substrate is other than a Si substrate, conditions are set so that each element constituting the present invention operates. Needless to say, it can be used if it is set.

  For example, when the semiconductor substrate 31 is a Si substrate, electrons have a higher ionization rate than holes, so that the charge to be multiplied is more advantageous for electrons to increase the multiplication factor. When the semiconductor substrate 31 is made of Ge, since holes have a higher ionization rate than electrons, the charge to be multiplied is more advantageous for holes to increase the multiplication factor. As described above, the charge to be multiplied depending on the material of the semiconductor substrate 31 may be either an electron or a hole. If the semiconductor substrate 31 is made to be n-type or p-type, and the type of impurity in each impurity region is determined. Good.

The multiplication gate electrode 41 is formed on the gate oxide film 39, is made of, for example, polycrystalline silicon, and is an electrode to which a voltage is applied in order to multiply the charge. As the gate oxide film 39, an insulating layer made of SiO ₂ can be adopted.

The transfer gate electrode 43 is also formed on the gate oxide film 39, and is made of, for example, polycrystalline silicon, and is an electrode for applying a voltage to transfer charges.
The charge multiplication region 35 is a region where a depletion layer is generated by applying a voltage to the multiplication gate electrode 41 and a high electric field is generated. The charge multiplying region 35 is formed by adjusting the impurity concentration of the semiconductor substrate 31 so that the impurity concentration is optimal for multiplying the charge. For example, boron can be used as the impurity, and the impurity concentration can be adjusted to 1.6 × 10 ^{17 to} 4.8 × 10 ¹⁷ [cm ⁻³ ].

The PD impurity region 33 is a region where a photodiode (PD) is formed and charges are generated by incident light.
The output impurity region 37 is a region for outputting the charges transferred by the transfer gate electrode 43.

Here, the kind of impurities forming the PD impurity region 33 and the output impurity region 37 may be selected in consideration of whether the semiconductor substrate 39 is n-type or p-type, as described above. Good. For example, when the semiconductor substrate 39 is p-type, the PD impurity region 33 and the output impurity region 37 may be n-type. For example, arsenic can be employed as the impurity of the PD impurity region 33, and 1 × 10 ¹⁹ [cm ⁻³ ] can be employed as the impurity concentration. Further, arsenic can be employed as the impurity in the output impurity region 37, and 1 × 10 ¹⁹ [cm ⁻³ ] can be employed as the impurity concentration.

  In FIG. 3, an interlayer insulating film, a surface protective film, a microlens, various reset switches to be arranged in a pixel, and transistors serving as various pixel selection switches that are generally used for configuring the solid-state imaging device 1 are shown. Although not shown, it goes without saying that it may be appropriately formed in consideration of the number of wiring layers, the use environment, and the overall configuration of the device.

  FIG. 4 schematically shows a planar arrangement of each component of the solid-state imaging device 1. The PD impurity region 33, the multiplication gate electrode 41, the transfer gate electrode 43, and the output impurity are arranged along the horizontal direction in FIG. It can be seen that the regions 37 are sequentially arranged adjacent to each other.

  In the figure, although the gate oxide film 39 is omitted (hereinafter also omitted in the plan view), a contact hole 47 and wiring 49 on the output impurity region 37 not shown in FIG. 3 are drawn. is there.

Needless to say, the shape, relative size, and the like of each element can be appropriately adjusted in view of the necessity of pixel reduction or the like within a range that maintains the effectiveness of the present invention.
c) Next, the charge multiplication process in the solid-state imaging device 1 will be described with reference to FIG.

  As is generally known, a depletion layer is generated by a difference in impurity concentration between the PD impurity region 33 and the semiconductor substrate 31 and a voltage applied to the semiconductor substrate 31 and other components from the outside.

  Here, each component starts operation from an ideal initial state. A transistor or the like that serves as a reset switch necessary for this purpose is not shown in FIG. 5, but can be easily formed using a generally known MOS transistor or the like.

  When light (weak light) is incident on the PD impurity region 33, charges generated in the depletion layer (in the charge multiplication region 35), that is, electrons and holes, move toward the PD impurity region 33 and the semiconductor substrate 31, respectively. Here, attention is focused on the charges moving to the PD impurity region 33. When the semiconductor substrate 31 is a p-type Si substrate and the PD impurity region 33 is an n-type, the majority of the electrons moving to the PD impurity region 33 are electrons.

A voltage adjusted to an appropriate value is applied to the multiplication gate electrode 41 from the outside, and the charge that has moved to the PD impurity region 33 is injected into the charge multiplication region 35. When the charge assuming multiplication is an electron, the voltage applied to the multiplication gate electrode 41 is a positive value. At this time, in the charge multiplication region 35 in which the impurity concentration is adjusted in advance, an electric field strength suitable for avalanche multiplication (for example, 2.0 × 10 ^{5 to} 3.6 × 10 ⁵⁾ is provided immediately below the multiplication gate electrode 41. [V / cm]) can be generated inside the depletion layer. Such a depletion layer can be generated at a voltage (for example, 2.6 to 5.0 [V]) comparable to a power supply voltage used in a normal CMOS image sensor.

  When the injected charge reaches the depletion layer, avalanche multiplication is caused by the electric field in the depletion layer, and the charge is multiplied. The charge having the opposite polarity to the injected one generated at this time moves in the back surface direction (downward in the figure) according to the electric field generated between the front surface (upper surface) and the back surface (lower surface) of the semiconductor substrate 31.

While the voltage is applied to the multiplication gate electrode 41, the multiplied charge having the same polarity as the injected charge remains in the charge multiplication region 35.
In a state where a voltage is applied to the multiplication gate electrode 41, an appropriate voltage is applied to the transfer gate electrode 43, and charges remaining in the charge multiplication region 35 (that is, re-injected into the PD impurity region 33 and multiplied). Transfer) to the output impurity region 37. Here, as the voltage applied to the transfer gate electrode 43, a voltage (for example, 2.6 to 5.0 [V]) about the power supply voltage of a general CMOS image sensor is sufficient.

After the start of charge transfer by applying a voltage to the transfer gate electrode 43, the voltage applied to the multiplication gate electrode 41 is returned to the initial state.
In this embodiment, in this way, a slight charge generated by weak light can be multiplied within the pixel without applying a special high voltage to increase power consumption. As a result, it is possible to increase the signal at the pixel output portion compared to the conventional method of amplifying the signal after transferring the charge outside the pixel, and the influence of noise mixed during the signal transfer outside the pixel. It can be reduced relatively. That is, according to the present embodiment, an improved S / N can be obtained.

d) Next, the timing of driving the applied voltage to the gate electrode in the solid-state imaging device 1 will be described with reference to FIG.
Here, each component starts operation from an ideal initial state. The voltage pulse applied to the multiplication gate electrode 41 may be one time. However, in order to obtain a sufficient multiplication factor, a plurality of voltage pulses may be applied as shown in the upper part of FIG. At this time, a plurality of voltage pulses are applied after a sufficiently short time so that the charges multiplied immediately after each voltage pulse returns to the initial state are multiplied again by the above-described multiplication process. A pulse is to be applied.

  As shown in the lower part of FIG. 6, the last voltage pulse applied to the multiplication gate electrode 41 and the voltage pulse applied to the transfer gate electrode 43 are not adjusted by appropriate adjustment in consideration of the transient state of each voltage pulse waveform. Set so that the parts overlap.

Therefore, in this embodiment, the charge multiplication factor can be controlled to a desired value by appropriately adjusting the number of voltage pulses applied to the multiplication gate electrode 41.
e) Next, an application example of this embodiment will be described.

FIG. 7 schematically shows the upper surface side of the solid-state imaging device of Application Example 1.
As shown in FIG. 7, in this solid-state imaging device 51, the portion (gray portion) reaching the surface of the semiconductor substrate 55 in the PD impurity region 53 is an n-gon (for example, an octagon) when viewed from above, and the multiplication gate The electrode 57, the charge multiplication region 59, the transfer gate electrode 61, and the output impurity region 63 have one side when the periphery of the portion of the n-square PD impurity region 53 reaching the surface of the semiconductor substrate 55 is viewed from above. It is formed so as to surround any one of the (n-1) sides (here, three sides). Note that the contact hole 65 and the wiring 67 are similarly formed along the output impurity region 63.

  That is, in the first application example, the multiplication gate electrode 57, the charge multiplication region 59, the transfer gate electrode 61, and the output impurity region are provided in a range that does not hinder the functions of the necessary pixel components to be arranged in the pixel. 63 is arranged so as to surround the periphery of the PD impurity region 53 when viewed from above.

  Therefore, in this application example 1, since the charge multiplication effect can be estimated in proportion to the areas of the multiplication gate electrode 57 and the charge multiplication region 59 as viewed from above, the design is adapted to the weak light to be detected. Can be easily done.

FIG. 8 schematically shows the upper surface side of the solid-state imaging device of Application Example 2.
As shown in FIG. 8, in the solid-state imaging device 71, among the multiplication gate electrode 73, the charge multiplication region 75, the transfer gate electrode 77, and the output impurity region 79, the multiplication gate electrode 73 and the charge are included. The multiplication region 75 is formed so as to surround the entire periphery of the portion of the PD impurity region 81 reaching the surface of the semiconductor substrate 83 (octagonal gray portion) as viewed from above. Note that the contact hole 85 and the wiring 87 are similarly formed along the output impurity region 79.

Therefore, in this application example 2, since the areas of the multiplication gate electrode 73 and the charge multiplication region 75 viewed from the top surface are maximized, the charge multiplication effect can also be maximized.
[Second Embodiment]
Next, the second embodiment will be described, but the description of the same contents as the first embodiment will be omitted or simplified.

a) First, the configuration of the solid-state imaging device of the present embodiment will be described.
FIG. 9 is a cross-sectional view schematically showing a solid-state imaging device, and FIG. 10 is a plan view thereof.
As shown in FIGS. 9 and 10, the solid-state imaging device 91 of the second embodiment has the same arrangement as that of the first embodiment, and a PD impurity region 95, a charge multiplication region 97, and a semiconductor substrate 93. , An output impurity region 99, a gate oxide film 101, a multiplication gate electrode 103, and a transfer gate electrode 105.

In particular, in the present embodiment, the impurity concentration of the charge multiplying region 97 is set independently of the impurity concentration of the semiconductor substrate 93. For example, the impurity concentration of the charge multiplying region 97 is set to 1.6 × 10 ^{17 to} 4.8 × 10 ¹⁷ [cm ⁻³ ], and the impurity concentration of the semiconductor substrate 93 is 1.0 × 10 ¹⁵ [cm ^{−]. 3} ] is set.

That is, the impurity concentration of the charge multiplying region 97 is formed by independently implanting and diffusing an appropriate impurity (for example, boron) so that the optimum impurity concentration for multiplying the charge is obtained.
As a result, it becomes easy to simultaneously determine the determination of the impurity concentration of the semiconductor substrate 93 suitable for the design of various elements other than the charge multiplication region 97 and the acquisition of the optimum impurity concentration for charge multiplication.

b) Next, the charge multiplication process in this embodiment will be described.
Also in the present embodiment, charge multiplication can be performed basically in the same manner as in the first embodiment.

As shown in FIG. 11, when light enters the PD impurity region 95 , charges (positive and negative) generated in the depletion layer move toward the PD impurity region 95 and the semiconductor substrate 93, respectively.
A voltage is applied to the multiplication gate electrode 103 to inject the charges transferred to the PD impurity region 95 into the charge multiplication region 97. When the injected charge reaches the depletion layer, avalanche multiplication is caused by the electric field in the depletion layer, and the charge is multiplied.

  Then, by applying a voltage to the transfer gate electrode 105 in a state where a voltage is applied to the multiplication gate electrode 103, charges remaining in the charge multiplication region 95 can be transferred to the output impurity region 99.

[Third Embodiment]
Next, the third embodiment will be described, but the description of the same contents as the second embodiment will be omitted or simplified.

a) First, the configuration of the solid-state imaging device of the present embodiment will be described.
FIG. 12 is a cross-sectional view schematically showing a solid-state imaging device, and FIG. 13 is a plan view thereof.
As shown in FIGS. 12 and 13, the solid-state imaging device 111 according to the third embodiment has a PD impurity region 115 and (impurity concentration is set independently) on the semiconductor substrate 113, as in the second embodiment. A charge multiplication region 117, an output impurity region 119, a gate oxide film 121, a multiplication gate electrode 123, and a transfer gate electrode 125.

  In particular, in the present embodiment, the PD impurity region 115 is formed to extend right below the multiplication gate electrode 123 and the charge multiplication region 117 at an appropriate depth away from the surface (upper surface) of the semiconductor substrate 113. .

With such a structure, it becomes easy to inject charges from the PD impurity region 115 into the charge multiplication region 117, and the detection efficiency with respect to a weak incident signal is improved.
b) Next, the charge multiplication process in this embodiment will be described.

  As shown in FIG. 14, first, when light (weak light) is incident on the PD impurity region 115, charges generated in the depletion layer, that is, electrons and holes, move toward the PD impurity region 115 and the semiconductor substrate 113, respectively. . Here, attention is focused on the charges moving to the PD impurity region 115.

  Next, a voltage adjusted to an appropriate value is applied to the multiplication gate electrode 123 from the outside, and the charge that has moved to the PD impurity region 115 is injected into the charge multiplication region 117. Since the PD impurity region 115 is extended below the multiplication gate electrode 123 and the charge multiplication region 117, it is easy to inject charges into the charge multiplication region 117 from this extended portion.

  At this time, in the charge multiplication region 117 in which the impurity concentration is adjusted in advance, a depletion layer with an electric field strength suitable for avalanche multiplication can be generated immediately below the multiplication gate electrode 123.

  When the injected charge reaches the depletion layer, avalanche multiplication is caused by the electric field in the depletion layer, and the charge is multiplied. While the voltage is applied to the multiplication gate electrode 123, the multiplied charge having the same polarity as the injected charge remains in the charge multiplication region 117.

Next, the voltage applied to the multiplication gate electrode 123 is returned to the initial value. As a result, the multiplied charge is reinjected into the extended portion of the PD impurity region 115.
Subsequently, an appropriate voltage is applied to the transfer gate electrode 125 to transfer the charge reinjected into the PD impurity region 115 to the output impurity region 119.

  In this way, in this embodiment, a slight charge generated by weak light can be multiplied within the pixel without applying a special high voltage to increase power consumption. As a result, compared with the conventional method of amplifying the signal after transferring the charge to the outside of the pixel, the signal at the pixel output portion can be increased and the influence of noise mixed during the signal transfer outside the pixel. Can be relatively reduced. That is, according to the present embodiment, it is possible to obtain a further improved S / N.

c) Next, the timing of driving the applied voltage to the gate electrode in the solid-state imaging device 111 will be described with reference to FIG.
Here, each component starts operation from an ideal initial state. The voltage applied to the multiplication gate electrode 123 may be one time, but in order to obtain a sufficient multiplication factor, a plurality of voltage pulses may be applied as shown in the upper part of FIG.

  Further, as shown in the lower part of FIG. 15, after the voltage pulse applied to the multiplication gate electrode 123 returns to the initial value (in FIG. 15, it is 0 V as an example), the voltage is applied to the transfer gate electrode 125 for output. Charge is transferred to the impurity region 119.

  The final voltage pulse applied to the multiplication gate electrode 123 and the voltage pulse applied to the transfer gate electrode 125 are partially overlapped by appropriate adjustment in consideration of the transient state of each voltage pulse waveform. It may be set.

Therefore, in this embodiment, the charge multiplication factor can be controlled to a desired value by appropriately adjusting the number of voltage pulses applied to the multiplication gate electrode 123.
In the present embodiment, as in the above-described application examples 1 and 2, the multiplication gate electrode 123, the charge multiplication region 117, and the transfer are performed in a range that does not hinder the functions of the necessary pixel components to be arranged in the pixel. An extended portion of the gate electrode 125, the output impurity region 119, and the PD impurity region 115 directly below the charge multiplying region 117 surrounds the periphery of the portion of the PD impurity region 115 reaching the surface of the semiconductor substrate 113 from the top surface. You may arrange as follows.

  In particular, it is preferable to arrange the entire periphery of the portion of the PD impurity region 115 that reaches the surface of the semiconductor substrate 113 so as to be surrounded by the multiplication gate electrode 123 and the charge multiplication region 117.

[Fourth Embodiment]
Next, the fourth embodiment will be described, but the description of the same contents as the third embodiment will be omitted or simplified.

a) First, the configuration of the solid-state imaging device of the present embodiment will be described.
FIG. 16 is a cross-sectional view schematically showing a solid-state image sensor, and FIG. 17 is a plan view thereof.
As shown in FIGS. 16 and 17, the solid-state imaging device 131 of the fourth embodiment has a PD impurity region 135 and (impurity concentration is set independently) on the semiconductor substrate 133, as in the third embodiment. A charge multiplication region 137, an output impurity region 139, a gate oxide film 141, a multiplication gate electrode 143, and a transfer gate electrode 145.

  In particular, in the present embodiment, the PD impurity region 135 passes immediately below the charge multiplication region 137 immediately below the multiplication gate electrode 143, and the surface of the semiconductor substrate 133 in the gap between the multiplication gate electrode 143 and the transfer gate electrode 145. It is formed so as to extend. That is, the tip of the output impurity region 139 of the PD impurity region 135 is extended until it contacts the lower surface of the gate oxide film 141.

  With such a structure, it becomes easy to inject charges from the PD impurity region 135 into the charge multiplication region 137, and the charge after multiplication is transferred to the output impurity region 139 after charge multiplication. As a result, the detection efficiency for a weak incident signal is improved.

b) Next, the charge multiplication process in this embodiment will be described.
As shown in FIG. 18, in this embodiment, compared to the third embodiment, the PD impurity region extended to the gap between the multiplication gate electrode 143 and the transfer gate electrode 145 after the charge multiplication operation is completed. The difference is that the multiplied charge is transferred from the tip of 135 to the output impurity region 139 through just below the transfer gate electrode 145.

In this way, the path through which the multiplied charge passes during charge transfer is shortened, and charge transfer is facilitated.
In the present embodiment, as in the third embodiment, the portion of the PD impurity region 135 that extends to the surface of the semiconductor substrate 133 in the gap between the multiplication gate electrode 137 and the transfer gate electrode 145 is excluded. The portion reaching the surface of the semiconductor substrate 133 is formed in an n-gon shape when viewed from above, and the multiplication gate electrode 137, the charge multiplication region 137, the transfer gate electrode 145, the output impurity region 139, and the PD impurity region 135 Among these, the portion extending to the surface of the semiconductor substrate 133 in the gap between the multiplication gate electrode 137 and the transfer gate electrode 145 passing directly under the charge multiplication region 137 is the (multiplier of the PD impurity region 135 of the n-gonal portion. (Except for the portion extending to the surface of the semiconductor substrate 133 in the gap between the gate electrode 137 and the transfer gate electrode 145) When viewed from the top may be formed so as to surround leaving any side of one side ~ (n-1) sides.

[Fifth Embodiment]
Next, the fifth embodiment will be described, but the description of the same contents as the third embodiment will be omitted or simplified.

FIG. 19 is a cross-sectional view schematically showing a solid-state image sensor, and FIG. 20 is a plan view thereof.
As shown in FIGS. 19 and 20, the solid-state imaging device 151 of the fifth embodiment includes a PD impurity region 155 (having an extended portion) and (impurities) on a semiconductor substrate 153, as in the third embodiment. A charge multiplying region 157 (concentration set independently), an output impurity region 159, a gate oxide film 161, a multiplying gate electrode 163, and a transfer gate electrode 165 are provided.

  In particular, in this embodiment, it is disposed between the gate oxide film 161 and the PD impurity region 155, its right end is in contact with the charge multiplication region 157, and its left end is a depth along the side end of the PD impurity region 155. A surface / side surface impurity region 167 extending in the direction is provided.

  As the impurity of the surface / side surface impurity region 167, for example, boron can be adopted, and one of the functions of the surface / side surface impurity region 167 is dark current caused by the surface level existing on the surface of the PD impurity region 155. To reduce the impact. In addition to this, the charge multiplying region 157 has an effect of extracting a charge having a polarity opposite to that of the charge injected from the PD impurity region 155 into the charge multiplying region 157 and serving as a noise component. As a result, fluctuations in the number of charges due to charge multiplication can be reduced, and noise can be reduced.

  Note that transistors and the like that serve as reset switches necessary to realize the above-described functions are not shown in FIGS. 19 and 20, but can be easily formed using generally known MOS transistors or the like. it can.

[Sixth Embodiment]
Next, the sixth embodiment will be described, but the description of the same contents as the fourth embodiment will be omitted or simplified.

FIG. 21 is a sectional view schematically showing a solid-state imaging device, and FIG. 22 is a plan view thereof.
As shown in FIGS. 21 and 22, the solid-state imaging device 171 of the sixth embodiment is formed on the semiconductor substrate 173 (extending to the gate oxide film covering the charge multiplication region), as in the fourth embodiment. PD impurity region 175 having a portion), charge multiplying region 177 (impurity concentration is set independently), output impurity region 179, gate oxide film 181, multiplying gate electrode 183, and transfer gate And an electrode 185.

  In the present embodiment, like the fifth embodiment, it is disposed between the gate oxide film 181 and the PD impurity region 175, the right end thereof is in contact with the charge multiplication region 177, and the left end thereof is the PD impurity region 175. A surface / side surface impurity region 187 extending in the depth direction along the side edge of the substrate is provided.

Therefore, in this embodiment, the same effect as the fourth embodiment and the fifth embodiment is obtained.
[Seventh Embodiment]
Next, the seventh embodiment will be described, but the description of the same contents as the third embodiment will be omitted or simplified.

FIG. 23 is a cross-sectional view schematically showing a solid-state image sensor.
As shown in FIG. 23, as in the third embodiment, the solid-state imaging device 191 of the seventh embodiment includes a semiconductor substrate 193, a PD impurity region 195 (having an extended portion), and an impurity concentration independent of each other. Charge multiplication region 197, output impurity region 199, gate oxide film 201, multiplication gate electrode 203, and transfer gate electrode 205.

  In particular, in the present embodiment, the PD impurity region 195, the charge multiplying region 197, the output impurity region 199, the gate oxide film 201, the multiplying gate electrode 203, and the transfer gate electrode 205 are configured in the same manner as in the second embodiment. Is formed on the surface (upper surface) of the epitaxial layer 207 formed on the semiconductor substrate 193.

  By adjusting the conditions for implanting impurities into the epitaxial layer 207, it is easy to adjust the impurity concentration in the charge multiplication region 105 and the like to an optimum value for charge multiplication independently of the impurity concentration in the epitaxial layer 207. .

In the present embodiment, the solid-state imaging device 191 is operated by controlling the impurity concentration of the epitaxial layer 207 to a relatively low concentration as compared with the semiconductor substrate 193, for example, 10 ¹⁴ [cm ⁻³ ] or less. At this time, the thickness of the depletion layer formed from the PD impurity region 195 toward the semiconductor substrate 193 can be made sufficient.

  Therefore, when the wavelength of the input light including the desired signal is relatively long, such as in the near-infrared light band, the length of light penetration into the semiconductor becomes long. Thus, the thickness of the depletion layer is made sufficiently thick. By doing so, the sensitivity in a desired wavelength band can be made high.

  Conversely, when the wavelength of the input light including the desired signal is relatively short, the thickness of the epitaxial layer 207 is reduced to make the depletion layer thinner, and this is necessary while reducing the sensitivity of unnecessary long wavelength signals. Sensitivity on the short wavelength side can be ensured.

  At the same time, the thickness of the epitaxial layer 207 is made substantially the same as the thickness of the depletion layer, and the impurity concentration of the semiconductor substrate 193 is made relatively high to reduce the resistance value, so that the response to high-frequency input light is not impaired. There is an effect to do.

  Also in this embodiment, it goes without saying that the structure formed on the surface of the epitaxial layer 207 may be the same structure as that of the first, second, and fourth to sixth embodiments described above.

[Eighth Embodiment]
Next, the eighth embodiment will be described, but the description of the same contents as the third embodiment will be omitted or simplified.

FIG. 24 is a cross-sectional view schematically showing a solid-state imaging device.
As shown in FIG. 24, the solid-state imaging device 211 of the eighth embodiment includes a PD impurity region 215 (having an extended portion) and an impurity concentration (on an impurity concentration) on a semiconductor substrate 213, as in the third embodiment. A charge multiplying region 217 (set independently), an output impurity region 219, a gate oxide film 221, a multiplying gate electrode 223, and a transfer gate electrode 225 are provided.

  In particular, in the present embodiment, as in the fifth embodiment, it is disposed between the gate oxide film 221 and the PD impurity region 215, the right end thereof is in contact with the charge multiplication region 217, and the central portion thereof is the PD. A surface / center impurity region 227 extending in the depth direction through the impurity region 215 is provided.

Therefore, in this embodiment, the same effect as the third embodiment and the fifth embodiment is obtained.
That is, the surface / center impurity region 227 (having the same composition as the surface / side impurity regions) has the above-described effect of “reducing fluctuations in the number of charges due to charge multiplication and reducing noise”. Play.

  Further, among the multiplication gate electrode 223, the charge multiplication region 217, the transfer gate electrode 225, the output impurity region 219, and the PD impurity region 215, an extended portion immediately below the charge multiplication region 217 is used as the semiconductor of the PD impurity region 215. Even in the case where the periphery of the portion reaching the surface of the substrate 213 is surrounded as viewed from above, the charge is increased from the PD impurity region 215 by the surface / center impurity region 227 formed in the depth direction in the central portion of the PD impurity region 215. It is possible to maintain the action of extracting the charge, which has a polarity opposite to the charge injected into the double region 217 and becomes a noise component, from the charge multiplication region 217.

[Ninth Embodiment]
Next, the ninth embodiment will be described, but the description of the same contents as those of the fourth and eighth embodiments will be omitted or simplified.

FIG. 25 is a cross-sectional view schematically showing a solid-state imaging device.
As shown in FIG. 25, the solid-state imaging device 231 of the ninth embodiment is similar to the fourth embodiment in that an extended portion (covering the charge multiplication region and reaching the gate oxide film is formed on the semiconductor substrate 233. PD impurity region 235, charge multiplication region 237 (impurity concentration is set independently), output impurity region 239, gate oxide film 241, multiplication gate electrode 243, and transfer gate electrode 245 And.

  In particular, in the present embodiment, like the eighth embodiment, it is disposed between the gate oxide film 241 and the PD impurity region 235, the right end thereof is in contact with the charge multiplication region 237, and the central portion thereof is the PD impurity. A surface / center impurity region 247 extending in the depth direction through the region 235 is provided.

Therefore, in this embodiment, the same effects as those in the fourth and eighth embodiments are obtained.
In addition, this invention is not limited to the said embodiment at all, and it cannot be overemphasized that it can implement with a various aspect in the range which does not deviate from this invention.

It is explanatory drawing explaining the principle of this invention. It is a block diagram which shows the solid-state imaging device of 1st Embodiment. It is sectional drawing which shows typically the solid-state image sensor of 1st Embodiment. It is a top view which shows typically the solid-state image sensor of 1st Embodiment. It is a schematic diagram which shows the charge multiplication process in 1st Embodiment. It is a timing diagram of the applied voltage drive to the gate electrode in the first embodiment. It is a top view which shows typically the solid-state image sensor of the application example 1 of 1st Embodiment. It is a top view which shows typically the solid-state image sensor of the application example 2 of 1st Embodiment. It is sectional drawing which shows typically the solid-state image sensor of 2nd Embodiment. It is a top view which shows typically the solid-state image sensor of 2nd Embodiment. It is a schematic diagram which shows the charge multiplication process in 2nd Embodiment. It is sectional drawing which shows typically the solid-state image sensor of 3rd Embodiment. It is a top view which shows typically the solid-state image sensor of 3rd Embodiment. It is a schematic diagram which shows the charge multiplication process in 3rd Embodiment. It is a timing diagram of the applied voltage drive to the gate electrode in the third embodiment. It is sectional drawing which shows typically the solid-state image sensor of 4th Embodiment. It is a top view which shows typically the solid-state image sensor of 4th Embodiment. It is a schematic diagram which shows the charge multiplication process in 4th Embodiment. It is sectional drawing which shows typically the solid-state image sensor of 5th Embodiment. It is a top view which shows typically the solid-state image sensor of 5th Embodiment. It is sectional drawing which shows typically the solid-state image sensor of 6th Embodiment. It is a top view which shows typically the solid-state image sensor of 6th Embodiment. It is sectional drawing which shows typically the solid-state image sensor of 7th Embodiment. It is sectional drawing which shows the solid-state image sensor of 8th Embodiment typically. It is sectional drawing which shows typically the solid-state image sensor of 9th Embodiment. It is explanatory drawing of a prior art.

Explanation of symbols

1, 51, 71, 91, 111, 131, 151, 171, 191, 211, 231, ... pixels (solid-state imaging device)
31, 55, 83, 93, 113, 133, 153, 173, 193, 213, 233... Semiconductor substrate 33, 53, 81, 95, 115, 135, 155, 175, 195, 215, 235... PD impurity region 35 , 59, 75, 97, 117, 137, 157, 177, 197, 217, 237 ... Charge multiplication regions 37, 63, 79, 99, 119, 139, 159, 179, 199, 219, 239 ... Output impurities Regions 39, 101, 121, 141, 161, 181, 201, 221, 241 ... Gate oxide films 41, 57, 73, 103, 123, 143, 163, 183, 203, 223, 243 ... multiplication gate electrode 43, 61, 77, 105, 125, 145, 165, 185, 205, 225, 245 ... transfer gate electrodes 167, 187 ... Surface / side impurity regions 227, 247 ... surface / center impurity region 207 ... epitaxial layer

Claims (17)

On the semiconductor substrate,
A gate oxide,
A PD impurity region forming a photodiode that generates charge by incident light; and
A multiplication gate electrode for multiplying the charge;
A charge multiplication region provided opposite to the multiplication gate electrode and for multiplying the charge generated in the PD impurity region by the multiplication gate electrode;
A transfer gate electrode for transferring the multiplied charge;
An output impurity region for outputting the transferred charge;
A solid-state imaging device having a pixel configuration including:
The multiplication gate electrode and the transfer gate electrode are disposed on the opposite side (hereinafter referred to as the upper surface side) of the gate oxide film, and the semiconductor substrate side (hereinafter referred to as the lower surface side) of the gate oxide film. The PD impurity region, the charge multiplication region, and the output impurity region are disposed,
The charge multiplication region is formed immediately below the multiplication gate electrode with the gate oxide film interposed therebetween, and an impurity diffusion region having an impurity concentration set independently of the surrounding impurity concentration. Wherein the impurity concentration is formed as the impurity diffusion region having an impurity concentration suitable for multiplying charges,
Furthermore, the PD impurity region, solid-state image sensor further comprising a portion adjacent to at least the charge multiplication regions as viewed from top. A portion of the PD impurity region reaching the surface of the semiconductor substrate is an n-gon when viewed from above.
The multiplication gate electrode, the charge multiplication region, the transfer gate electrode, and the output impurity region are the periphery of the portion of the n-shaped PD impurity region reaching the semiconductor substrate surface as viewed from above. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is formed so as to surround any one of sides 1 to (n−1). The at least the multiplication gate electrode and the charge multiplication region are formed so as to surround the entire periphery of the portion of the PD impurity region reaching the surface of the semiconductor substrate as viewed from above. the solid-state imaging device according to 1. The PD portion of the impurity region, the solid-state imaging device according to claim 1, characterized in that it is extended to just below the said multiplication gate electrode and the charge multiplication regions. A portion of the PD impurity region reaching the surface of the semiconductor substrate is an n-gon when viewed from above.
The multiplication gate electrode, the charge multiplication region, the transfer gate electrode, the output impurity region, and a portion of the PD impurity region that extends to directly below the charge multiplication region are the n 2. The rectangular portion of the PD impurity region formed so as to surround a portion of the PD impurity region reaching the surface of the semiconductor substrate so as to surround any one of sides 1 to (n-1) when viewed from above. 5. The solid-state imaging device according to 4 . At least the multiplication gate electrode, the charge multiplication region, and a portion of the PD impurity region that extends to a position immediately below the charge multiplication region is a portion of the PD impurity region that reaches the surface of the semiconductor substrate. The solid-state imaging device according to claim 4, wherein the solid-state imaging device is formed so as to surround the entire periphery when viewed from above. A part of the PD impurity region passes immediately below the charge multiplication region immediately below the multiplication gate electrode, and reaches the surface of the semiconductor substrate in the gap between the multiplication gate electrode and the transfer gate electrode. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is formed so as to extend to the surface. Of the PD impurity region, the portion reaching the semiconductor substrate surface excluding the portion extending to the semiconductor substrate surface in the gap between the multiplication gate electrode and the transfer gate electrode is an n-gonal shape when viewed from above.
The multiplication gate electrode, the charge multiplication region, the transfer gate electrode, the output impurity region, and the multiplication gate electrode and the transfer through the PD impurity region immediately below the charge multiplication region. The portion extending to the semiconductor substrate surface in the gap with the gate electrode extends to the semiconductor substrate surface in the gap between the multiplication gate electrode and the transfer gate electrode in the PD impurity region in the n-gonal portion. 8. The semiconductor device according to claim 7, wherein the semiconductor substrate is formed so as to surround any one of sides 1 to (n-1) when viewed from the upper surface around the portion of the semiconductor substrate surface excluding the portion. Solid-state imaging device. In the PD impurity region, an impurity region having a polarity opposite to that of the PD impurity region is formed on an upper surface side thereof and on a side surface along a lower surface direction of a peripheral portion that is not adjacent to the charge multiplication region when viewed from the upper surface. the solid-state imaging device according to any one of claims 1 to 6, characterized in that it comprises. The PD impurity region has a polarity opposite to that of the PD impurity region so as to be deeper than the depth of the PD impurity region toward the lower surface in the upper surface side and the central portion of the PD impurity region when viewed from the upper surface. the solid-state imaging device according to any one of claims 1 to 6, characterized in that it comprises an impurity region. Of the PD impurity region, the surface of the region reaching the semiconductor substrate surface excluding the portion extending to the semiconductor substrate surface in the gap between the multiplication gate electrode and the transfer gate electrode, and the region of the region as viewed from above 9. The solid according to claim 7 , wherein an impurity region having a polarity opposite to that of the PD impurity region is provided on a side surface along a lower surface direction of a peripheral portion not adjacent to the charge multiplication region. Imaging device. The multiplication gate electrode, the charge multiplication region, the transfer gate electrode, the output impurity region, and the multiplication gate electrode and the transfer through the PD impurity region immediately below the charge multiplication region. The portion extending to the surface of the semiconductor substrate in the gap with the gate electrode is a semiconductor excluding the portion of the PD impurity region extending to the surface of the semiconductor substrate in the gap between the multiplication gate electrode and the transfer gate electrode. A semiconductor formed so as to surround a region reaching the substrate surface as viewed from above and excluding a portion of the PD impurity region extending to the semiconductor substrate surface in the gap between the multiplication gate electrode and the transfer gate electrode When viewed from the surface and the upper surface of the region reaching the substrate surface, the distance from the center of the region toward the lower surface is greater than the depth of the PD impurity region. The solid-state imaging device according to claim 7 or 8, characterized in that it comprises an impurity region having a polarity. An epitaxial layer is laminated on the semiconductor substrate, and at least the PD impurity region, the charge multiplication region, and the output impurity region are formed on the upper surface side of the epitaxial layer. Item 13. The solid-state imaging device according to any one of Items 1 to 12 . It is a drive method of the solid-state image sensing device according to any one of claims 1 to 13 ,
A step of applying a voltage to the multiplication gate electrode to cause avalanche multiplication in the charge multiplication region when charges generated in the PD impurity region by the incident light are injected into the charge multiplication region;
Returning the voltage applied to the multiplication gate electrode to an initial value;
Applying a voltage to the transfer gate electrode to transfer the multiplied charge to the output impurity region;
A method for driving a solid-state imaging device, comprising: The step of applying a voltage to the multiplication gate electrode and the step of applying a voltage to the transfer gate electrode are driven at a timing such that a part of each step overlaps. The method for driving a solid-state imaging device according to claim 14 . The step of returning the applied voltage to the initial value after applying the voltage to the multiplication gate electrode and the step of applying the voltage to the transfer gate electrode are performed at a timing at which a part of each step overlaps. The solid-state imaging device driving method according to claim 14 , wherein the driving is performed after setting. The step of applying a voltage to the multiplication gate electrode and the step of returning the voltage applied to the multiplication gate electrode to an initial value are repeated until a predetermined signal intensity is obtained to control the charge multiplication factor. The method for driving a solid-state imaging device according to any one of claims 14 to 16 .