JP5321300B2 - Distortion compensation circuit and wireless transmission device using the same - Google Patents

Description

  The present invention relates to a distortion compensation circuit having a function of compensating for nonlinear characteristics of a high-power amplifier used in, for example, a radio transceiver, and a radio transmission apparatus using the same.

  In general, a highly efficient high power amplifier (HPA) has low linearity of input / output characteristics. Therefore, when power is amplified using such an amplifier, a desired output may not be obtained due to distortion of input / output characteristics. Therefore, in order to compensate for the distortion of such an amplifier, a distortion that is generated by digital signal processing and is applied to the input of the amplifier, the reverse distortion characteristic opposite to the distortion characteristic of the amplifier is applied to the input signal of the amplifier. A distortion compensation circuit that obtains a desired amplifier output by performing compensation processing has been proposed (see, for example, Non-Patent Document 1).

Thesis by Lei Ding, "Digital predistortion of power amplifiers for wireless application", Georgia institute of Technology, March 2004

The distortion compensation circuit is generally applied to an amplifying device for a wireless transmitter. This amplifying apparatus includes a distortion compensation circuit, a digital / analog converter (DAC) for converting a digital transmission signal into analog, a frequency converter for converting a transmission signal analog-converted by the DAC into a carrier frequency, And an amplifier that amplifies and outputs the frequency-converted transmission signal.
The distortion compensation circuit acquires a digital transmission signal (input signal) before being amplified by the amplifier, and also acquires a transmission signal (output signal) after being amplified by the amplifier as a digital signal. Is used to perform distortion compensation processing. Therefore, between the distortion compensation circuit and the amplifier, a frequency converter for converting an analog output signal into a baseband frequency from a carrier frequency in order to feed back an analog output signal as a digital output signal to the distortion compensation circuit. In addition, an analog / digital converter (ADC) or the like for converting an analog output signal into a digital signal is provided, and the distortion compensation circuit acquires the output signal via these.

  Here, in the distortion compensation performed by the distortion compensation circuit, distortion compensation cannot be performed accurately unless the acquired input signal and output signal match each other on the time axis. On the other hand, the distortion compensation circuit acquires an input signal included in a sampling interval that is an interval set with a predetermined time width, acquires an output signal corresponding to the sampling interval, and acquires these acquired input signals. And the output signal to synchronize the timing and then perform distortion compensation.

  However, the signals processed by the ADC, DAC, and frequency converter are affected by low frequency jitter caused by these devices, and fluctuations occur on the time axis. For this reason, between the input signal and the output signal that is the signal after the input signal has passed through the ADC, DAC, and frequency converter, fluctuations on the time axis due to the influence of jitter cause a sampling interval. Even in the case of included input / output signals corresponding to each other, there is a problem that timing advance and delay occur locally in the sampling interval.

  FIG. 4 is an example of a graph showing an input signal and an output signal included in the sampling period. In FIG. 4, the horizontal axis indicates time, and the vertical axis indicates amplitude. In the figure, comparing the profiles of both signals, a point k1 in the input signal corresponds to a point k2 in the output signal, and a point l1 in the input signal corresponds to a point l2 in the output signal. Here, when the shift width M1 between the points k1 and k2 is compared with the shift width M2 between the points l1 and l2, the shift width M1 is larger than the shift width M2. For this reason, both signals in the sampling interval do not have their entire profiles shifted in the time axis direction as they are, but the timing advance and delay are mixed locally in the sampling interval. I understand that.

  As shown in FIG. 4, when a timing shift occurs locally within the sampling interval, for example, even if the timing synchronization is achieved by relatively shifting both signals in the time axis direction, Therefore, it is difficult to synchronize the timing, which may reduce the accuracy of distortion compensation.

  The present invention has been made in view of such circumstances, and a distortion compensation circuit capable of performing distortion compensation with high accuracy even when there is a shift in the timing between input and output signals due to the influence of jitter. An object of the present invention is to provide a wireless transmission device used.

  (1) The present invention is a distortion compensation circuit for performing distortion compensation on input / output characteristics of an amplifier based on an input signal and an output signal of the amplifier, and the input signal included in a predetermined time width section And a synchronization processing unit that obtains the output signal and synchronizes timing between the input signal and the output signal, and the input signal and the output signal that are synchronized in timing by the synchronization processing unit. A model estimation unit that estimates a model representing the input / output characteristics of the amplifier, and performs distortion compensation of the amplifier by giving an input signal a characteristic opposite to the input / output characteristics using an inverse model of the model A synchronization compensator, wherein the synchronization processing unit sets a plurality of small sections having a time width shorter than the time width of the section in the section, and sets a timing for each of the plurality of small sections. It is characterized by performing the grayed synchronization.

  According to the distortion compensation circuit having the above-described configuration, the synchronization processing unit synchronizes the timing for each of the plurality of small sections having a time width shorter than the time width of the section, and therefore is interposed between the distortion compensation unit and the amplifier. Even if there is a local shift in the timing between the input signal and the output signal within the interval due to the influence of jitter caused by a digital / analog converter, an analog / digital converter, etc. The influence of slack can be suppressed as much as possible. As a result, the input / output characteristics of the amplifier can be estimated more accurately, and distortion compensation can be performed with high accuracy.

(2) Further, the synchronization processing unit may set the plurality of small sections by dividing the section into a plurality of sections, and in this case, the acquired input / output signals can be efficiently used. it can.
(3) Further, the synchronization processing unit generates a plurality of divided signals obtained by dividing one of the input signal and the output signal for each of the plurality of small sections, and timings of the plurality of divided signals. May be synchronized with the other of the input signal and the output signal.
In this case, the timing can be synchronized by sweeping each divided signal in the time axis direction with the other signal of the input signal and the output signal as a reference, and the input / output signals in the interval can be quickly Can be synchronized.

(4) Further, the present invention is a wireless transmission device including a transmitter having an amplifier and a distortion compensation circuit that performs distortion compensation on input characteristics of the amplifier, wherein the distortion compensation circuit is the above-described distortion compensation circuit. It is characterized by being.
According to the radio transmission apparatus having the above configuration, since the distortion compensation circuit described above is provided, the input / output characteristics of the amplifier can be estimated more accurately, and distortion compensation can be performed with high accuracy.

  As described above, according to the distortion compensation circuit of the present invention and the wireless transmission device using the same, even if the timing between the input and output signals is shifted due to the influence of jitter, the distortion compensation can be performed with high accuracy. it can.

1 is a circuit diagram showing a hardware configuration of an amplifying apparatus incorporating a distortion compensation circuit according to an embodiment of the present invention. It is a functional block diagram of the distortion compensation circuit which a digital processing part has functionally. It is a schematic diagram for demonstrating the aspect of the synchronous process which a synchronous process part performs. It is an example of the graph which shows the input signal and output signal which are included in a sampling area.

Next, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram showing an amplifying device portion in a wireless transmission device according to an embodiment of the present invention. The wireless transmission device MS includes an amplification device 1 for amplifying a transmission signal from a wireless transmitter or the like. The amplifying apparatus 1 includes a digital processing unit 2 that functionally includes the distortion compensation circuit (DPD) 20 and an analog processing unit 3 that includes a high-power amplifier (HPA).

The digital processing unit 2 applies a transmission signal as an input signal input to the amplifier 4 to the analog processing unit 3 as a digital signal, and acquires an output signal output from the amplifier 4 from the analog processing unit 3 as a digital signal.
In the analog processing unit 3, a digital / analog converter (DAC) 5, a low-pass filter (LPF) 6, and a first frequency conversion unit 7 are arranged between the digital processing unit 2 and the signal input terminal of the amplifier 4. It is connected. A digital input signal output from the digital processing unit 2 is converted into an analog signal and converted into a carrier frequency through these signals, and is then supplied to the amplifier 4.
An antenna 8 is connected to the output terminal of the amplifier 4, and an output signal output from the amplifier 4 is transmitted from the antenna 8 as a transmission signal.

The analog processing unit 3 includes a coupler 9 for obtaining an output signal of the amplifier 4, a second frequency conversion unit 10, a low-pass filter 11, between the signal output terminal of the amplifier 4 and the digital processing unit 2. An analog / digital converter (ADC) 12 is arranged and connected.
The output signal of the amplifier 4 is converted into a baseband frequency and digitally converted by passing through these signals, and then supplied to the digital processing unit 2.

FIG. 2 is a functional block diagram of a distortion compensation circuit functionally included in the digital processing unit 2.
The distortion compensation circuit 20 estimates the input / output characteristics of the amplifier 4 based on the input signal to the amplifier 4 and the output signal of the amplifier 4 acquired from the analog processing unit 3, and performs distortion compensation processing on the input / output characteristics. To obtain desired amplification characteristics, and an input signal buffer unit 21 for storing the input signal of the amplifier 4, an output signal buffer unit 22 for storing the output signal of the amplifier 4, A synchronization processing unit 23 that reads out the input signal and the output signal accumulated in both the buffer units 21 and 22 and synchronizes the timing of both signals is provided. The distortion compensation circuit 20 further includes a model estimation unit 24 that estimates a model representing input / output characteristics of the amplifier 4 using the input signal and the output signal that have been subjected to synchronization processing in the synchronization processing unit 23, and A distortion compensation unit 25 that performs distortion compensation based on the input / output characteristic model estimated by the model estimation unit 24 is provided.

  The distortion compensator 25 performs a distortion compensation process according to the input / output characteristics of the amplifier 4 on the transmission signal (the signal before distortion compensation) given to the amplifying apparatus 1 and inputs the input signal (after distortion compensation) to the amplifier 4 Output signal). The amplifier 4 is supplied with an input signal subjected to distortion compensation in advance from the distortion compensator 25. Therefore, the amplifier 4 can output an output signal without distortion (or with little distortion).

Here, the input / output characteristic of the amplifier 4 is a non-linear characteristic, and is expressed by, for example, a power series polynomial shown in the following formula (1). In the following formula (1), z is an output signal of the amplifier 4, y is an input signal of the amplifier 4, and a _i is a coefficient of each order.

Based on the above equation (1), the distortion compensator 25 calculates a power series polynomial shown in the following equation (2) to obtain the input signal y of the amplifier 4. In the following formula (2), a _i ′ is a coefficient of each order indicating the inverse characteristic of the amplifier.

As shown in the above formula (2), the distortion compensator 23 is based on each order coefficient a _i ′ indicating the inverse characteristic of the amplifier 4 as a model representing the input / output characteristic of the amplifier 4, and thereby the distortion characteristic of the amplifier 4. Is added to the signal x, and distortion compensation is performed by canceling distortion caused by the amplifier 4.

Each order coefficient a _i ′ indicating the inverse characteristic of the amplifier 4 in the above equation (2) is obtained by the model estimation unit 24. The model estimation unit 24 reads input / output signal data related to the input signal y and output signal z of the amplifier 4 given from the synchronization processing unit 23, and estimates a model representing the input / output characteristics of the amplifier 4 based on these. Then, the above-described respective coefficients a _i ′ as the estimated model are obtained.

The model estimation unit 24 has an amplifier model (inverse model) in which the input signal y is represented by a power series polynomial of the output signal z, and an input / output signal given from the synchronization processing unit 23 is applied to the model. The model is estimated. The model estimation unit 22 outputs each order coefficient, which is a value indicating the estimated model, to the distortion compensation unit 25 as each order coefficient a _i ′ indicating the inverse characteristic of the amplifier 4.

  The input signal buffer unit 21 accumulates the input signal supplied to the amplifier 4 for a sampling interval set as a predetermined time width interval, and outputs the accumulated input signal to the synchronization processing unit 23. Similarly to the input signal buffer unit 21, the output signal buffer unit 22 accumulates the output signal from the amplifier 4 for a sampling period having a predetermined time width, and outputs the accumulated output signal to the synchronization processing unit 23. To do. The output signal buffer unit 22 adjusts the timing for storing the output signal so as to store the output signal corresponding to the input signal stored in the input signal buffer unit 21.

The synchronization processing unit 23 acquires the input signal and the output signal included in the sampling period output from both the signal buffer units 21 and 22, and synchronizes the timing between the input signal and the output signal.
FIG. 3 is a schematic diagram for explaining an aspect of the synchronization processing performed by the synchronization processing unit. Here, the digital input signal supplied to the amplifier 4 and the digital output signal from the amplifier 4 are composed of a plurality of discrete data associated with time and amplitude, and input composed of a plurality of discrete data. The signal and the output signal are schematically shown in a band shape extending in the time axis direction (left and right direction on the paper).

  In the present embodiment, sampling is set, for example, at a frequency of 100 MHz and a section of about 100 μs. In this case, the number of discrete data included in the sampling section is about 10,000. The number of data necessary for the model estimation unit 24 of the present embodiment to perform model estimation is about 8000 points of the data, and the synchronization processing unit 23 is synchronized with timing of at least about 8000 points of data. An input / output signal is generated and output to the model estimation unit 24.

  When the synchronization processing unit 23 of the present embodiment acquires the output signal output from the output signal buffer unit 22 and included in the sampling period, a plurality of small sections having a time width shorter than the time width of the sampling period Is set within the sampling interval, and timing synchronization is performed for each of the plurality of small intervals.

  More specifically, as shown in FIG. 3, the synchronization processing unit 23 sets three subsections of the first subsection D1, the second subsection D2, and the third subsection D3 in the sampling section. Then, for each of these small sections, the output signal for the sampling section (and related discrete data) is divided to generate three divided signals S1 to S3.

  Next, the synchronization processing unit 23 synchronizes the timings of the three divided signals S1 to S3 with the input signals for the sampling period.

  The synchronization processing unit 23 individually processes each of the divided signals S1 to S3 so that the amplitude profile of each of the divided signals S1 to S3 and the amplitude profile of the input signal are most correlated. Sweep in the time axis direction while comparing with the amplitude profile. And the timing which can take a correlation between both most is acquired, and both are synchronized at the timing.

  Here, since the output signal buffer unit 22 adjusts the timing of storing the output signal so as to store the output signal corresponding to the input signal stored in the input signal buffer unit 21, each of the divided signals S1 to S3. in each, the timing synchronization can be established with respect to the input signal can be estimated whether any range previously. For this reason, the synchronization processing unit 23 estimates in advance a range to be swept in the time axis direction in order to obtain a correlation between the divided signals S1 to S3, and performs timing synchronization in the estimated range. In this case, for each of the divided signals S1 to S3, the divided signals are swept within a necessary range without comparing them over the entire area of the input signal, so that timing can be quickly synchronized.

  Note that the signals included in the portions T1, T2, and T3 that are not synchronized between the input signal and any one of the divided signals shown in FIG. 3 are not output to the model estimation unit 24, and distortion compensation is performed. It is never used.

As described above, after the timing of each of the divided signals S1 to S3 is synchronized with the input signal, the synchronization processing unit 23 outputs the input signal and each divided signal that are synchronized with each other to the model estimating unit 24. .
The model estimation unit 24 given the input signal and each divided signal that are synchronized with each other performs model estimation as described above.

Here, the path for outputting the input signal from the distortion compensation circuit 20 to the amplifier 4 includes a DAC 5, an LPF 6 and a first frequency converter 7 for processing the input signal, as shown in FIG. The second frequency conversion unit 10, the LPF 11, and the ADC 12 are interposed in the path for feeding back the output signal from the amplifier 4 to the distortion compensation circuit 20.
Therefore, the input signal that has passed through the distortion compensation circuit 20 is input to the amplifier 4 after passing through the DAC 5, the LPF 6, and the first frequency conversion unit 7 until it is fed back as an output signal. It passes through the unit 10, the LPF 11, and the ADC 12. For this reason, the output signal is affected by low frequency jitter caused by the DAC 5, the first frequency conversion unit 7, the second frequency conversion unit 10, and the ADC 12, and fluctuations occur on the time axis. Due to the influence of frequency jitter, timing advance and delay are mixed locally between the input signal and the output signal.

  In this regard, according to the distortion compensation circuit 20 of the present embodiment, the synchronization processing unit 23 synchronizes timing for each of the three small sections having a time width shorter than the time width of the sampling section. Even if a local deviation occurs in the timing between the input signal and the output signal in the sampling period due to the influence of jitter caused by the DAC 5 or ADC 12 interposed between the amplifier 4 and the like, the influence of the deviation is suppressed as much as possible. However, timing synchronization can be performed. As a result, the input / output characteristics of the amplifier 4 can be estimated more accurately, and distortion compensation can be performed with high accuracy.

  Further, in the present embodiment, the synchronization processing unit 23 sets a plurality of small sections by dividing the sampling section into a plurality of parts, so that the timing synchronization can be performed by efficiently using the acquired input / output signals. it can.

  Further, the synchronization processing unit 23 generates three divided signals S1 to S3 divided for each of the three small sections in which the output signal is set, and synchronizes the timing of each of the divided signals S1 to S3 with the input signal. Therefore, the timing can be synchronized by sweeping each of the divided signals S1 to S3 in the time axis direction with the input signal as a reference, and the timing of the input / output signals can be quickly synchronized within the sampling interval. .

  The present invention is not limited to the above embodiments. In the above embodiment, the output signal is divided into a plurality of divided signals and the timing of both signals is synchronized with the input signal as a reference. However, the input signal is divided into a plurality of divided signals and the output signal is used as a reference. It can also be configured to perform timing synchronization. Further, both the input signal and the output signal can be divided into a plurality of divided signals for each set subsection, and the timing can be synchronized between the divided signals belonging to the corresponding subsections. .

  With respect to the present invention, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is not meant to be described above, but is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

DESCRIPTION OF SYMBOLS 20 Distortion compensation circuit 23 Synchronization processing part 24 Model estimation part 25 Distortion compensation part MS radio transmitter

Claims (4)

A distortion compensation circuit that performs distortion compensation on input / output characteristics of an amplifier based on an input signal and an output signal of the amplifier,
A synchronization processing unit that acquires the input signal and the output signal included in a section of a predetermined time width, and synchronizes timing between the input signal and the output signal;
A model estimator for estimating a model representing input / output characteristics of the amplifier using the input signal and the output signal synchronized in timing with each other by the synchronization processing unit;
A distortion compensation unit that performs distortion compensation of the amplifier by giving an input signal a characteristic opposite to the input / output characteristic using an inverse model with respect to the model,
The synchronization processing unit is configured to set a plurality of small sections having a time width shorter than the time width of the section in the section and perform timing synchronization for each of the plurality of small sections ,
The model estimation unit and the distortion compensation unit perform the distortion compensation by estimating the model for each of the sections including the input signal and the output signal whose timing is synchronized for each of the plurality of small sections. A characteristic distortion compensation circuit.   The distortion compensation circuit according to claim 1, wherein the synchronization processing unit sets the plurality of small sections by dividing the section into a plurality of sections.   The synchronization processing unit generates a plurality of divided signals obtained by dividing one of the input signal and the output signal for each of the plurality of small sections, and the timing of each of the plurality of divided signals is input to the input signal. The distortion compensation circuit according to claim 1, wherein the distortion compensation circuit is synchronized with the other of the signal and the output signal. A wireless transmission device including an amplifier and a transmission unit having a distortion compensation circuit that performs distortion compensation on input characteristics of the amplifier,
The wireless transmission device according to claim 1, wherein the distortion compensation circuit is the distortion compensation circuit according to claim 1.

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