JP5315209B2 - 冗長構成を生成するための周辺機器相互接続入出力仮想化デバイスの使用 - Google Patents
冗長構成を生成するための周辺機器相互接続入出力仮想化デバイスの使用 Download PDFInfo
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- JP5315209B2 JP5315209B2 JP2009246376A JP2009246376A JP5315209B2 JP 5315209 B2 JP5315209 B2 JP 5315209B2 JP 2009246376 A JP2009246376 A JP 2009246376A JP 2009246376 A JP2009246376 A JP 2009246376A JP 5315209 B2 JP5315209 B2 JP 5315209B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/085—Retrieval of network configuration; Tracking network configuration history
- H04L41/0853—Retrieval of network configuration; Tracking network configuration history by actively collecting configuration information or by backing up configuration information
- H04L41/0856—Retrieval of network configuration; Tracking network configuration history by actively collecting configuration information or by backing up configuration information by backing up or archiving configuration information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0895—Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
- H04L41/0897—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities by horizontal or vertical scaling of resources, or by migrating entities, e.g. virtual resources or entities
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Hardware Redundancy (AREA)
- Storage Device Security (AREA)
Description
Claims (9)
- 冗長システム構成を生成するためのデータ処理システム実施方法であって、
各仮想機能について仮想機能パス許可テーブルを生成するステップであって、前記仮想機能パス許可テーブルは、当該仮想機能パス許可テーブルに関連付けられた仮想機能が複数のシステムにおける1組のアドレス範囲へアクセスする許可を得ているかを定義するエントリを複数有し、前記複数のエントリそれぞれが、無効な機能間アクセスを防止する境界をさらに定義し、前記仮想機能が、シングルルートまたはマルチルート周辺機器相互接続デバイスによって実行される、前記生成するステップと、
データをディスクに書き込むためのディスク書き込み動作のリクエスタからのディスク書き込み要求を受信して、要求されたデータを前記仮想機能から提供するステップと、
前記1組のアドレス範囲のうちの選択された第1のアドレス範囲内に第1の受信バッファを生成し、且つ、前記1組のアドレス範囲のうちの選択された第2のアドレス範囲内に第2の受信バッファを生成するステップであって、前記選択された第2のアドレスは、前記選択された第1のアドレスを有するシステムと異なるシステム上にある、前記生成するステップと、
前記仮想機能のための仮想機能作業待ち行列エントリを生成するステップであって、前記仮想機能作業待ち行列エントリは、前記第1の受信バッファ及び前記第2の受信バッファの各アドレスを含む、前記生成するステップと、
前記仮想機能パス許可テーブルにおいて、前記各選択されたアドレス範囲の使用を前記仮想機能が許可されているかどうかを判定するステップと、
前記仮想機能は許可されていることに応答して、前記要求されたデータを、前記第1の受信バッファ及び前記第2の受信バッファに書き込むステップと、
前記書き込みに応答して、前記リクエスタに完了通知を発行するステップと
を含む、前記方法。 - 前記仮想機能パス許可テーブル内にエントリが存在していることが、1次パスおよび対応する2次パスによる前記1つまたは複数のシステム内のシステムへの機能のアクセスを許可することである、請求項1に記載の方法。
- 前記仮想機能パス許可テーブル内にエントリが存在していないことが、1次パスおよび対応する2次パスによる前記1つまたは複数のシステム内のシステムへの機能のアクセスを許可しないことである、請求項1に記載の方法。
- 前記仮想機能パス許可テーブルが、各仮想機能と1組の仮想階層の間の対応、又は、各仮想機能と1組の論理パーティション内の1組のアドレス範囲の間の対応を含む、請求項1〜3のいずれか一項に記載の方法。
- 前記複数のエントリそれぞれが、前記仮想機能と前記複数のシステムのうちの一つのシステムにおけるアドレス範囲との間の1次通信パスと当該1次通信パスの代替通信パスとを有する、請求項1〜4のいずれか一項に記載の方法。
- 前記1次通信パスが優先パスであり、当該優先通信パスが利用不可能であることに応答して、前記代替通信パスの1つを使用する、請求項1〜5のいずれか一項に記載の方法。
- 冗長システム構成を生成するためのデータ処理システムであって、
バスと、
前記バスに接続されたコンピュータ実行可能命令を含むメモリと、
前記コンピュータ実行可能命令を実行する中央プロセッサ・ユニットであって、前記コンピュータ実行可能命令が、請求項1〜6のいずれか一項に記載の方法の各ステップを実行するように前記データ処理システムに指令する、前記中央プロセッサ・ユニットと、
を備えている、前記データ処理システム。 - 冗長システム構成を生成するためのデータ処理システムであって、
バスと、
前記バスに接続されたコンピュータ実行可能命令を含むメモリと、
前記コンピュータ実行可能命令を実行する中央プロセッサ・ユニットと
を備えており、
前記メモリが、
各仮想機能について仮想機能パス許可テーブルであって、前記仮想機能パス許可テーブルは、当該仮想機能パス許可テーブルに関連付けられた仮想機能が複数のシステムにおける1組のアドレス範囲へアクセスする許可を得ているかを定義するエントリを複数有し、前記複数のエントリそれぞれが、無効な機能間アクセスを防止する境界をさらに定義し、前記仮想機能が、シングルルートまたはマルチルート周辺機器相互接続デバイスによって実行される、前記仮想機能パス許可テーブルと、
前記仮想機能のための仮想機能作業待ち行列エントリであって、前記仮想機能作業待ち行列エントリは、前記1組のアドレス範囲のうちの選択された第1のアドレス範囲内に生成された第1の受信バッファ及び前記1組のアドレス範囲のうちの選択された第2のアドレス範囲内に生成された第2の受信バッファの各アドレスを含み、前記選択された第2のアドレスは、前記選択された第1のアドレスを有するシステムと異なるシステム上にある、前記仮想機能作業待ち行列エントリと、
を記憶し、
前記コンピュータ実行可能命令が、
データをディスクに書き込むためのディスク書き込み動作のリクエスタからのディスク書き込み要求を受信して、要求されたデータを前記仮想機能から提供することと、
前記仮想機能パス許可テーブルにおいて、前記各選択されたアドレス範囲の使用を前記仮想機能が許可されているかどうかを判定することと、
前記仮想機能は許可されていることに応答して、前記要求されたデータを、前記第1の受信バッファ及び前記第2の受信バッファに書き込むことと、
前記書き込みに応答して、前記リクエスタに完了通知を発行すること
を実行するように前記データ処理システムに指令する、
前記データ処理システム。 - 冗長システム構成を生成するためのコンピュータ・プログラムであって、
コンピュータに、請求項1〜6のいずれか一項に記載の方法の各ステップを実行させる、前記コンピュータ・プログラム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US12/332,957 US8346997B2 (en) | 2008-12-11 | 2008-12-11 | Use of peripheral component interconnect input/output virtualization devices to create redundant configurations |
US12/332957 | 2008-12-11 |
Publications (2)
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JP2010140471A JP2010140471A (ja) | 2010-06-24 |
JP5315209B2 true JP5315209B2 (ja) | 2013-10-16 |
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Country Status (3)
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US (1) | US8346997B2 (ja) |
JP (1) | JP5315209B2 (ja) |
KR (1) | KR101107408B1 (ja) |
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-
2008
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-
2009
- 2009-09-10 KR KR1020090085512A patent/KR101107408B1/ko not_active IP Right Cessation
- 2009-10-27 JP JP2009246376A patent/JP5315209B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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KR101107408B1 (ko) | 2012-01-19 |
US8346997B2 (en) | 2013-01-01 |
JP2010140471A (ja) | 2010-06-24 |
US20100153592A1 (en) | 2010-06-17 |
KR20100067601A (ko) | 2010-06-21 |
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