JP5310567B2 - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

Disclosed is a thin film transistor, which permits an application method having difficulty in shape control to be applied to and a channel length and a channel width to be easily controlled. A method for manufacturing such thin film transistor is also disclosed. A portion surrounded by a pair of source/drain electrodes (12, 13) and a pair of insulating thin films (17) serves as a channel. A semiconductor thin film (15) which forms the channel is formed of an organic material or carbon nanotubes or a mixed material containing carbon nanotubes.

Description

  The present invention relates to a thin film transistor (TFT) having an organic material or a carbon nanotube as a semiconductor layer, and more particularly to a thin film transistor having a small variation in transistor characteristics and a method for manufacturing the same.

  Thin film transistors are widely used as switching elements for display in liquid crystal display devices and the like. Conventionally, thin film transistors (hereinafter also referred to as TFTs) have been made using amorphous or polycrystalline silicon. However, a CVD (Chemical Vapor Deposition) apparatus used to make a TFT using such silicon is very expensive, and an increase in the size of a display apparatus using TFT is accompanied by a significant increase in manufacturing cost. There was a problem.

  In addition, since the process of forming an amorphous or polycrystalline silicon film is performed at a very high temperature, the types of materials that can be used as a substrate are limited. That is, there is a problem that a lightweight resin substrate cannot be used.

  In order to solve the above problems, TFTs using organic substances or carbon nanotubes instead of amorphous or polycrystalline silicon have been proposed. Vacuum deposition and coating methods are known as film formation methods used when forming TFTs with organic materials or carbon nanotubes. According to these film formation methods, the process temperature required for film formation is relatively low. Can be.

  For this reason, TFTs using organic substances or carbon nanotubes have the advantage that there are few restrictions when selecting materials used for the substrate, and their practical application is expected.

  In fact, in recent years, TFTs using organic substances have been actively reported. Non-patent documents 1 to 12 are examples of this.

  Examples of organic substances used in the organic compound phase of the TFT include multimers such as conjugated polymers and thiophenes (see Patent Documents 1 to 5), metal phthalocyanine compounds (see Patent Document 6), condensed aromatic hydrocarbons such as pentacene ( Patent Documents 7 and 8) are used in the form of a simple substance or a mixture with other compounds.

  On the other hand, TFTs using carbon nanotubes have also been actively announced, and Non-Patent Documents 13 and 14 show that they have silicon or silicon or better performance.

  In addition, by using organic materials and carbon nanotubes as the material for the semiconductor layer, not only hard materials such as glass can be used for the substrate of the device, but the entire device can be made flexible by applying resin or plastic. Research into flexible TFTs has been actively conducted.

  Furthermore, as a manufacturing process for organic or carbon nanotube TFTs, a coating process using a solution or dispersion can be adopted, so research on manufacturing methods applied to coating processes and printing processes aimed at reducing costs is also actively conducted. It has been broken.

Here, a cross-sectional structure of a typical organic or carbon nanotube TFT is shown in FIG. The TFT 110 includes a gate electrode (layer) 114 and an insulator layer 116 on a substrate 111 in this order, and includes a source electrode 112 and a drain electrode 113 formed on the insulator layer 116 with a predetermined interval. A semiconductor layer 115 is formed on the insulator layer 116 that includes the partial surfaces of both the electrodes 112 and 113 and is exposed between the electrodes 112 and 113. In the TFT 110 having such a configuration, the semiconductor layer 115 forms a channel region, and an on / off operation is performed by controlling a current flowing between the source electrode 112 and the drain electrode 113 with a voltage applied to the gate electrode 114. To do.
JP-A-8-228034 JP-A-8-228035 Japanese Patent Laid-Open No. 9-232589 Japanese Patent Laid-Open No. 10-125924 Japanese Patent Laid-Open No. 10-190001 JP 2000-174277 A JP-A-5-55568 JP 2001-94107 A Japanese Patent Laid-Open No. 2004-080026 F. Ebisawa et al., Journal of Applied Physics, 54, 3255, 1983 A. Assadi et al., Applied Physics Letter, 53, 195, 1988 G. Guillaud et al., Chemical Physics Letter, 167, 503, 1990 X. Peng et al., Applied Physics Letter, 57, 2013, 1990 G. Horowitz et al., Synthetic Metals, 41-43, 1127, 1991 S. Miyauchi et al., Synthetic Metals, 41-43, 1991 H. Fuchigami et al., Applied Physics Letter, 63, 1372, 1993 H. Koezuka et al., Applied Physics Letter, 62, 1794, 1993 F. Garnier et al., Science, 265, 1684, 1994 AR Brown et al., Synthetic Metals, 68, 65, 1994 A. Dodabalapur et al., Science, 268, 270, 1995 T. Sumimoto et al., Synthetic Metals, 86, 2259, 1997 K. Kudo et al., Thin Solid Films, 331, 51, 1998 K. Kudo et al., Synthetic Metals, 102, 900, 1999 K. Kudo et al., Synthetic Metals, 111-112, 11 pages, 2000

In the case where the TFT 110 is to be manufactured uniformly and without variation, the channel length (the distance between the source electrode and the drain electrode) and the channel width (the length of contact between each electrode and the channel-constituting semiconductor layer) are changed between the TFTs. If they cannot be made identical, it is very difficult to make the characteristics of the manufactured TFTs identical.
In order to keep the TFT performance constant, channel material deposition control is also important, but electrode manufacturing control for determining channel length and channel width is also very important.

  In particular, when applying a coating method in which an electrode material and a channel material are produced from a solution or a dispersion, it is very difficult to control the shape of the bent part and the terminal part of the electrode. This causes variations in channel length and channel width, particularly variations in channel width, and causes variations in TFT characteristics. In addition, when the channel material is applied over a wide range, the plane of the TFT is in a state like the TFT 110 shown in FIG. 2, and the application shape is elliptical or indeterminate, so it is difficult to control the application range. This is directly linked to the difficulty in controlling the channel length and channel width.

Patent Document 9 discloses a technique for forming an organic semiconductor material uniformly by providing an insulating film on a source electrode and a drain electrode.
However, in the structure of the invention disclosed in Patent Document 9, the channel width cannot be controlled even though the channel length can be controlled.

  The present invention has been made in view of such problems, and it is possible to apply a coating method in which shape control is difficult, and to provide a thin film transistor in which channel length and channel width can be easily controlled, and a method for manufacturing the same. Objective.

  In order to achieve the above object, the present invention provides, as a first aspect, a semiconductor thin film that forms a channel in a region surrounded by a pair of source / drain electrodes and a pair of insulating thin films that intersect with the pair. The present invention provides a thin film transistor characterized by being formed of an organic material or a carbon nanotube or a mixture containing carbon nanotubes.

  In order to achieve the above object, the present invention provides, as a second aspect, an organic material, a carbon nanotube, or a carbon nanotube in a region surrounded by a pair of source / drain electrodes and a pair of insulating thin films intersecting with them. The present invention provides a method for manufacturing a thin film transistor, characterized by providing a channel formed of a mixture containing nanotubes.

  According to the present invention, it is possible to provide a thin film transistor that can be applied with a coating method whose shape control is difficult, and that can easily control the channel length and the channel width, and a method for manufacturing the same.

  The thin film transistor according to the present invention is a thin film transistor having a source electrode and a drain electrode, and a semiconductor thin film forming a channel with a portion sandwiched between a pair of source / drain electrodes and a pair of insulating thin films intersecting with the organic thin film as an organic It is characterized by being formed of a material or a carbon nanotube or a mixture containing carbon nanotubes. In this structure, a TFT having a controlled size can be obtained by setting the distance between the source electrode or the drain electrode as the channel length and the length of the electrode sandwiched between the insulating thin films as the channel width.

If the pair of source / drain electrodes do not cross each other, the TFT characteristics can be exhibited no matter how they are arranged. However, considering the arrangement of a plurality of source / drain electrodes and combinations with various other functional elements, they are parallel. It is preferable to arrange in. For the same reason, it is preferable to arrange the pair of insulating thin films in parallel. Further, by arranging the pair of source / drain electrodes and the pair of insulating thin films at right angles, the effect of unnecessary carrier components can be eliminated.
With such an arrangement, it is possible to realize an ideal TFT in which the source electrode and the drain electrode facing the source electrode are present at the shortest distance regardless of the portion.

In addition, a semiconductor layer that forms a channel may be provided over the source electrode, the drain electrode, the insulating thin film, or depending on the stacked structure, respectively.
In a transistor using an organic material, a carbon nanotube, or a mixture containing carbon nanotubes, a carrier conducted in a channel is a carrier injected from a source electrode unlike a silicon semiconductor. Therefore, the amount of carriers injected into the channel can be controlled by controlling the channel width, and the outside of the region where the semiconductor layer constituting the channel is surrounded by the pair of source or drain electrodes and the insulating thin film Even if present in the transistor, the transistor characteristics are not greatly affected.

  However, if the area of one semiconductor layer exists outside the pair of insulating thin films and the pair of insulating thin films are in contact with the outer source electrode or drain electrode, carrier injection also occurs from there. However, an increase in carriers, that is, an increase in drain current is caused to cause variation in device characteristics. For this reason, it is necessary not to contact the area of the semiconductor layer constituting the channel with the source electrode or the drain electrode located outside the pair of insulating thin films.

  Note that the TFT characteristics can be obtained regardless of the contact type (top contact type, bottom contact type) and gate type (top gate type, bottom gate type), but the source or drain electrode, the channel semiconductor layer, In order to control the length of contact (channel width), it is necessary to form an insulating thin film between the channel semiconductor layer and the source / drain electrodes. Specifically, in the case where the TFT 20 is a bottom gate bottom contact type element, as shown in FIG. 3, a gate electrode 14 as a third electrode, a gate insulating film 16, a pair of source / drain electrodes 12, 13, and a pair The insulating thin film 17 and the semiconductor thin film 15 constituting the channel need to be laminated on the substrate 11 in this order.

  Similarly, when the TFT 20 is a bottom gate top contact type element, as shown in FIG. 4, a gate electrode 14 as a third electrode, a gate insulating film 16, a semiconductor thin film 15 constituting a channel, and a pair of insulating thin films. 17, it is necessary to laminate the source / drain electrodes 12 and 13 on the substrate 11 in this order. When the TFT 20 is a top gate / bottom contact type device, as shown in FIG. 5, a pair of source / drain electrodes 12 and 13, a pair of insulating thin films 17, a semiconductor thin film 15 constituting a channel, and a gate insulating film 16 are provided. The gate electrode 14 as the third electrode needs to be stacked on the substrate 11 in this order. Further, in the case where the TFT 20 is a top gate top contact type element, as shown in FIG. 6, a semiconductor thin film 15, a pair of insulating thin films 17, a pair of source / drain electrodes 12 and 13, and a gate insulating film 16 constituting a channel. The gate electrode 14 as the third electrode needs to be stacked on the substrate 11 in this order.

  The TFT structure to which the present invention is applied is a structure in which the channel length and the channel width can be manufactured uniformly, and is not limited to the process of forming each constituent material. Therefore, it can be formed by a general thin film manufacturing method such as vacuum deposition, sputtering, or coating.

  Hereinafter, preferred embodiments of the present invention will be described.

  FIG. 7 shows the configuration of the TFT according to this embodiment. As shown in FIG. 7, the TFT 20 includes a pair of source electrode 12 and drain electrode 13, and includes an insulating thin film 17 that intersects with the source electrode 12 and the drain electrode 13. Regardless of the shape of the ends of the electrodes 12 and 13 and the channel layer 15 of any shape, only the region surrounded by the electrodes 12 and 13 and the insulating thin film 17 acts as a channel, and thus has a certain characteristic. A TFT is obtained.

  The material that can be used as the substrate 11 is not particularly limited as long as it is a material that can hold a TFT formed thereon, such as an inorganic material such as glass or silicon, or a plastic such as an acrylic resin. In addition, when the TFT structure can be sufficiently supported by components other than the substrate, a substrate-less structure can be used.

  Examples of materials that can be used for the source electrode 12, the drain electrode 13, and the gate electrode 14 include indium tin oxide (ITO), tin oxide, gold, silver, platinum, copper, indium, aluminum, and magnesium. In addition to metals and alloys such as magnesium-indium alloy, magnesium-aluminum alloy, aluminum-lithium alloy, aluminum-scandium-lithium alloy, and magnesium-silver alloy, organic materials such as conductive polymers can be mentioned. Is not to be done.

  The compound contained in the semiconductor layer 15 has semiconductor characteristics such as condensed polycyclic aromatic compounds such as tetracene and pentacene, phthalocyanine compounds such as copper phthalocyanine and zinc phthalocyanine, polymers such as amine compounds, polythiophene and polyvinylcarbazole. The organic compound or the carbon nanotube and the mixture containing the carbon nanotube can be used, but the material is not particularly limited as long as the material has semiconductor characteristics.

  As materials that can be used for the gate insulating film 16 and the insulating thin film 17, in addition to inorganic compounds such as silicon dioxide film and silicon nitride film, organic insulating materials such as acrylic resin and polyimide can be used. The material of these films is applicable as long as it has electrical insulation, and is not limited to a specific material.

  As a method for forming the electrodes 12, 13, and 14, known electrode forming processes such as vacuum deposition, sputtering, etching, and lift-off can be used, and the method is not limited to a specific method. In addition, when using an organic material such as a conductive polymer, a silver paste or a dispersion containing metal particles, or a metal organic compound as an electrode, a spin coating method, a dip method, a dispenser method, an ink jet method, etc. A solution process can also be utilized and is not limited to a particular method.

  As a method for forming the gate insulating film 16 and the insulating thin film 17, solution processes such as a spin coating method, a dip method, a dispenser method, and an ink jet method can be used in addition to a dry process such as a vacuum evaporation method and a sputtering method. It is not limited to a specific method.

  The film thickness of the semiconductor thin film layer 15 in the TFTs 30a to 30d is not particularly limited. However, in general, if the film thickness is too thin, defects such as pinholes are likely to occur. Conversely, if the film thickness is too thick, the channel length becomes long or a high applied voltage is required, which causes deterioration in TFT performance. The range of several nm to 1 μm is preferable.

  The film thickness of the insulating thin film 17 is not particularly limited. In the case of the bottom gate bottom contact type, it is possible to use it as a partition wall when forming a channel by increasing the film thickness. In the case of other structures, if the film thickness is excessively large, it becomes difficult to form an electrode, a gate insulating film, a gate electrode, or the like to be formed later, and to maintain the necessary characteristics. Further, since it is only necessary to cut off the contact between the source or drain electrode and the channel material, it is desirable that the range be from several tens of nm to several hundreds of nm.

  In addition, since the TFT according to the present invention has a structure for controlling a region in which the source or drain electrode and the semiconductor layer are in direct contact with each other, the TFT has a structure having an insulating thin film between the source or drain electrode and the semiconductor layer. For example, the order of laminating these parts and other constituent members is arbitrary.

  EXAMPLES Hereinafter, although this invention is demonstrated in detail based on an Example, this invention is not limited to a following example, unless it deviates from the summary.

The organic TFT 20 shown in FIG. 7 was prepared by the following procedure.
First, chromium was formed into a film having a thickness of 100 nm on a glass substrate 11 by a vacuum deposition method to form a gate electrode 14. Next, a silicon dioxide film having a thickness of 200 nm was formed on the gate electrode 14 by sputtering, and this was used as the insulator layer 16. Further, two nano-silver colloid solutions are formed on the insulator layer 16 with a line width of 200 μm and an interval of 200 μm using a dispenser device, and heated at 150 ° C. for 30 minutes to form the source electrode 12 and the drain electrode 13. did.

  Subsequently, two polymethyl methacrylate solutions were formed with a line width of 200 μm and an interval of 1000 μm using a dispenser device, and heated at 120 ° C. for 30 minutes to form an insulating thin film 17.

  Subsequently, four drops of the poly (3-hexyl) thiophene solution having a diameter of 500 μm are applied to a region surrounded by the source electrode 12, the drain electrode 13, and the insulating thin film 17 using a dispenser device, and the semiconductor layer 15. And TFT 101 was obtained.

  Twenty TFTs were produced by the same manufacturing method, current values were measured when the gate voltage was −20 V and the drain voltage was −10 V, and the ratio between the maximum current and the minimum current was calculated. As a result, the value of the ratio was 1.13, which was a favorable value as compared with Comparative Example 1.

[Comparative Example 1]
A TFT was formed in the same manner as in Example 1 except that the insulator thin film 17 was not formed. For the prepared TFT, the ratio between the maximum value and the minimum value of the current value measured under the same conditions as in Example 1 was 10.9.

  A TFT was produced in the same manner as in Example 1 except that the compounds shown in Table 1 were used as the semiconductor material, and TFTs 103 to 106 were obtained. For the fabricated TFTs 103 to 106, the ratio between the maximum value and the minimum value of the current values measured under the same conditions as in Example 1 was the result shown in Table 1, respectively. For any TFT, the ratio between the maximum current value and the minimum current value was good.

First, chromium was formed into a film having a thickness of 100 nm on a glass substrate 11 by a vacuum deposition method to form a gate electrode 14. Next, a silicon dioxide film having a thickness of 200 nm was formed on the gate electrode 14 by sputtering, and this was used as the insulator layer 16. Subsequently, 4 drops of a poly (3-hexyl) thiophene solution having a diameter of 500 μm are applied using a dispenser device to form a semiconductor layer 15. Polymethylmethacrylate is then formed on the semiconductor layer 15 using a dispenser device. Two solutions with a line width of 200 μm and an interval of 1000 μm were formed and heated at 120 ° C. for 30 minutes to form an insulating thin film 17.
Further, two nano silver colloidal solutions are formed on the semiconductor layer 15 and the insulating thin film 17 at a line width of 200 μm and an interval of 200 μm by using a dispenser device in a shape orthogonal to the insulating thin film 17, and at 150 ° C. for 30 minutes. The source electrode 12 and the drain electrode 13 were formed by heating, and the TFT 107 was obtained.

  Twenty TFTs were manufactured by the same manufacturing method, and current values at a gate voltage of −20 V and a drain voltage of −10 V were measured, and a ratio between the maximum current and the minimum current was calculated. As a result, the ratio was 1.08, and a good value was obtained as compared with Comparative Example 2.

[Comparative Example 2]
A TFT was produced in the same manner as in Example 3 except that the insulating thin film 17 was not formed, and a TFT 108 was obtained.
For the manufactured organic TFT 108, the ratio of the maximum value and the minimum value of the current value measured under the same conditions as in Example 3 was 15.2.

  A TFT was produced in the same manner as in Example 3 except that the compounds shown in Table 2 were used as the semiconductor material, and TFTs 109 to 112 were obtained. For the fabricated TFTs 109 to 112, the ratio between the maximum value and the minimum value of the current value measured under the same conditions as in Example 3 was as shown in Table 2, respectively. The ratio between the maximum current value and the minimum current value was good for any TFT.

  First, four drops of poly (3-hexyl) thiophene solution having a diameter of 500 μm are applied onto a substrate 11 made of polyethylene naphthalate using a dispenser device to form a semiconductor layer 15. Using an apparatus, two polymethyl methacrylate solutions were formed with a line width of 200 μm and an interval of 1000 μm, and heated at 120 ° C. for 30 minutes to form an insulating thin film 17.

  Next, two nano-silver colloidal solutions are formed on the semiconductor layer 15 and the insulating thin film 17 at a line width of 200 μm and an interval of 200 μm using a dispenser device in a shape orthogonal to the insulating thin film 17 and 30 at 150 ° C. The source electrode 12 and the drain electrode 13 were formed by partial heating. Subsequently, a silicon dioxide film having a thickness of 200 nm was formed thereon by sputtering, and this was used as the insulator layer 16. Finally, gold was formed into a film having a thickness of 100 nm by a vacuum evaporation method to form a gate electrode 14 to obtain a TFT 113.

Twenty TFTs were produced by the same manufacturing method, and the voltage values when the gate voltage was −20 V and the drain voltage was −10 V were measured, and the ratio between the maximum current and the minimum current was calculated. As a result, the value of the ratio was 1.24, and an excellent value was obtained as compared with Comparative Example 3.

[Comparative Example 3]
A TFT was produced in the same manner as in Example 5 except that the insulating thin film 17 was not formed, and a TFT 114 was obtained. For the manufactured TFT 114, the ratio of the maximum value and the minimum value of the current values measured under the same conditions as in Example 5 was 9.87.

  A TFT was produced in the same manner as in Example 5 except that the compounds shown in Table 3 were used as the semiconductor material, and TFTs 115 to 118 were obtained. For the fabricated TFTs 115 to 118, the ratio between the maximum value and the minimum value of the current values measured under the same conditions as in Example 5 was as shown in Table 3, respectively. For any TFT, the ratio between the maximum current value and the minimum current value was good.

  First, two nanosilver colloidal solutions are formed on a polyethylene naphthalate substrate 11 using a dispenser device at a line width of 200 μm and an interval of 200 μm, and heated at 150 ° C. for 30 minutes to form a source electrode 12 and a drain electrode 13. Formed. Next, using a dispenser device, two polymethyl methacrylate solutions are formed at positions perpendicular to the electrodes 12 and 13 with a line width of 200 μm and a spacing of 1000 μm, and heated at 120 ° C. for 30 minutes, thereby insulating thin film 17. Formed. Subsequently, 4 drops of a poly (3-hexyl) thiophene solution having a diameter of 500 μm are applied to a region surrounded by the source electrode 12, the drain electrode 13, and the insulating thin film 17 using a dispenser device, and the semiconductor layer 15 is applied. Formed.

  On these, a silicon dioxide film was formed to a thickness of 200 nm by sputtering, and this was used as the insulator layer 16. Finally, gold was deposited with a film thickness of 100 nm by a vacuum deposition method to form the gate electrode 14 to obtain a TFT 119.

  Twenty TFTs were produced by the same method, and the current values when the gate voltage was −20 V and the drain voltage was −10 V were measured, and the ratio between the maximum current and the minimum current was calculated. As a result, the value of the ratio was 1.65, and a good value was obtained as compared with Comparative Example 4.

[Comparative Example 4]
A TFT was produced in the same manner as in Example 7 except that the insulating thin film 17 was not formed, and a TFT 120 was obtained. For the produced organic TFT 120, the ratio between the maximum value and the minimum value of the current value measured under the same conditions as in Example 7 was 20.8.

  A TFT was produced in the same manner as in Example 7 except that the compound shown in Table 4 was used as the semiconductor material, and TFTs 121 to 124 were obtained. For the fabricated TFTs 121 to 124, the ratio between the maximum value and the minimum value of the current values measured under the same conditions as in Example 7 was as shown in Table 4, respectively. The ratio between the maximum current value and the minimum current value was good for any TFT.

  In addition, said embodiment is an example of suitable implementation of this invention, This invention is not limited to this, A various deformation | transformation is possible.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-009556 for which it applied on January 18, 2008, and takes in those the indications of all here.

It is a figure which shows the cross-sectional structure of a general TFT. It is a figure which shows the planar structure of a general TFT. It is a figure which shows the cross-sectional structure at the time of comprising TFT concerning this invention by a bottom gate bottom contact type | mold. It is a figure which shows the cross-sectional structure at the time of comprising TFT concerning this invention by a bottom gate top contact type | mold. It is a figure which shows the cross-sectional structure at the time of comprising TFT concerning this invention by a top gate bottom contact type | mold. It is a figure which shows the cross-sectional structure at the time of comprising TFT concerning this invention by a top gate top contact type | mold. It is a figure which shows the structure of TFT which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Substrate 12 Source electrode 13 Drain electrode 14 Gate electrode 15 Semiconductor layer 16 Insulator layer 17 Insulating thin film 20 TFT

Claims (18)

A pair of insulating thin films surrounded by a pair of source / drain electrodes and a semiconductor thin film,
A site surrounded by the pair of source / drain electrodes and the pair of insulating thin films intersecting with the pair is a channel,
A thin film transistor, wherein the semiconductor thin film forming the channel is formed of an organic material, a carbon nanotube, or a mixture containing carbon nanotubes.   2. The thin film transistor according to claim 1, wherein the pair of source / drain electrodes are arranged in parallel.   3. The thin film transistor according to claim 1, wherein the pair of insulating thin films are arranged in parallel.   4. The thin film transistor according to claim 1, wherein the pair of source / drain electrodes and the pair of insulating thin films are orthogonal to each other. 5.   A gate electrode as a third electrode, a gate insulating film, the pair of source / drain electrodes, the pair of insulating thin films, and a semiconductor thin film constituting the channel are stacked in this order from the substrate side. The thin film transistor according to any one of claims 1 to 4.   The pair of source / drain electrodes, the pair of insulating thin films, the semiconductor thin film constituting the channel, the gate insulating film, and the gate electrode as the third electrode are stacked in this order from the substrate side. The thin film transistor according to any one of claims 1 to 4.   A semiconductor thin film that constitutes the channel, the pair of insulating thin films, the pair of source / drain electrodes, a gate insulating film, and a gate electrode as a third electrode are stacked in that order from the substrate side. The thin film transistor according to any one of claims 1 to 4.   9. The thin film transistor according to claim 1, wherein the semiconductor thin film constituting the channel is formed on the basis of a solution or dispersion containing a channel constituting semiconductor material.   10. At least one of a gate electrode, a gate insulating film, the source electrode, the drain electrode, and an insulating thin film is formed based on a solution or a dispersion liquid. The thin film transistor according to any one of the above.   A method of manufacturing a thin film transistor, characterized in that a channel formed of an organic material or carbon nanotubes or a mixture containing carbon nanotubes is provided in a portion surrounded by a pair of source / drain electrodes and a pair of insulating thin films intersecting with them .   12. The method of manufacturing a thin film transistor according to claim 11, wherein the pair of source and drain electrodes are arranged in parallel.   13. The method of manufacturing a thin film transistor according to claim 11, wherein the pair of insulating thin films are arranged in parallel.   14. The method of manufacturing a thin film transistor according to claim 11, wherein the pair of source / drain electrodes and the pair of insulating thin films are arranged so as to be orthogonal to each other.   3. A gate electrode as a third electrode, a gate insulating film, the pair of source / drain electrodes, the pair of insulating thin films, and a semiconductor thin film constituting the channel are stacked in order from the substrate side. Item 15. The method for producing a thin film transistor according to any one of Items 11 to 14.   The pair of source / drain electrodes, the pair of insulating thin films, the semiconductor thin film constituting the channel, a gate insulating film, and a gate electrode as a third electrode are stacked in order from the substrate side. Item 15. The method for producing a thin film transistor according to any one of Items 11 to 14.   The semiconductor thin film constituting the channel, the pair of insulating thin films, the pair of source / drain electrodes, the gate insulating film, and the gate electrode as the third electrode are laminated in order from the substrate side. Item 15. The method for producing a thin film transistor according to any one of Items 11 to 14.   19. The method of manufacturing a thin film transistor according to claim 11, wherein the semiconductor thin film constituting the channel is formed based on a solution or dispersion containing a channel constituting semiconductor material.   The gate electrode, the gate insulating film, the source electrode, the drain electrode, or the insulating thin film is formed on the basis of a solution or a dispersion liquid. The manufacturing method of the thin-film transistor of any one of Claims 1.

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