JP5300814B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

As the semiconductor device is miniaturized, the parasitic capacitance of the copper wiring becomes equal to the input / output capacitance of the transistor itself, which hinders the speeding up of the element operation. Therefore, it has been actively studied to introduce an insulating film having a relative dielectric constant lower than that of conventional silicon oxide (SiO ₂ , relative dielectric constant k≈4). However, when the relative dielectric constant k is decreased, the mechanical strength of the insulating film is deteriorated. In particular, when the relative dielectric constant k is smaller than 3.5, a sufficient mechanical strength cannot be secured, which is a problem. Hereinafter, in the present invention, a film having a relative dielectric constant k smaller than 3.5 is referred to as a “low dielectric constant film”.

  In a thermal cycle test after packaging a semiconductor device, for example, the temperature is changed from −65 ° C. to 150 ° C., so that the low dielectric film receives stress from the resin portion, and as a result, the low dielectric film peels off. There was a case. As the mechanical strength of the low dielectric film is weaker, the peeling becomes more prominent. In terms of location, peeling is particularly noticeable near the chip corner where stress is concentrated.

  In general, a chip of a semiconductor device deteriorates the operation characteristics of the device when moisture enters the inside. Therefore, a chip is called a seal ring (also referred to as a “guard ring”) in order to prevent moisture from entering from the outer peripheral side surface of the chip. A pattern is formed. As a seal ring, metal parts such as contacts and wirings used in the chip are arranged in the vertical direction, and these layers are connected by a metal groove-like structure to form a metal wall. It is arranged in a closed loop shape. The seal ring has a quadrangular shape along the outer periphery at a predetermined interval from the outer periphery of the chip when seen in a plan view.

  As described above, when the low dielectric constant film is destroyed by the stress received from the resin, the cracks eventually develop and reach the seal ring. When the crack reaches the seal ring, the seal ring is easily broken. Once the seal ring is broken, moisture penetrates into the chip, which hinders device operation. In an extreme example, the crack progresses as much as 500 μm, and the wiring inside the chip may be cut directly.

  Several techniques have been proposed to prevent cracks from breaking the seal ring. For example, in US Pat. No. 6,365,958B1 (Patent Document 1), a plurality of layers of lattice wirings are arranged in the vertical direction, and the lattice wirings adjacent to each other in the vertical direction are connected by metal vias. Is disposed outside the seal ring as a sacrificial pattern for stopping the progress of cracks. In US Pat. No. 5,572,067 (Patent Document 2), a lower layer wiring parallel to the direction from the corner of the chip toward the center intersects with an upper layer wiring perpendicular to the chip and is connected to each other by a via. It is disclosed that a corner structure is arranged at a chip corner portion. In US Patent Application Publication No. US2004 / 0002198A1 (Patent Document 3), a dummy metal pattern using a non-rectangular seal ring and connecting lower layer wiring and upper layer wiring in a lattice shape at the chip corner portion of the seal ring is disclosed. It is disclosed to place it on both sides of the seal ring.

  Japanese Patent Application Laid-Open No. 2004-172169 (Patent Document 4) discloses that a reinforcing pattern in which a lower layer wiring and an upper layer wiring are connected by a via or a wall-shaped reinforcing pattern made of copper is arranged in the vicinity of a chip corner. Yes.

US Patent US 6,365,958B1 US Pat. No. 5,572,067 US Patent Application Publication No. US2004 / 0002198A1 JP 2004-172169 A

  As described above, even if a structure serving as a sacrificial pattern is arranged in the vicinity of the chip corner by the respective proposed techniques, the seal ring cannot be sufficiently prevented from being broken by the crack. In addition, if the sacrifice pattern is too large, there is a problem that an area for arranging a circuit or the like becomes narrow.

  Therefore, an object of the present invention is to provide a semiconductor device that can prevent the seal ring destruction due to a crack more efficiently and strongly.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device including a low dielectric constant film having a relative dielectric constant of less than 3.5, and is a moisture shielding wall having a closed loop shape in plan view. One or more seal rings are provided, and at least one of the seal rings includes a seal ring convex portion in the vicinity of the chip corner, and the seal ring convex portion has a convex shape inside the closed loop shape, An outer seal ring which is a moisture shielding wall having a closed loop shape when viewed in plan and surrounds the seal ring is further provided, and the seal ring and the outer seal ring are separated when viewed in plan.

  According to the present invention, since the seal ring collides with a crack that progresses so as to spread from the chip corner as a starting point, the seal ring collides with a shape closer to the shape drawn by the actual crack tip. Can be prevented.

It is the fragmentary sectional view of the semiconductor device shown in order to demonstrate the advancing state of the crack which inventors found. It is the fragmentary top view of the semiconductor device shown in order to demonstrate the advancing state of the crack which inventors found. It is the 1st explanatory view of the nature of the crack which inventors found. It is the 2nd explanatory view of the nature of the crack which inventors found. It is a fragmentary top view of the semiconductor device in Embodiment 1 based on this invention. It is a fragmentary sectional view of the semiconductor device in Embodiment 1 based on this invention. It is a fragmentary sectional view of the other example of the semiconductor device in Embodiment 1 based on this invention. It is a fragmentary top view of the further another example of the semiconductor device in Embodiment 1 based on this invention. It is a fragmentary top view of the semiconductor device in Embodiment 2 based on this invention. It is a fragmentary top view of the semiconductor device in Embodiment 3 based on this invention. It is a fragmentary top view of the semiconductor device in Embodiment 4 based on this invention. It is a fragmentary top view of the semiconductor device in Embodiment 5 based on this invention. It is a fragmentary top view of the semiconductor device in Embodiment 6 based on this invention.

  First, prior to making the present invention, the inventors examined in detail how cracks occurred. The actual occurrence of cracks as a result will be described with reference to FIGS. FIG. 1 shows a cross-sectional view in the vicinity of a chip corner of a semiconductor device. A silicon oxide film 101, a silicon carbonitride film 102, a silicon oxide film 103, a silicon carbonitride film 104a, a low dielectric constant film 105a, a silicon carbonitride film 104b, and a low dielectric constant film 105b are arranged on the semiconductor device substrate 100 in order from the bottom. The silicon carbonitride film 104c, the low dielectric constant film 105c, the silicon carbonitride film 104d, the silicon oxide film 106, the silicon carbonitride film 104e, the silicon oxide film 107a, the silicon oxide film 107b, and the silicon nitride film 108 are stacked. A contact 110 is disposed so as to penetrate the silicon oxide film 101. Copper wiring 111 is arranged on the upper side of silicon oxide film 101. An interlayer connection portion 112 is provided so as to penetrate the low dielectric constant film 105a and connect to the copper wiring 111 from above. A copper wiring 113 is arranged so as to be embedded in the low dielectric constant film 105 a above the interlayer connection portion 112. Further, the interlayer connection part 114, the copper wiring 115, the interlayer connection part 116, and the copper wiring 117 are arranged in this order while repeating in the same manner. An interlayer connection portion 118 is disposed so as to penetrate the silicon oxide film 106 and connect to the copper wiring 117 from above. A copper wiring 119 is arranged so as to be embedded in the silicon oxide film above the interlayer connection portion 118. Interlayer connection portion 120 is arranged so as to penetrate through silicon oxide film 107a and to be connected to copper wiring 119 from above. Aluminum wiring 121 is arranged on the upper side of interlayer connection portion 120. The aluminum wiring 121 is disposed so as to be placed on the upper side of the silicon oxide film 107a and is covered with the silicon oxide film 107b. A silicon nitride film peeling prevention groove 122 is provided near the end of the chip so as to dig out the silicon oxide film 107b and the silicon nitride film. The contact 110 to the aluminum wiring 121 form a wall shape and constitute a seal ring 123 for preventing moisture intrusion.

  In the thermal cycle test, a force is applied in the direction of arrow 2 by being pulled by contraction of a resin (not shown) covering the upper side. Since the low dielectric constant film has low mechanical strength, the crack 1 is generated starting from the chip corner. As a result of examining the cracks in the low dielectric constant film in detail, the inventors have found the following.

  First of all, it was found that crack 1 is likely to occur particularly at the lower interface of the low dielectric constant film. Further, the inventors have found that the crack 1 has the highest probability of occurring in the lowest dielectric constant film among the plurality of low dielectric constant films.

  Secondly, the actual state of the shape of the crack when viewed in plan was clarified. A plan view of this semiconductor device is shown in FIG. In the conventional way of thinking, it was thought that the tip of the crack starting from the chip corner 4 proceeds in the direction of the arrow 20 in a state of a straight line 22 that forms an angle of 45 ° with each of two sides sandwiching the chip corner 4. The inventors have found that the tip of the crack actually progresses so as to spread from the broken line 24a to the broken line 24b in the direction of the arrow 21 instead of a simple straight line.

  Thirdly, the crack is generated not only at the lower interface of the low dielectric constant film 105a as shown in FIG. 3 and progressing along the interface as it is, but also at the point of progress as shown in FIG. It has also been found that when the copper wiring 111 that completely blocks the low dielectric constant film 105a is encountered, it travels over the upper side of the copper wiring 111 and further proceeds along the low dielectric constant film 105b.

Based on these findings, the present invention has been made.
(Embodiment 1)
(Constitution)
With reference to FIGS. 5 and 6, the semiconductor device according to the first embodiment of the present invention will be described. This semiconductor device is a semiconductor device including low dielectric constant films 105a, 105b, and 105c having a relative dielectric constant of less than 3.5, and includes a seal ring 123 that is a moisture shielding wall having a closed loop shape when seen in a plan view. At least one of the seal rings 123 includes the seal ring convex portion 10 that is inwardly convex in the vicinity of the chip corner 4. Even if the seal ring convex portion 10 has a convex shape inwardly in the vicinity of the chip corner 4, a temporary effect can be obtained, but here, as a more preferable configuration, two chip end faces 5 sandwiching the chip corner 4 are provided. 6 has a seal ring hypotenuse 9 that forms an approximately equal angle with respect to 6 and faces the tip corner 4. The seal ring convex portion 10 can obtain a temporary effect only by having the seal ring oblique side 9, but here, as a more preferable configuration, the first side parallel to the two chip end faces 5 and 6 sandwiching the chip corner 4 is used. 7 and second side 8.

  This semiconductor device includes a sacrificial pattern 124 that is a wall-like structure for preventing the progress of cracks on the outside of the seal ring convex portion 10 when viewed from the center of the chip. FIG. 6 shows a cross-sectional view taken along the line VI-VI in FIG. The sacrificial pattern 124 may have a configuration in which the upper portion of the seal ring 123 is eliminated, that is, a configuration in which a wall similar to the seal ring 123 is formed only in portions corresponding to the layers of the low dielectric constant films 105a, 105b, and 105c. The sacrificial pattern 124 to be a wall for preventing the progress of cracks has a structure in which a plurality of wiring layers are connected vertically at an interlayer connection portion. Each interlayer connection part included in the sacrificial pattern 124 is not a hole-shaped member but a groove-shaped member.

  The sacrificial pattern 124 may have a structure that reaches the same height as the seal ring 123, that is, the layer of the aluminum wiring, as shown in FIG. Alternatively, for example, the sacrificial pattern 124 may be extended upward in the configuration of FIG. 6 so that the sacrificial pattern 124 exists at the same height as the wiring 119, that is, an intermediate configuration between FIG. 6 and FIG.

  The effects of the present invention can be obtained if there are at least one sacrificial pattern 124, but it is preferable that there are a plurality of sacrificial patterns 124. In the example of FIG. 5, the sacrificial pattern group 3 is configured by providing a plurality of sacrificial patterns 124. . The sacrificial pattern group 3 includes a linear sacrificial pattern 13 in addition to a plurality of polygonal sacrificial patterns 124. Each of the polygonal line sacrificial patterns 124 has a sacrificial side 11 of the sacrificial pattern which forms an angle substantially equal to the two chip end faces 5 and 6 sandwiching the chip corner 4 and faces the chip corner 4. The sacrificial pattern hypotenuse 11 is longer as it is closer to the center of the chip.

(Action / Effect)
In the present embodiment, at least one of the seal rings 123 includes the seal ring convex portion 10 that protrudes inward in the vicinity of the chip corner 4, and thus proceeds from the chip corner 4 as a starting point. As a result, the seal ring collides with a crack closer to the shape drawn by the actual crack tip. As a result, the progress of the crack can be prevented more efficiently. Furthermore, in the present embodiment, the seal ring convex portion 10 has the seal ring hypotenuse 9, so that the seal ring 123 stands up in parallel with the hypotenuse part at the center of the advancing crack tip. Therefore, the seal ring 123 is not easily broken by the crack. Further, in the present embodiment, since the seal ring convex portion 10 has the first side 7 and the second side 8, the seal ring 123 is resistant to cracks that progress like the broken lines 24a and 24b shown in FIG. It will be arrange | positioned in parallel in each place and will become stronger with respect to a crack.

  In the present embodiment, since the sacrificial pattern 124 is arranged, a crack that progresses so as to spread from the chip corner 4 reaches the sacrificial pattern 124 before reaching the seal ring 123 and is prevented from progressing. Become. Since the sacrificial pattern 124 is a metal structure that is formed in a wall shape as a whole using the groove-like interlayer connection portion, the crack that has progressed along the lower interface of a certain low dielectric constant film However, even if it hits a wiring layer with a sacrificial pattern 124 and rides on the upper low dielectric constant film, further progress can be prevented.

  In the present embodiment, a plurality of sacrificial patterns 124 are provided as shown in FIG. 5. However, if a plurality of sacrificial patterns 124 are provided in this manner, even if the cracks destroy some of the sacrificial patterns 124, they proceed further inside. Even if it does, the probability that the progress of the crack is stopped before the crack reaches the seal ring 123 is increased. Further, in the present embodiment, preferably, each of the sacrificial patterns 124 has the sacrificial pattern hypotenuse 11, so that the sacrificial pattern 124 stands parallel to the line drawn by the crack tip. Therefore, the sacrificial pattern 124 can more effectively prevent the progress of cracks. Further, as the crack progresses toward the center of the chip, the hypotenuse part formed by the crack tip becomes longer as shown in FIG. 2, but the sacrificial pattern hypotenuse 11 is formed at the tip center as in the semiconductor device in the present embodiment. If it is arranged so as to become longer as it approaches, the sacrificial pattern hypotenuse 11 that has become longer with respect to the hypotenuse of the tip of the crack will come into contact with each other as the crack progresses. To be able to hinder.

  Particularly in the preferred configuration as shown in FIG. 5, the cracks reach the seal ring 123 only after all the sacrificial patterns 124 have been destroyed, so that the sacrificial patterns 124 arranged in a limited area work. Can be used most effectively.

In the example shown in FIG. 5, the sacrificial pattern group 3 includes a plurality of linear sacrificial patterns 13 and a plurality of polygonal sacrificial patterns 124, but instead of the sacrificial pattern group 3, FIG. As shown, it may be a sacrificial pattern group 14 in which only a plurality of linear sacrificial patterns 13 are arranged in parallel.
In this case, the line drawn by the tip of the developing crack and the shape of the sacrificial pattern do not necessarily completely coincide with each other, but the effect of preventing the progress by a plurality of sacrificial patterns 13 rising one after another against the progressing crack. Has the advantage of being easy to design. The sacrificial pattern 13 also has a sacrificial pattern hypotenuse 11.

  In the region surrounded by the seal ring convex portion 10, a configuration in which only one linear sacrificial pattern 13 is arranged instead of a sacrificial pattern group, a configuration in which only one polygonal sacrificial pattern 124 is arranged, Although the configuration in which only two linear sacrificial patterns 13 and one broken line sacrificial pattern 124 are arranged in total is also less effective in suppressing crack progression than the above-described example, the technology of the present invention It is within the range intended by the philosophy.

  The plurality of sacrificial patterns 124 included in the sacrificial pattern group 3 are preferably arranged so that the sacrificial pattern oblique side 11 becomes longer as the sacrificial pattern 124 closer to the center of the chip. The sacrificial patterns 124 of the sacrificial patterns 124 are not limited to the case where the sacrificial patterns 124 are arranged in this order. Can be obtained. Therefore, it can be said that at least some of the plurality of sacrificial patterns are preferably arranged so that the sacrificial side of the sacrificial pattern becomes longer as the sacrificial pattern is closer to the center of the chip.

(Embodiment 2)
(Constitution)
With reference to FIG. 9, a semiconductor device according to the second embodiment of the present invention will be described. In this semiconductor device, a sacrificial pattern group 12 composed of a plurality of sacrificial patterns is arranged in a region outside the seal ring convex portion 10 when viewed from the center of the chip. The sacrificial pattern group 12 includes a closed loop sacrificial pattern 23. In the example shown in FIG. 9, particularly preferably, the sacrificial pattern group 12 includes a plurality of closed-loop sacrificial patterns 23, and the plurality of closed-loop sacrificial patterns 23 are arranged concentrically. The sacrificial pattern included in the sacrificial pattern group 12 is parallel to the seal ring 123 near the seal ring 123. Of the plurality of sacrificial patterns included in the sacrificial pattern group 12, a portion close to the chip corner 4 is a linear sacrificial pattern 13. The structure of other parts is the same as that described in the first embodiment.

(Action / Effect)
In the present embodiment, since the closed loop sacrificial pattern 23 is included, it is possible to prevent moisture from entering the region surrounded by the sacrificial pattern 23. A low dielectric constant film is very easy to permeate moisture as compared with a silicon oxide film or the like. The mechanical strength of the low dielectric constant film is further deteriorated if moisture enters, but the moisture does not enter inside the closed loop sacrificial pattern 23 unless the sacrificial pattern 23 is destroyed. Deterioration can be prevented, and the progress of cracks can be suppressed. Particularly, when a plurality of closed-loop sacrificial patterns 23 are arranged concentrically, it is preferable because the outermost sacrificial pattern 23 can collectively form a wide area without entering moisture. Even if the outer closed-loop sacrificial pattern is destroyed, if one or more closed-loop sacrificial patterns remain inside, moisture intrusion can be prevented in some regions.

  In the present embodiment, the semiconductor device includes the sacrificial pattern group 12. However, even if only one closed-loop sacrificial pattern is arranged instead of the sacrificial pattern group 12, the semiconductor device is compared with the above example. However, some effects can be obtained although the effects are inferior.

(Embodiment 3)
(Constitution)
With reference to FIG. 10, a semiconductor device according to the third embodiment of the present invention will be described. This semiconductor device corresponds to the double seal ring in the example shown in FIG. 8 in the first embodiment. That is, this semiconductor device includes a seal ring 123a and a seal ring 123b. A sacrificial pattern group 14 in which a plurality of linear sacrificial patterns 13 are arranged in parallel is disposed outside the seal ring 123a as viewed from the center of the chip. Each sacrificial pattern 13 is arranged so as to form an angle substantially equal to the two chip end faces 5 and 6 sandwiching the chip corner 4 and to face the chip corner 4.

(Action / Effect)
In the present embodiment, since the seal rings are multiplexed, the probability that the seal ring closest to the center of the chip is destroyed when the crack progresses and the operation of the device is hindered can be kept low.

  In the present embodiment, the seal ring is doubled, but the number is not limited to double, and may be triple or more. However, it should also be noted that increasing the number of seal rings reduces the area available within the seal ring. In the present embodiment, a configuration in which seal rings are multiplexed in the example of FIG. 8 is shown, but the same idea can be applied to other configurations. For example, seal rings may be multiplexed in the examples of FIGS. The seal ring may be multiplexed in the examples of FIGS.

(Embodiment 4)
(Constitution)
With reference to FIG. 11, a semiconductor device according to the fourth embodiment of the present invention will be described. This semiconductor device includes a sacrificial pattern group 17 composed of a plurality of sacrificial patterns. The sacrificial pattern group 17 includes an internal sacrificial pattern group 16 including a plurality of sacrificial patterns 13 including a sacrificial pattern oblique side 11 which forms an angle substantially equal to the two chip end faces 5 and 6 sandwiching the chip corner 4 and faces the chip corner 4. The inner sacrificial pattern group 16 is arranged so as to surround from the outside, and includes a substantially L-shaped sacrificial pattern 15 including two sides parallel to the two chip end faces 5 and 6 sandwiching the chip corner 4.

(Action / Effect)
In this embodiment, since the L-shaped sacrificial pattern 15 is provided, even if an initial crack is generated on the chip end faces 5 and 6 when the wafer is diced, the L-shaped sacrificial pattern 15 can be suppressed to some extent. If the initial crack is the starting point and the crack progresses toward the center of the chip during the thermal cycle test, the plurality of sacrificial patterns 13 included in the internal sacrificial pattern group 16 suppress the progress of the crack. Thus, the combination of the L-shaped sacrificial pattern 15 and the internal sacrificial pattern group 16 is effective in suppressing the progress of cracks. In the example of FIG. 11, one L-shaped sacrificial pattern 15 is used, but the L-shaped sacrificial pattern 15 may be double or more. Further, the example of FIG. 11 has a configuration in which the L-shaped sacrificial pattern 15 is combined with the example of FIG. 8, but an L-shaped sacrificial pattern may be combined with other embodiments.

(Embodiment 5)
(Constitution)
With reference to FIG. 12, a semiconductor device according to the fifth embodiment of the present invention will be described. This semiconductor device corresponds to a configuration in which an external seal ring 25 is added to the example shown in FIG. 8 in the first embodiment. That is, this semiconductor device includes a sacrificial pattern group 14 composed of a plurality of sacrificial patterns 13, but is closed loop when viewed in plan so as to surround the sacrificial pattern group 14 and the seal ring 123 from the outside of the sacrificial pattern group 14. An external seal ring 25 that is a moisture shielding wall is provided. Although only a part of the semiconductor device is shown in FIG. 12, the external seal ring 25 is also connected to a part not shown, and is arranged in a closed loop along the outline of the entire semiconductor device.

(Action / Effect)
In the present embodiment, since the external seal ring 25 is provided, even if an initial crack is generated on the chip end surfaces 5 and 6 when the wafer is diced, the external seal ring 25 can suppress the crack to some extent. Therefore, the same effect as in the fourth embodiment can be obtained. Furthermore, since the outer seal ring 25 also plays a role of protecting the inner region from moisture ingress, it is possible to prevent the mechanical strength of the inner region from the outer seal ring 25 from being reduced by moisture ingress.

  In the example of FIG. 12, the external seal ring 25 surrounds the sacrificial pattern group 14 and the seal ring 123, but even if there is only one sacrificial pattern instead of the sacrificial pattern group 14, the external seal ring 25 is similarly externally connected. A seal ring may be provided.

  In the example of FIG. 12, the number of the outer seal rings 25 is one, but the number of the outer seal rings 25 may be double or more. Further, the example of FIG. 12 has a configuration in which the external seal ring 25 is combined with the example of FIG. 8, but an external seal ring may be combined with other embodiments.

(Embodiment 6)
(Constitution)
With reference to FIG. 13, a semiconductor device according to the sixth embodiment of the present invention will be described. This semiconductor device includes a sacrificial pattern group 19. This semiconductor device corresponds to the sacrificial pattern group 14 in the example of FIG. The sacrificial pattern group 19 is similar to the sacrificial pattern group 14, but includes a coupling layer 18 connected to each other. The sacrifice pattern group 19 is also basically a collection of individual sacrifice patterns. In the example of FIG. 13, the sacrifice pattern group 19 is a collection of a plurality of linear sacrifice patterns 26. The sacrificial pattern 26 includes a plurality of wiring layers as viewed in the thickness direction. In the example of FIG. 13, the sacrificial patterns 26 are connected to each other in at least one of the plurality of wiring layers. A layer in which the sacrificial patterns are connected in this way is referred to as a “connection layer” 18. It can be said that the sacrificial pattern group 19 is an aggregate of a plurality of sacrificial patterns 26 connected to each other via the connecting layer 18.

(Action / Effect)
In the present embodiment, since the sacrificial patterns 26 are connected to each other by the coupling layer 18, the sacrificial pattern group 19 as a whole can be increased in strength, and the ability to resist the progress of cracks is further improved.

  It is preferable that the coupling layer 18 has a mesh shape when viewed in plan as in the example shown in FIG. This is because the overall strength can be increased efficiently by such a configuration. Note that the coupling layer may be a single layer or a plurality of layers.

  It should be noted that the sacrificial pattern is preferably arranged so as to block the lower layer of the low dielectric constant film as can be said in common to all the embodiments so far. The “low dielectric constant film in the lowest layer” refers to one layer when there is only one low dielectric constant film. Since cracks are likely to occur in the lowermost layer of the low dielectric constant film, if the sacrificial pattern is disposed so as to block the lower dielectric layer film in the lowermost layer, the crack is reduced in FIG. The same phenomenon that reaches the seal ring 123 after progressing along the lower interface will occur between the crack and the sacrificial pattern. That is, the effect is particularly remarkable in suppressing the progress of cracks. It is preferable that the sacrificial pattern is disposed so as to block the lower interface of the low dielectric constant film that is the lowest layer.

  Even in a semiconductor device including a plurality of low dielectric constant films, the present invention can provide a remarkable effect. In a semiconductor device including a plurality of low dielectric constant films, the sacrificial pattern is preferably arranged so as to block all of the plurality of low dielectric constant films. As described with reference to FIG. 4, when the crack reaches the wiring layer while progressing, the crack climbs onto the upper layer and continues to proceed. However, it is preferable that the sacrificial pattern is arranged so as to block all of the plurality of low dielectric constant films, since even if the cracks run up by one, it can be effectively suppressed.

  Furthermore, as can be said in common to all of the embodiments so far, the sacrificial pattern is preferably arranged separately from the seal ring in plan view. In all of the figures shown so far, the sacrificial pattern was arranged separately from the seal ring in plan view, but when the sacrificial pattern is broken and peeled off, It is possible to reduce the probability of occurrence of a situation in which the seal ring is peeled off by being pulled by the displacement of the portion.

  In each of the above embodiments, when referring to the postures of the seal ring hypotenuse 9 and the sacrificial pattern hypotenuse 11 and the like, “the angles are substantially equal to the two chip end faces 5 and 6 sandwiching the chip corner 4. Although the expression is used, for example, when the chip corner 4 is a right angle, not only means that the posture is at an angle of 45 ° with respect to the two chip end faces 5 and 6, but 40 to The case where the angle is 50 ° is also included. That is, for example, a situation in which the tilt is 40 ° with respect to the chip end surface 5 and 50 ° with respect to the chip end surface 6 is also included. However, it is most preferable to make an angle of approximately 45 ° with respect to both of the chip end faces 5 and 6. This is because it is possible to face the proceeding crack more precisely from the front.

  In addition, the said embodiment disclosed this time is an illustration in all the points, Comprising: It is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

  1 Crack, 2 (indicating the direction of shrinkage), 3, 12, 14, 17, 19 Sacrificial pattern group, 4 Chip corner, 5, 6 Chip end face, 7 First side, 8 Second side, 9 Seal ring hypotenuse 10 seal ring convex part, 11 sacrificial pattern hypotenuse, 13, 26 (straight) sacrificial pattern, 15 L-shaped sacrificial pattern, 16 internal sacrificial pattern group, 25 external seal, 18 connecting layer, 20, 21 Arrow indicating progress) 22 (representing crack tip), 23 (closed loop) sacrificial pattern, 24a, 24b (representing crack tip) broken line, 25 external seal ring, 100 semiconductor substrate, 101, 103, 106, 107a, 107b Silicon oxide film, 102, 104a, 104b, 104c, 104d, 104e Silicon carbonitride film, 105a, 105b 105c, low dielectric constant film, 108 silicon nitride film, 110 contact, 111, 113, 115, 117, 119 copper wiring, 112, 114, 116, 118, 120 interlayer connection part, 121 aluminum wiring, 122 silicon nitride film peeling prevention Groove, 123, 123a, 123b Seal ring, 124 (folded linear) sacrificial pattern.

Claims (34)

A semiconductor device including a low dielectric constant film having a relative dielectric constant of less than 3.5, and including one or more seal rings that are moisture shielding walls that are closed-loop when viewed in plan,
At least one of the seal rings includes a seal ring convex portion in the vicinity of the tip corner, and the seal ring convex portion has a convex shape inside the closed loop shape,
An outer seal ring that is a moisture shielding wall that is closed loop when viewed in plan and surrounds the seal ring;
The semiconductor device, wherein the seal ring and the external seal ring are separated in plan view. The seal ring convex portion has a sealing ring hypotenuse opposite the equal correct an angle and the tip corner for the two chip end face sandwiching the chip corner, the semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein the seal ring convex portion has a first side and a second side parallel to two chip end faces sandwiching the chip corner.   A sacrificial pattern, which is a wall-like structure for preventing the development of cracks, is provided outside the seal ring convex portion as viewed from the center of the chip, and the sacrificial pattern is provided between the seal ring and the outer seal ring. The semiconductor device according to claim 1, wherein: is formed. The sacrificial pattern have the sacrificial pattern hypotenuse opposite the equal correct an angle and the tip corner two chip end face sandwiching the chip corner, the semiconductor device according to claim 4.   The semiconductor device according to claim 4, comprising a sacrificial pattern group including a plurality of the sacrificial patterns. A plurality of sacrificial pattern contained in the sacrificial pattern group has a sacrificial pattern hypotenuse opposite the equal correct an angle and the tip corner two chip end face sandwiching the chip corner respectively, the semiconductor device according to claim 6 .   8. The semiconductor device according to claim 7, wherein at least a part of the plurality of sacrificial patterns is arranged such that the sacrificial side of the sacrificial pattern becomes longer as the sacrificial pattern is closer to the center of the chip.   The semiconductor device according to claim 4, wherein the sacrificial pattern is a closed loop sacrificial pattern.   8. The semiconductor device according to claim 6, wherein the sacrificial pattern group includes a closed loop sacrificial pattern.   8. The semiconductor device according to claim 6, wherein the sacrificial pattern group includes a plurality of closed-loop sacrificial patterns, and the plurality of closed-loop sacrificial patterns are arranged concentrically. The sacrificial pattern group, and the internal sacrificial pattern group including a sacrificial pattern hypotenuse opposite the equal correct an angle and the tip corner two chip end face sandwiching the chip corner, so as to surround the internal sacrificial pattern group from the outside It is disposed, and a L-shaped sacrificial patterns of unrealized L-shaped with each of the two chip end face parallel two sides sandwiching the chip corner, the semiconductor device according to claim 6.   The semiconductor device according to claim 6, wherein the plurality of sacrificial patterns include coupling layers connected to each other.   The semiconductor device according to claim 13, wherein the connection layer has a mesh shape when seen in a plan view.   15. The semiconductor device according to claim 4, wherein the sacrificial pattern is disposed so as to block a lower dielectric constant film in a lowermost layer.   The semiconductor device according to claim 4, wherein a plurality of the low dielectric constant films are included, and the sacrificial pattern is disposed so as to block all of the plurality of low dielectric constant films. A silicon nitride film covering the upper surface of the semiconductor device and the seal ring;
The semiconductor device according to claim 4, wherein a groove is formed in the silicon nitride film between the seal ring and the chip end surface.   The semiconductor device according to claim 4, wherein the sacrificial pattern is arranged separately from the seal ring and the external seal ring in plan view. A semiconductor substrate;
A first insulating layer formed on the semiconductor substrate;
A second insulating layer formed on the first insulating layer and including a low dielectric constant film having a relative dielectric constant of 3.5 or less;
A third insulating layer formed on the second insulating layer;
A seal ring formed in the first insulating layer, the second insulating layer, and the third insulating layer and having a closed loop shape when seen in a plan view,
The seal ring has a seal ring convex portion in the vicinity of the corner of the chip,
At least between the first insulating layer and the second insulating layer, the seal ring convex portion has a convex shape inside the closed loop shape,
The relative dielectric constant of the low dielectric constant film is smaller than the relative dielectric constant of the first insulating layer,
An outer seal ring that is a moisture shielding wall that is closed loop when viewed in plan and surrounds the seal ring;
The semiconductor device, wherein the seal ring and the external seal ring are separated in plan view.   The semiconductor device according to claim 19, wherein the seal ring has a quadrangular shape along the outer periphery of the chip when seen in a plan view.   The semiconductor device according to claim 19, wherein the seal ring convex portion is formed so as to prevent the progress of a crack caused between the first insulating layer and the second insulating layer. It further has a wall-shaped sacrificial pattern formed so as to prevent the development of cracks,
The sacrificial Pa Tan viewed from the center of the chip, provided outside of the seal ring convex portion,
The sacrificial pattern is formed between the seal ring and the outer seal ring,
The semiconductor device according to claim 19, wherein the sacrificial pattern is arranged separately from the seal ring and the external seal ring in plan view. The seal ring is a moisture barrier;
The seal ring convex portion has a sealing ring hypotenuse facing the two form an equal correct angle relative to tip end face and the tip corner of sandwiching a corner of the chip, the semiconductor device according to claim 19.   The semiconductor device according to claim 19, further comprising a resin that covers the chip. A semiconductor substrate;
A first insulating layer formed on the semiconductor substrate;
A second insulating layer formed on the first insulating layer and including a low dielectric constant film having a relative dielectric constant of 3.5 or less;
A third insulating layer formed on the second insulating layer;
A seal ring formed in the first insulating layer, the second insulating layer, and the third insulating layer and having a closed loop shape when seen in a plan view,
The seal ring is
A first side formed along the end surface of the first chip;
A second side of one end and the end of the first side is connected, is formed on the second chip end face and the flat row,
A third side of the other end and one end of the second side are electrically connected, is formed on the first chip end face and the flat row,
The other end and one end of the third side are connected, and the fourth side is formed along the second chip end surface,
The first side, the second side, the third side and the fourth side are present at least between the first insulating layer and the second insulating layer,
The relative dielectric constant of the low dielectric constant film is smaller than the relative dielectric constant of the first insulating layer,
A corner portion of the chip is formed by the first chip end surface and the second chip end surface,
The seal ring includes a seal ring convex portion in the vicinity of a corner of the chip,
The seal ring convex portion has a convex shape inside the closed loop shape,
The seal ring convex portion has the second side and the third side,
An outer seal ring that is a moisture shielding wall that is closed loop when viewed in plan and surrounds the seal ring;
The semiconductor device, wherein the seal ring and the external seal ring are separated in plan view.   26. The semiconductor device according to claim 25, wherein the seal ring has a quadrangular shape along the outer periphery of the chip when seen in a plan view.   26. The semiconductor device according to claim 25, wherein the second side and the third side are formed so as to prevent the development of a crack caused between the first insulating layer and the second insulating layer. Further comprising a sacrificial path Tan formed wall shape so as to prevent the development of cracks, the sacrificial Pa Tan viewed from the center of the chip, provided in farther than the second side and third side, The semiconductor device according to claim 25.   26. The semiconductor device according to claim 25, wherein the seal ring is a moisture blocking wall.   26. The semiconductor device according to claim 25, wherein an upper side of the chip is covered with a resin. The seal ring further includes a fifth side to which the other end and the other end of the second side are connected, and to which one end and the other end of the third side are connected,
The fifth side has a constant correct angle relative to the first tip end surface and the second chip end face, the semiconductor device according to claim 25.   32. The semiconductor device according to claim 31, wherein the second side, the third side, and the fifth side constitute the seal ring convex portion that is convex inside the closed loop shape. A sacrificial pattern, which is a wall-like structure for preventing the progress of cracks, is provided outside the seal ring convex portion as seen from the center of the chip.
26. The semiconductor device according to claim 25, wherein the sacrificial pattern is formed between the seal ring and the external seal ring.   34. The semiconductor device according to claim 33, wherein the sacrificial pattern is arranged separately from the seal ring and the external seal ring in plan view.

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