JP5300291B2 - Semiconductor system and its startup method - Google Patents

Description

  The present invention relates to a semiconductor system having a plurality of semiconductor chips and a method for starting such a semiconductor system.

  In a semiconductor system including a plurality of semiconductor chips such as a multi-chip package (hereinafter referred to as “MCP”), activation processing is performed on each of the plurality of semiconductor chips. Since the start-up processes of the respective semiconductor chips are performed simultaneously, the peak currents at the time of start-up overlap. In such a case, if a power supply device having a low power supply capability such as a battery is used, the power supply voltage of each semiconductor chip may not reach a desired value, and the startup process may be delayed or not performed normally. is there.

Patent Documents 1 and 2 propose a technique for preventing the peak currents of a plurality of semiconductor chips from overlapping each other.
Patent document 1 is an invention about power-on control of a system constituted by a plurality of devices. In Patent Document 1, power is turned on to each device in the system with a predetermined time interval. Overlapping peak currents is prevented by shifting the power-on timing between devices. However, since each device is activated after a predetermined time interval, the setting of each device becomes complicated. In addition, the timer for monitoring the time interval must be operated under an unstable power supply voltage, and there is no guarantee that it will operate normally.
Patent Document 2 is an invention relating to a method for starting a computer system having a plurality of nodes. When the power is turned on, the activation order is instructed to each node. Each node determines its own order and starts up sequentially. Each node is activated in order to prevent the peak current from overlapping. The activation order is sent from a station for activation order management different from the node. Since this station operates under an unstable power supply voltage, there is no guarantee that the startup sequence can be managed normally.

Patent Document 3 is a technique for adjusting the output level of a plurality of semiconductor modules mounted on a system. The output level is adjusted in response to a start signal supplied from the outside, and an end signal is output after the adjustment is completed. The end signal is input to the next module as a start signal. When the adjustment of the output levels of all the semiconductor modules is completed, the semiconductor modules can be used. Such a patent document 3 relates to adjustment of an output level which is a part of a startup process of a semiconductor module. By sequentially supplying the power supply voltage, the plurality of semiconductor modules adjust the output level sequentially. Therefore, the current peaks of the semiconductor modules that flow due to the adjustment of the output level do not overlap.
JP 59-205628 Japanese Patent Laid-Open No. 02-304607 JP 2001-92572 A (paragraphs 0035 to 0046, FIGS. 4 to 6)

As described above, in the conventional technique, it is not always possible to reliably control the timing of power-on of a plurality of devices in the system. For this purpose, there is a demand for a technique that sequentially performs start-up processes of semiconductor chips and reliably operates so that the peak currents of the semiconductor chips do not overlap.
Further, in the conventional technology, power supply fluctuation due to activation of other devices in the system is not taken into consideration. For example, in an apparatus that performs analog sensing at the time of activation, a drop in power supply voltage due to activation of another apparatus, voltage fluctuation due to noise, etc. greatly affects sensing.

  In view of such problems, it is a main object of the present invention to provide a semiconductor system that can normally start a plurality of semiconductor chips even when the power supply capability of the power supply device is low.

  The semiconductor system of the present invention that solves the above problems is a set of a plurality of semiconductor chips and one of each of the plurality of semiconductor chips, and each of them completes the startup process of the semiconductor chip that forms the set. And a plurality of start control devices connected in series for outputting a start completion signal indicating that. Each of the plurality of start control devices has at least one of a power supply voltage for operating the semiconductor chip being a predetermined value or more and a fluctuation amount of the power supply voltage being a predetermined fluctuation amount or less. A semiconductor that forms a set when a detection unit that outputs a detection signal by detection and the detection signal and the power supply voltage equal to or higher than the predetermined value or the start-up completion signal output from the start-up control device in the previous stage are input A start instruction unit that outputs a start instruction signal for instructing start of a chip start process; and a start execution unit that receives the start instruction signal and causes the paired semiconductor chips to execute a start process. The start instruction unit included in at least one start control device in the second and subsequent stages receives the start signal when the detection signal and the start completion signal output from the start control device in the previous stage are input. It outputs an instruction signal, at least one of the plurality of activation control apparatus starts processing of all the semiconductor chips to output an end signal indicating the completion.

In the semiconductor system of the present invention configured as described above, at least one of the second and subsequent start control devices has a detection signal and a start completion signal from the previous start control device after the power supply voltage exceeds a predetermined value. In response to this, the starting process of the semiconductor chip to be paired is performed. Therefore, the semiconductor chip activation process is not performed at the same timing as that of the activation controller at the previous stage, and the peak currents of all the semiconductor chips do not flow simultaneously. Therefore, the semiconductor chip in the semiconductor system can be normally activated.
Each activation control device can detect the fluctuation of the power supply voltage accompanying the activation process of the preceding semiconductor chip by the detection unit. For this reason, it is possible to secure a power supply voltage for an optimal startup process for each semiconductor chip.
When all the activation control devices in the second and subsequent stages perform the activation process of the semiconductor chip to be paired according to the detection signal and the activation completion signal from the activation control device in the previous stage, the activation control apparatus in the first stage The start-up process of the semiconductor chips that are paired in sequence is performed. For this reason, the peak currents at the start of all the semiconductor chips are generated at different timings.
The startup control devices in the second and subsequent stages that perform the startup processing of the semiconductor chips that are paired according to the detection signal and the power supply voltage perform the startup processing of the semiconductor chips at substantially the same timing as the startup control device in the first stage. Therefore, the timing of generating the peak current at the time of startup is adjacent. Operation becomes unstable when the peak current generation timings at the start of all semiconductor chips are adjacent, but normal operation when the timings of peak current generation at the start of two or three semiconductor chips are adjacent, for example In the case of a power supply apparatus that supplies a power supply voltage to the extent possible, no problem arises in operation even if the timing of peak current generation is adjacent in such a configuration. In addition, since a plurality of semiconductor chips are activated at a time, the activation time of the entire semiconductor system can be increased.
The number of semiconductor chips that can be activated substantially simultaneously is determined by the capability of the power supply device. Therefore, the number of activation control devices in the second and subsequent stages depending on the capability of the power supply device can be determined according to the detection signal and the power supply voltage.
In addition, when the start processing of all the semiconductor chips is completed, an end signal is output, so that a device outside the semiconductor system can be notified of the start of all the semiconductor chips in the semiconductor system.

In such a semiconductor system of the present invention, at least one of the semiconductor chips or at least one of the plurality of activation control devices includes a control unit capable of controlling the operation of the semiconductor chip or the semiconductor chip forming a group. Also good. In such a configuration, the activation control device outputs the activation completion signal to the outside of the semiconductor system. The control unit controls the operation of the semiconductor chip by an input signal from the outside of the semiconductor system.
In such a configuration, the semiconductor chip for which the startup process has been completed can be operated before the startup process for the entire semiconductor system is completed. For example, any one semiconductor chip has a storage area in which predetermined data such as boot data is stored, and this semiconductor chip or a startup control device paired with this semiconductor chip is connected to the semiconductor chip. In the case where a reading unit capable of reading the data from the storage area is provided, the activation control device outputs the activation completion signal to the outside of the semiconductor system. The reading unit reads the data from the storage area of the semiconductor chip by an input signal from the outside of the semiconductor system. As a result, during boot processing of other semiconductor chips, for example, when boot data is stored in the storage area, boot processing using the boot data can be executed, so that the boot processing of the entire semiconductor system is accelerated.

In the semiconductor system of the present invention as described above, at least one of the semiconductor chips and the activation control device that is paired with the semiconductor chip may be integrally configured. For example, it is realized by a configuration using the same silicon bulk, bonding of silicon bulk, adjacent arrangement, or a stacked configuration.
Further, a plurality of activation control devices connected in series may be provided in parallel. Even in this case, each activation control device is configured to be paired with a semiconductor chip.
Furthermore, the start control device that outputs the output signal may include an end signal generation unit that outputs the end signal when the start completion signals are input from all the start control devices.

  A semiconductor system activation method according to the present invention includes: a plurality of semiconductor chips; and a plurality of activation control devices that are connected to each other in series with each of the plurality of semiconductor chips. Is the method. In this activation method, each of the plurality of activation control devices has a power supply voltage applied to a semiconductor chip paired with the activation control device exceeding a predetermined value, and a fluctuation amount of the power supply voltage is a predetermined fluctuation amount. A step of detecting at least one of the following and outputting a detection signal; and the first-stage activation control device receives the detection signal output from its own device, and enters the set of semiconductors At least one of the step of causing the chip to execute the start-up process, the step of outputting a start-up completion signal when the start-up process of the semiconductor chip in the set is completed, and the start-up control devices in the second and subsequent stages are output from the own device. When the detection signal and the start completion signal output from the start control device in the previous stage are input, a step of causing the semiconductor chip to be set to execute start processing, and a start process of the semiconductor chip to be set There comprising a step of outputting a startup completion signal and ends, at least one of the plurality of activation control apparatus, a step of activation processing for all of the semiconductor chip to output an end signal indicating the completion, the. The step of outputting the end signal includes, for example, a step of generating the end signal when the start completion signals are input from all the start control devices. With the end signal, it is possible to notify the external device of the semiconductor system that the activation of all the semiconductor chips in the semiconductor system has been completed. Such a method is particularly effective when the startup processing proceeds in parallel.

  According to the present invention as described above, the start control device performs the start processing of the semiconductor chips forming a set by the power supply voltage detection signal and the power supply voltage or the start completion signal, so that the peak currents at the start of each semiconductor chip do not overlap. . Therefore, even if the power supply capability of the power supply device is low, the semiconductor chip in the semiconductor system can be normally activated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a configuration diagram of a semiconductor system according to a first embodiment of the present invention. This semiconductor system is configured by an MCP 1 including a plurality of semiconductor chips (first to nth semiconductor chips 21 to 2n). In the MCP 1, the first to nth semiconductor chips 21 to 2n may be mounted side by side on the substrate of the package, and the first to nth semiconductor chips 21 to 2n are mounted in a stacked structure. Also good. The first to nth semiconductor chips 21 to 2n are any devices such as a nonvolatile semiconductor memory device, a dedicated semiconductor device, a volatile semiconductor memory device, and a processing device such as a CPU (Central Processing Unit). Also good.

Each of the first to nth semiconductor chips 21 to 2n includes an activation control device. The first to nth semiconductor chips 21 to 2n and the first to nth activation control devices 31 to 3n are each configured as a “set”. The first to n-th activation control devices 31 to 3n instruct the activation process of the first to n-th semiconductor chips to be paired. The first to nth activation control devices 31 to 3n output activation completion signals PUOK1 to PUOKn when the activation processing of the first to nth semiconductor chips as a pair ends. When activation completion signals PUOK1 to PUOK1 to n are output from all of the first to nth activation control devices 31 to 3n, activation processing of the first to nth semiconductor chips 21 to 2n built in the MCP1 from the first activation control device 31 is performed. An end signal indicating that has been completed is output.
In this embodiment, the first to n-th activation control devices 31 to 3n are configured integrally with the first to n-th semiconductor chips 21 to 2n, respectively, but these are separate and independent devices. May be provided in the MCP 1.

The first to n-th activation control devices 31 to 3n are connected in series. The first to n-th activation control devices 31 to 3n operate by applying a power supply voltage VDD and a ground voltage VSS for operating the first to n-th semiconductor chips 21 to 2n, respectively. The second to n-th activation control devices 32 to 3n in the second and subsequent stages receive the activation completion signals PUOK1 to n-1 output from the first to n-1th activation control devices 31 to 3n-1 in the previous stage, respectively. Upon receipt, the second to nth semiconductor chips 22 to 2n forming a set are caused to execute a startup process. The first activation control device 31 in the first stage causes the first semiconductor chip 21 to execute activation processing by transition of the power supply voltage VDD.
As described above, since the startup control devices 32 to 3n in the second and subsequent stages do not execute the startup process unless receiving the startup completion signal from the startup control apparatus in the previous stage, two or more semiconductor chips simultaneously perform the startup process. There is no.

FIG. 2 is a configuration diagram of the first to n-th activation control devices 31 to 3n.
Each of the first to n-th activation control devices 31 to 3n includes a power supply voltage detection unit 41, an activation instruction unit 42, an activation execution unit 43, and an end signal generation unit 44. Only the end signal generator 44 provided in the activation control device that outputs the end signal needs to operate effectively. In this embodiment, only the end signal generation unit 44 of the first start control device 31 operates effectively, and the end signal generation units 44 of the second to nth start control devices 32 to n do not operate. Activation completion signals PUOK1 to PUOKn are input from the first to nth activation control devices 31 to 3n to the end signal generation unit 44 of the first activation control device 31 that operates effectively. For example, the ground voltage VSS is input to the end signal generation units 44 of the other second to n-th activation control devices 31 to 3n. When the ground voltage VSS is input, the end signal generation unit 44 can perform only an invalid operation. Since the first semiconductor chip 21 finishes the startup process first, the first startup control device 31 first starts normal operation. Therefore, the end signal is output more accurately than when the end signal is output from the second to n-th activation control devices 23 to 3n. In this way, by the first activation control device 31 paired with the first semiconductor chip 21 that normally ends the activation process first, it is monitored whether the second to n-th semiconductor chips 32 to 3n in the subsequent stage are normally terminated. The configuration leads to improved reliability. In particular, when the first activation control device 31 is disposed at a position that is electrically close to the power supply that supplies the power supply voltage VDD to the MCP 1, the power supplied to the first semiconductor chip 21 and the first activation control device 31. Since the voltage drop of the voltage VDD is small, the possibility of starting failure is reduced and the reliability is improved. Each component is configured as an electronic circuit, for example.

The power supply voltage detection unit 41 receives the power supply voltage VDD and the ground voltage VSS, and at least one of the power supply voltage VDD being equal to or higher than a predetermined value and the fluctuation amount of the power supply voltage VDD being equal to or smaller than the predetermined fluctuation amount. When either one is detected, the detection signal VCCOK is output. Such a power supply voltage detection part 41 is realizable with a comparator, for example. When detecting that the power supply voltage VDD is equal to or higher than a predetermined value, the power supply voltage detection unit 41 compares, for example, the power supply voltage VDD with a predetermined value. For example, if the power supply voltage VDD is equal to or higher than a voltage (for example, 1.0 V) that ensures the normal operation of the first to nth semiconductor chips 21 to 2n, the power supply voltage detector 41 outputs the detection signal VCCOK. When detecting that the fluctuation amount of the power supply voltage VDD is equal to or less than the predetermined fluctuation amount, for example, the power supply voltage detecting unit 41 compares the fluctuation amount of the power supply voltage VDD with the predetermined fluctuation amount. If the fluctuation amount of the power supply voltage VDD is such that malfunction such as analog sensing does not occur (for example, 0.2 V or less), the power supply voltage detector 41 outputs the detection signal VCCOK. The detection signal VCCOK is input to the activation instruction unit 42.
The power supply voltage detector 41 may be configured to detect the noise amount of the ground voltage VSS. Such a configuration prevents malfunction and improves reliability.

The activation instruction unit 42 has different signals to be input depending on whether it is provided in the first activation control device 31 in the first stage or in the second to n-th activation control devices 32 to 3n in the second and subsequent stages. However, it is the same for generating a start instruction signal instructing start of start processing of the first to nth semiconductor chips to be paired by inputting a signal.
The activation instruction unit 42 provided in the first activation control device 31 generates an activation instruction signal based on the detection signal VCCOK input from the power supply voltage detection unit 41 and the power supply voltage VDD equal to or higher than a predetermined value. The power supply voltage VDD is preferably input through the internal wiring of the MCP 1. The activation instruction unit 42 provided in the second to n-th activation control devices 32 to 3n outputs the detection signal VCCOK input from the power supply voltage detection unit 41 and the first to n-th activation control signals 31 to 3n-1 in the previous stage. The activation instruction signal is generated by the activation completion signals PUOK1 to n−1.
When the first semiconductor chip 21 and the second semiconductor chip 22 are the same function device, the input to the activation instruction unit 42 of the first activation control device 31 is as described above. This is because they are the same silicon bulk by the same design. However, when the first semiconductor chip 21 and the second semiconductor chip 22 are different functional devices, the activation instruction unit 42 of the first activation control device 31 may generate an activation instruction signal only by the detection signal VCCOK. Good.

  The activation instruction unit 42 can be realized by an AND circuit, for example. In this case, the activation instruction unit 42 of the first activation control device 31 indicates that the power supply voltage detection unit 41 indicates that the power supply voltage VDD is greater than or equal to a predetermined value and that the fluctuation amount of the power supply voltage VDD is less than or equal to the predetermined fluctuation amount. If at least one of them is detected and the detection signal VCCOK is logic “1” and the power supply voltage VDD is equal to or higher than a predetermined value and logic “1”, a start instruction signal is generated. In the activation instruction units 42 of the second to n-th activation control devices 32 to 3n, the power supply voltage detection unit 41 has the power supply voltage VDD equal to or higher than a predetermined value and the fluctuation amount of the power supply voltage VDD is equal to or smaller than the predetermined fluctuation amount. And the detection signal VCCOK is logic “1”, the first to n−1th semiconductor chips 21 to 2n−1 are completely activated, and the activation completion signals PUOK1 to n−1 are logic. If “1”, an activation instruction signal is generated. The activation instruction signal is input to the activation execution unit 43.

The activation execution unit 43 causes the first to nth semiconductor chips 21 to 2n to execute the activation process in response to the activation instruction signal input from the activation instruction unit 42. When the activation process is completed, activation completion signals PUOK1 to PUOKn are generated. The generated start completion signals PUOK1 to n-1 are input to the second to nth start control devices 32 to 3n in the next stage. In addition, the start completion signals PUOK 1 to n are also input to the end signal generation unit 44. In this embodiment, since the output signal is output from the end signal generation unit 44 of the first activation control device 21, the activation completion signal from the activation execution unit 43 of all the activation control devices 31 to 3n to the first activation control device 21. PUOK1 to n are input.
The activation process includes activation of internal voltage generation circuits provided in the first to nth semiconductor chips 21 to 2n, activation of an oscillator, activation of a memory sense amplifier, and the like. At the start-up, a current of several tens of milliamperes is generated, and the peak current is several hundred milliamperes. It is difficult to cover all of these peak currents with components such as a smoothing capacitor and a filter externally added to the semiconductor chip. This is because these components are also in operation and often do not hold a sufficient amount of charge. In the present embodiment, the first to n-th activation control devices 31 to 3n are paired with the detection signal VCCOK of the power supply voltage VDD and the power supply voltage VDD or the activation completion signals PUOK1 to n−1. Since the 2n start-up process is performed, the peak currents at the time of start-up of the first to nth semiconductor chips 21 to 2n do not occur simultaneously. Therefore, even if the power supply capability of the power supply device (especially the power supply capability corresponding to the peak current consumption) is low, the first to nth semiconductor chips 21 to 2n in the MCP 1 can be started normally.

The end signal generation unit 44 outputs an end signal when the start completion signals PUOK1 to PUOKn are input from all the start control devices 31 to 3n. The end signal is output to the outside of MCP1. FIG. 3 is an example of a specific circuit configuration diagram of the end signal generation unit 44.
The end signal generation unit 44 is configured by connecting a resistance element 45 and switching elements 461 to 46n (for example, N-channel enhancement transistors) of the same number as the activation control devices 31 to 3n connected in series. A power supply voltage VDD is applied to the resistance element 45. The ground voltage VSS is applied to the switching element 46n. The switching elements 461 to 46n are controlled to be opened and closed by activation completion signals PUOK1 to PUOKn. When the activation completion signals PUOK1 to PUn are input from all the activation control devices 31 to 3n, the switching elements 461 to 46n are all closed (conductive state), and the logic “0” represented by the ground voltage VSS is It is output as an end signal indicating that the activation of the first to nth semiconductor chips 21 to 2n has ended (ready state). If any one of the switching elements 461 to 46n is in an open state (non-conducting state), that is, if there is any one of the start control devices 31 to 3n not outputting the start completion signals PUOK1 to PUOKn, the power supply voltage VDD The represented logic “1” is output (busy state). If a mechanism for cutting off the current flowing through the resistance element 45 is provided after shifting to the ready state, wasteful current consumption can be reduced.
The activation completion signal PUOKn output from the n-th activation control device 3n at the final stage may be output to the outside of the MCP 1 as an end signal. In such a configuration, the end signal generation unit 44 is not necessary, and it is not necessary to collect the activation completion signals PUOK1 to PUOKn in one activation control device. This simplifies wiring handling and the like.

In the MCP 1 configured as described above, the first to nth semiconductor chips 21 to 2n are activated as shown in the timing chart of FIG.
First, the power supply voltage VDD and the ground voltage VSS are applied to the first to nth activation control devices 31 to 3n. In the first to n-th activation control devices 31 to 3n, the power supply voltage detection unit 41 causes the power supply voltage VDD to be equal to or higher than a predetermined value, and the fluctuation amount of the power supply voltage VDD is equal to or smaller than the predetermined fluctuation amount. When one of them is detected, a detection signal VCCOK is output. Usually, since the power supply voltage VDD and the ground voltage VSS are simultaneously applied to the first to n-th activation control devices 31 to 3n, the detection signal VCCOK is output at the same timing. When there is a semiconductor chip that potentially holds a local defect current or the like in the MCP 1, a detection signal VCCOK of a semiconductor chip that is disposed electrically far away from the power source that supplies the power supply voltage VDD and the ground voltage VSS to the MCP 1 May be delayed. The power supply voltage detection unit 41 detects a power supply voltage that is optimal for the start-up process, corresponding to a defect current value that varies depending on the power supply model in the MCP 1 and the manufacturing conditions of the individual semiconductor chips. Therefore, it is possible to apply the optimum voltage for the starting process to the first to nth semiconductor chips 21 to 2n.
Next, the activation instruction unit 42 of the first activation control device 31 paired with the first semiconductor chip 21 outputs an activation instruction signal with the detection signal VCCOK and the power supply voltage VDD equal to or higher than a predetermined value. Since the activation instruction units 42 of the other second to n-th activation control devices 32 to 3n output activation instruction signals by the activation completion signals PUOK1 to n-1 and the detection signal VCCOK of the previous stage, at this timing, The start instruction signal is not output. As described above, the activation instruction unit 42 of the first activation control device 31 can output an activation instruction signal only with the detection signal VCCOK.

In the first activation control device 31, an activation instruction signal is input to the activation execution unit 43. The activation execution unit 43 causes the first semiconductor chip 21 to execute activation processing in response to the input of the activation instruction signal. When the activation process of the first semiconductor chip 21 is completed, an activation completion signal PUOK1 is output from the activation execution unit 43. The activation completion signal PUOK1 is input to the end signal generation unit 44 and the activation instruction unit 42 of the second activation control device 32.
In the end signal generation unit 44, the switching element 461 is closed by the activation completion signal PUOK1. The power supply voltage VDD supplied to the second to nth semiconductor chips 22 to 2n may locally drop due to a peak current generated by the startup process of other semiconductor chips. Therefore, the logic of the detection signal VCCOK may fluctuate in a semiconductor chip that is arranged electrically far from the power supply that supplies the power supply voltage VDD and the ground voltage VSS. The power supply voltage detector 41 detects a change in the power supply voltage VDD accompanying the startup process of another semiconductor chip. If the detection signal VCCOK is not generated, the semiconductor chip is not activated. If the power supply voltage VDD is not suitable for starting the semiconductor chip, the detection signal VCCOK is not generated. Therefore, the power supply voltage detection unit 41 can absorb the influence of the voltage drop of the power supply voltage VDD due to activation of other semiconductor chips.

  The activation instruction unit 42 of the second activation control device 32 generates an activation instruction signal according to the activation completion signal PUOK1 and the detection signal VCCOK. The activation instruction signal is input to the activation execution unit 43. The activation execution unit 43 causes the second semiconductor chip 22 to execute activation processing in response to the input of the activation instruction signal. When the startup process of the second semiconductor chip 22 is completed, a startup completion signal PUOK2 is output from the startup execution unit 43. The activation completion signal PUOK2 is input to the end signal generation unit 44 of the first activation control device 32 and the activation instruction unit 42 of the third activation control device 33. In the end signal generation unit 44, the switching element 462 is closed by the activation completion signal PUOK2.

Thereafter, the same operation is executed up to the start control device 3n which is a set of the nth semiconductor chip 2n. Thereby, the starting process of the first to nth semiconductor chips 21 to 2n is completed. In the end signal generation unit 44, all the switching elements 461 to 46n are closed by the activation completion signals PUOK1 to PUOKn. Therefore, an end signal of logic “0” is output to the outside of MCP1.
The start-up times of the first to nth semiconductor chips 21 to 2n vary depending on each function and circuit scale. Further, as described above, the start-up time varies due to a voltage drop or voltage variation caused by a start-up process of another semiconductor chip, such as a defect current that varies depending on the power supply model in the MCP 1 and the manufacturing conditions of individual semiconductor chips.

As described above, in the present embodiment, the startup processes of the first to nth semiconductor chips 21 to 2n are performed at different timings without using any devices other than the first to nth startup control devices 31 to 3n. Therefore, normal startup processing can be performed without overlapping peak currents. Further, since no other device is used, the other device becomes unstable due to insufficient power supply voltage, and normal startup processing is not hindered. Specifically, each of the first to n-th activation control devices 31 to 3n determines the stability of the power supply voltage VDD supplied to the first to n-th semiconductor chips 21 to 2n by the power supply voltage detection unit 41. The activation instruction unit 42 interferes with the activation sequence by the activation completion signals PUOK1 to PUn, which are internal busy signals corresponding to the activation sequence. Therefore, the first to nth semiconductor chips 21 to 2n are theoretically started sequentially regardless of the environmental conditions.
In summary, (1) even if the startup time of the first to nth semiconductor chips 21 to 2n varies due to unstable current supply at startup, startup is optimal by the first to nth startup control devices 31 to 3n. Since it is theoretically performed sequentially under the conditions, the starting currents do not overlap. (2) The power supply voltage detection unit 41 and the start instruction unit of the first to nth start control devices 31 to 3n even if there is a change in peak current due to an unstable voltage change at start-up or a defective current of the preceding semiconductor chip Since the start-up is theoretically and sequentially performed under the optimum conditions by 42, the start-up currents do not overlap. (3) Even if a variation (variation in transistor characteristics, etc.) occurs in the manufacture of each semiconductor chip and the activation current value and the activation time vary, the first to nth activation control devices 31 to 3n cancel the variation. Since start-up is theoretically performed sequentially under optimum conditions, the start-up currents do not overlap. (4) Since the startup is theoretically performed sequentially under the optimum conditions without depending on the power supply model in the MCP 1, the startup currents do not overlap.

  It is desirable that the first to nth semiconductor chips 21 to 2n have a large start-up current and are arranged electrically close to the power supply that supplies the power supply voltage VDD and the ground voltage VSS. If the power supply for supplying the power supply voltage VDD and the ground voltage VSS is on the first semiconductor chip 21 side, the voltage drop of the power supply voltage VDD associated with the start-up current can be minimized by starting sequentially from the first semiconductor chip 21. . If the voltage drop of the power supply voltage VDD accompanying the startup current is small, the possibility of startup failure is low.

  As a further application, when the starting current of the nth semiconductor chip 2n is smaller than the starting currents of the first to n−1th semiconductor chips 21 to 2n−1, it is paired with the n−1th semiconductor chip 2n−1. An end signal may be output from the (n-1) th activation control device 3n-1. Specifically, activation completion signals PUOK1 to n-1 are input from the first to n-1th activation control devices 31 to 3n-1 to the end signal generation unit 44 of the n-1th activation control device 3n-1. An end signal is output. Alternatively, the activation completion signal PUOKn-1 that is the output of the activation execution unit 43 of the n-1st activation control device 3n-1 is output as the end signal. The controller that controls the MCP 1 accesses the first to n−1th semiconductor chips 21 to 2n−1 at high speed with ideal voltages without considering the voltage drop caused by the starting current of the nth semiconductor chip 2n. it can.

(Second Embodiment)
FIG. 5 is a configuration diagram of a semiconductor system according to the second embodiment of the present invention. This semiconductor system is configured by an MCP 2 including a plurality of semiconductor chips (semiconductor memory chip 20 and first to nth semiconductor chips 21 to 2n). The MCP 2 has a configuration in which the semiconductor memory chip 20 paired with the activation control device 30 is provided in front of the first semiconductor chip 21 of the MCP 1 of the first embodiment. For example, a part of the semiconductor memory chip 20 is a boot area that is read at the time of booting. The boot area is a recording area in which boot data (for example, various programs and various data typified by boot loader (IPL)) essential for boot processing of the system having the MCP 2 are recorded. The boot area may be provided in a normal memory array of the semiconductor memory chip 20.

  Unlike the first embodiment, the activation instruction unit 42 of the activation control device 31 that is paired with the first semiconductor chip 21 is output from the detection signal VCCOK and the activation control device 30 that is paired with the semiconductor chip memory 20. A start instruction signal is output in response to the completion signal PUOK.

  FIG. 6 is a configuration diagram of the activation control device 30. In FIG. 6, elements having the same functions and names as those of the first to n-th activation control devices 31 to 3 n in FIG. 2 are denoted by the same reference numerals. Each component of the activation control device 30 is configured as an electronic circuit, for example.

Among the components of the activation control device 30, the power supply voltage detection unit 41, the activation instruction unit 42, and the activation execution unit 43 are the power supply voltage detection units of the first to nth activation control devices 31 to 3n of the first embodiment. 41, the activation instruction unit 42, and the activation execution unit 43. The start completion signal PUOK output from the start execution unit 43 is input as a boot ready signal to an external device such as a memory controller provided outside the MCP 2 in addition to being input to the first start control device 31 in the next stage. The
The activation control device 30 includes a memory access unit 47 for accessing a recording area of the semiconductor memory chip 20. The activation completion signal PUOK is also input to the memory access unit 47. When the boot area is in a normal memory array of the semiconductor memory chip 20, the memory access unit 47 can also be used as an access control unit that accesses the normal memory array.

  The memory access unit 47 can access the recording area of the semiconductor memory chip 20 when the activation completion signal PUOK is input. When the external device recognizes whether or not the semiconductor memory chip 20 can be accessed by the boot ready signal, a boot read signal that is an input signal for instructing reading of boot data, for example, is input from the external device to the memory access unit 47. When a boot read signal is input, the memory access unit 47 reads boot data from the boot area of the semiconductor memory chip 20 and sends it to an external device. Thus, even when the first to nth semiconductor chips 21 to 2n are executing the startup process, the external device can read the boot data in advance from the semiconductor memory chip 20 and perform the boot process.

In this embodiment, the semiconductor memory chip 20 is used, but even a processing device such as a CPU can perform a processing operation while another semiconductor chip is executing a startup process. With such a configuration, even if the other semiconductor chip in the MCP 2 is being activated, the preceding process can be performed by the semiconductor chip that has already completed the activation process.
Note that the completion of the activation process of the semiconductor memory chip 20 may be notified outside the MCP 2 by inputting another signal different from the activation completion signal PUOK to the external device as a boot ready signal. For example, it may be a signal indicating completion of internal setting of redundant information for relieving a defective memory cell. Further, it may be a signal indicating completion of loading of the boot data into the cache memory. In this case, the memory access unit 47 accesses the cache memory in response to the boot read signal.

In FIG. 6, compared to FIG. 2, the activation control device 30 is configured to include the memory access unit 47 instead of the end signal generation unit 44, but of course, a configuration including both components is also possible. It is. Further, the memory access unit 47 may be provided on the semiconductor memory chip 20 side. In this case, the boot read signal is input to the semiconductor memory chip 20 via the start control device 30 or directly.
Similarly to MCP1, MCP2 also performs an operation represented by the time chart of FIG. The difference from the MCP 1 is that the semiconductor memory chip 20 that has completed the startup process can perform a memory array access operation in parallel with the startup process operations of the other first to nth semiconductor chips 21 to 2n.

  Preferably, the semiconductor memory chip 20 and the first to n-th semiconductor chips 21 to 2n are executed from those that are electrically close to the power supply that supplies the power supply voltage VDD and the ground voltage VSS to the MCP2. If the power supply for supplying the power supply voltage VDD and the ground voltage VSS is electrically close to the semiconductor memory chip 20, the semiconductor memory chip 20 is sequentially activated to reduce the voltage drop and voltage fluctuation of the power supply voltage VDD accompanying the boot data reading. It can be minimized. This is because there is a low possibility that the activation of the first to nth semiconductor chips 21 to 2n that simultaneously execute processing will fail. It is also effective when a plurality of semiconductor chips are activated in parallel.

  In both MCP1 and MCP2 described above, the activation instruction unit 42 included in the activation controller in the first stage generates an activation instruction signal from the detection signal VCCOK and the power supply voltage VDD. With such a configuration, the activation control devices in the subsequent stages operate in accordance with each operating condition one by one in order. However, if the power supply capability of the power supply device that supplies the power supply voltage VDD has a margin, some parallel activation processes of a plurality of semiconductor chips may be possible. This is effective when the semiconductor chips that are activated in parallel are semiconductor chips having different functions. In such a case, the start instruction unit 42 included in the start control device other than the first stage may generate a start instruction signal from the detection signal VCCOK and the power supply voltage VDD. For example, when the activation control devices are connected in series in 10 stages, the activation instruction unit 42 included in the activation control devices in the first and sixth stages generates an activation instruction signal from the detection signal VCCOK and the power supply voltage VDD. Two control devices operate in parallel. In particular, it should be noted that when the functions of the first-stage and sixth-stage semiconductor chips activated by the first-stage and sixth-stage activation control devices are different, the peak current generation times are different. Further, the start times of the second and seventh semiconductor chips that are activated by the second and seventh and subsequent activation control devices are also different. The activation instruction unit 42 provided in the activation control devices in the second and seventh stages controls the activation execution unit 43 including the state of the detection signal VCCOK, and therefore includes the influence of the voltage drop of the power supply voltage VDD and the power fluctuation. Reliable and optimal startup processing. As a result, the startup time of the entire MCP can be increased.

  In order for the start instruction unit 42 provided in the start control device other than the first stage to generate the start instruction signal from the detection signal VCCOK and the power supply voltage VDD, the start control device is configured so that the power supply voltage VDD and the start completion signal PUOK of the previous stage are You may provide the switch which inputs one into the starting instruction | indication part 42. FIG. The user who uses MCP1 or MCP2 can start the entire MCP at high speed so as not to exceed the capacity of the power supply device by appropriately setting the switch of each start control device according to the start-up current of each semiconductor chip. It becomes possible to do.

  In the MCP 1, the first to n-th semiconductor memory chips 21 to 2n and the first to n-th activation control devices 31 to 3n connected in series are one, but a plurality of the same configurations are arranged in parallel. The structure provided may be sufficient. The same applies to MCP2. Further, the present invention is not limited to the MCP, and may be a package on package, for example. The semiconductor chip in the semiconductor system is not limited to the laminated structure.

1 is a configuration diagram of a semiconductor system according to a first embodiment. It is a block diagram of the 1st-nth starting control apparatus. It is a specific circuit block diagram of an end signal generation part. It is a time chart explaining the starting process of the 1st-nth semiconductor chip. It is a block diagram of the semiconductor system used as 2nd Embodiment. It is a block diagram of a starting control apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 2 ... MCP, 20 ... Semiconductor memory chip, 21-2n ... 1st-nth semiconductor chip, 30 ... Start-up control apparatus, 31-3n ... 1st-nth start-up control apparatus, 41 ... Power supply voltage detection part, 42 ... Start-up instruction unit, 43 ... Start-up execution unit, 44 ... End signal generation unit, 45 ... Resistance element, 461-46n ... Switching element, 47 ... Memory access unit

Claims (9)

A plurality of semiconductor chips;
Each of the plurality of semiconductor chips is paired with each other, and each of the plurality of startups connected in series outputs a startup completion signal indicating that the startup processing of the semiconductor chips forming the set is completed A control device, and
Each of the plurality of activation control devices is
Detection that outputs a detection signal by detecting at least one of a power supply voltage for operating the semiconductor chip being a predetermined value or more and a fluctuation amount of the power supply voltage being a predetermined fluctuation amount or less. And
When the detection signal and the power supply voltage equal to or higher than the predetermined value or the start completion signal output from the start control device in the previous stage are input, a start instruction for instructing start of start processing of the semiconductor chip to be paired A start instruction unit for outputting a signal;
A startup execution unit that receives the startup instruction signal and causes the semiconductor chip to be set to execute startup processing;
The activation instructing unit provided in at least one activation control device in the second and subsequent stages outputs the activation instruction signal when the detection signal and the activation completion signal output from the activation controller in the previous stage are input.
At least one of the plurality of start control devices outputs an end signal indicating that start processing of all the semiconductor chips has ended.
Semiconductor system. At least one of the semiconductor chips or at least one of the plurality of activation control devices includes a control unit capable of controlling the operation of the semiconductor chip or a set of semiconductor chips.
The activation control device outputs the activation completion signal to the outside of the semiconductor system,
The control unit controls the operation of the semiconductor chip by an input signal from the outside of the semiconductor system.
The semiconductor system according to claim 1. Any one of the semiconductor chips has a storage area in which predetermined data is stored,
The semiconductor chip or the activation control device paired with the semiconductor chip includes a reading unit capable of reading the data from the storage area of the semiconductor chip.
The activation control device outputs the activation completion signal to the outside of the semiconductor system,
The reading unit reads the data from the storage area of the semiconductor chip by an input signal from the outside of the semiconductor system.
The semiconductor system according to claim 2. Boot data is stored in the storage area,
The semiconductor system according to claim 3. At least one of the semiconductor chips and the activation control device paired with the semiconductor chips are integrally configured.
The semiconductor system of any one of Claims 1-4. The plurality of startup control devices connected in series are provided in parallel, and each startup control device is a set with one semiconductor chip.
The semiconductor system of any one of Claims 1-5. The start control device that outputs the output signal includes an end signal generation unit that outputs the end signal when the start completion signals are input from all the start control devices.
The semiconductor system of any one of Claims 1-6. A semiconductor system activation method comprising: a plurality of semiconductor chips; and a plurality of activation control devices that are paired with each of the plurality of semiconductor chips and connected in series.
Each of the plurality of activation control devices
Detecting at least one of a power supply voltage applied to a semiconductor chip paired with the activation control device exceeding a predetermined value and a fluctuation amount of the power supply voltage being a predetermined fluctuation amount or less; Outputting a detection signal;
The first stage startup control device
When the detection signal output from its own device is input, a step of causing the semiconductor chip that is the set to execute a startup process;
A step of outputting a start completion signal when the start processing of the semiconductor chip to be the set is completed;
At least one of the second and subsequent activation control devices
When the detection signal output from the device itself and the start completion signal output from the start-up control device in the previous stage are input, a step of causing the semiconductor chip to be the group to execute start-up processing;
A step of outputting a start completion signal when the start processing of the semiconductor chip to be the set is completed;
At least one of the plurality of activation control devices is
Outputting an end signal indicating that start-up processing of all the semiconductor chips has been completed,
A method for starting a semiconductor system. The step of outputting an end signal is
When the start completion signal is input from all the start control devices, the step of generating the end signal,
The method for starting a semiconductor system according to claim 8.

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