JP2007164822A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate wiring arrangements for supplying a signal for a power-on operation timing control. <P>SOLUTION: A plurality of semiconductor chips (11, 12, 13) are connected with daisy chain by bonding wires by which a power-on control signal can be propagated. Each of the plurality of semiconductor chips includes a timing adjustment circuit for shifting a process timing corresponding to the fetched power-on control signal among the plurality of semiconductor chips. By the above timing adjustment circuit, concentration of currents is avoided by shifting the process timing of the above power-on control signal among the plurality of semiconductor chips. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device formed by stacking a plurality of semiconductor chips, and relates to a technique effective when applied to, for example, a memory card.

  2. Description of the Related Art A memory card is known that has an electrically rewritable nonvolatile memory and a card controller and is formed in a card shape (see, for example, FIG. 1 in Patent Document 1).

  A memory module built in a memory card or the like does not have an external signal that can control the power-on operation in the chip independently of the potential of the power supply, detects the power supply potential, and based on the detected signal In addition, power-on operations such as resetting the internal logic and starting up the power generated in the chip are performed.

  In addition, in products such as a flash memory having a function of performing a chip internal power supply activation operation equivalent to a power-on operation as a restart operation after a standby operation by a terminal for standby control or the like, an internal power supply or the like by a deep standby control signal Is deactivated to reduce power consumption during non-operation, and the deep standby control signal is deactivated prior to normal operation, whereby the internal power supply and the like are reactivated to return to a normal operable state.

Japanese Patent Laying-Open No. 2005-258851

  In a configuration in which multiple chips mounted on a memory module detect the same power supply potential or the same control signal and determine the start of the power-on operation, the power-on operation is duplicated between the multiple chips, and the current consumption is leveled I can't. In order to solve this, it is necessary to shift the power-on operation timing among a plurality of chips using signals generated in the chip or supplied from the outside. The inventor of the present application examined the power-on operation timing control between the plurality of chips. As the number of the plurality of chips mounted on the memory module increases, the power-on signal for supplying the power-on operation timing control is supplied. It has been found that wiring is complicated. For example, a control circuit for generating a standby release signal for power-on operation timing control may be provided, and the wait release signal may be individually supplied from the control circuit for each chip. The control circuit is provided with a number of standby release signal output terminals corresponding to the number of chips that are subject to reset release, and these pins are connected individually to the multiple chips by wiring for standby release signals. Must.

  An object of the present invention is to provide a technique for easily carrying out wiring for supplying a signal for controlling a power-on operation timing even in a laminated chip or the like.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in a semiconductor integrated circuit device including a plurality of semiconductor chips each capable of activating / deactivating an internal circuit by a control signal, the plurality of semiconductor chips are daisy chain connected by wiring capable of propagating the control signal. Each of the plurality of semiconductor chips includes a timing adjustment circuit for shifting the processing timing corresponding to the fetched control signal between the plurality of semiconductor chips.

  According to the above configuration, the plurality of semiconductor chips are daisy chained by the wiring capable of propagating the control signal, and the timing adjustment circuit shifts the processing timing corresponding to the fetched control signal between the plurality of semiconductor chips. To avoid current concentration. This enables daisy chain connection by the bonding wire capable of propagating the control signal, and facilitates the routing of the wiring for supplying the signal for controlling the power-on operation timing.

  At this time, the semiconductor chip includes a first terminal and a second terminal, and when one of the first terminal and the second terminal is used for inputting the control signal, the other is used for outputting the control signal. It is said.

  A forward circuit enabling signal transmission from the first terminal to the second terminal; a reverse circuit enabling signal transmission from the second terminal to the first terminal; and the forward circuit. And a selection circuit capable of selectively controlling the reverse direction circuit to be in a conductive state, and the forward direction circuit and the reverse direction circuit can each include the timing adjustment circuit.

  It is possible to provide a selection terminal capable of determining the selection state of the selection circuit by setting with a fuse or a non-volatile memory or a bonding option at the time of assembly.

  The timing adjustment circuit includes control logic for delaying and transmitting the logic change at the first terminal to the second terminal, and delaying and transmitting the logic change at the second terminal to the first terminal. Can be configured.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the wiring for supplying the signal for controlling the power-on operation timing can be easily routed as compared with the case of supplying different timings to each chip.

  FIG. 1 shows a memory module as an example of a semiconductor integrated circuit device according to the present invention.

  The memory module 1 shown in FIG. 1 includes a plurality of module configuration memory chips 11 to 13 and a module control chip 10 that enables power-on control of the module configuration memory chips 11 to 13. Each of the plurality of module-configured memory chips has a power-on control input terminal RI that can capture a power-on control signal and a power-on control output terminal RO that can output a power-on control signal.

  The module control chip 10 has a power-on control output terminal RO that can output a power-on control signal. When the module control chip 10 and the module component chips 11, 12, and 13 are arranged in this order, they are combined as follows. The power-on control output terminal RO of the module control chip 10 is coupled to the power-on control input terminal RI of the module component chip 11. The power-on control output terminal RO of the module configuration chip 11 is coupled to the power-on control input terminal RI of the module configuration chip 12. The power-on control output terminal RO of the module configuration chip 12 is coupled to the power-on control input terminal RI of the module configuration chip 13. The power-on control output terminal RO of the module component chip 12 is coupled to the power-on control input terminal of a module component chip (not shown) that is similarly connected thereafter. As described above, the plurality of module component chips 11 to 13 are daisy chain connected to each other.

  In the above configuration, the power-on control signal RO0 is output from the power-on control output terminal RO of the module control chip 10, and is input as the signal RI1 to the power-on control input terminal RI of the module configuration chip 11. A power-on control signal RO1 is output from the power-on control output terminal RO of the module component chip 11, and is input as a signal RI2 to the power-on control input terminal RI of the module component chip 12. A power-on control signal RO2 is output from the power-on control output terminal RO of the module component chip 12, and is input to the power-on control input terminal RI of the module component chip 13 as a signal RI3.

  During the power-on reset period or standby period in the memory module 1, the output signal RO0 from the power-on control output terminal RO of the module control chip 10 is set to a low level, and the power-on control of the module control chip 10 is performed at power-on or restart. Assume that the output signal RO0 from the output terminal RO is set to the high level.

  Here, the power-on control signal input / output via the power-on control output terminal RO or the power-on control input terminal RI is an example of the control signal in the present invention.

  FIG. 2 shows the operation timing of the main part in the configuration shown in FIG.

  In the chip 11 denoted by reference numeral 11, the internal restart signal RSTR of the chip 11 for recognizing the transition to the power-on state by activating the power-on control input terminal RI and activating the internal circuit of the chip 11 is high. To the level. Further, in the chip 12 denoted by reference numeral 12, the power-on control input terminal RI connected to the control output terminal RO of the chip 11 is set to high level, so that the internal restart signal RSTR of the chip 12 is set to high level. The module component chip 11 does not transition the output signal RO1 to the high level immediately after receiving the high level signal Rl1 at the power-on control input terminal RI. Wait until the start-up completion signal of the internal power supply or the ready signal READY delayed in power-on becomes valid. This is by starting activation of the internal power supply of the module chip 11 and waiting for a sufficient time so that the activation ends or activation current peaks do not overlap, and then transitioning the output signal RO1 to the power-on state level. This is to prevent the internal power-on activation periods from overlapping in relation to the module component chip 12 at the next stage. Conversely, when a low level indicating a standby state is received by the power-on control input terminal RI, the internal power supply inactivation of the module chip 11 is started and the output RO1 is immediately shifted to a low level indicating the standby state. As a result, the low level indicating the standby state is also propagated to the module component chip 12 at the next stage. The chip 12 operates in the same manner as the chip 11, the transition to the power-on state is delayed, and the transition to the standby state is immediately propagated to the next element. The timing adjustment is performed between the module component chips 12 and 13 as well as the relationship between the module component chips 11 and 12.

  In this way, the current consumption during chip internal power supply startup is averaged by shifting the chip internal power supply startup timing between the module mounted chips connected in series in this daisy chain. It is possible to prevent the maximum current consumption value of the entire module from increasing due to the overlapping peak of the current consumption temporarily when the chip internal power supply is turned on.

  FIG. 3 shows the configuration of the main part of the module component chips 11 to 13.

  A pad 33 corresponding to the power-on control input terminal RI and a pad 34 corresponding to the power-on control output terminal RO are provided. The module component chips 11 to 13 incorporate a timing adjustment circuit 30 as shown in FIG. The input terminal of the timing adjustment circuit 30 is coupled to the power-on control input terminal RI and is coupled to the ground GND via the pull-down resistor 31. The output terminal of the timing adjustment circuit 30 is coupled to the power-on control output terminal RO and coupled to the ground GND via the pull-down resistor 32.

  The timing adjustment circuit 30 includes a buffer 301, a delay circuit 302 for keeping the output valid during the transition of the output terminal RO, a delay circuit 303 constituting a rising edge delay circuit, an AND logic 304, an OR logic 305, and a buffer 306. including.

  The one-level signal from the power-on control input terminal RI is transmitted to the buffer 306 as the R1 signal via the buffer 301, and also transmitted to the internal circuit as an internal circuit (not shown) restart signal of the chip. Activate the circuit. When the activation of the internal circuit is completed, the module component chip changes the RD2 signal to an effective level (here, 1 level). For the RD2 signal, the buffer 306 is turned on to enable OE via the OR logic 305, and the rising transition of the power-on control input terminal RI is propagated to the power-on control output terminal RO.

  On the other hand, the output of the buffer 301 includes a delay circuit 302 for keeping OE valid during the transition time of the output buffer, a delay circuit 303 and an AND logic 304 constituting a rising edge delay circuit for delaying and transmitting the rising transition. Then, the RD1 signal is led to the OR logic 305 in the same manner as the RD2 signal, and the output enable signal OE of the buffer 306 is formed.

  The operation of the above configuration will be described.

  FIG. 4 shows the operation timing of the main part in the configuration shown in FIG.

  The chip internal power supply restart signal RSTR is set to high level with the rising edge of the power-on control input terminal RI as a base point. The module-configured chip activates the internal power supply when RSTR becomes valid, and the internal power supply ready signal RD2 returns to the ready state (high level) again when the internal power supply of the chip is completed. By returning to the ready state, the output enable signal OE is set to a high level, whereby the buffer 17 is turned on. As a result, the rising edge from the power-on control input terminal RI is next from the power-on control output terminal RO. Propagate to stage chip.

  During the period when the power-on control input terminal RI is at a high level, the power-on control output terminal RO is also maintained at a high level.

  The internal power supply of the chip is set to the standby state based on the falling edge of the signal at the power-on control input terminal RI. Further, the fall of the signal at the power-on control input terminal RI is propagated from the power-on control output terminal RO to the next chip without delay.

  In the circuit, the output buffer is operated for a period when the power-on control input terminal RI is at the high level + the delay period of the delay circuit, and the high level and the rising / falling edge of the power-on control input terminal RI are propagated to the power-on control output terminal RO. . While the power-on control input terminal RI is at a low level, the pull-down circuit holds the power-on control output terminal RO at a low level. Although not specifically shown, when the current consumption limit during standby is loose, the output buffer 306 is always turned on, and the AND logic of the RD1 signal and the OE signal is inserted into the input to configure the same logic, and the pull-down resistor is omitted. It goes without saying that it is possible.

  The rising edge delay circuit is a circuit for setting a timeout when the internal power supply ready signal does not operate normally and propagating the power-on control input terminal RI to the power-on control output terminal RO. Although it is set to be long, if the current consumption peak time at the time of current startup is shorter than the internal power supply startup period, it can be set shorter than the internal power supply startup period. In that case, a power supply ready signal is not necessarily required.

It is also possible to make a chip in which the rising edge delay time is set to “0”, that is, a chip that does not delay the rising propagation. In this case, the propagation delay time becomes shorter than the number of stages in the daisy chain, and multiple chips connected to the daisy chain start powering up at the same time. It is possible to set the power-on timing at a timing shifted for each of a plurality of chips by sandwiching a module-configured chip having a delay set between the peak allowable value and the like. It is also possible to adjust the rising skew time between chips by setting the rising edge delay time as a variable delay circuit and arbitrarily setting the delay time with a fuse, ROM or the like.
According to the above example, the following operational effects can be obtained.

  According to the above example, the following operational effects can be obtained.

  (1) It is possible to set so that the consumption current peaks at the time of chip internal power source activation at the time of power-on between chips connected in a daisy chain are not overlapped, thereby avoiding an increase in the consumption current peak of the entire module. be able to.

  (2) By connecting with a control signal daisy chain, it is not necessary to connect separate bonding wires from the package body for each chip, and productivity is improved.

  Next, a specific description will be given of the case where the plurality of module configuration chips are incorporated into one module.

A case is considered where the formation positions of the pads 54, 55, and 56 of the power-on control input terminal RI and the pads 57, 58, and 59 of the power-on control output terminal RO are equal to each other between the above-described module components. In such a case, in order to daisy chain connect the plurality of module configuration chips, for example, as shown in FIG. 5, the bonding wires 51, 52, 53 between the chips are connected to the chips 11-13 so as to be inclined. To do. As a result, the module constituent chips 11 to 13 form a daisy chain connection as shown in FIG.
However, the bondings 51, 52, and 53 that are inclined with respect to the chips 11 to 13 require many short wire length bondings for each chip, and the chip mounting angle with respect to the bonding apparatus must be appropriately changed. The bonding work becomes troublesome. Further, the bonding wires 51, 52, and 53 that are inclined with respect to the chips 11 to 13 have paths intersecting with the inter-chip bonding wires (not shown) that connect the bonding pads of each chip in parallel. Therefore, it may be difficult to secure the wire interval. In order to avoid such inconvenience, as shown in FIG. 6, it is preferable that the direction in which signals flow between the RI pad 33 and the RO pad 34 can be changed in each chip.

  That is, a forward circuit 61 capable of transmitting a signal from the pad 33 to the pad 34, and a reverse circuit 62 capable of transmitting a signal from the pad 34 to the pad 33, and the forward circuit 61 and the reverse direction. An input / output direction selection circuit 63 capable of selectively activating the circuit 62 is provided, and the control of the input / output direction selection circuit 63 makes it possible to change the direction of signal flow between the pad 33 and the pad 34. To do. When the forward direction circuit 61 is selectively turned on by the input / output direction selection circuit 63, a signal can be transmitted from the pad 33 to the pad 34, and the reverse direction is transmitted by the input / output direction selection circuit 63. When the circuit 62 is selectively turned on, a signal can be transmitted from the pad 34 toward the pad 33. The selection state of the input / output direction selection circuit 63 can be set in a programmable manner by a fuse circuit that can be appropriately blown, a bonding option, or the like.

  Here, the forward direction circuit 61 and the backward direction circuit 62 are basically configured in the same logic as the timing adjustment circuit 30 in FIG. 3, and in this case, the OE of the buffer 306 is configured in a multiplexed configuration. A circuit such as a delay can be shared by adding a circuit that enables selection in the forward and reverse directions and selects the RD1 signal from the effective input terminal side.

  FIG. 7 shows an example of bonding when the circuit configuration shown in FIG. 6 is adopted.

  When the circuit configuration in FIG. 6 is applied to the module configuration chips 11, 12, and 13 shown in FIG. 7, the pads 54, 55, and 56 in the module configuration chips 11, 12, and 13 in FIG. 33, the pads 57, 58, and 59 in the module component chips 11, 12, and 13 in FIG. 7 correspond to the pads 34 in FIG.

  The plurality of module component chips 11, 12, and 13 are stacked in a state where they are shifted so that the pad position is visible. By reversing the terminal functions of the even-numbered or odd-numbered chips by the input / output direction selection circuit 63, the input pad 58 is positioned in the vicinity of the output pad 57, and the output pad An input pad 56 is positioned in the vicinity of 55. Therefore, the output pad 57 and the input pad 58 are connected by the bonding wire 73, and the output pad 55 and the input pad 56 are connected by the bonding wire 72, thereby performing daisy chain connection. In this case, the bonding wires are parallel to each other. Such bonding can be performed more easily than the bonding shown in FIG. In addition, since it is not necessary for the path to cross an inter-chip bonding wire (not shown) that connects the bonding pads of each chip in parallel, it is easy to secure the wire interval.

  FIG. 8 shows another example of bonding when the circuit configuration shown in FIG. 6 is adopted.

  In the bonding shown in FIG. 8, it is possible to increase or decrease the number of stages in the daisy chain and the number of chips in each stage by bonding all the wirings as shown by 81 and 82 instead of the series. .

  FIG. 9 shows another bonding example when the circuit configuration shown in FIG. 6 is adopted.

  The selection operation of the input / output direction selection circuit 63 shown in FIG. 6 can be configured to be controllable by the logic state of the external terminal. In that case, as shown in FIG. 9, inversion selection pads 92, 93, 94 for determining the selection operation of the input / output direction selection circuit 63 are formed in the module configuration chips 11, 12, 13, respectively. When the inversion selection pads 92, 93, 94 are formed in this way, the selection operation of the input / output direction selection circuit 63 is arbitrarily determined depending on whether the inversion selection pads 92, 93, 94 are connected to the bonding option pads 91 or not. Can do. For example, the bonding option pad 91 is at a ground level. In the example shown in FIG. 9, the inversion selection terminal 93 is connected to the bonding option pad 91 by the bonding wire 74, so that the function of the terminal in the module component chip 12 is inverted with respect to the other chips 11 and 13. I am letting.

  FIG. 10 shows another bonding example when the circuit configuration shown in FIG. 6 is adopted.

  In the configuration shown in FIG. 10, inversion selection pads 92, 93, 94 and non-inversion selection pads 101, 102, 103 for determining the selection operation of the input / output direction selection circuit 63 are provided. The setting for inverting the terminal and the setting for not inverting the function of the terminal are performed separately. In this example, the inversion selection pads 92, 93, 94 are selectively coupled to the bonding option pad 91-1, and the non-inversion selection pads 101, 102, 103 are selectively used as the bonding option pad 91-2. Combined.

  FIG. 11 shows another configuration example of the timing adjustment circuit 30.

  An output buffer 114 for outputting a signal from the pad 33 and an output buffer control circuit 115 for controlling the operation of the output buffer 114 are provided. An output buffer 118 for outputting a signal from the pad 34 and an output buffer control circuit 117 for controlling the operation of the output buffer 118 are provided. An input buffer 121 for taking in an input signal from the pad 33, a drive element 122 and a pull-up resistor 120 for pulling up the input terminal side of the input buffer 121 are provided. An input buffer 124 for capturing an input signal from the pad 34, a drive element 125 and a pull-up resistor 126 for pulling up the input terminal side of the input buffer 124 are provided. A NAND gate 123 for obtaining the NAND logic of the output signals of the input buffers 121 and 124 is provided, and the operation of the driving elements 122 and 125 is controlled by the output signal of the NAND gate 123. Further, when the OR logic of the force buffers 121 and 124 is obtained by the OR gate 116, the restart signal RSTR is formed. Further, the output signal of the input buffer 121 is supplied to the output buffer control circuit 117, and the output signal of the input buffer 124 is supplied to the output buffer control circuit 115.

  Based on the output signal of the input buffer 124 and the internal power supply ready signal RD2, the output buffer control circuit 115 forms an output signal DO and an output enable signal OE to enable it to be externally output. The output buffer 114 is supplied. Based on the output signal of the input buffer 121 and the internal power supply ready signal RD2, the output buffer control circuit 117 forms an output signal DO and an output enable signal OE to enable it to be externally output. The output buffer 118 is supplied.

  FIG. 12 shows a configuration example of the output buffer control circuits 115 and 117.

  As shown in FIG. 12, the output buffer control circuits 115 and 117 include a rising edge delay circuit 126 that detects and delays a rising edge, a NOR gate 123, and a pulse edge detection circuit 127. The rising edge delay circuit 126 includes a delay circuit 121 for delaying the input signal DI and an AND gate 122 for obtaining an AND logic between the output signal of the delay circuit 121 and the input signal DI. The OR logic between the output signal of the rising edge delay circuit 126 and the internal power supply ready signal RD2 is obtained by the OR gate 123. The output signal of the OR gate 123 is output as output data DO and transmitted to the pulse edge detection circuit 127. The pulse edge detection circuit 127 has a function of detecting the pulse edge of the output signal of the OR gate 123, a delay circuit 124 for delaying the output signal of the NOR gate 123, the output signal of the delay circuit 124 and the NOR gate And a gate 125 for obtaining an exclusive OR with 123 outputs. The output signal of the pulse edge detection circuit 127 is an output enable signal OE.

  In the above configuration, the high level of the pad 33 is maintained by the resistance ratio between the pull-up resistor 120 and the pull-down resistor 31, and the high level of the pad 34 is maintained by the resistance ratio of the pull-up resistor 126 and the pull-down resistor 32. The

  When the pad 33 transitions to a low level by driving another chip, the output buffer 117 is driven immediately by the delay time of the delay circuit 124 in the pulse edge detection circuit 127 to propagate the low level to the pad 34 and drive. Element 125 is turned off to eliminate the involvement of pull-up resistor 126. This falling transition of the pad 34 drives the pad 33 to a low level for a certain period via the output buffer 114, but causes some inconvenience because the driving direction is the same as the input from another chip. Absent.

  When both pads 33 and 34 are at a low level, if the pad 33 transitions to a high level by driving another chip, the pad 33 is delayed for a predetermined time by the rising edge delay circuit 126 and then passed through the output buffer 118 for a predetermined time. The pad 34 is driven to the high level, and the pull-up resistor 126 is involved by making the driving element 125 conductive, so that the potential of the pad 34 is held at the high level even after the driving force of the output buffer 118 is lost. The rising transition of the pad 34 drives the pad 33 to a high level for a certain period via the output buffer 114, but does not cause any inconvenience because the driving direction is the same as the input from another chip.

  When the input terminal is the pad 34, that is, when an input signal is given to the pad 34, the signal propagates in the opposite direction. Further, if the node state at the time of power-on permits, a circuit for eliminating the involvement of the pull-down resistor can be added at the time of pulling up both terminals, or a circuit for damping the driving force of the output buffer can be added when the transmission line is long.

  According to the above configuration, the pads 33 and 34 can be provided with both functions for signal input and signal output. In other words, the pads 33 and 34 are respectively used as input / output pads. Therefore, in the daisy chain connection between the plurality of module constituent chips 11, 12, 13, it is not necessary to distinguish the input / output directions of the pads 33, 34, so that a bonding option is not required, or a fuse or the like is internally provided. Since the memory element is not necessary, it is not necessary to distinguish each chip, and the bonding and assembly processes can be simplified.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  In the above description, the case where the invention made by the present inventor is mainly applied to the memory module which is the field of use behind the present invention has been described. However, the present invention is not limited to this and is applied to various semiconductor integrated circuit devices. Can be widely applied.

  The present invention can be applied on condition that at least a plurality of semiconductor chips are included.

1 is a block diagram illustrating a configuration example of a memory module as an example of a semiconductor integrated circuit device according to the present invention. It is an operation | movement timing diagram of the principal part in the structure shown by FIG. It is a circuit diagram of a configuration example of a main part in the module configuration chip included in the memory module. FIG. 4 is an operation timing chart of a main part in the circuit configuration shown in FIG. 3. It is explanatory drawing about the bonding between several chips | tips. FIG. 5 is a block diagram illustrating another configuration example of a main part of the module configuration chip included in the memory module. It is explanatory drawing of the example of bonding in the case of employ | adopting the circuit structure shown by FIG. It is another explanatory drawing of the example of bonding in the case of employ | adopting the circuit structure shown by FIG. It is another explanatory drawing of the example of bonding in the case of employ | adopting the circuit structure shown by FIG. It is another explanatory drawing of the example of bonding in the case of employ | adopting the circuit structure shown by FIG. It is another example of a circuit diagram of the principal part in the said module structure chip | tip contained in the said memory module. FIG. 12 is a circuit diagram illustrating a configuration example of a main part in FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory module 10 Module control chip 11-13 Module structure memory chip 30 Timing adjustment circuit 33,34 Pad 61 Forward direction circuit 62 Reverse direction circuit 63 Input / output direction selection circuit

Claims (7)

A semiconductor integrated circuit device including a plurality of semiconductor chips each capable of activating / deactivating an internal circuit by a control signal,
The plurality of semiconductor chips are daisy chain connected by wiring capable of propagating the control signal, and each of the plurality of semiconductor chips has a processing timing corresponding to the captured control signal between the plurality of semiconductor chips. A semiconductor integrated circuit device comprising a timing adjustment circuit for shifting in a step.   The semiconductor chip includes a first terminal and a second terminal. When one of the first terminal and the second terminal is used for inputting the control signal, the other is used for outputting the control signal. The semiconductor integrated circuit device according to claim 1. A positive direction circuit that enables signal transmission from the first terminal to the second terminal direction by being enabled, and a signal from the second terminal to the first terminal direction by being enabled. A reverse circuit that enables transmission, and a selection circuit that can selectively control the forward circuit and the reverse circuit to an effective state,
3. The semiconductor integrated circuit device according to claim 2, wherein each of the forward direction circuit and the backward direction circuit includes the timing adjustment circuit.   4. The semiconductor integrated circuit device according to claim 3, further comprising a selection terminal capable of determining a selection state of the selection circuit by bonding.   When the shift to the active polarity of the input signal connected to the input terminal and the output terminal is autonomously determined, and the transition from the first terminal to the active polarity is detected, the first terminal to the second terminal 2. Control logic for transmitting a signal in the direction of the terminal and transmitting a signal in the direction from the second terminal to the first terminal when a transition from the second terminal to the active polarity is detected. The semiconductor integrated circuit device described.   3. The semiconductor integrated circuit device according to claim 2, wherein the plurality of semiconductor chips are stacked, and an input / output relationship between the first terminal and the second terminal is different for each stacked semiconductor chip.   2. The semiconductor integrated circuit device according to claim 1, wherein a delay between the first terminal and the second terminal can be adjusted so as to fulfill an original purpose from a chip internal signal.

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