JP5292437B2 - Display control circuit and display drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce circuits in a data line drive circuit and to minimize the data line drive circuit. <P>SOLUTION: A timing control circuit 104 receives display data 102 in an order based on the line-directional array order of pixels of a display panel, changes the order of the display data into an order by a display data of N pixels (where N is an integer satisfying 1&le;N&lt;M) in the display data of M pixels (where M is an integer satisfying 1&lt;M&lt;(the number of pixels of one line)) operated by each display control circuit, and outputs display data 108 in accordance with the changed order to data line control circuits 116-1 and 116-2. When the data line control circuit 116-1 receives input of the display data 108 corresponding to N pixels, the data line control circuit 116-2 outputs an input enable signal 117-2 to the data line control circuit 116-2, the input enable signal allowing the other data line control circuit 116-2 to start receiving input of the display data. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a data line driving circuit that generates a gradation voltage according to display data and applies it to a display panel, and a display control circuit that outputs display data and a control signal (synchronization signal, clock signal, etc.) to the data line driving circuit. In particular, the present invention relates to a data line driving circuit and a display control circuit such as a liquid crystal display, an organic EL display, a plasma display, and a field emittance display.

As conventional techniques, Patent Document 1 discloses a serial-parallel converter that rearranges serially supplied segments of digital pixel data into parallel pixel data, and converts the parallel pixel data into analog red, green, and blue signals. 6 D / A converters for converting 2 pixels at a time, multiple column drivers including analog sample and hold modules that simultaneously sample 6 analog signals, and multiple simultaneous rows of digital pixel data A display driving system including a timing controller supplied to the column driver is disclosed.
In Patent Document 2, the horizontal direction of pixel portions arranged in a matrix is divided into M (M is an integer), and display data for each horizontal line is applied to each of the M divided pixel portions. The display data of the pixel portion which has a multi-gradation drive circuit and is divided into M by M multi-gradation drive circuits arranged in the horizontal direction is divided into N (N is an integer), and 1 / ( M × N) latch circuit that sequentially captures and temporarily stores the corresponding digital display data for the horizontal lines, and converts the corresponding digital display data for 1 / (M × N) horizontal lines into analog display data each time it is captured. A D / A converter and a sample hold circuit for taking analog display data for 1 / M horizontal lines. After all M multi-grayscale drive circuits have taken analog display data for 1 / M horizontal lines, 1 Horizontal A liquid crystal display device that simultaneously applies analog display data corresponding to in to a display pixel portion is disclosed.
In the above prior art, since one multi-gradation drive circuit (column driver) has a D / A converter having a capacity smaller than the capacity of analog display data applied simultaneously to the display pixel portion, that is, the number of D / A converters is small. Therefore, the multi-tone drive circuit (column driver) can be downsized.

JP-T-2002-517790 Japanese Patent Laid-Open No. 5-80722

  However, in any conventional technique, digital display data is continuously transferred from the timing controller to one multi-grayscale driving circuit (column driver), that is, first display data is first transferred to the first multi-grayscale driving circuit. And after the transfer of the display data to the first multi-gradation drive circuit is completed, the second display data is transferred to the second multi-gradation drive circuit. When the number of display data bits per pixel increases from 8 bits to 10 bits, for example, the D / A converter capacity is insufficient. On the other hand, in order to make up for the insufficient capability of the D / A converter, it is necessary to increase the number of D / A converters, which increases the size of the multi-tone drive circuit.

  It is an object of the present invention to provide a display drive circuit that is reduced in size by reducing internal circuits and a display control circuit for realizing such a display drive circuit.

  According to the present invention, display data input by a display control circuit (for example, a timing control circuit) in an order in accordance with the arrangement order of pixels of a display panel in a line direction is displayed on each display driving circuit (for example, a data line driving circuit). Display data for M pixels (1 <M <number of pixels for one line, M is an integer, for example, M = 6) for N pixels (1 ≦ N <M, N is an integer, for example, N = 2) ), And the display data is output to each display drive circuit according to the changed order. Here, the changed order is the order in which the next display drive circuit takes charge of display data for every N pixels of display data. Each display drive circuit outputs an enable signal to other display drive circuits when display data for N pixels is input. As a result, the display control circuit is responsible for each display drive circuit to each display drive circuit within an interval (horizontal scanning period) in which the plurality of display drive circuits collectively apply the line-unit grayscale voltages to the display panel. The display data is output in multiple times. This is because the first display data is smaller than the first display data group (display data group for M pixels) corresponding to the first grayscale voltage group collectively applied to the display panel by the first display driving circuit. (Display data for N pixels) is output to the first display drive circuit, and then the second display data corresponding to the second grayscale voltage group collectively applied to the display panel by the second display drive circuit. Second display data (display data for N pixels) smaller than the group (display data group for M pixels) is output to the second display drive circuit.

In the present invention, when the display drive circuit includes a plurality of conversion circuits (for example, a DA conversion circuit), the display control circuit receives display data in an order according to the arrangement order of the pixels in the line direction of the display panel, The order of display data is equivalent to Y pixels (1 ≦ X) of the display data corresponding to X pixels handled by each conversion circuit (1 <X <number of pixels handled by each display drive circuit, X is an integer, for example, X = 3). Y <X, Y is an integer, for example, Y = 1) is changed to the order of each display data, and the display data is output to each display driving circuit according to the changed order. That is, the present invention. What changed the order of display data for a plurality of display drive circuits in the above invention is to change the order of display data for a plurality of conversion circuits in the display drive circuit. Of course, two order changes may be combined.

  According to the present invention, the display driving circuit sets a reference voltage generation circuit that generates a reference voltage for each R, G, or B, and sets a γ characteristic for each R, G, or B with respect to the display voltage generation circuit. RGB that generates a plurality of gradation voltages from a register and a reference voltage, and selects and outputs an analog gradation voltage corresponding to digital display data for each R, G, or B from the plurality of gradation voltages A common conversion circuit is provided. That is, the γ characteristic can be adjusted for each R, G, or B.

  According to the present invention, the display data input in the order in accordance with the arrangement order of the pixels of the display panel in the line direction is equivalent to M pixels (1 for each display drive circuit (for example, data line drive circuit)). <M <number of pixels for one line, where M is an integer) The display data is changed to the order of display data for N pixels (1 ≦ N <M, N is an integer), and the order after the change However, since the display data for the next display drive circuit is assigned to the display data for every N pixels, the circuits in the display control circuit (for example, the DA converter circuit and the latch circuit) can be reduced, and the display drive circuit Can be miniaturized.

  Further, according to the present invention, the order of display data input in the order according to the arrangement order of the pixels of the display panel in the line direction is equivalent to X pixels (1 <X) that each conversion circuit in the display control circuit takes charge of. <In order to change the order of display data for Y pixels (1 ≦ Y <X, Y is an integer) among the display data of the number of pixels in which each display drive circuit is responsible, X is an integer) Circuits (for example, DA conversion circuits and latch circuits) can be reduced, and the display drive circuit can be downsized.

  In addition, according to the present invention, γ correction can be performed for each R, G, or B, so that RGB γ characteristics can be made uniform, and image reproducibility can be improved.

1A and 1B are diagrams illustrating a first embodiment, in which FIG. 1A is a diagram illustrating a configuration, and FIG. 1B is a diagram illustrating a relationship of data rearrangement in display data 102 and display data 108; 2 is a diagram showing a configuration of a timing control circuit 104. FIG. It is a figure which shows the structure of the data line drive circuit 116-1. It is a figure which shows the structure of sample hold circuit 310-j. FIG. 6 is a timing chart showing the operation of the timing control circuit 104. It is a timing chart showing the operation of the data line drive circuit 116-1, 116-2. FIG. 8 is a diagram illustrating a second embodiment, where (A) is a diagram illustrating a configuration, and (B) is a diagram illustrating a relationship of rearrangement of data in display data 102 and display data 108. 3 is a diagram illustrating a configuration of a gradation reference voltage generation circuit 703. FIG. 7 is a timing chart showing the operation of the gradation reference voltage generation circuit 703. FIG. It is a figure which shows the structure of 3rd embodiment. 2 is a diagram illustrating a configuration of an output circuit 121. FIG. FIG. 12 is a diagram showing a configuration of an output circuit 121 different from FIG. 11. FIGS. 11A and 11B are diagrams illustrating transfer timing of display data, FIG. 11A is a diagram illustrating transfer timing in the output circuit 121 in FIG. 11, and FIG. 12B is a diagram illustrating transfer timing in the output circuit 121 in FIG. 12;

The present invention will be described in detail below with reference to examples.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1A is a diagram showing a configuration of the present invention, and the liquid crystal display system has a resolution of 12 × 3 pixels, 10 pixels / 1024 gray scale display.

  Reference numeral 100 denotes an external system (for example, a personal computer), 101 denotes a liquid crystal display panel, and 12 columns Y1 to Y12 in the column direction on the data side and 3 rows from X1 to X3 in the row direction on the scanning side. And a plurality of pixels arranged in a 12 × 3 matrix. Reference numerals 102 and 103 denote display data and control signals input from the external system 100, and the display data 102 is composed of 8 bits or 10 bits per pixel. 104 is a timing control circuit (TCON) for outputting display data and control signals, 105 is a setting signal for the timing control circuit 104, and the timing control circuit 104 stores display data for a plurality of lines (for example, two lines) therein. Line memories 106-1 and 106-2. Each of the line memories 106-1 and 106-2 has a storage capacity for one line, and the two of the line memories 106-1 and 106-2 have a storage capacity for one line. 107 is a scanning line driving circuit control signal for determining the applied voltage timing in the row direction in the liquid crystal display panel 101, and 108 is the timing control circuit 104 for one horizontal scanning period (the data line driving circuits 116-1 and 116-2 are for one line). The display data is rearranged (changed in order) within the interval in which the grayscale voltages are collectively applied to the pixels of the liquid crystal display panel 101). 109 is a synchronous clock for display data, 110 is an alternating signal for controlling the polarity of the gradation voltage applied to the liquid crystal display panel 101, and 111 is an output of the gradation voltage to be applied to the liquid crystal display panel 101 for the liquid crystal display panel 101. This is an output signal that defines the timing. Reference numeral 112 is a reference voltage input from the outside, and consists of two levels of voltage values. 113 is a gradation reference voltage generation circuit, and 114 is a gradation reference voltage. The gradation reference voltage generation circuit 113 divides the reference voltage to generate a gradation reference voltage 114 having 18 levels. Reference numeral 115 denotes a scanning line driving circuit that determines a voltage to be applied to the scanning line based on the scanning line driving circuit control signal 107. Reference numerals 116-1 and 116-2 denote data line driving circuits. The internal circuit configuration has the same function. The data line driving circuit 116-1 outputs gradation voltages corresponding to display data to the data lines Y1 to Y6 of the liquid crystal display panel 101, and the data line driving circuit 116-2 outputs to Y7 to Y12. The number of data line driving circuits 116 is preferably 3 or more, but in the present embodiment, it is set to 2 for convenience of explanation. Reference numeral 117-1 is an input enable signal for the data line driving circuit 116-1, and 117-2 is an input enable signal for the data line driving circuit 116-2. The input enable signal 117-1 is always at a high level, and the input enable signal 117-2 is output from the data line driving circuit 116-1. The data line driving circuits 116-1 and 116-2 start capturing display data based on the display data 108, the output signal 111, and the input enable signals 117-1 and 117-2. 118 is a timing control circuit in the data line driving circuit 116, 119 is a voltage dividing circuit that divides the gradation reference voltage 114 and generates gradation voltages of a total of 2048 levels of positive 1024 levels and negative 1024 levels, 120 is a divided gradation voltage. Reference numerals 121-1 and 121-2 are conversion blocks for converting digital data into analog data by selecting one level voltage from the gradation voltage 120 based on the display data 108 and the AC signal 110. Both 121-2 have equivalent functions. An output circuit 122 outputs analog data (gradation voltage) to the liquid crystal display panel 101. However, the line memory 106 may have only one line memory for one line.

FIG. 1B is a diagram showing the relationship of data rearrangement in the display data 102 and the display data 108 shown in FIG. 1A. D1, D2,..., D12 are columns of the liquid crystal display panel 101, respectively. This is 8-bit or 10-bit display data corresponding to the direction terminals Y1, Y2,. The timing control circuit 104 converts the display data 102 inputted in the order of D1, D2,... D12 (horizontal pixel arrangement order of the liquid crystal display panel) into D1, D4, D7, D10,. The display data 108 is output. If there is one conversion block 121 in the data line driving circuit 116, the order of the display data 108 is D1, D7, D4, D10, D2, D8, D5, D11, D3, D9, D6, D12. Also good. That is, in this case, the timing control circuit 104 alternately outputs the display data 108 to the data line driving circuit 116-1 and the data line driving circuit 116-2. If the number of data line driving circuits 116 is N, D1 goes to the first data line driving circuit 116-1, D7 goes to the second data line driving circuit 116-2, and the third data line driving circuit 116-2. D13, ...
-You may output to the Nth data line drive circuit 116-N in order of D (6N-5). Here, D1 to D6 are display data groups that the data line driving circuit 116-1 outputs to the liquid crystal display panel 101 during one horizontal period, that is, display data groups that are simultaneously (collectively) output to the liquid crystal display panel 101. is there.

  FIG. 2 is a diagram showing a detailed configuration of the timing control circuit 104. 200 is an interface for inputting display data 102, control signal 103, and setting signal 105 from external system 200, 201 is a timing adjustment circuit, 202-1 and 201-2 are display data bit number selection circuits, and 203 is the number of data bits. Is a lookup table for converting. The timing adjustment circuit 201 is based on the control signal 103 and the setting signal 105, the timing signal 204 serving as a reference for the internal operation of the timing control circuit 104, the memory control signals 205-1 and 205-2 defining the memory access timing, and the internal reference clock. 206 is generated. Reference numeral 207 denotes display data composed of 10 bits. When the display data 102 input from the external system 100 is 8 bits per pixel, the number of circuits 201-1 and 201-2 are used to change the system via the lookup table 203. By selecting, the 8-bit display data is converted to 10-bit display data. When the display data 102 is 10 bits, the display data that has been passed through by selecting a system that does not go through the lookup table 203 is obtained. Write to the line memories 106-1 and 106-2 based on the memory control signals 205-1 and 205-2. Reference numeral 208 denotes display data read from the line memories 106-1 and 106-2. Reference numeral 209 denotes a PLL circuit that multiplies the internal reference clock 206 to generate the reference clock 210. A display data timing adjustment circuit 211 generates display data 108 based on the timing signal 204, display data 208, and reference clock 210. Reference numeral 212 denotes a data line driving circuit timing adjustment circuit which receives a synchronization clock 109, an AC signal 110, and an output signal 111 necessary for the operation of the data line driving circuits 116-1 and 116-2 based on the timing signal 204 and the reference clock 210. Generate. A scanning line driving circuit timing adjustment circuit 213 generates a scanning line driving control signal 107 necessary for the operation of the scanning line driving circuit 115 based on the timing signal 204 and the reference clock 210.

  FIG. 3 is a diagram showing a detailed configuration of the data line driving circuit 116-1. In FIG. 1, blocks having equivalent functions are denoted by the same reference numerals. 301-i (i = 1, 2) is the first latch circuit, 302-i is the first latch signal, 303 is the alternating signal for determining the polarity of the gradation voltage, and 304-i is the display data. The first latch circuit 301-i latches the 10-bit display data 108 and the AC signal 303 with the first latch signal 302-i, and generates 11-bit display data 304-i. 305-i is a second latch circuit, 306 is a second latch signal, 307-i is display data, and the second latch circuit 305-i latches display data 304-i with the second latch signal 306. Display data 307-i is obtained. 308-i is a DA conversion circuit, 309-i is an output voltage, and the DA conversion circuit 308-i is a 2048 level gradation voltage generated by dividing the 18 level gradation reference voltage 114 by the voltage dividing circuit 119. A voltage level of one level is selected from 119 based on the display data 307-i and output as an output voltage 309-i. Here, the first latch circuit 301-1, the second latch circuit 305-1, and the DA conversion circuit 308-1 constitute the conversion block 121-1 shown in FIG. -2, the second latch circuit 305-2, and the DA conversion circuit 308-2 constitute a conversion block 121-2. 310-j (j = 1 to 6) is a sample hold circuit, 311-k (k = 1, 2, 3) is a control signal group of the sample hold circuit 310-j, and 312-j is a sample hold circuit 310-j. Is an output voltage output from. As shown in the figure, the control signal group 311-1 is input to the sample hold circuits 310-1 and 310-4, and the control signal group 311-2 is input to the sample hold circuits 310-2 and 310-5. Then, the control signal group 311-3 is input to the sample hold circuits 310-3 and 310-6. The sample hold circuit 310-j performs sampling and hold operations of the output voltages 309-1 and 309-2 based on the control signal group 310-k, respectively, so that the sample hold circuit 310-j can perform the appropriate timing (for example, the timing of one horizontal scanning cycle). Output voltage 312-j (gray scale voltage) is output. Reference numeral 313 denotes a group of six output switches corresponding to the output terminals, and reference numeral 314 denotes a control signal for determining an on state and an off state of the output switch group. The data line driving circuit 116-2 is obtained by changing the input enable signal 117-1 to 117-2 in FIG. 3, and the output enable signal in the data line driving circuit 116-2 has no data line driving circuit as a slave. Makes no sense to do so.

  FIG. 4 is a diagram showing a configuration of the sample hold circuit 310-j (j = 1 to 6), and each of the sample hold circuits 310-1 to 310-6 shown in FIG. 3 has a function equivalent to that of FIG. .

  401 is a buffer amplifier, 402-1 and 402-2 are sampling signals, 403-1 and 403-2 are switch circuits that are turned on and off by the sampling signals 402-1 and 402-2, and 404-1, 404- 2 is a holding capacitor, 405-1 and 405-2 are hold signals, 406-1 and 406-2 are switch circuits that are turned on and off by the hold signals 405-1 and 405-2, and 407 is an output buffer. . The sampling signals 402-1 and 402-2 and the hold signals 405-1 and 405-2 are components of the control signal group 311-j.

  FIG. 5 is a timing chart showing the operation of the timing control circuit 104.

  FIG. 6 is a timing chart showing the operation of the data line driving circuits 116-1 and 116-2.

  The operation of each circuit will be described based on the above drawings.

  Since the liquid crystal display panel 101 in this embodiment has a matrix structure of 12 × 3 pixels, display data 102 for one line and 12 pixels corresponding to Y1, Y2,..., Y12 of the liquid crystal display panel 101 is D1, D2. ,..., D12 are sequentially transferred. The input display data 102 passes through the line memories 105-1 and 105-2 in the timing control circuit 104, and as shown in FIG. 1B, D1, D4, D7, D10, D2, D5, D8, D11. , D3, D6, D9, and D12 are rearranged and output as display data 108.

  This operation will be described in detail with reference to FIGS. When the input signal (display data 102) from the external system 100 is 8 bits, the display data 102 input to the timing control circuit 104 is displayed on the liquid crystal display by interpolating and expanding the 8-bit data using the lookup table 203. The converted display data 207 consisting of 10 bits per pixel corresponding to the characteristics of the panel 101 is obtained. When the input signal is 10 bits, it is directly transferred to the line memories 105-1 and 105-2 without going through the lookup table 203.

  When γ correction is performed, the data may be converted from 10 bits to 10 bits as necessary. Whether the number of bits of the input signal is 8 bits or 10 bits may be determined by the bit selection circuits 202-1 and 202-2, or by the external system 100 and determined by the bit selection circuits 202-1 and 202-. 2 may be controlled. The γ correction refers to adjusting the amplitude and inclination of the γ characteristic (voltage-gradation characteristic).

  The display data 207 obtained in this way is one of the line memories 106-1 and 106-2 based on the memory control signals 205-1 and 205-2 generated by the timing adjustment circuit 201 based on the control signal 103. The data is written to one side and is read out as display data 208 from the other line memory where writing is not performed. The writing and reading at this time are performed in units of one horizontal scanning period as shown in FIG. 5. For example, when writing is sequentially performed to the line memory 105-1, D1, D2, D3. From the other line memory 105-2, display data one line before is read as D1, D4, D7, D10,..., D9, D12 as described above. In the next horizontal scanning period, data D1, D2, D3,..., D12 are written in the line memory 105-2 that has been previously read, and the lines that were written before one horizontal scanning period are written. In the same manner as the reading order from the memory 105-1 and 105-2, D1, D4, D7, D10,..., D9, D12 are read out.

  The read display data 207 is set by the display data timing adjustment circuit 211 to a reset signal RST in an invalid display data area shaded with display data shown in FIG. The reset signal RST has a specific pattern, and the data line driving circuits 116-1 and 116-2 reset the internal circuit when detecting this signal pattern after the output signal 111 rises.

  At the same time, a synchronous clock 109 synchronized with display data which is a control signal of the data line driving circuits 116-1 and 116-2, an alternating signal 110 for determining the positive polarity and the negative polarity of the gradation voltage for the liquid crystal display panel 101, and An output signal 111 for determining the output timing of the gradation voltage to the liquid crystal display panel 101 is generated by the data line driving circuit timing adjustment circuit 212, and a scanning driving circuit control signal 107 for controlling the scanning line driving circuit 115 is generated by the scanning driving circuit. It is generated by the timing adjustment circuit 213. The PLL circuit 209 is provided in order to reduce the number of data buses of display data by multiplying the internal reference clock 206 and to realize high-speed transfer of display data and a synchronous clock. . The display data 108 including the reset signal generated in this way, the synchronous clock 109, the AC signal 110, and the output signal 111 are sent to the data line driving circuits 116-1 and 116-2 via a multi-drop bus configuration. Forwarded. At the same time, the scanning line driving circuit control signal 107 is transferred to the scanning line driving circuit 115. The operation of the scanning line driving circuit 115 is the same as that of the conventional example and will not be described in detail here.

  The operation of the data line driving circuits 116-1 and 116-2 based on the display data rearranged as described above will be described with reference to FIGS.

  The data line driving circuits 116-1 and 116-2 both have the same circuit, and start to capture display data based on the display data 108, the synchronous clock 109, the output signal 111, and the input enable signals 117-1 and 117-2. To do. Specifically, when the data line driving circuits 116-1 and 116-2 detect the RST signal in the display data 108 in a state in which the output signal 110 is at a high level, Counting is started by a counter that counts the internal synchronization clock. Here, since the input enable signal 117-1 is always at a high level, the data line driving circuit 116-1 becomes a data line driving circuit in a master state, and the display data is taken in after a predetermined clock after detecting the RST signal. In order to start, the first latch signals 302-1 and 302-2 are generated based on the count value of the counter described above. On the other hand, since the data line driving circuit 116-2 is in the slave state of the data line driving circuit 116-1 via the input enable signal 117-2, no latch signal is generated at this stage.

  The first latch signals 302-1 and 302-2 are signals whose display data is shifted by one pixel, and the first latch circuit 301-1 in the data line driving circuit 116-1 is the first latch signal 302. -1 based on the first latch circuit 301-2 and the display data D4 based on the first latch signal 302-2 at the next clock together with the AC signal 303 for determining the polarity of the gradation voltage. The data is latched to generate display data 304-1 and 304-2 consisting of a total of 11 bits including 10 bits of display data and 1 bit of the AC signal. Since the AC signal 303 is generally constant in at least one horizontal scanning period, it may be reflected at any timing until the gradation voltage is determined.

  At the same time, the timing control circuit 118 in the data line driving circuit 116-1 generates the input enable signal 117-2 based on the count value of the counter. The input enable signal 117-2 is a signal for instructing start of display data capture in the data line driving circuit 116-2.

  In this embodiment, since it is composed of conversion blocks for two pixels 121-1 and 121-2, display data for two pixels is captured by a single enable signal. Accordingly, as shown in FIG. 6, the input enable signal 117-2 is set to the high level before D7 which is the first display data corresponding to the data line driving circuit 116-2 is transferred in one horizontal scanning period. Output. Based on the input enable signal 117-2, the data line driving circuit 116-2 receives the display data of D7 and D10 in the same manner as 116-1, and the first latch circuits 301-1 and 301 in the data line driving circuit 116-2, respectively. -2 to capture.

  In this way, D1 and D4 captured by the data line driving circuit 116-1 and D7 and D10 captured by the data line driving circuit 116-2 are then second based on the second latch signal 306. Are latched by the latch circuits 305-1 and 305-2, and display data 307-1 and 307-2 consisting of 11 bits are obtained. At the same time, the gradation reference voltage 114 consisting of 18 levels is divided by the voltage dividing circuit 119 to obtain a gradation voltage 120 consisting of a total of 2048 levels of positive 1024 levels and negative 1024 levels. The gradation voltage 120 obtained in this way is input to the DA conversion circuits 308-1 and 308-2. The DA conversion circuits 308-1 and 308-2 select one level voltage from the 2048 level gradation voltage 120 based on the 11-bit display data 307-1 and 307-2, respectively, and output voltages 309-1 and 309-. 2 is generated.

Through the above operation, the digital data is converted to the analog voltage based on the display data D1, D4, D7, and D10, and the converted voltages are output voltages 309-1 and 309- of the data line driving circuits 116-1 and 116-2, respectively. 2 is generated.
Next, the display data is transferred to D2, D5, D8, and D11. When each circuit operates in time series, the data is taken in based on the internal counter of the timing control circuit 118, and D1, D4, Similarly to D7 and D10, D2, D5, D8, and D11 are incorporated into the data line driving circuits 116-1 and 116-2, respectively. That is, if the display data D1 and D2 are fetched when the count value of the internal counter of the data line driving circuit 116-1 is 1, 2, the next time the count value becomes 5, 6, the display is performed. Data D2 and D5 are taken in and output voltages 309-1 and 309-2 are generated via DA conversion circuits 308-1 and 308-2. On the other hand, the data line driving circuit takes in D8 and D11 based on the input enable signal 117-2 and converts it into an output voltage.
The same applies to the display data D3, D6, D9, and D12 transferred next. Therefore, the output voltage 309-1 in the data line driving circuit 116-1 is a voltage based on D1, D2, and D3 in one horizontal scanning period, and the output voltage 309-2 is a voltage based on D4, D5, and D6. Further, the output voltage 309-1 in the data line driving circuit 116-2 is a voltage based on D7, D8, and D9 in one horizontal scanning period, and the output voltage 309-2 is a voltage based on D10, D11, and D12. Hereinafter, as shown in FIG. 6 determined based on Dx (x = 1 to 12), the voltage level is denoted as Vx.
The output voltage Vx thus generated is subjected to a voltage level holding operation in each sample and hold circuit 310-j. This operation will be described next. The output voltage Vx input to each sample and hold circuit 310-j is based on the sampling signal 402-1 or sampling signal 402-2 shown in FIG. It is written in either one of 404-2. As shown in FIG. 6, the voltage to be written is written alternately in the storage capacitors 404-1 and 404-2 every horizontal scanning period, with the horizontal scanning period of two rows as one cycle. For example, in the scanning period corresponding to the portion indicated by (3) in FIG. 6, the output voltages V1 (3) and V4 (3) that are first converted into analog voltages in the data line driving circuit 116-1 respectively. Data is written in the holding capacitors 404-1 of the sample hold circuits 310-1 and 310-4. Next, the switch circuit 403-1 is opened at the timing before the voltage levels of the output voltages 309-1 and 309-2 change from V1 (3), V4 (3) to V2 (3), V5 (3). The writing operation is defined as a holding operation. When the voltage level changes to V2 (3) and V5 (3), the switch circuit 403-1 in the sample hold circuits 310-2 and 310-5 is changed from the open state to the closed state, so that the corresponding holding capacitors 404- 1 is written. The same operation is performed when the voltage level changes from V2 (3), V5 (3) to V3 (3), V6 (3). With the above operation, the writing / holding operation of the output voltages V1 (3) to V6 (3) is performed on the holding capacitors 404-1 in the sample hold circuits 310-2 to 310-6. In the next horizontal scanning period, the writing and holding operations of the output voltages V1 (4) to V6 (4) are performed on the holding capacitors 404-2 in the sample hold circuits 310-2 to 310-6.
When writing is performed to the storage capacitors 404-1 of all the data line driving circuits 116-1 and 116-2 by transferring all the display data for one row, the switch circuit 403-1 is in an open state. By simultaneously opening all the switch circuits 406-1 of the sample hold circuit 310-j, the held voltage level is read out, and is amplified based on the output buffer 111 after being amplified through the output buffer 407. By opening / closing the output switch group by the control signal 314, the voltage levels V1 (3) to V6 (3) are output to the liquid crystal display panel 101. The liquid crystal display panel 101 realizes display by performing gradation display based on voltages output from the data line driving circuits 116-1 and 116-2 in each scanning period.
As described above, according to the present embodiment, the first latch circuit is required for each output terminal in the conventional data line driving circuit, that is, 12 circuits are required according to the present embodiment. The second latch circuit and the DA converter circuit need only be two circuits, and the circuit scale can be greatly reduced. Instead, a sample-and-hold circuit for the number of output terminals is required, but the increasing circuit is a circuit that holds analog data, so if the number of display data bits increases, the total chip size can be reduced. It becomes possible.
Further, in this embodiment, a plurality of data line driving circuits are regarded as one circuit, and display data is transferred not in units of data line driving circuits but in units of conversion blocks. That is, D1 is input to the conversion block 121-1, then D4 is input to the conversion block 121-2, then D2 is input to the conversion block 121-1, and then D5 is input to the conversion block 121-2. And then. D3 is input to the conversion block 121-1, and then D6 is input to the conversion block 121-2. As a result, the bus configuration related to the data line driving circuit can be set to the same multi-drop format as that of the prior art, so that the conventional assets can be utilized for the board design of the data line driving circuit. Furthermore, since the display data bus and the synchronous clock bus can be designed in the same bus format, the influence of the delay of the display data and the synchronous clock for each chip can be ignored, so that display data can be transferred at higher speed.
Here, the number of conversion blocks in one data line driving circuit is defined by the period during which the sample-and-hold circuit samples the output voltage. If a long period can be secured for one sampling, the conversion block 121 including the DA conversion circuit can be secured. Can be reduced. As shown in this embodiment, by performing data transfer in units of conversion blocks 121 instead of in units of chips as in the prior art, it is possible to secure a sufficiently long sample and hold period, thereby realizing a smaller chip for the data line driving circuit. It becomes possible. It is sufficient that the sampling period can be secured for about 1 microsecond. When this is applied to the actual liquid crystal display panel 101, for example, a liquid crystal display panel having a resolution of 1366 × RGB × 768 suitable for a wide-screen TV liquid crystal display 414 is obtained. 10 output data line driving circuits are applied, and the display data bus and the synchronous clock bus are divided into a left and right multi-drop data bus structure 1 horizontal scanning period is 20 microseconds, and conversion per data line driving circuit is performed. If the number of blocks is 36, the number of output terminals corresponding to one conversion block is 11 or 12, so that 20 ÷ 12 = 1.6 microseconds can be secured in the sampling period. Similarly, when ten data line drive circuits with 384 outputs are applied to a liquid crystal display panel having a resolution of 1280 × RGB × 768 and the data bus configuration is divided into left and right, conversion per data line drive circuit is performed. Even when the number of blocks is 32, the sample hold period is 1.6 microseconds, and in any case, a sufficient sample hold period can be secured.

Next, in addition to the first embodiment, a case where a display device with higher image quality is provided by changing the gradation reference voltage will be described with reference to FIGS.
FIG. 7A is a diagram illustrating a configuration of the second embodiment, and 701 to 703 are different from those in FIG. Similarly to the first embodiment, the display data is 10 bits per pixel, the liquid crystal display panel 101 is one pixel composed of three RGB pixels, and the column electrodes Y1, Y4, Y7, Y10 correspond to the display color R, Y2, Y5, Y8, and Y11 correspond to the display color G, and Y3, Y6, Y9, and Y12 correspond to the display color B. Reference numeral 701 denotes a timing control circuit, reference numeral 702 denotes a gradation reference voltage generation circuit control signal, reference numeral 703 denotes a gradation reference voltage generation circuit, and reference numeral 704 denotes a gradation reference voltage.
FIG. 7B shows the transfer order of the display data 102 and 108 and, as a result, is similar to FIG. 1, but in this embodiment, data corresponding to the display color R in one horizontal scanning period. Is transferred first, then data corresponding to the display color G is transferred, and finally data corresponding to the display color B is transferred.
FIG. 8 is a diagram showing a configuration of the gradation reference voltage generation circuit 703. 801-R, 801-G, and 801-B generate gradation reference voltages corresponding to the display colors of R, G, and B, respectively. Voltage dividing circuits 802-R, 802-G, and 802-B are gradation reference voltages corresponding to the R, G, and B display colors divided by the voltage dividing circuit, and 803 is a gradation reference voltage generation. Based on the circuit control signal 702, a selection circuit for selecting one of the gradation reference voltages from among 802-R, 802-G, and 802-B, 804 is the selected gradation reference voltage, and 805 is the gradation reference voltage. 806 is a register for setting a γ characteristic, that is, a voltage value for a gradation number, for each of R, G, and B display colors.
FIG. 9 is a timing chart showing the operation of the gradation reference generation voltage generation circuit 703.
The operation of the second embodiment will be described based on the above drawings.
As shown in FIG. 7A, the timing control circuit 701 in the present embodiment generates a gradation reference voltage generation circuit control signal 702 based on the control signal 103 in addition to the signals shown in the first embodiment.
As shown in FIG. 9, the gradation reference voltage generation circuit control signal 702 is a 2-bit signal used for switching the gradation reference voltages 802-R, 802-G, and 802-B in the gradation reference voltage generation circuit 703. . Before describing the logic of the gradation reference voltage generation circuit 703, the operation of the gradation reference voltage generation circuit 703 will be described.
The gradation reference voltage generation circuit 703 includes the circuit shown in FIG. The voltage dividing circuits 801-R, 801-G, and 801-B generate gradation reference voltages 802-R, 802-G, and 802-B each having a voltage value of 18 levels by dividing the reference voltage 112, respectively. To do. The gradation reference voltages 802-R, 802-G, and 802-B are gradation reference voltages corresponding to the γ characteristics of the display color R, display color G, and display color B of the liquid crystal display panel 101, respectively. Constant voltage.
Here, the voltage value of 802-R is VR17>VR16>...> VR0, the voltage value of 802-G is VG17>VG16>...> VG0, and the voltage value of 802-B is VB17>VB16>...> VB0. The generated gradation reference voltages 802 -R, 802 -G, and 802 -B are selected by the selection circuit 803 as the gradation reference voltage 804 based on the gradation reference voltage generation circuit control signal 702. In this selection method, as shown in FIG. 6, when the gradation reference voltage generation circuit control signal 702 consisting of 2 bits is “00”, VR17 is selected from VR17, VG17, and VB17, and VR16, VG16, and VB16 are selected. VR16 is selected from ..., VR0 is selected from VR0, VG0, VB0, and in the case of "01", VG17 is selected from VR17, VG17, VB17, and VG16 is selected from VR16, VG16, VB16, ..., VG0 is selected from VR0, VG0, VB0, and in the case of "10", VB17 is selected from VR17, VG17, VB17, VB16 is selected from VR16, VG16, VB16, ..., VR0, VG0, Select VB0 from VB0. The gradation reference voltage 804 thus selected is amplified by the amplifier circuit 805 and then supplied to the data line driving circuits 116-1 and 116-2 as the gradation reference voltage 704. Here, as shown in FIG. 1B, in this embodiment, the display colors of the liquid crystal display panel 101 are first displayed in the DA conversion circuits 308-1 and 308-2 in the data line driving circuit for one horizontal scanning period. Analog conversion corresponding to R is performed, then conversion corresponding to display color G is performed, and finally analog conversion corresponding to display color B is performed. Therefore, in one horizontal scanning period, the output voltages corresponding to D1, D4, D7, and D10 corresponding to the display color R are first applied to the sample and hold circuits 311-1 and 311-4 of the data line driving circuits 116-1 and 116-2. In the period of writing, the gradation reference voltage 703 is set to the gradation reference voltage 802-R corresponding to the display color R. From R to the gradation reference voltage 802-G corresponding to the display color G. Next, the output voltages corresponding to the display colors G, D2, D5, D8, and D11, are output until the writing to the sample hold circuits 311-2 and 311-5 of the data line driving circuits 116-1 and 116-2 is completed. The gradation reference voltage 703 is set to the gradation reference voltage 802-G corresponding to the display color G, and the gradation reference voltage 703 is changed from 802-G to the gradation reference voltage 802-B corresponding to the display color B after the writing is completed. . Next, output voltages corresponding to display colors B, D3, D6, D9, and D12, are output until writing to the sample hold circuits 311-3 and 311-6 of the data line driving circuits 116-1 and 116-2 is completed. The gradation reference voltage 703 is set to the gradation reference voltage 802-B, and the gradation reference voltage 703 is changed from 802-B to the gradation reference voltage 802-R corresponding to the display color R after the writing is completed. The gradation reference voltage generation circuit control signal 702 may be generated by the timing control circuit 701 so that such switching is performed, and this can be easily realized based on the input control signal 103.
As described above, according to the present embodiment, a gradation reference voltage input terminal for each display color is provided for the data line driving circuits 116-1 and 116-2, or a voltage dividing circuit for each display color is used as data. Since it is not necessary to provide in the line drive circuit, it is possible to set γ correction for each display color (RGB) based on the gradation reference voltage without increasing the chip size of the data line drive circuit. .

Next, a specific configuration when the number of outputs of the data line driving circuit is set to a more realistic value will be described with reference to FIGS. Hereinafter, the description of the present embodiment will not be made for portions that functionally overlap with the first embodiment.
FIG. 10 is a diagram showing the configuration of this embodiment. In the present embodiment, the horizontal resolution of the liquid crystal display panel 101 is set to 1280 × 3 pixels, and column electrodes thereof are counted as Y1, Y2,..., Y3840 from the left side in the drawing. The number of output terminals per data line driving circuit is 384 outputs. Therefore, ten data line driving circuits indicated by 116-1 to 116-10 are used, and a display data bus and a synchronous clock bus having a high transfer speed are paired in a multi-drop configuration in which five left and right are paired. Multi-drop transfer is performed in which an alternating signal and an output signal having a slow transfer speed are in the form of a left and right common bus.
Reference numeral 1001-1 denotes a display data and synchronous clock data bus for five data line driving circuits 116-1 to 116-5 (first group) on the left side of the drawing, and 1001-2 denotes five data line driving circuits on the right side of the drawing. This is a data bus for display data and a synchronous clock for 116-6 to 116-10 (second group). Reference numeral 1002 denotes a data bus for alternating signals and output signals.
FIG. 11 is a diagram showing a configuration of the output circuit 122 in the data line driving circuits 116-1 to 116-10 having output terminals of 384 outputs. The block has a function equivalent to that of the data line driving circuit shown in FIG. Are denoted by the same reference numerals.
FIG. 12 is a diagram showing the configuration of the output circuit 122 different from that in FIG. 11. Like FIG. 10, blocks having the same functions as those of the data line driving circuit shown in FIG.
13A is a timing chart showing the transfer order of display data 1001-1 and 1001-2 when the output circuit shown in FIG. 11 is provided, and FIG. 13B is a case where the output circuit shown in FIG. 12 is provided. FIG. 10 is a timing chart showing the transfer order of the display data 1001-1 and 1001-2.
The operation of this embodiment will be described based on the above drawings.
The output circuit 121 shown in FIG. 11 includes 32 DA conversion circuits indicated by 308-1 to 308-32 and 384 sample hold circuits indicated by 310-1 to 310-384. The hold circuit is connected to the liquid crystal panel via the switch circuit 313. In this output terminal, the output terminal of the sample hold circuit 310-1 is connected to Y1, the output terminal of 310-2 is connected to Y2,..., 310-384 are connected to Y384. Since the DA conversion circuit is composed of 32 pieces, the first latch circuit and the second latch circuit (not shown) are also composed of 32 pieces.
The connection form between the DA conversion circuits 308-1 to 308-32 and the sample hold circuits 310-1 to 310-384 is such that the output terminal of the DA conversion circuit 308-1 is connected to the sample hold circuits 310-1 to 310-12. , 308-2 are connected to sample hold circuits 310-13 to 310-24,..., 308-32 are connected to 310-373 to 310-384.
The control signal group 311-1 of the sample hold circuit corresponds to the sample hold circuits 310-1, 310-13, 310-25,... 310-361, 310-373, 311-2 is 310-2, 310-14, 310-26, ... 310-362, 310-374, ..., 311-12 are 310-12, 310-24, 310-36, ... 310-372, 310 -384 corresponds to a circuit having a subscript of 12 and the corresponding sample and hold circuits operate simultaneously.
As shown in FIG. 13A, the display data transfer order in this configuration is as follows: D1 in the horizontal scanning period for the display data bus on the left side of the drawing having the data line driving circuits 116-1 to 116-5. D13, D25,..., D1909, and display data for every 12 pixels are transferred from D1. Since the number of DA conversion circuits for five data line driving circuits is 5 × 32 = 160, when display data for 160 pixels is transferred, the display data again returns to display data corresponding to the data line driving circuit 116-1. Display data for 160 pixels is transferred again every 12 pixels as D2, D14,..., D1910. By repeating this 12 times, the display data for 160 × 12 = 1920 pixels is transferred, and the transfer of the display data corresponding to all the column electrodes of the data line driving circuits 116-1 to 116-5 is completed. .
Similarly, to the display data bus on the right side of the drawing, display data for every 12 pixels is transferred from D1921 for 160 pixels, then display data for every 12 pixels is transferred from D1922 for 160 pixels, and so on. By repeating the 12th floor, the transfer of display data corresponding to all the column electrodes of the data line driving circuits 116-6 to 116-10 is completed.
Further, the output circuit 121 shown in FIG. 12 includes 32 DA conversion circuits indicated by 308-1 to 308-32 and 310-1 to 31.
The output terminal connected to the liquid crystal panel through the switch circuit 313 from each sample and hold circuit is composed of 384 sample and hold circuits indicated by reference numerals 0 to 384. The output terminal of the sample and hold circuit 310-1 is Y1 and 310. -2 output terminal is connected to Y2,..., 310-384 output terminals are connected to Y384.
The connection form between the DA conversion circuits 308-1 to 308-32 and the sample hold circuits 310-1 to 310-384 is the sample hold circuit 310-1, 310-33 having 12 output terminals of the DA conversion circuit 308-1. 310-65, ..., 310-353, and the output terminal of 308-2 is connected to 310-2, 310-34, 310-66, ..., 310-354, ... 308-32 output terminals are connected to 310-32, 310-64, 310-96,..., 310-384.
Further, the control signal group 311-1 of the sample hold circuit corresponds to the sample hold circuits 310-1 to 310-32, 311-2 corresponds to 310-33 to 310-64,. Corresponding to 310-353 to 310-384, the corresponding sample hold circuits operate simultaneously.
As shown in FIG. 13B, the display data transfer order in this configuration is as shown in FIG. 13B. For the display data bus on the left side of the drawing having the data line driving circuits 116-1 to 116-5, the data lines in one horizontal scanning period. The display data D1 to D32 for 32 pixels corresponding to Y1 to Y32 of the drive circuit 116-1 are transferred, then D385 to D416 corresponding to Y1 to Y32 of 116-2 are transferred, and then 116-3. D769 to D800 corresponding to Y1 to Y32 are transferred, and then D1537 to D1568 corresponding to Y1 to Y32 of 116-5 are transferred. When display data for 160 pixels corresponding to the data line driving circuits 116-1 to 116-5 is transferred in this way, display data D33 to D64 corresponding to Y33 to Y64 of the data line driving circuit 116-1 are transferred again. Next, display data D417 to D448 corresponding to Y33 to Y64 of 116-2 are transferred, and the display data for 1920 pixels is transferred by repeating this. Similarly, display data shifted by 1920 pixels from the transfer order on the left side of the drawing is similarly transferred to the display data bus on the right side of the drawing.
As described above, in the data line driving circuit using the sample and hold circuit, the display data is transferred in a pattern according to the connection relation of the DA conversion circuit, the sample and hold circuit, and the sample and hold circuit control signal in the data line driving circuit. A multi-drop display data bus can be realized.
According to the embodiment of the present invention, the display data is transferred in units of conversion blocks in the data line driving circuit, so that the multi-drop format using the data line driving circuit having a small chip area even when the number of bits is large. The display data bus can be realized. Further, by transferring display data for one line to each data line driving circuit for each color, it is possible to change the consistency for each color using an analog voltage.

  DESCRIPTION OF SYMBOLS 100 ... External system (Pc), 101 ... Liquid crystal display panel, 102 ... Display data, 103 ... Control signal, 104 ... Timing control circuit, 105 ... Setting signal of timing control circuit 104, 106-1, 106-2 ... Line memory , 107... Scanning line drive circuit control signal, 108... Display data, 109... Synchronous clock, 110 .. alternating signal, 111... Output signal, 112. 115, scanning line driving circuit, 116-1, 116-2 ... data line driving circuit, 117-1 ... input enable signal of data line driving circuit 116-1, 117-2 ... data line driving circuit, 116-2 ,... Timing control circuit, 119... Voltage dividing circuit, 120. 1-2 ... Conversion block, 122 ... Output circuit, 200 ... Interface, 201 ... Timing adjustment circuit, 202-1, 202-2 ... Bit number selection circuit, 203 ... Look-up table, 204 ... Timing signal, 205-1 205-2 ... Memory control signal, 206 ... Internal reference clock, 207 ... Display data, 208 ... Display data, 209 ... PLL circuit, 210 ... Reference clock, 211 ... Display data timing adjustment circuit, 212 ... Data line drive circuit timing adjustment Circuit, 213... Scanning line drive circuit timing adjustment circuit, 301-1 and 301-2 ... first latch circuit, 302-1 and 302-2 ... first latch signal, 303 ... alternating signal, 304-1 304-2 ... display data, 305-1 and 305-2 ... second latch circuit, 306-1 and 306- ... second latch signal, 307-1, 307-2 ... display data, 308-1, 308-2 ... DA conversion circuit, 309-1, 309-2 ... output voltage, 310-1 to 310-6 ... sample Hold circuit, 311-1 to 311-3, control signal group of sample hold circuit, 312-1 to 312-12, output voltage, 313, output switch group, 314, control signal, 401, buffer amplifier, 402-1, 402-2 ... Sampling signal, 403-1, 403-2 ... Switch circuit, 404-1, 404-2 ... Holding capacitor, 405-1, 405-2 ... Hold signal, 406-1, 406-2 ... Switch circuit 407, output buffer, 701, timing control circuit, 702, gradation reference voltage generation circuit control signal, 703, gradation reference voltage generation circuit, 704, gradation reference. Voltage, 801-R ... Voltage divider circuit corresponding to display color R, 801-G ... Voltage divider circuit corresponding to display color G, 801-B ... Voltage divider circuit corresponding to display color B, 802-R ... Display color. Tone reference voltage corresponding to R, 802-G ... Tone reference voltage corresponding to display color G, 802-B ... Tone reference voltage corresponding to display color B, 803 ... Selection circuit, 804 ... Tone reference voltage 805: Amplifier circuit, 806: Register.

Claims (14)

Met display control circuit for outputting the display data to the plurality of display driving circuit for applying a gradation voltage corresponding to display data to the pixels of the display panel,
An input circuit for receiving the display data in an order according to an arrangement order of pixels in the line direction of the display panel;
The order of the display data is determined for N pixels (1 ≦ N <M, where N is an integer) of display data for M pixels (1 <M <number of pixels for one line, M is an integer) for each display driving circuit. A control circuit to change the order of each display data (integer),
An output circuit for outputting the display data to the plurality of display drive circuits according to the order after the change,
Each of the plurality of display driving circuits has N gradation voltage D / A conversion blocks and M sample and hold circuits ,
Each of the gradation voltage D / A conversion blocks has one D / A conversion circuit,
The output from the D / A conversion circuit is held is sent to the sample-and-hold circuit,
There are M / N sample-and-hold circuits for one D / A converter circuit ,
The order after the change is the order in which the N gradation voltage D / A conversion blocks are assigned to the display data for each display data of the N pixels .
Display control circuit. A memory for storing display data for one or more lines of pixels of the display panel;
2. The control circuit according to claim 1, wherein the control circuit writes the display data to the memory in an order according to an arrangement order of pixels of the display panel in a line direction, and reads the display data from the memory in the changed order. Display control circuit.   The display control circuit according to claim 2, further comprising a conversion circuit that converts a number of bits of the display data from the input circuit and outputs the converted display data to the memory. The display panel includes a pixel for displaying R, a pixel for displaying B, and a pixel for displaying G.
The display control circuit according to claim 1, wherein the display data for N pixels is display data for each R, G, or B.   The display control circuit according to claim 1, wherein the output circuit outputs the display data to the plurality of display drive circuits via a bus common to the plurality of display drive circuits. The plurality of display drive circuits are divided into a plurality of groups,
The control circuit changes the order of the display data for each group,
The display control circuit according to claim 1, wherein the output circuit outputs the display data to the display drive circuit for each group in parallel between the groups via a common bus for each group.   The display control circuit according to claim 1, wherein the control circuit changes an order of the display data for each line of pixels of the display panel. A display driving circuit for applying a gradation voltage corresponding to display data to a pixel of a display panel,
An input circuit for inputting the display data from a display control circuit;
N conversion circuits for converting the digital display data into the analog gradation voltage;
M sample and hold circuits;
An output circuit for applying the gradation voltage to the pixel,
The display control circuit receives the display data in an order according to the arrangement order of the pixels of the display panel in the line direction, and the order of the display data is for M pixels (each of the plurality of display driving circuits). Of the display data of 1 <M <number of pixels for one line, M is an integer), the display data is changed to the order of display data for N pixels (1 ≦ N <M, N is an integer), and the order is changed according to the changed order. Output display data to the plurality of display drive circuits,
The changed order is the order in which the N conversion circuits are in charge of display data for each display data of N pixels,
Output from the conversion circuit is held is sent to the sample-and-hold circuit,
There are M / N sample-and-hold circuits for one conversion circuit .
Display drive circuit. A plurality of the conversion circuits are provided,
The display drive circuit according to claim 8 , wherein the input circuit sequentially outputs display data for the N pixels to the plurality of conversion circuits. A plurality of display drive circuits that apply a grayscale voltage corresponding to display data to the pixels of the display panel in units of lines, and a display control circuit that outputs the display data to the display drive circuit;
Each of the plurality of display driving circuits has N gradation voltage D / A conversion blocks and M sample and hold circuits,
Each of the gradation voltage D / A conversion blocks has one D / A conversion circuit,
The output from the D / A conversion circuit is sent to and held by the sample and hold circuit,
There are M / N sample-and-hold circuits for one D / A converter circuit,
The display control circuit receives the display data in order according to the order of arrangement of the line direction of the pixels of the display panel, the order of the display data, M pixels (1 each display driving circuit is responsible <M <The number of pixels for one line, M is an integer) The display data is changed to the order of display data for N pixels (1 ≦ N <M, N is an integer), and the display data is changed according to the changed order. Output to each display drive circuit,
The sequence after the change, in some order der consisting of display data the N pixels of N gradation voltage D / A conversion block for each display data is in charge,
Display circuit. The display driving circuit, when input display data of the N pixels, the enable signal for the other display drive circuit starts to input the display data to claim 10 to be output to the other display drive circuit The display circuit described. The display data for N pixels is display data for each R, G, or B,
The display circuit according to claim 10 , wherein the display driving circuit converts the digital display data into the analog gradation voltage for each display data of the N pixels. The display circuit according to claim 12 , further comprising a reference voltage generation circuit that generates a reference voltage for each of R, G, or B for the display drive circuit to generate a plurality of gradation voltages. The display circuit according to claim 13 , further comprising a register for setting a γ characteristic for each of R, G, or B for the reference voltage generation circuit.

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