JP5291567B2 - Test apparatus and conditional branch determination method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test device for a semiconductor device which can simultaneously match-detect a plurality of states. <P>SOLUTION: A match detection circuit 10 receives M (M is a natural number) signals from a DUT 102, and determines which of N (N is an integer of 2 or more) predetermined states each of the M signals matches. L (=M&times;N) first determination units 12 are provided for a corresponding one of combinations of M signals and N states. A first determination unit 12 corresponding to the i-th (1&le;i&le;M) signal and the j-th (1&le;j&le;N) state compares the level of the i-th signal with an expected value expected in the i-th state, and when the level of the i-th signal matches the expected value expected in the i-th state, asserts a first determination signal. N second determination units 18 are provided for a corresponding one of the N states. A second determination unit 18 corresponding to k (1&le;k&le;N) receives M first determination signals from M first determination unit 12 corresponding to the k-th state, and when all the M first determination signals are asserted, asserts a second determination signal. The test device 100 performs conditional branch processing depending on the N second determination signals. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device test apparatus.

  A test apparatus is used to evaluate a semiconductor device such as a memory or an SOC (System On Chip). The test apparatus evaluates a DUT (device under test) based on a test sequence program (also simply referred to as a test program) defined by the user. The test apparatus sequentially executes the processes described in the test program in synchronization with the test cycle.

  In the test apparatus, it may be determined whether or not the status signal from the DUT satisfies a predetermined condition, and conditional branch processing according to the determination result may be executed. This conditional branch determination process is also referred to as a match detection process or simply a match process. For example, a DUT incorporating a PLL (Phase Locked Loop) circuit or a DLL (Delay Locked Loop) circuit outputs a LOCK signal indicating whether or not a transition to a certain appropriate state is made after the power is turned on. The test apparatus monitors this LOCK signal, detects that the PLL circuit or DLL circuit has transitioned from the unlocked state to the locked state, and executes the subsequent test sequence. The conditional branching process in this case is performed for the LOCK signal.

  As another example, consider a NAND flash memory (hereinafter simply referred to as a flash memory). When a flash memory is instructed to write or read data from the outside, it is necessary to prohibit external access while the processing is being executed. Therefore, the flash memory is in a state indicating whether the data writing / reading process is being executed (busy state) or a state where the next process may be started (ready state) after the process is completed. A signal (hereinafter simply referred to as status signal R / B) is output. For example, in the status signal R / B, a high level indicates a ready state, and a low level indicates a busy state. A memory tester that evaluates such a flash memory monitors the R / B signal and executes conditional branch processing.

In order to execute the conditional branch process, a function called match detection is implemented in the test apparatus. The outline of the match detection process is as follows. What is match detection processing?
1. The status signal defined as the detection target is
2. In a predefined test cycle,
3. Determine whether it matches the expected value,
4). It can be defined as a process of branching (jumping) to a predetermined test sequence when they match.

  A test pin (status signal) that is a target of match detection is described by a mnemonic called “MACTH” in the test program. A test cycle for performing match detection is described by a mnemonic called a flag sense instruction such as “FLAG”. An expected value is also defined in the test program, and a test pattern address indicating a predetermined test sequence is also defined in the test program.

JP 2000-40389 JP 2005-44499 A

For example, consider a case where a memory tester detects success (Erase Completed state) and failure (Erase Error state) of a flash memory erase operation. The test apparatus reads the two status signals IO_0 and IO_6 after executing data erasure (Erase) of the DUT. Match detection is performed based on the read first status signal IO_0 and second status signal IO_6. In particular,
(Condition 1) IO_0 = 1 and IO_6 = 1
(Condition 2) IO_0 = 1 and IO_6 = 0
Is determined. Condition 1 is a determination condition for the Erase Error state, and Condition 2 is a determination condition for the Erase Complete state.

  Conventionally, conditions 1 and 2 cannot be determined at the same time, and it is necessary to determine conditions 1 and 2 separately for each cycle. That is, condition 1 is determined in a certain cycle, and if the result is true, the process branches to a sequence corresponding to the Erase_Error state. If the determination result is false, condition 2 is determined in another cycle, and if the result is true, it is necessary to branch to a sequence corresponding to the Erase_Complete state.

  If a plurality of states can be detected at the same time, the test cycle can be shortened and the test time can be reduced.

  The present invention has been made in view of such circumstances, and one of the exemplary purposes of an embodiment thereof is to provide a test apparatus capable of simultaneously detecting a plurality of states.

One embodiment of the present invention relates to a test apparatus that receives a signal from a device under test and executes conditional branch processing according to a combination of the levels of the signal. This test apparatus receives M signals (M is a natural number) from the device under test, and the combination of the levels coincides with any of the predetermined N (N is an integer of 2 or more) states. A match detection circuit for determining whether or not. The match detection circuit includes L (L = M × N) first determination units and N second determination units.
The L first determination units are provided for each combination of M signals and N states. The first determination unit corresponding to the i-th (1 ≦ i ≦ M) signal and the j-th (1 ≦ j ≦ N) state sets the level of the i-th signal to the expected value expected in the j-th state. And a first determination signal that is asserted when they match is generated.
Each of the N second determination units is provided for each of the N states. The second determination unit corresponding to the k-th (1 ≦ k ≦ N) state receives M first determination signals from the M first determination units corresponding to the k-th state, and receives the M first determination signals. When all the 1 determination signals are asserted, a second determination signal that is asserted is generated. The test apparatus executes conditional branch processing according to the N second determination signals.

  In this aspect, the second determination signal output from the kth second determination unit is asserted when a condition regarding the kth state is satisfied. According to this aspect, N second determination signals corresponding to N states can be generated at the same time, and it can be simultaneously determined which of a plurality of states matches.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  According to an aspect of the present invention, a plurality of states can be detected simultaneously.

It is a block diagram which shows the structure of the test apparatus which concerns on embodiment. It is a figure which shows the relationship between a status signal and each state. It is a figure which shows the relationship between status data and a match code. It is a figure which shows operation | movement of the pattern sequence branch part in a 1st mode and a 2nd mode. It is a flowchart which shows the operation | movement in the 1st mode of the test apparatus of FIG. 3 is a flowchart showing an operation in a second mode of the test apparatus of FIG. 1.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 1 is a block diagram showing a configuration of a test apparatus 100 according to the embodiment. The test apparatus 100 is a memory tester that tests the DUT 102 such as a flash memory.
The test apparatus 100 receives some signals (hereinafter referred to as status signals) from the DUT 102, and executes conditional branch processing according to the combination of the levels of the status signals. The conditional branch processing is as described in relation to the prior art.

  The test apparatus 100 includes a plurality of I / O pins Pio, a timing comparator TCP provided for each of the plurality of I / O pins Pio, and a match detection circuit 10. In FIG. 1, only two I / O pins and corresponding elements are shown, and the others are omitted.

A status signal from the DUT 102 is input to each I / O pin Pio.
The timing comparator TCP is provided for each I / O pin Pio, and the level (high level H / low) of the status signal input to the corresponding I / O pin at the timing (edge timing) specified by the strobe signal STRB. Level L) is determined. For example, the timing comparator TCP includes a level comparator LCP and a flip-flop FF.

The level comparator LCP compares the input status signal with a predetermined threshold voltage, and generates a level signal SH / SL indicating the comparison result. For example, in a general memory tester, the level comparator LCP compares the status signal IO_x with the upper threshold voltage VOH, and generates a level signal SH that is asserted (high level) when IO_x <VOH. The level comparator LCP compares the status signal IO_x with the lower threshold voltage VOL, and generates a level signal SL that is asserted (high level) when IO_x> VOL. That is, the memory tester determines the following three states according to the 2-bit SH / SL signal.
SH = L (0), SL = H (1)... Status state is H (1) SH = H (1), SL = L (0)... Status signal is L (0) SH = H ( 1), SL = H (1)... Status signal is in a high impedance (Hi-Z) state

  Alternatively, VOH and VOL may be the same voltage, and a 1-bit level signal SH / SL that is a first level when IO_x <VOH and a second level when IO_x> VOL may be generated. In this case, it is possible to determine whether the status signal is H or L.

  In the present embodiment, the format of the level signal SH / SL is not limited to these. “Form” means the number of bits, high level / low level allocation, and the like. In the following description, signals indicating at least whether the status signal is a high level or a low level are collectively referred to as a level signal SH / SL. It will be understood by those skilled in the art that the circuit configuration subsequent to the level comparator LCP should be designed according to the format of the level signal SH / SL.

The flip-flop FF latches the level signal SH / SL from the corresponding level comparator LCP at the edge timing of the strobe signal STRB. The strobe signal STRB is a signal generated in a block (not shown) of the test apparatus 100 and is synchronized with the test sequence cycle of the test apparatus 100. The i-th timing comparator TCP _i outputs the level signal SH / SL latched by the flip-flop FF as the level signal S _i .

The match detection circuit 10 receives M (M is a natural number) level signals S _{1 to} S _M from M timing comparators TCP, and the combination of these levels is N (N is 2 or more). It is determined which of the two states matches. The match detection circuit 10 is configured to be switchable between a first mode (multiple match mode) and a second mode (normal match mode).

In the present embodiment, M = 2 and N = 3 will be described as an example. Specifically, the M status signals include a status signal IO_0 and a status signal IO_6. The N states correspond to three modes of EraseComplete, EraseError, and Retry (NotReady). FIG. 2 is a diagram illustrating a relationship between a status signal and a state (Mode).
First state φ ₁ EraseComplete
Second state φ ₂ EraseError
Third state φ ₃ Retry

In the test apparatus 100, three conditions ₁ to 3 corresponding to the first state φ ₁ to the third state φ ₃ are set. That is, when the first condition is true, a first state phi _1.
(Condition 1) IO_6 = 1 and IO_0 = 1
(Condition 2) IO_6 = 1 and IO_0 = 0
(Condition 3) IO — 6 = 0

(First mode)
First, a configuration related to the first mode (multiple match mode) will be described.
In relation to the first mode, the match detection circuit 10 includes L (L = M × N) first determination units 12 and N second determination units 18.

The L first determination units 12 are provided for each combination of M (M = 2) status signals IO_0 and IO_6 and N ( N = 3 ) states φ _{1 to} φ ₃ .
The first determination unit 12 corresponding to the combination of the i-th (1 ≦ i ≦ M) status signal and the j-th (1 ≦ j ≦ N) state is denoted by 12 _{i, j} with a suffix. The first signal is IO_ 6, the second signal is IO_ 0.

The first determination section _{12 i, j} is the i-th level signal _{S i} which indicates the level status signals, and compares the expected value data _{EXP i, j} to be expected in the j-th state phi _j, when matched A first determination signal SJ _{i, j} to be asserted (high level) is generated.

In light of the above conditions 1 to 3, each expected value data EXP _{i, j} is as follows.
EXP _1,1 = 1
EXP _2,1 = 1
EXP _{1, 2} = 1
EXP _2,2 = 0
EXP _1,3 = 0
“1” indicates a high level and “0” indicates a low level. Relative Here the third condition, the second signal IO_ 0 are redundant (Do not care).

The first determination unit 12 can switch between three states: (i) an expected value of 1, (ii) an expected value of 0, and (iii) a non-target for match detection.
(I) In a state where the expected value is 1, the first determination unit 12 _{i, j} compares the input level signal S _i with “1”, and asserts the first determination signal SJ _{i, j} when they match. (High level), negate (Low level) when they do not match.
(Ii) In a state where the expected value is 0, the first determination unit 12 _{i, j} compares the input level signal S _i with “0”, and asserts the first determination signal SJ _{i, j} when they match. (High level), negate (Low level) when they do not match.
(Iii) In the non-target state, the first determination unit 12 _{i, j} outputs the first determination signal SJ _{i, j} that is always asserted (high level) regardless of the value of the input level signal S _i .

Each first determination unit 12 includes a first logic gate 14 and a second logic gate 16.
The first logic gate 14 of the first determination unit 12 _{i, j} compares the level signal S _i with the expected value data EXP _{i, j} . Then, when the level signal S _i matches the expected value data EXP _{i, j} , a high level is output, and when it does not match, a low level is output. The first logic gate 14 can be configured using an X N OR gate.

The second logic gate 16 receives the non-target control signal DC _{i, j} indicating whether or not the first determination unit 12 _{i, j is} to be matched and the output of the first logic gate 14. When the non-target control signal DC _{i, j} is negated (low level), the first determination unit 12 is a target of matching, and the second logic gate 16 uses the output of the first logic gate 14 as it is as the first determination signal SJ. Output as _{i and j} . When the non-target control signal DC is asserted (high level), the first determination unit 12 is not matched, and the second logic gate 16 receives the asserted (high level) first determination signal SJ _{i, j} . Output. The second logic gate 16 can be configured using an OR gate.

An expected value decoder 26 is provided in association with the first determination unit 12. A control signal CNT _{i, j} from the register 28 is input to the expected value decoder 26 _{i, j} . The expected value decoder 26 _{i, j} sets the state of the corresponding first determination unit 12 _{i, j} to one of the following three in accordance with the control signal CNT _{i, j} .
(A) High expectations (expected value 1)
The expected value decoder 26 _{i, j} outputs EXP _{i, j} = 1, and negates (low level) the non-target control signal DC.
(B) Low expectation (expected value 0)
The expected value decoder 26 _{i, j} outputs EXP _{i, j} = 0, and negates the non-target control signal DC (low level).
(C) Non-target state Expected value decoders 26 _{i and j} assert (high level) the non-target control signal DC.

For example, the control signal CNT _{i, j} is 2-bit data, and the value “01” corresponds to 1 expectation, “11” corresponds to 0 expectation, and “00” corresponds to non-object.

The control signal CNT _{i, j} , in other words, the expected value EXP _{i, j} and the non-target control signal DC are fixedly defined in the pin condition setting sentence, not in the pattern program.

Each of the N second determination units 18 ₁ to 18 _N is provided for each of the N states. The second determination unit 18 _k corresponding to the k-th (1 ≦ k ≦ N) state includes M first determination units 12 _{1, k to} 12 _{M, k} to M number of first determination units corresponding to the k-th state. 1 determination signal _{SJ 1,} k _{~SJ M,} subjected to _k. The second determination unit 18 _k is a second determination that is asserted (high level) when all the _M first determination signals SJ _{1, k to} SJ _{M, k} are asserted, and negated (low level) otherwise. A signal CASE _k is generated.

The k-th second determination signal CASE _k is asserted when the condition k is true, that is, when the k-th state φk.

The test apparatus 100 executes conditional branch processing according to _N second determination signals CASE _{1 to} CASE N corresponding to the N states φ _{1 to} φ _N, respectively.

The test apparatus 100 further includes a priority encoder 20. The priority encoder 20 receives N second determination signals CASE _{1 to} CASE _N , that is, N-bit data (hereinafter referred to as state data) CASE [N−1: 0]. The second determination signal CASE ₁ corresponds to the most significant bit (MSB) of the state data CASE, and CASE _N corresponds to the least significant bit (LSB) of the state data CASE.

  The priority encoder 20 performs priority encoding on the N-bit state data CASE [N-1: 0] to generate a match code Match_Code. The match code Match_Code indicates the bit position of “1” at the highest position of the state data CASE [N−1: 0]. FIG. 3 is a diagram illustrating the relationship between the status data and the match code. In the figure, “X” indicates redundancy.

  The above is the configuration of the match detection circuit 10 related to the first mode (multiple match mode).

  The match code Match_Code is input to the pattern sequence branching unit 32 via the selector 30. The pattern sequence branching unit 32 specifies address registers A to D according to the match code Match_Code in the first mode (multiple match mode).

  The configuration after the pattern sequence branching unit 32 is the same as that of the general test apparatus 100. Each address A to D describes a jump destination address, and the program counter (PC) 40 issues an instruction to load the jump destination address (LoadJumpAddress instruction). The address generator 42 generates an address pattern based on the loaded address.

(Second mode)
Next, the configuration of the match detection circuit 10 related to the second mode (normal match mode) will be described. In relation to the second mode, the match detection circuit 10 includes M third determination units 22 and a fourth determination unit 24.

Each of the M third determination units 22 is provided for each of the M status signals (IO_0, IO_6). The third determination unit 22 _i corresponding to the i-th signal compares the level of the i-th signal S _i with the expected value EXP _i set and updated for each cycle, and is asserted when they match. A signal Norm_Match _i is generated.
The third determination unit 22 is configured in the same manner as the first determination unit 12, but the expected value EXP given to the third determination unit 22 is the expected value for the first determination unit 12 in that it is described in the pattern program. Different from EXP. That is, when the determination conditions are different for each cycle, different expected values EXP are given to the third determination unit 22 for each cycle.

The fourth determination unit 24 generates a fourth determination signal Norm_Matched that is asserted when all of the _M third determination signals Norm_Match _{1 to} Norm_Match _M are asserted.

  A selector 30 is provided to switch between the first mode (multiple match mode) and the second mode (normal match mode). The selector 30 receives the fourth determination signal Norm_Matched and the match code Match_Code, selects one according to the control signal Multi_Match, and outputs the selected one to the pattern sequence branching unit 32. Specifically, in the first mode, the control signal Multi_Match is asserted, and the selector 30 selects the match code Match_Code. When the control signal Mult_Match is negated (0) in the second mode, the selector 30 selects the fourth determination signal Norm_Matched.

In this way, the pattern sequence branching unit 32 executes the conditional branching process according to the _M second determination signals CASE _{1 to} CASE _M in the first mode, and outputs the fourth determination signal Norm_Matched in the second mode. A corresponding conditional branch process can be executed.

  FIG. 4 is a diagram illustrating the operation of the pattern sequence branching unit 32 in the first mode and the second mode.

The above is the configuration of the test apparatus 100. Next, the operation will be described.
FIG. 5 is a flowchart showing an operation in the first mode of the test apparatus 100 of FIG. The test apparatus 100 erases the data in the flash memory (DUT 102) (S100). Subsequently, the status signals IO_0 and IO_6 indicating the state of the flash memory are read (S102). Subsequently, the second determination signals CASE _{1 to} CASE _M are generated using the read status signals IO_0 and IO_6 (S104), and then the match code Match_Code is generated (S106). Subsequently, a conditional branch process corresponding to the match code Match_Code is executed (S108).

  According to the first mode, a plurality of branch conditions can be determined simultaneously. That is, the test cycle can be shortened and the test time can be shortened.

Further, since the second determination signals CASE _{1 to} CASE _M are converted into the match code Match_Code using the priority encoder 20, the following advantages are obtained.

That is, in the embodiment, as shown in FIG. 2, the conditions 1 to 3 do not become true at the same time. Therefore, whether the branch process is performed according to the second determination signals CASE _{1 to} CASE _{M or} the branch process is performed using the match code Match_Code, the result is the same. However, depending on the mode to be detected, it may be assumed that a plurality of states occur simultaneously. That is, a situation may occur in which some of the plurality of conditions are true at the same time and some of the second determination signals CASE _{1 to} CASE _M are asserted (“1”) at the same time. In this case, by generating the match code Match_Code by the priority encoder 20, the plurality of second determination signals CASE ₁ to CASE _M can be prioritized in order and conditional branching can be performed. In other words, the user may assign the first condition φ ₁ , the second condition φ ₂ ... In order from the highest priority. That is, the user only has to describe the pin condition setting sentence in consideration of the priority order, and there is no need to describe a branch process according to the priority order in the test program. Thereby, high usability can be provided to the user of the test apparatus 100.

  In addition, for each first determination unit 12, it is possible to switch between a match detection target and a non-target. That is, whether or not each status signal is included in the condition of each state can be set independently, and a match condition can be freely set using any combination of status signals.

FIG. 6 is a flowchart showing an operation in the second mode of the test apparatus 100 of FIG. Processes S200 to S202 are the same as processes S100 to S102 in the first mode. Subsequent to the process S202, the condition 2 is determined (S204). Specifically, the third determination unit 22 ₁ sets the expected value EXP ₁ for the status signal IO_0 to “0”, and the third determination unit 22 ₂ sets the expected value EXP ₂ for the status signal IO_6 to “1”. Is done. If the resulting fourth determination signal Norm_Matched is “1” (Y in S204), it is determined to be in the Erase Completed state, and the process branches to a predetermined sequence (S206).

If the fourth determination signal Norm_Matched is “0” (N in S204), the condition 1 is determined (S208). Specifically, the third determination unit 22 ₁ sets the expected value EXP ₁ for the status signal IO_0 to “1”, and the third determination unit 22 ₂ sets the expected value EXP ₂ for the status signal IO_6 to “1”. Is set. If the resulting fourth determination signal Norm_Matched is “1” (Y in S208), it is determined that an Erase Error state has occurred and branches to a predetermined sequence (S210). If the fourth determination signal Norm_Matched is “0” (N in S208), it is determined as the Retry state.

  It should be understood by those skilled in the art that the determination order of the conditions 1 and 2 can be arbitrarily changed in the flowchart of FIG. Processing for determining condition 3 may be performed.

According to the test apparatus 100 of FIG. 1, by providing the third determination unit 22 and the fourth determination unit 24, different conditions can be switched for each cycle.
In addition, it is possible to switch the match detection target and non-target for each third determination unit 22. In other words, even in the second mode, the user can freely set a match condition using any of a plurality of status signals.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  For example, in the embodiment, the case where the third determination unit 22 is provided separately from the first determination unit 12 has been described, but the present invention is not limited to this. For example, the third determination unit 22 may be omitted, and the first determination unit 12 may be used as the third determination unit 22 in the second mode. In this case, the expected value EXP and the non-target control signal DC given to the first determination unit 12 may be switched in the first mode and the second mode. According to this modification, the circuit area can be reduced.

  In the embodiment, the case has been described in which the expected value EXP and the non-target control signal DC for the first determination unit 12 are described in the pin condition setting sentence instead of in the pattern program. It may be configured.

  In the embodiments, the logic system in which “assert” is assigned to a high level and “negate” is assigned to a low level has been described as an example. However, those skilled in the art can understand that they may be inverted. In this case, an inverter or a logic gate having an inverting input may be used as appropriate.

  Although the case where the test apparatus 100 is a tester for flash memory has been described in the embodiment, the present invention is not limited to this. The test apparatus 100 may be a tester for testing other memories, or a tester for testing SOC or the like. Further, the state to be determined by the match detection process can be arbitrarily set without being limited to those described above, and these are also included in the scope of the present invention.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

DESCRIPTION OF SYMBOLS 10 ... Match detection circuit, 12 ... 1st determination part, TCP ... Timing comparator, LCP ... Level comparator, FF ... Flip-flop, 14 ... 1st logic gate, 16 ... 2nd logic gate, 18 ... 2nd determination part, 20 Priority encoder, 22 ... Third determination unit, 24 ... Fourth determination unit, 26 ... Expected value decoder, 28 ... Register, 30 ... Selector, 32 ... Pattern sequence branching unit, 40 ... PC, 42 ... Address generator, 100 ... Test equipment, 102 ... DUT.

Claims (4)

A match that receives M signals (M is a natural number) from the device under test and determines which of the predetermined combinations of levels (N is an integer of 2 or more). With a detection circuit,
The match detection circuit includes:
Each is L (L = M × N) first determination units provided for each combination of the M signals and the N states, and the i-th (1 ≦ i ≦ M) signal and The first determination unit corresponding to the j-th (1 ≦ j ≦ N) state compares the level of the i-th signal with the expected value expected in the j-th state, and is asserted when they match. L first determination units that generate determination signals;
Each of the N second determination units provided for each of the N states, and the second determination unit corresponding to the kth (1 ≦ k ≦ N) state corresponds to the kth state. M number of the first determination signals are received from the M number of first determination units, and when all the M number of the first determination signals are asserted, N number of second determination signals that are asserted are generated. A second determination unit;
A priority encoder that priority-encodes N-bit state data having each of the N second determination signals as a bit, and generates a match code indicating the position of the most asserted bit in the N-bit state data; ,
Including
The test apparatus performs processing according to the match code . The match detection circuit includes:
Each of the M third determination units is provided for each of the M signals, and the third determination unit corresponding to the i-th signal sets the level of the i-th signal for each cycle. An M number of third determination units that generate a third determination signal that is asserted when they match,
A fourth determination unit that generates a fourth determination signal to be asserted when all of the M third determination signals are asserted;
Further comprising
The test apparatus is configured to be able to switch between a first mode and a second mode, and in the first mode, executes a conditional branch process according to the N second determination signals, and in the second mode, the second mode 4. The test apparatus according to claim 1, wherein conditional branch processing is executed in accordance with the four determination signals.   2. The L first determination units are configured to be individually settable to output a first determination signal that is asserted regardless of the value of an input signal. The test apparatus described in 1. A condition for receiving M (M is a natural number) signals from the device under test and determining which of the N combinations (N is an integer of 2 or more) of the combinations of levels. A branch determination method,
For each combination of the M signals and the N states, the level of the i-th signal is compared with the expected value expected in the j-th state, and a first determination signal that is asserted when they match is generated. And steps to
generating a second determination signal that is asserted when all of the M first determination signals corresponding to the kth (1 ≦ k ≦ N) state are asserted;
Priority encoding N-bit state data with each of the N second determination signals as a bit, and generating a match code indicating the position of the most asserted bit of the N-bit state data;
Executing a process according to the match code;
A conditional branch determination method comprising:

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