JP5282124B2 - Packet transfer apparatus and packet transfer method - Google Patents

Description

  The present invention relates to a packet transfer apparatus and a packet transfer method for transferring a received packet to another apparatus.

  2. Description of the Related Art Conventionally, a multiport switch and a plurality of devices connected to the multiport switch via a plurality of serial buses are provided, and the transmission source device selects at least one transmission destination device from the plurality of devices. A transmission unit that transmits data to the selected transmission destination device through the multiport switch and the serial bus, and a transmission unit that receives data from the transmission source device through the multiport switch and the serial bus. A data transmission system is known (see, for example, Patent Document 1).

  In this conventional data transmission system, when the transmission unit selects a plurality of destination devices, transmission is performed to the selected plurality of destination devices based on the reception rates of the selected plurality of destination devices. By determining the ratio of the amount of data to be transmitted, data is efficiently transmitted to a plurality of selected transmission destination devices.

International Publication No. 2010/122896 Pamphlet

  However, the conventional technology as described above has a problem in that an interface standard of a packet formed by data to be transmitted must be determined in advance between a transmission source device and a transmission destination device.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a packet transfer apparatus and a packet transfer method capable of transferring a packet regardless of the packet interface standard.

  The packet transfer device of the present invention is a packet transfer device for transferring a received packet to another device (3a to 3c), and a write address of the fragment to the storage medium (21) of the other device and the fragment of the received packet. A packet converter (11) that converts the received packet into a plurality of transfer packets including a packet transfer unit (12) that transfers the transfer packet to the other device. The unit specifies the write address in the transfer packet so as to reserve a reserved area for writing the length of the received packet immediately before the area in which the fragment is written to the storage medium, and the transfer packet On the condition that the transfer of the received packet has been completed, the transfer packet includes data indicating the length of the received packet and the start address of the reserved area. It generates Tsu bets, the packet transfer unit is configured to forward the transfer packet generated by the packet conversion unit to the other apparatus.

  With this configuration, since the transfer destination device can reproduce the received packet by reading out the data for the length written in the reserved area from the storage medium, the packet transfer device of the present invention has a packet interface. Packets can be transferred regardless of the standard.

  The packet conversion unit may convert the format of the received packet into a transfer packet in which the write address is stored at a specific position in the payload.

  In addition, the packet conversion unit may convert the format of the received packet into a transfer packet that conforms to the Serial RapidIO (registered trademark) standard.

  The packet conversion unit may convert the format of the received packet into a transfer packet in which the write address is added to a header.

  The packet transfer method of the present invention is the packet transfer method using the packet transfer device (1a to 1c) for transferring the received packet to the other device (3a to 3c). A packet conversion step for converting the format of the received packet into a plurality of transfer packets including a write address of the fragment for the storage medium (21) of the device; a packet transfer step for transferring the transfer packet to the storage medium; And the packet converting step assigns the write address to the transfer packet so as to reserve a reserved area for writing the length of the received packet immediately before the area for writing the fragment to the storage medium. On the condition that the address designation step to be designated and the transfer of the transfer packet have been completed, A packet generation step of generating a transfer packet including data representing the length of the packet and a start address of the reserved area, wherein the packet transfer step includes the transfer packet generated in the packet generation step The step of transferring is included.

  Therefore, since the transfer destination device can reproduce the received packet by reading the length of data written in the reserved area from the storage medium, the packet transfer method of the present invention complies with the packet interface standard. The packet can be transferred independently.

  The present invention can provide a packet transfer apparatus and a packet transfer method capable of transferring a packet without depending on the packet interface standard.

It is a block diagram of the system comprised by the packet transfer apparatus which concerns on embodiment of this invention. It is a conceptual diagram for demonstrating the transfer operation | movement of the packet transfer apparatus which concerns on embodiment of this invention. It is a conceptual diagram which shows the memory map of the buffer of the packet receiver which is a packet transfer destination of the packet transfer apparatus which concerns on embodiment of this invention. It is a conceptual diagram for demonstrating the other example of the transfer operation | movement of the packet transfer apparatus which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  As shown in FIG. 1, the system according to the embodiment of the present invention includes a plurality of packet transfer apparatuses 1a to 1c, a switch 2, and a plurality of packet reception apparatuses 3a to 3c, and includes a plurality of packet transfer apparatuses 1a. The packets received by ˜1c are transmitted to any of the plurality of packet receiving devices 3a-3c.

  In FIG. 1, three packet transfer apparatuses 1a to 1c and packet reception apparatuses 3a to 3c are shown, respectively, but the number is not limited. In the following description, the packet transfer apparatuses 1a to 1c are collectively referred to as “packet transfer apparatus 1”, and the packet reception apparatuses 3a to 3c are collectively referred to as “packet reception apparatus 3”.

  The packet transfer apparatus 1 includes a packet reception unit 10 that receives a packet, a packet conversion unit 11 that converts a received packet into a plurality of transfer packets, and a packet transfer unit 12 that transfers a transfer packet to the packet reception apparatus 3. It has.

  In the present embodiment, the packet reception unit 10, the packet conversion unit 11, and the packet transfer unit 12 are integrally configured by a combination of hardware elements such as a logic circuit or an FPGA (Field Programmable Gate Array).

  The packet receiving device 3 includes a packet receiving unit 20 that receives a transfer packet transmitted from the packet transfer device 1 via the switch 2, a buffer 21 that buffers the transfer packet, and further transfers the transfer packet to another device. A packet transmission unit 22 for transmission.

  In the present embodiment, the packet receiving unit 20 and the packet transmitting unit 22 are integrally configured by a combination of hardware elements such as a logic circuit, or an FPGA. The buffer 21 is configured by a storage medium such as a RAM (Random Access Memory).

  IDs are assigned to the packet transfer apparatus 1 and the packet reception apparatus 3 in advance. The switch 2 transmits the transfer packet transferred from the packet transfer device 1 to any one of the packet reception devices 3 based on the ID included in the header of the transfer packet.

  The packet receiving unit 10 of the packet transfer apparatus 1 can receive a packet conforming to an arbitrary standard. The packet converting unit 11 fragments the received packet, and converts the format of the received packet into a plurality of transfer packets including each fragment and a write address of the fragment to the buffer 21 of the packet receiving device 3.

  Here, the transfer packet conforms to a standard in which a write address can be included in the header, and in this embodiment, conforms to the Serial RapidIO (hereinafter simply referred to as “sRIO”) standard. That is, the packet transfer unit 12 transfers the transfer packet to the packet receiving device 3 in accordance with the sRIO standard.

  sRIO performs high-speed communication such as 1.25 Gbps, 2.5 Gbps, and 3.125 Gbps between devices provided on a board such as a CPU (Central Processing Unit), DSP (Digital Signal Processing), and FPGA (Field Programmable Gate Array). It is a standard for the bus to be realized, and is also adopted as a transfer standard between backplanes and cases.

  The logical layer of sRIO can realize DMA (Direct Memory Address) for writing data to the memory, and at least the transfer source device ID (Source-ID) and the transfer destination device ID are included in the header. (Destination-ID) and the memory address of the transfer destination device can be specified.

  In the present embodiment, the ID of the packet transfer device 1 is specified as the ID of the transfer source device, the ID of the packet reception device 3 is specified as the ID of the transfer destination device, and the memory address of the transfer destination device is set. The address in the buffer 21 of the packet receiving device 3 is designated.

  Further, the packet conversion unit 11 sets a write address in the header of the transfer packet so as to secure a reserved area for writing the length of the received packet immediately before the area in which the fragment of the received packet is written in the buffer 21. It is designed to specify. In the present embodiment, the length of the reserved area is 4 bytes.

  That is, assuming that the buffer 21 is empty, the packet converting unit 11 secures 4 bytes from the head as a reserved area, and transfers the packet of the transfer packet so that the received packet fragments are sequentially written from the 5th byte. The write address is specified in the header.

  Assuming that data has been written to the buffer 21, the packet conversion unit 11 secures 4 bytes following the written data as a reserved area, and the received packet fragments are sequentially written thereafter. The write address is specified in the header of the transfer packet.

  The packet transfer unit 12 transfers the transfer packet that has been converted in format by the packet conversion unit 11 to the packet receiving device 3 via the switch 2.

  In addition, the packet conversion unit 11 performs transfer including data indicating the length of the received packet and the start address of the reserved area in the header on the condition that transfer of the transfer packet including all fragments of the received packet has been completed. Packet is generated. The packet transfer unit 12 transfers the transfer packet generated by the packet conversion unit 11 in this way to the packet receiving device 3.

  In the present embodiment, the packet receiving unit 20 of the packet receiving device 3 receives a transfer packet transferred from the packet transfer device 1 via the switch 2 in accordance with the sRIO standard.

  The buffer 21 has a storage area divided into a number of logical or physical segments 31a to 31c corresponding to the packet transfer apparatuses 1a to 1c. Hereinafter, the segments 31a to 31c are collectively referred to as “segment 31”.

  The packet receiving unit 20 of each packet receiving device 3 writes the payload of the transfer packet to the segment 31a at the position indicated by the write address included in the header of the transfer packet transferred from the packet transfer device 1a. It has become.

  Further, the packet receiving unit 20 of each packet receiving device 3 writes the payload of the transfer packet to the segment 31b at the position indicated by the write address included in the header of the transfer packet transferred from the packet transfer device 1b. It is like that.

  Similarly, the packet receiving unit 20 of each packet receiving device 3 places the payload of the transfer packet at the position indicated by the write address included in the header of the transfer packet transferred from the packet transfer device 1c with respect to the segment 31c. It comes to write.

  The packet transmission unit 22 is configured to transmit data written in the segments 31a to 31c to other devices in units of packets, for example, in a round robin method. Here, the data written in the segments 31a to 31c first represents the length of the received packet, and subsequently represents the received packet.

  For this reason, the packet transmission unit 22 reads out 4-byte data from the segment 31, and reads out data corresponding to the length of the received packet represented by the 4-byte data, that is, the received packet.

  A transfer operation of the packet transfer apparatus 1 configured as described above will be described with reference to FIG. Here, it is assumed that the received packet constitutes an Ethernet (registered trademark) frame 50.

  In FIG. 2, “H” represents the header of the Ethernet (registered trademark) frame 50, “D” represents the payload of the Ethernet (registered trademark) frame 50, and “F” represents Ethernet (registered trademark). A footer of the frame 50 is represented.

  The Ethernet (registered trademark) frame 50 received by the packet receiver 10 of the packet transfer apparatus 1 is fragmented by the packet converter 11 and transferred packets 51a to 51d to which the header Hs and footer Fs of the sRIO packet are added, respectively. And is transferred by the packet transfer unit 12.

  Here, in each header Hs of the sRIO packet, the packet conversion unit 11 specifies the ID of the packet transfer device 1 as the ID of the transfer source device, and the ID of the packet reception device 3 as the ID of the transfer destination device. The address in the segment 31 of the packet receiving device 3 is designated as the memory address of the transfer destination device.

  When transfer of the transfer packet including all fragments of the received packet is completed, the header Hs and footer Fs of the sRIO packet are added to the data L indicating the length of the received packet obtained by byte counting by the packet receiving unit 10 or the like. The transfer packet 52 is generated by the packet conversion unit 11 and transferred by the packet transfer unit 12.

  As described above, the data stored in the segment 31 based on the transfer packet transferred by the packet transfer apparatus 1 is as shown in FIG. In FIG. 3, “H” represents the header of the Ethernet (registered trademark) frame, “D” represents the payload of the Ethernet (registered trademark) frame, and “F” represents the Ethernet (registered trademark) frame. Represents the footer.

  As the data storage position, first, data L representing the length of the received packet is stored from the beginning of the segment 31, and then the header H, payload D, and footer F of the Ethernet (registered trademark) frame are stored. . Subsequently, data Ln representing the length of the next received packet is stored, and thereafter stored in the same manner. Therefore, by using the segment 31 as a ring buffer, the packet transmission unit 22 can sequentially read the length of the received packet and the received packets (H, D, D, D, F).

  As shown in FIG. 2, after the header H, payload D, and footer F of the Ethernet (registered trademark) frame are stored, the data L representing the length of the received packet is stored as the data storage order. The For subsequent received packets, data is stored in the same order.

  Hereinafter, storage of data in the segment 31 will be described in more detail. The write positions of each segment 31a to 31c are managed based on the value of the write pointer. The packet transfer unit 12 of each of the packet transfer apparatuses 1a to 1c manages the value of the write pointer of the corresponding segment 31a to 31c, and based on the value of the write pointer, the payload of the transfer packet, that is, the received packet Determine the write address.

  For example, as shown in FIG. 3, it is assumed that the segment 31 has been written to the address immediately before the address A0. At this time, the value of the write pointer is an address A0 that can be written next.

  Here, when trying to transfer the received packet, the packet transfer unit 12 secures the above-described reserved area (for example, 4 bytes) for the address A0 based on the value of the write pointer, and sets the address A1. The address is determined as a write address, the determined address A1 is designated, and the first transfer packet for transferring the received packet is transmitted.

  Then, the packet transfer unit 12 determines the write address (A2, A3, A4) by shifting the address by the transferred data length of the received packet, and determines the determined address (A2, A3, A4). Is specified, and subsequent transfer packets are transmitted.

  When transfer of the received packet is completed, the packet transfer unit 12 determines the address A0 of the reserved area as the write address, specifies the determined address A0, and transmits the transfer packet storing the data L indicating the length of the received packet To do.

  Thereafter, the packet transfer unit 12 updates the value of the write pointer so as to indicate the address A5 where the next write of the segment 31 is possible, and completes the transfer process for this received packet. Thereafter, each time the received packet is transferred, the packet transfer unit 12 repeatedly executes the transfer operation described above while updating the value of the write pointer.

  On the other hand, the read position of each segment 31a to 31c is managed based on the value of the read pointer. The packet transmission unit 22 of each of the packet reception devices 3a to 3c manages the read pointer value of the corresponding segment 31a to 31c, and determines the read address of the received packet based on the read pointer value.

  For example, as shown in FIG. 3, it is assumed that reading is performed from the segment 31 up to the address immediately before the address A0. At this time, the value of the read pointer is an address A0 that can be read next.

  Here, the packet transmission unit 22 sets the value of the read pointer to the value of the read pointer on the condition that the write pointer value indicates the address A0, the writing of data to the address A0 is completed, and the write pointer value indicates another address. The base address A0 is determined as a read address, the determined address A0 is specified, and data L representing the length of the received packet is read from the reserved area.

  Next, the packet transmission unit 22 determines the address A1 shifted from the address A0 by the reserved area as a read address, specifies the determined address A1, and the data for the length represented by the data L from the address A1, that is, Read the received packet.

  Thereafter, the packet transmitter 22 updates the value of the read pointer so as to indicate the address A5 shifted from the address A1 by the length indicated by the data L, and completes the read operation for the received packet. Thereafter, each time the received packet transferred by the packet transfer unit 12 and stored in the segment 31 is read, the packet transmission unit 22 repeatedly executes the read operation described above while updating the value of the read pointer.

  As described above, since the packet receiving device 3 can reproduce the received packet by reading the data corresponding to the length written in the reserved area from the buffer 21, the packet transfer device according to the present embodiment. 1 can transfer a packet regardless of the interface standard of the packet.

  In this embodiment, the transfer packet has been described as conforming to the sRIO standard. However, in the present invention, in the present invention, the transfer packet conforms to a standard in which a write address can be included in the header. It only has to be.

  Also, as shown in FIG. 4, the packet converter 11 may store the write address at a specific position in the payload and convert the format of the received packet into a transfer packet compliant with another transfer standard. In this case, the packet receiver 20 is configured to have a DMA function.

  4, “H” represents the header of the Ethernet® frame 50, “D” represents the payload of the Ethernet® frame 50, and “F” represents the Ethernet®. ) Represents the footer of the frame 50.

  Specifically, the Ethernet (registered trademark) frame 50 received by the packet receiving unit 10 of the packet transfer apparatus 1 is fragmented by the packet converting unit 11, and each of the header Hi, the write address Ui, and the footer Fi of the transfer packet. Are transferred to the transfer packets 61 a to 61 d with “” and transferred by the packet transfer unit 12.

  Here, the packet conversion unit 11 specifies the ID of the packet transfer device 1 as the ID of the transfer source device and the ID of the packet reception device 3 as the ID of the transfer destination device in the header Hs of the transfer packet. In the write address Ui, an address in the segment 31 of the packet receiving device 3 is designated as a memory address of the transfer destination device.

  When the transfer of the transfer packet including all fragments of the received packet is completed, the transfer packet header Hi, the write address Ui, and the data L representing the length of the received packet obtained by byte counting by the packet receiving unit 10 and the like. A transfer packet 62 with a transfer packet footer Fi is generated by the packet conversion unit 11 and transferred by the packet transfer unit 12.

  The packet transfer apparatus according to the present invention can be applied to, for example, an internal data transfer function of a test apparatus of a mobile terminal, in addition to being applied to a packet transfer apparatus arranged between devices provided on a board.

DESCRIPTION OF SYMBOLS 1, 1a-1c Packet transfer apparatus 2 Switch 3, 3a-3c Packet reception apparatus 10, 20 Packet reception part 11 Packet conversion part 12 Packet transfer part 21 Buffer 22 Packet transmission part 31, 31a-31c Segment

Claims (5)

In a packet transfer device that transfers received packets to other devices (3a to 3c),
A packet converter (11) for converting the format of the received packet into a plurality of transfer packets including the fragment of the received packet and the write address of the fragment for the storage medium (21) of the other device;
A packet transfer unit (12) for transferring the transfer packet to the other device;
The packet conversion unit designates the write address in the transfer packet so as to secure a reserved area for writing the length of the received packet immediately before the area in which the fragment is written to the storage medium, On the condition that transfer of the transfer packet is completed, a transfer packet including data indicating the length of the received packet and the start address of the reserved area is generated,
The packet transfer unit, wherein the packet transfer unit transfers the transfer packet generated by the packet conversion unit to the other device.   The packet transfer apparatus according to claim 1, wherein the packet conversion unit converts the format of the received packet into a transfer packet in which the write address is stored at a specific position of a payload.   3. The packet transfer apparatus according to claim 2, wherein the packet conversion unit converts the format of the received packet into a transfer packet compliant with the Serial RapidIO standard.   The packet transfer apparatus according to claim 1, wherein the packet conversion unit converts the format of the received packet into a transfer packet in which the write address is added to a header. In a packet transfer method using a packet transfer device (1a to 1c) for transferring a received packet to another device (3a to 3c),
A packet conversion step for converting the format of the received packet into a plurality of transfer packets including the fragment of the received packet and the write address of the fragment for the storage medium (21) of the other device;
A packet transfer step of transferring the transfer packet to the storage medium,
The packet conversion step includes:
An address designating step for designating the write address in the transfer packet so as to reserve a reserved area for writing the length of the received packet immediately before the area in which the fragment is written to the storage medium;
A packet generation step of generating a transfer packet including data indicating the length of the received packet and the start address of the reserved area on the condition that the transfer of the transfer packet is completed,
The packet transfer step includes:
A packet transfer method comprising the step of transferring the transfer packet generated in the packet generation step.

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