CN114385241A

CN114385241A - Method for completing programmable atomic transaction

Info

Publication number: CN114385241A
Application number: CN202111224820.5A
Authority: CN
Inventors: T·M·布鲁尔
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2020-10-20
Filing date: 2021-10-20
Publication date: 2022-04-22
Also published as: US20220121474A1; US11693690B2

Abstract

The present application relates to a method of completing a programmable atomic transaction. Disclosed in some examples are methods, systems, computing devices, and machine-readable media that define instructions of a programmable atomic transaction that are executed as a last instruction and terminate a thread of execution, wait for all outstanding store operations to complete, clear a programmable atomic lock, and send a completion response back to an issuing process. This ensures that the programmable atomic lock is cleared when the transaction completes. By coupling thread termination with clearing the lock bit, this ensures that the thread cannot terminate without clearing the lock.

Description

Method for completing programmable atomic transaction

Statement regarding government support

The invention was made with U.S. government support under agreement No. HR00111890003 awarded by DARPA. The united states government has certain rights in this invention.

Technical Field

This application relates generally to chiplets. In particular, the present application relates to a method of completing a programmable atomic transaction.

Background

Chiplets are an emerging technology for integrating various processing functionalities. Typically, a chiplet system is made up of precision modules (each referred to as a "chiplet") integrated on an interposer and interconnected, in many instances as needed, through one or more established networks to provide the desired functionality to the system. The interposer and the included chiplets can be packaged together to facilitate interconnection with other components of a larger system. Each chiplet can include one or more individual integrated circuits or "chips" (ICs), possibly in combination with discrete circuit components, and commonly coupled to a respective substrate for attachment to an interposer. Most or all of the chiplets in the system will be individually configured for communication over one or more established networks.

The configuration of chiplets as individual modules of a system is different from such systems implemented on a single chip containing different device blocks (e.g., Intellectual Property (IP) blocks) on one substrate (e.g., a single die), such as a system-on-a-chip (SoC), or multiple discrete packaged devices integrated on a Printed Circuit Board (PCB). Generally, chiplets provide better performance (e.g., lower power consumption, reduced latency, etc.) than discrete packaged devices, and chiplets provide greater production benefits than single-die chips. These production benefits may include higher yields or reduced development costs and time.

A chiplet system can include, for example, one or more application (or processor) chiplets and one or more support chiplets. Here, the distinction between an application chiplet and a support chiplet is merely a reference to a possible design scenario for a chiplet system. Thus, for example, a composite visual chiplet system can include (by way of example only) an application chiplet to generate a composite visual output and a support chiplet such as a memory controller chiplet, a sensor interface chiplet, or a communication chiplet. In a typical use case, a composite visual designer may design an application chiplet and obtain support chiplets from other parties. Thus, design expenditures (e.g., in terms of time or complexity) are reduced by avoiding the functionality involved in designing and producing support chiplets. Chiplets also support tight integration of IP blocks that might otherwise be difficult, such as IP blocks fabricated using different processing techniques or using different feature sizes (or with different contact techniques or pitches). Accordingly, an assembly of multiple ICs or an assembly of ICs having different physical, electrical or communication characteristics may be assembled in a modular fashion to provide an assembly that achieves the desired functionality. The chiplet system can also facilitate adaptation to the needs of different larger systems into which the chiplet system will be incorporated. In an example, an assembly of ICs or other assemblies may be optimized for a specific function of power, speed, or heat generation, as may occur with sensors, which may be more easily integrated with other devices than if attempted on a single die. In addition, by reducing the overall size of the die, the yield of chiplets tends to be higher than that of more complex single-die devices.

Disclosure of Invention

In one aspect, the present application provides an apparatus comprising: a memory array; a memory controller coupled to the memory array, the memory controller comprising an internal memory storing a lock structure for controlling access to one or more memory locations of the memory array; a programmable atomic cell coupled to a memory controller and comprising: an instruction memory configured to store one or more instruction sets; and a processor configured to: receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in an instruction memory; setting a lock for a portion of a memory array in a lock structure of an internal memory of a memory controller, the lock preventing subsequent access to the portion of the memory array; executing the instruction set; and executing an instruction to terminate execution of the instruction set, the instruction to terminate execution of the instruction set including an operation to clear the lock.

In another aspect, the present application provides a method comprising: at a programmable atomic unit coupled to a memory controller and including a processor: receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions being stored in a memory of a programmable atomic unit; setting a lock in a lock structure of an internal memory of a memory controller coupled to a programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of the memory coupled to the memory controller; executing the instruction set; and executing an instruction to terminate execution of the instruction set, the instruction to terminate execution of the instruction set including an operation to clear the lock.

In another aspect, the present application provides a non-transitory machine-readable medium storing instructions that, when executed by a machine, cause the machine to perform operations comprising: receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions being stored in a memory of a programmable atomic unit; setting a lock in a lock structure of a memory controller coupled to a programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; executing the instruction set; and executing an instruction to terminate execution of the instruction set, the instruction to terminate execution of the instruction set including an operation to clear the lock.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIGS. 1A and 1B illustrate examples of chiplet systems according to some examples of the present disclosure.

FIG. 2 illustrates components of an example of a memory controller chiplet according to some examples of the present disclosure.

Fig. 3 illustrates components in an example of a Programmable Atomic Unit (PAU), according to some examples of the present disclosure.

Fig. 4 illustrates a request package for requesting execution of a particular programmable atomic transaction, in accordance with some examples of the present disclosure.

Fig. 5 illustrates a programmable atomic transaction response message in accordance with some examples of the disclosure.

Fig. 6 illustrates a flow diagram of a method of executing a programmable atomic termination instruction, according to some examples of the disclosure.

Fig. 7 illustrates an example terminate instruction in accordance with some examples of the present disclosure.

Fig. 8 is a block diagram of a memory controller according to some examples of the present disclosure.

Fig. 9 is a block diagram of an example of a machine with which, in, or by which embodiments of the present disclosure may operate, according to some examples of the present disclosure.

Detailed Description

FIG. 1, described below, provides an example of a chiplet system and components operating therein. As explained below, such a chiplet system can include a memory controller having a programmable atomic unit that executes a programmable atomic transaction including one or more instructions. The programmable atomic unit sets a lock when the programmable atomic transaction begins execution, the lock providing exclusive memory access to one or more memory locations of a memory controlled by a memory controller. For example, if the programmable atomic transaction is an increment operation that increments a value of a specified memory location, the programmable atomic unit sets a lock on the specified memory location that persists until the programmable atomic transaction completes. This lock is set by the programmable atomic unit when the programmable atomic transaction begins execution and must be cleared when the programmable atomic transaction completes. If the lock is not cleared, future programmable atomic transactions that require the particular lock will not be allowed to execute. In some examples, as disclosed herein, a terminate instruction is defined that is executed as the last instruction of a programmable atomic transaction, that terminates the execution thread, waits for all outstanding stores to complete, clears the programmable atomic lock, and sends a completion response back to the issue processor. This ensures that the programmable atomic lock is cleared when the programmable atomic transaction completes.

In some examples, the termination instruction is included in a programmable atomic transaction instruction set as supplied by a creator of the programmable atomic transaction (e.g., supplied by a process on an application chiplet). The programmable atomic unit may check to ensure that the terminating instruction is the last instruction in the instruction set and reject instruction sets that do not meet this condition. In other examples, the terminating instruction is not included in the instruction set and is automatically performed by the processor of the programmable atomic unit after reaching a last instruction of the programmable atomic transaction or after a threshold number of instructions in the instruction set.

FIGS. 1A and 1B illustrate an example of a chiplet system 110 according to an embodiment. FIG. 1A is a representation of a chiplet system 110 mounted on a peripheral board 105 that can be connected to a wider computer system, for example, through peripheral component interconnect express (PCIe). Chiplet system 110 includes a package substrate 115, an interposer 120, and four chiplets, namely an application chiplet 125, a host interface chiplet 135, a memory controller chiplet 140, and a memory device chiplet 150. Other systems may include many additional chiplets to provide additional functionality, as will be apparent from the discussion below. The packaging of the chiplet system 110 is illustrated with a lid or cover plate 165, but other packaging techniques and structures for the chiplet system can be used. FIG. 1B is a block diagram that labels components in a chiplet system for clarity.

The application chiplets 125 are illustrated as including a Network On Chip (NOC)130 to support a network of chiplets 155 for inter-chiplet communication. In an example embodiment, the NOC130 may be included on an application chiplet 125. In an example, the NOC130 can be defined in response to a selected supporting chiplet (e.g., chiplets 135, 140, and 150), thus enabling a designer to select an appropriate number or chiplet network connections or switches for the NOC 130. In an example, the NOC130 may be located on a separate chiplet or even within the interposer 120. In the example as discussed herein, the NOC130 implements a Chiplet Protocol Interface (CPI) network.

CPI is a packet-based network that supports virtual channels to enable flexible and high-speed interaction between chiplets. CPI enables bridging from the chiplet network to the chiplet network 155. For example, the advanced extensible interface (AXI) is a widely used specification for designing on-chip communications. The AXI specification, however, covers a large number of physical design options, such as the number of physical channels, signal timing, power, etc. Within a single chip, these options are typically selected to meet design goals such as power consumption, speed, and the like. However, to achieve flexibility in a chiplet system, an adapter such as a CPI is used to interface between the various AXI design options that can be implemented in the various chiplets. CPI bridges the chiplet network across the chiplet network 155 by enabling mapping of physical channels to virtual channels and encapsulating time-based signaling with a packetization protocol.

CPI may use a variety of different physical layers to transmit packets. The physical layer may include simple conductive connections, or may include drivers to increase voltage, or otherwise facilitate transmission of signals over longer distances. An example of such a physical layer may include an Advanced Interface Bus (AIB), which in various examples may be implemented in the interposer 120. The AIB transmits and receives data using source synchronous data transfer with a forwarding clock. Packets are transferred across the AIB at a Single Data Rate (SDR) or a Double Data Rate (DDR) relative to the transmitted clock. The AIB supports various channel widths. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60, … …), and for DDR mode, the AIB channel width is a multiple of 40 bits: (40, 80, 120, … …). The AIB channel width encompasses both the transmitted and received signals. A channel may be configured with a symmetric number of Transmit (TX) and Receive (RX) input/outputs (I/os), or with an asymmetric number of transmitters and receivers (e.g., all transmitters or all receivers). A channel may act as an AIB master or slave depending on which chiplet provides the master clock. The AIB I/O unit supports three clock modes: asynchronous (i.e., not clocked), SDR, and DDR. In various examples, a non-clocked mode is used for the clock and some control signals. SDR modes may use dedicated SDR-only I/O units, or dual SDR/DDR I/O units.

In an example, a CPI packet protocol (e.g., point-to-point or routable) may use symmetric receive and transmit I/O units within the AIB channel. The CPI stream protocol allows for more flexible use of AIB I/O units. In an example, an AIB channel of a streaming mode may configure an I/O unit to be all TX, all RX, or half TX and half RX. The CPI packet protocol may use AIB channels in either SDR or DDR modes of operation. In an example, the AIB channel is configured in increments of 80I/O units (i.e., 40 TX and 40 RX) for SDR mode and 40I/O units for DDR mode. The CPI streaming protocol may use AIB channels in either SDR or DDR modes of operation. Here, in the example, the AIB channel is incremented by 40I/O units for both SDR and DDR modes. In an example, each AIB channel is assigned a unique interface identifier. The identifier is used during CPI reset and initialization to determine the paired AIB channels across adjacent chiplets. In an example, the interface identifier is a 20-bit value that includes a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit chaining identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32-51 of the shift register are used to transfer the 20-bit interface identifier in both directions across the AIB interface.

The AIB defines a stacked AIB channel set as an AIB channel column. The AIB channel column has a number of AIB channels plus supplemental channels. The auxiliary channel contains signals for AIB initialization. All AIB channels within a column (except for the auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and have the same number of data I/O signals). In the example, the AIB channels are numbered in successively increasing order, starting with AIB channels adjacent to the AUX channel. The AIB channel adjacent to AUX is defined as AIB channel zero.

Typically, the CPI interface on individual chiplets can include serialization-deserialization (SERDES) hardware. SERDES interconnects are well suited for scenarios requiring high speed signaling as well as low signal counts. However, SERDES may cause additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level Cyclic Redundancy Check (CRC)), link-level retries, or forward error correction. However, where low latency or energy consumption is a major concern for ultra-short distance chiplet-to-chiplet interconnects, a parallel interface can be utilized whose clock rate allows data transfer with minimal latency. CPI contains components for minimizing both latency and energy consumption of these ultra-short distance chiplet interconnects.

For flow control, CPI employs a credit-based technique. For example, a receiving party of the application chiplet 125 provides credits representing available buffers to a sending party, such as the memory controller chiplet 140. In an example, the CPI recipient includes a buffer for each virtual channel for a given transmission time unit. Thus, if the CPI recipient supports five messages and a single virtual channel in time, the recipient has five buffers arranged in five rows (e.g., one row per unit time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of one CPI packet.

Upon transmission by the sender to the recipient, the sender decrements the available credit based on the transmission. Once all the credits of the receiver are exhausted, the sender stops sending packets to the receiver. This ensures that the receiver always has a buffer available to store the transmission.

As the receiver processes the received packets and releases the buffer, the receiver communicates the available buffer space back to the sender. The sender may then use this credit return to allow additional information to be transmitted.

Also illustrated is a chiplet mesh network 160 that uses direct chiplet-to-chiplet technology without the need for a NOC 130. The chiplet mesh network 160 can be implemented in a CPI or another chiplet-to-chiplet protocol. Chiplet mesh network 160 typically implements a chiplet pipeline in which one chiplet acts as an interface to the pipeline while other chiplets in the pipeline interface only interface with themselves.

In addition, a dedicated device interface, such as one or more industry standard memory interfaces 145 (e.g., synchronous memory interfaces, such as DDR5, DDR 6), may also be used to interconnect the chiplets. The connection of a chiplet system or individual chiplets to an external device, such as a larger system, can be through a desired interface, such as a PCIE interface. In an example, the external interface can be implemented, for example, by a host interface chiplet 135 that provides a PCIE interface external to the chiplet system 110 in the depicted example. Such interfaces are typically employed when conventions or standards in the industry have converged upon such proprietary interfaces 145. The illustrated example of a Double Data Rate (DDR) interface 145 connecting the memory controller chiplet 140 to a Dynamic Random Access Memory (DRAM) memory device 150 is such an industry practice.

Among the many possible support chiplets, the memory controller chiplet 140 is likely to be present in the chiplet system 110 because of the almost ubiquitous use of storage for computer processing and the use of sophisticated advanced technologies for memory devices. Thus, the use of memory device chiplets 150 and memory controller chiplets 140 produced by other techniques enables chiplet system designers to obtain robust products produced by mature manufacturers. Typically, memory controller chiplet 140 provides a memory device specific interface to read, write, or erase data. Often, memory controller chiplets 140 can provide additional features such as error detection, error correction, maintenance operations, or atomic operation execution. For some types of memory, maintenance operations are often specific to the memory device 150, such as garbage collection in NAND flash or storage class memory, temperature adjustment in NAND flash memory (e.g., cross temperature management). In an example, the maintenance operation may include logical-to-physical (L2P) mapping or management to provide a hierarchy of indirection between physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at some times by a host processor or memory controller, and at other times by a DRAM memory device or logic associated with one or more DRAM devices, such as an interface chip (in an example, a buffer).

An atomic transaction is one or more data manipulation operations that may be performed, for example, by the memory controller chiplet 140. In other chiplet systems, atomic transactions can be performed by other chiplets. For example, an "incremental" atomic transaction may be specified by the application chiplet 125 in a command that includes a memory address and possibly an increment value. Upon receiving the command, the memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 140 provides an indication of command success to the application chiplet 125. Atomic transactions avoid transmitting data across the chiplet mesh network 160, reducing latency for executing such commands.

Atomic transactions may be classified as built-in atomic or programmable (e.g., custom) atomic transactions. Built-in atomic transactions are a limited set of operations that are implemented invariantly in hardware. A programmable atomic transaction is a small program having one or more instructions (e.g., an instruction set) that can be executed on a Programmable Atomic Unit (PAU) (e.g., a Custom Atomic Unit (CAU)) of the memory controller chiplet 140. FIG. 1 illustrates an example of a memory controller chiplet discussing PAUs.

Memory device chiplets 150 can be or include any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, Random Access Memory (RAM), such as DRAM, Synchronous DRAM (SDRAM), graphics double data rate type 6SDRAM (GDDR6 SDRAM), and the like. Examples of non-volatile memory devices include, but are not limited to, NAND (NAND) type flash memory, storage class memory (e.g., phase change memory or memristor-based technologies), ferroelectric ram (feram), and so forth. The illustrated example includes the memory device 150 as a chiplet, however, the memory device 150 can reside elsewhere, such as in a different package on the peripheral board 105. For many applications, multiple memory device chiplets can be provided. In an example, these memory device chiplets can each implement one or more storage technologies. In an example, a memory chiplet can include multiple stacked memory dies of different technologies, such as one or more SRAM devices stacked or otherwise in communication with one or more DRAM devices. Memory controller 140 can also be used to coordinate operations among multiple memory chiplets in chiplet system 110; for example, one or more memory chiplets are utilized in one or more levels of cache storage and one or more additional memory chiplets are used as main memory. The chiplet system 110 can also include multiple memory controllers 140, as can be used to provide memory control functionality for individual processors, sensors, networks, and the like. A chiplet architecture such as chiplet system 110 provides the advantage of allowing adaptation to different memory storage technologies and different memory interfaces by an updated chiplet configuration without the need to redesign the rest of the system architecture.

FIG. 2 illustrates components of an example of a memory controller chiplet 205 according to an embodiment. Memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., to communicate with off-die memory 275), a network communication interface 225 (e.g., to interface with chiplet network 285 and communicate with other chiplets), and a set of atom and merge units 250. The components of this set may include, for example, a write merge unit 255, a memory hazard unit 260, a built-in atomic unit 265 (for performing built-in atomic transactions), or a Programmable Atomic Unit (PAU)270 (for performing programmable atomic transactions). The various components are illustrated logically, and they need not be implemented. For example, built-in atomic unit 265 might include different devices along the path to off-die memory. For example, built-in atomic unit 265 may be in an interface device/buffer on a memory chiplet, as discussed above. In contrast, programmable atomic unit 270 may be implemented in a separate processor on memory controller chiplet 205 (but in various examples may be implemented in other locations, such as on a memory chiplet).

The off-die memory controller 220 is directly coupled to the off-die memory 275 (e.g., via a bus or other communication connection) to provide write operations and read operations to and from one or more off-die memories, such as the off-die memory 275 and the off-die memory 280. In the depicted example, the off-die memory controller 220 is also coupled to the atomic and merge unit 250 for outputs and to the cache controller 215 (e.g., a memory-side cache controller) for inputs.

In an example configuration, cache controller 215 is directly coupled to cache 210 and may be coupled to network communication interface 225 for input (e.g., incoming read or write requests) and coupled for output to off-die memory controller 220.

The network communication interface 225 includes a packet decoder 230, a network input queue 235, a packet encoder 240, and a network output queue 245 to support a packet-based chiplet network 285, such as a CPI. The chiplet network 285 can provide packet routing between and among processors, memory controllers, mixed-thread processors, configurable processing circuits, or communication interfaces. In such packet-based communication systems, each packet typically includes destination and source addressing, as well as any data payloads or instructions. In an example, depending on the configuration, the chiplet network 285 can be implemented as a set of crossbar switches with a folded Clos configuration, or a mesh network providing additional connections.

In various examples, chiplet network 285 can be part of an asynchronous switching fabric. Here, the data packets may be routed along any of a variety of paths such that any selected data packet may arrive at an addressed destination at any of a number of different times depending on the route. Additionally, the chiplet network 285 can be implemented at least in part as a synchronous communication network, such as a synchronous mesh communication network. Both configurations of a communication network are considered for examples according to the present disclosure.

Memory controller chiplet 205 can receive packets with source addresses, read requests, and physical addresses, for example. In response, the off-die memory controller 220 or cache controller 215 will read the data from the specified physical address (which may be in the off-die memory 275 or in the cache 210) and assemble the response packet into a source address containing the requested data. Similarly, the memory controller chiplet 205 can receive packets having a source address, a write request, and a physical address. In response, the memory controller chiplet 205 writes the data to the specified physical address (which can be in the cache 210 or in the off-die memory 275 or 280) and assembles the response packet into a source address containing an acknowledgement that the data is stored to memory.

Thus, where possible, memory controller chiplet 205 can receive read and write requests over chiplet network 285 and process the requests using cache controller 215 that interfaces with cache 210. If the cache controller 215 is unable to handle the request, the off-die memory controller 220 handles the request by communicating with the off-

die memory

275 or 280, the atomic and merge unit 250, or both. As mentioned above, one or more levels of cache may also be implemented in off-

die memory

275 or 280; and in some such instances may be directly accessible by the cache controller 215. Data read by off-die memory controller 220 may be cached in cache 210 by cache controller 215 for subsequent use.

The atomic and merge unit 250 is coupled to receive (as input) the output of the off-die memory controller 220 and provide the output to the cache 210, the network communication interface 225, or directly to the chiplet network 285. Memory hazard unit 260, write merge unit 255, and built-in (e.g., predetermined) atomic unit 265 may each be implemented as a state machine having other combinational logic circuitry (e.g., adders, shifters, comparators, and gates, or gates, xor gates, or any suitable combination thereof) or other logic circuitry. These components may also include one or more registers or buffers to store operands or other data. The PAU 270 may be implemented as one or more processor cores or control circuitry, as well as various state machines with other combinational or other logic circuitry, and may also include one or more registers, buffers, or memories to store addresses, executable instructions, operands, and other data, or may be implemented as a processor. An example PAU 270 is shown in fig. 3.

The write merge unit 255 receives the read data and the request data and merges the request data and the read data to produce a single unit having the read data and a source address to be used in the response or return data packet. Write merge unit 255 provides the merged data to a write port of cache 210 (or equivalently, to cache controller 215 for writing to cache 210). Optionally, the write merge unit 255 provides the merged data to the network communication interface 225 to encode and prepare a response or return data packet for transmission over the chiplet network 285.

When the requested data is for a built-in atomic operation, built-in atomic unit 265 receives the request and read data from write merge unit 255 or directly from off-die memory controller 220. An atomic transaction is conducted and the resulting data is written to cache 210 using write merge unit 255 or provided to network communication interface 225 to encode and prepare response or return data packets for transmission over chiplet network 285.

Built-in atomic unit 265 handles predefined atomic transactions, such as fetch and increment or compare and swap. In an example, these transactions perform simple read-modify-write operations to a single memory location that is 32 bytes in size or less. An atomic memory transaction is initiated from a request packet transmitted via the chiplet network 285. The request packet has a physical address, an atomic operator type, an operand size, and optionally up to 32 bytes of data. The atomic transaction reads-modifies-writes a cache memory line of cache 210, filling the cache memory as necessary. The atomic transaction response may be a simple completion response, or a response with up to 32 bytes of data. Example atomic memory transactions include fetch and, fetch and OR, fetch and XOR, fetch and Add, fetch and subtract, fetch and increment, fetch and decrement, fetch and min, fetch and max, fetch and swap and compare and swap. In various example embodiments, 32-bit and 64-bit operations and operations on 16 or 32 bytes of data are supported. The methods disclosed herein are also compatible with hardware that supports larger or smaller operations and more or less data.

Built-in atomic transactions may also involve requests for "standard" atomic standards on the requested data, such as relatively simple single cycle integer atoms, e.g., fetch and increment or compare and swap, whose throughput will be the same as a conventional memory read or write operation that does not involve an atomic operation. For these operations, cache controller 215 may generally reserve a cache line in cache 210 by setting a hazard bit (in hardware) so that the cache line cannot be read by another process at the time of the translation. Data is obtained from off-die memory 275 or cache 210 and provided to built-in atomic unit 265 for the requested atomic transaction. After the atomic transaction, in addition to providing the resulting data to packet encoder 240 to encode outgoing data packets for transmission over chiplet network 285, built-in atomic unit 265 provides the resulting data to write merge unit 255, which also writes the resulting data to cache 210. After writing the resulting data to cache 210, memory hazard unit 260 will clear any corresponding hazard bits that are set.

The PAU 270 enables high performance (high throughput and low latency) of programmable atomic transactions (also referred to as "custom atomic transactions" or "custom atomic operations") that is comparable to the performance of built-in atomic transactions. Instead of performing multiple memory accesses, in response to an atomic transaction request specifying a programmable atomic transaction and a memory address, circuitry in the memory controller chiplet 205 communicates the atomic transaction request to the PAU 270 and sets a hazard bit stored in a memory hazard register corresponding to the memory address of the memory row used in the atomic operation to ensure that no other operations (read, write, or atomic transaction) are performed on the memory row, which is then cleared after the atomic transaction is completed. The additional, direct data path provided for PAU 270 to perform programmable atomic transactions allows additional write operations without any limitations imposed by the bandwidth of the communication network and without any increased congestion of the communication network.

The PAU 270 includes a multithreaded processor 320, such as a RISC-V ISA based multithreaded processor, having one or more processor cores and further having an extended instruction set for executing programmable atomic transactions. When provided with an extended instruction set for executing programmable atomic transactions, the processor 320 of the PAU 270 may be embodied as one or more mixed-thread processors. In some example embodiments, the processor 320 of the PAU 270 provides a barrel-round-robin instantaneous thread switch to maintain a higher instruction-per-clock rate.

The PAU 270 may include local memory 305, such as Static Random Access Memory (SRAM), NAND, phase change memory, and the like. Local memory 305 may include registers 335, instruction memory 325, and cache 330. The local memory 305 may be accessed by the processor 320 through the memory controller 310.

Programmable atomic transactions involving requests for programmable atomic transactions on requested data may be performed by PAU 270. A user may prepare programming code in the form of one or more instructions to provide such programmable atomic transactions. For example, a programmable atomic transaction may be a relatively simple multi-cycle operation, such as a floating point addition, or may be a relatively complex multi-instruction operation, such as a Bloom filter insert. The programmable atomic transactions may be the same as or different from the predetermined atomic transactions, so long as they are defined by the user and not the system vendor. For these operations, cache controller 215 may reserve a cache line in cache 210 by setting a hazard bit (in hardware) so that the cache line cannot be read by another process at the time of the translation. Data is obtained from the cache 210 or the off-

die memory

275 or 280 and provided to the PAU 270 for the requested programmable atomic transaction. After the atomic operation, the PAU 270 provides the resulting data to the network communication interface 225 to directly encode outgoing data packets with the resulting data for transmission over the chiplet network 285. Additionally, the PAU 270 provides the resulting data to the cache controller 215, which also writes the resulting data to the cache 210. After writing the resulting data to cache 210, cache controller 215 will clear any corresponding hazard bits that are set.

In selected examples, the approach taken for programmable atomic transactions is to provide a plurality of generic programmable atomic transaction request types that can be sent to the memory controller chiplet 205 over the chiplet network 285 from an originating source, such as a processor or other system component. The cache controller 215 or the off-die memory controller 220 identifies the request as a programmable atomic transaction and forwards the request to the PAU 270. In representative embodiments, the PAU 270: (1) is a programmable processing element capable of efficiently conducting user-defined atomic transactions; (2) memory, arithmetic and logical operations, and control flow decisions may be loaded and stored; and (3) utilize a RISC-V ISA with a new specialized instruction set to facilitate interaction with

such controllers

215, 220 to conduct user-defined transactions in an atomic manner. In a desirable example, the RISC-V ISA contains a complete instruction set that supports high-level language operators and data types. The PAU 270 may leverage the RISC-V ISA, but will typically support a more limited instruction set and limited register file sizes to reduce the die size of the unit when included within the memory controller chiplet 205.

As mentioned above, memory hazard clearing unit 260 will clear the set hazard bits of the retained cache line prior to writing the read data to cache 210. Thus, when write merge unit 255 receives a request and reads data, memory hazard clearing unit 260 may transmit a reset or clear signal to cache 210 to reset the set memory hazard bits of the retained cache line. Also, resetting this hazard bit will also release pending read or write requests relating to the specified (or reserved) cache line, providing the pending read or write requests to the inbound request multiplexer for selection and processing.

Fig. 3 illustrates a block diagram of a programmable atomic unit 270, in accordance with some examples of the present disclosure. As previously described, the programmable atomic unit may include one or more programmable atomic transactions specified by one or more atomic instruction sets stored in instruction memory 325 that are customized and operate on memory managed by the memory controller. The instructions of an atomic transaction may be specified by an application and/or process external to programmable atomic unit 270, which may reside on memory controller chiplet 205, other chiplets (e.g., application chiplet 125), or off-chiplet devices. In some examples, instructions of the programmable atomic transaction are loaded by the operating system when registered by the process. To perform the programmable atomic transaction, the initiating process sends a CPI message containing instructions to perform the requested programmable atomic transaction on the local memory 305 of the programmable atomic unit 270 by providing an index into the local memory of the programmable atomic unit 270. Programmable atomic transactions may utilize cache 330, registers 335, and other memory of local memory 305 during execution. The local memory controller 310 may manage the local memory 305. In some examples, the programmable atomic unit 270 may not require a local memory controller because the local memory 305 may be SRAM.

Upon requesting execution of a particular programmable atomic transaction, the request processor may send a CPI request packet indicating a particular memory location within the programmable atomic unit (e.g., a partition within the local memory 305), the CPI request including previously loaded programmable atomic instructions to be executed, a location of memory managed by the memory controller chiplet 205 (e.g., off-die memory 275, 280) to be operated on, and one or more variable parameters. The processor (e.g., processor 320) then begins executing instructions at the indicated partition. FIG. 4 illustrates a request packet for requesting execution of a particular programmable atomic transaction. The fields are described as:

the programmable atomic transaction begins by executing a first instruction located at a partition in the programmable atomic transaction's instruction RAM (e.g., local memory 305 of programmable atomic unit 270) specified by a custom atomic partition index (CaPIdx). The operation starts at the first instruction within the partition. The CaPIdx can also be used to index into a control structure that contains additional information for the operation. The additional information includes a flag to indicate whether the transaction is valid, a number of partitions for the transaction, and an instruction execution limit. The number of partitions is used to verify that an operation is being performed within the appropriate partition. If execution in the improper partition is detected, an exception is detected and execution operations are terminated.

A response to the programmable atomic transaction is provided as a memory response. For example, fig. 5 illustrates a response message. The fields of the response message are as follows:

the programmable atomic unit may set a lock prior to executing the programmable atomic transaction, the lock providing exclusive memory access to an address range of a system memory (e.g., memory 275, 280) controlled by the memory controller. The lock may be set automatically when the programmable atomic transaction begins execution and the lock must be cleared when the programmable atomic transaction completes. If the lock is not cleared, future programmable atomic transactions that require the particular lock bit will not be allowed to begin execution.

Disclosed in some examples are methods, systems, computing devices, and machine-readable media that define instructions for a programmable atomic unit that are executed as a last instruction and terminate a thread of execution, wait for all outstanding store operations to complete, clear a programmable atomic lock, and send a completion response back to an issuing process. This ensures that the programmable atomic lock is cleared when the transaction is complete. By coupling thread termination with the clear lock bit, this ensures that the thread cannot terminate without clearing the lock.

Fig. 6 illustrates a flow diagram of a method 600 of executing a programmable atomic transaction and a terminate instruction, according to some examples of the disclosure. At operation 605, the programmable atomic unit may receive an instruction to execute a programmable atomic transaction. As previously described, the instruction may specify one of a plurality of programmable atomic transactions stored within a memory of the programmable atomic unit that define an operation to be performed for the particular programmable atomic transaction. The instructions may specify a particular programmable atomic transaction based on a memory partition identifier as previously described. At operation 610, a lock associated with a memory address provided with a programmable atomic transaction request may be set, the memory (e.g., off-die memory 275, 280) being controlled by a memory controller. In some examples, a lock may be used for one or more memory locations, such as a range of memory locations specified by a base address.

At operation 612, the programmable atomic unit may perform instructions of a programmable atomic transaction. Such instructions may include reading values from a memory (e.g., off-die memory 275, 280) controlled by a memory controller of which the programmable atomic unit 270 is a part. Such instructions may operate on values read from memory and may store modified values back to memory (e.g., off-die memory 275, 280). Such operation provides reduced latency to the process that invokes the PAU. At operation 615, the last programmable atomic instruction of the programmable atomic transaction may be executed. The instruction may be a termination instruction. The instruction may wait for an outstanding store operation at operation 620, clear the lock at operation 625, and send a response at operation 630. The response is shown in FIG. 5 and may include a status code, the result of the operation, and the like.

In some examples, the lock may be a bit in a register (e.g., a register stored in register 335), a value stored in a memory location (e.g., in local memory 305, off-die memory 275, 280), and so on. Locks may be more complex and may store information about when to set the lock, the calling process that set the lock, and so on. In some instances, locks may be set and cleared by submitting memory addresses to a hash function that indexes into a table of a linked list. Locks are set by adding a structure to the linked list that indicates the programmable atoms that currently have locks.

Fig. 7 illustrates an example terminate instruction 700 in accordance with some examples of the present disclosure. The EMD Atomic Return (EAR) instruction shown in FIG. 7 includes the following variable parameters:

the RC2 suffix option is as follows:

RC2 encoding	Suffix	Variable parameter counting
			0	R0 or no suffix	0
1	.R1	1
			2	.R2	2

An example assembly would be as follows:

example Assembly	Notes
		EAR.R0	#	0 Return variable parameter
EAR.R1 rs1	#1 in rs1 return variable parameter
		EAR.R2 rs1,rs2	#2 Return variable parameter in rs1, rs2

Fig. 8 illustrates a schematic diagram of a memory controller 800, according to some examples of the present disclosure. Fig. 8 is another example of a memory controller 205 and shows many of the same components as shown in fig. 2. For example, caches 820 and 885 are examples of cache 210; DRAM 845 is an example of off-die memory 275-280; atom/write merge 880 and programmable atom unit 895 may be instances of atom and merge unit 250; the other components of FIG. 8 may be examples of other components of FIG. 2, such as the off-die memory controller 220 and the cache controller 215. NOC request queue 805 receives requests from the network on chip and provides a small amount of queuing. The atomic request queue 810 receives requests from programmable atomic units and provides a small number of queues. An Inbound Request Multiplexer (IRM)815 selects between the sources of inbound memory requests. The three sources are in priority order: memory hazard requests, atomic requests, and inbound NOC requests. Cache (read) 802 and cache (write) 885 are SRAM data caches. The figure shows the cache (802 and 885) as two separate blocks, one providing read access and the other providing write access. Delay block 825 provides one or more pipeline stages to simulate the delay for SRAM cache read operations. A cache miss requires an access to memory to introduce the desired data into the cache. During this DRAM access time, the memory line is not available for other requests. The memory hazard block (set block 830 and clear block 890) maintains a table of hazard bits indicating which memory lines are unavailable for access. Inbound requests attempting to access the line with the hazard are held by the memory hazard block until the hazard is cleared. Once the hazard is cleared, the request is resent through the inbound request multiplexer. The memory line tag address is hashed into a hazard bit index. The number of hazard bits may be chosen to set the hazard collision probability to a sufficiently low level. An Inbound DRAM Control Multiplexer (IDCM)835 selects from inbound NOC requests and cache eviction requests. Bank request queue 840-each separately managed DRAM bank has a dedicated bank request queue to hold requests until they can be scheduled on the associated DRAM bank.

Scheduler 842 selects across bank request queue 840 to pick a request for an available DRAM bank. DRAM 845 represents one or more external DRAM devices. The request hit data queue 850 holds the request data from the cache hit until selected. Request miss data queue 855 holds data read from DRAM until selected. Miss request queue 860 is used to hold request packet information for cache misses until the request is selected. The hit request queue 865 holds request packet information for cache hits until selected. A Data Select Multiplexer (DSM)870 selects between DRAM read data and cache hit read data. The selected data is written to the SRAM cache. A Request Selection Multiplexer (RSM)875 selects between the hit request queue 860 and the miss request queue 865.

Atomic/write merge 880 merges the request data and the DRAM read data or, if the request is a built-in atom, the memory data and the request data are used as inputs for the atomic operation. Cache (write) block 885 represents a write port for the SRAM cache. Data from the NOC write request and data from the DRAM read operation are written to the SRAM cache. A memory hazard (clear) block 890 represents a hazard clear operation for a memory hazard structure. Clearing the hazard may release and send pending NOC requests to the inbound request multiplexer. Programmable atomic unit 895 handles programmable atomic transactions. The NOC Outbound Response Multiplexer (ORM)897 selects between the memory controller response and the custom atomic unit response and sends the selection to the NOC.

Fig. 9 illustrates a block diagram of an example machine 900 with which, in, or by which any one or more of the techniques (e.g., methods) discussed herein may be implemented. As described herein, an example may include, or be operable by, logic or multiple components or mechanisms in the machine 900. Circuitry (e.g., processing circuitry) is a collection of circuits implemented in a tangible entity of machine 900 that includes hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership may become flexible over time. The circuitry includes components that can perform specified operations when operating, either individually or in combination. In an example, hardware of a circuitry may be permanently designed to perform a specific operation (e.g., hardwired). In an example, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including machine-readable media physically modified (e.g., without changing the magnetic, electrically movable placement of the centralized particles, etc.) to encode instructions for specific operations. When physical components are connected, the underlying electrical properties of the hardware makeup change, for example, from an insulator to a conductor or vice versa. The instructions enable embedded hardware (e.g., an execution unit or loading mechanism) to generate, via the variable connections, components of circuitry in the hardware to perform portions of specific operations while in operation. Thus, in an example, a machine-readable medium element is part of circuitry or other component that is communicatively coupled to circuitry when the device is operating. In an example, any of the physical components may be used in more than one component in more than one circuitry. For example, under operation, an execution unit may be used in a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry, or reused by a third circuit in the second circuitry at a different time. The following are additional examples of these components with respect to the machine 900.

In alternative embodiments, the machine 900 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 900 may operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 900 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 900 may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

A machine (e.g., computer system) 900 may include a hardware processor 902 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a hardware processor core, or any combination thereof), a main memory 904, a static memory (e.g., a memory or storage device for firmware, microcode, Basic Input Output (BIOS), Unified Extensible Firmware Interface (UEFI), etc.) 906, and a mass storage device 908 (e.g., a hard drive, tape drive, flash memory device, or other block device), some or all of which may communicate with each other via an interconnect (e.g., bus) 930. The machine 900 may further include a display unit 910, an alphanumeric input device 912 (e.g., a keyboard), and a User Interface (UI) navigation device 914 (e.g., a mouse). In an example, the display unit 910, the input device 912, and the UI navigation device 914 may be a touch screen display. The machine 900 may additionally include a mass storage device (e.g., a drive unit) 908, a signal generation device 918 (e.g., a speaker), a network interface device 920, and one or more sensors 916, such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor. The machine 900 may include an output controller 928, such as a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., Infrared (IR), Near Field Communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, card reader, etc.).

The processor 902, the main memory 904, the static memory 906, or the registers of the mass storage device 908 may be or include a machine-readable medium 922 having stored thereon one or more sets of data structures or instructions 924 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 924 may also reside, completely or at least partially, within any of the processors 902, the main memory 904, the static memory 906, or registers of the mass storage device 908 during execution thereof by the machine 900. In an example, one or any combination of the hardware processor 902, the main memory 904, the static memory 906, or the mass storage device 908 may constitute the machine-readable medium 922. While the machine-readable medium 922 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 924.

The term "machine-readable medium" may include any medium that is capable of storing, encoding or carrying instructions for execution by the machine 900 and that cause the machine 900 to perform any one or more of the techniques of this disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, acoustic signals, etc.). In an example, a non-transitory machine-readable medium includes a machine-readable medium having a plurality of particles that have an invariant (e.g., stationary) mass, and thus are a composition of matter. Thus, a non-transitory machine-readable medium is a machine-readable medium that does not include a transitory propagating signal. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

In an example, information stored or otherwise provided on the machine-readable medium 922 may represent the instructions 924, such as the instructions 924 themselves or a format from which the instructions 924 may be derived. Such a format from which the instructions 924 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), and so forth. Information representing instructions 924 in the machine-readable medium 922 may be processed into the instructions by the processing circuitry to implement any of the operations discussed herein. For example, deriving instructions 924 from information (e.g., processed by processing circuitry) may include: compile (e.g., from source code, object code, etc.), interpret, load, organize (e.g., dynamically or statically linked), encode, decode, encrypt, decrypt, encapsulate, decapsulate, or otherwise manipulate information into instructions 924.

In an example, derivation of the instructions 924 can include assembly, compilation, or interpretation of information (e.g., by processing circuitry) to create the instructions 924 from some intermediate or pre-processed format provided by the machine-readable medium 922. When information is provided in multiple portions, the information can be combined, unpacked, and modified to create the instructions 924. For example, the information may be in multiple compressed source code packages (or object code, or binary executable, etc.) on one or several remote servers. The source code encapsulation may be encrypted when transmitted over a network and decrypted, decompressed, assembled (e.g., linked) if necessary, and compiled or interpreted at the local machine (e.g., into a separately executable library, etc.) and executed by the local machine.

The instructions 924 may further be transmitted or received over a communication network 926 using a transmission medium via the network interface device 920 utilizing any one of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a Local Area Network (LAN), a Wide Area Network (WAN), a packet data network (e.g., the internet), a mobile telephone network (e.g., a cellular network), a Plain Old Telephone (POTS) network, and a wireless data network (e.g., referred to as

Of the Institute of Electrical and Electronics Engineers (IEEE)802.11 family of standards, known as

IEEE 802.16 family of standards), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, and so forth. In an example, the network interface device 920 may include one or more physical jacks (e.g., ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 926. In an example, the network interface device 920 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine 900, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software. The transmission medium is a machine-readable medium. To better illustrate the methods and apparatus described herein, a non-limiting set of example embodiments are set forth below as being numberedExamples are given.

Other notes and examples

Embodiment 1 is an apparatus, comprising: a memory array; a memory controller coupled to the memory array, the memory controller comprising an internal memory storing a lock structure for controlling access to one or more memory locations of the memory array; a programmable atomic unit coupled to the memory controller and comprising: an instruction memory configured to store one or more instruction sets; and a processor configured to: receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in the instruction memory; setting a lock for a portion of the memory array in the lock structure of the internal memory of the memory controller, the lock preventing subsequent access to the portion of the memory array; executing the set of instructions; and executing an instruction to terminate the execution of the set of instructions, the instruction to terminate the execution of the set of instructions comprising an operation to clear the lock.

In example 2, the subject matter of example 1 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

In example 3, the subject matter of examples 1-2 includes wherein the instructions to terminate the execution of the instruction set further comprise an operation to wait for an outstanding store operation to complete before clearing the lock.

In example 4, the subject matter of examples 1-3 includes, wherein the instructions to terminate the execution of the set of instructions further comprises: an operation to wait for an outstanding store operation to complete before clearing the lock; and an operation to send a response to a process that sent the instructions to execute the set of instructions after performing the operation to wait for outstanding store operations to complete and the operation to clear the lock.

In example 5, the subject matter of example 4 includes, wherein the response comprises one or more values stored in a register of the programmable atomic unit.

In example 6, the subject matter of examples 1-5 includes, wherein the lock is a bitmap in a register of the programmable atomic unit.

In example 7, the subject matter of examples 1-6 includes, wherein the memory array comprises one or more Random Access Memory (RAM) banks.

Example 8 is a method, comprising: at a programmable atomic unit coupled to a memory controller and including a processor: receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in a memory of the programmable atomic unit; setting a lock in a lock structure of an internal memory of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; executing the set of instructions; and executing an instruction to terminate the execution of the set of instructions, the instruction to terminate the execution of the set of instructions comprising an operation to clear the lock.

In example 9, the subject matter of example 8 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

In example 10, the subject matter of examples 8-9 includes wherein the instructions to terminate the execution of the instruction set further comprise operations to wait for outstanding store operations to complete before clearing the lock.

In example 11, the subject matter of examples 8-10 includes, wherein the instructions to terminate the execution of the set of instructions further comprises: an operation to wait for an outstanding store operation to complete before clearing the lock; and an operation to send a response to a process that sent the instructions to execute the set of instructions after performing the operation to wait for outstanding store operations to complete and the operation to clear the lock.

In example 12, the subject matter of example 11 includes, wherein the response comprises one or more values stored in a register of the programmable atomic unit.

In example 13, the subject matter of examples 8-12 includes, wherein the lock is a bitmap in a register of the programmable atomic unit.

In example 14, the subject matter of examples 8-13 includes, wherein the memory array comprises one or more Random Access Memory (RAM) banks.

Example 15 is a non-transitory machine-readable medium storing instructions that, when executed by a machine, cause the machine to perform operations comprising: receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in a memory of a programmable atomic unit; setting a lock in a lock structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; executing the set of instructions; and executing an instruction to terminate the execution of the set of instructions, the instruction to terminate the execution of the set of instructions comprising an operation to clear the lock.

In example 16, the subject matter of example 15 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

In example 17, the subject matter of examples 15-16 includes wherein the instructions to terminate the execution of the instruction set further comprise operations to wait for outstanding store operations to complete before clearing the lock.

In example 18, the subject matter of examples 15-17 includes, wherein the instructions to terminate the execution of the set of instructions further comprises: an operation to wait for an outstanding store operation to complete before clearing the lock; and an operation to send a response to a process that sent the instructions to execute the set of instructions after performing the operation to wait for outstanding store operations to complete and the operation to clear the lock.

In example 19, the subject matter of example 18 includes, wherein the response comprises one or more values stored in a register of the programmable atomic unit.

In example 20, the subject matter of examples 15-19 includes, wherein the lock is a bitmap in a register of the programmable atomic unit.

In example 21, the subject matter of examples 15-20 includes, wherein the memory array comprises one or more Random Access Memory (RAM) banks.

Example 22 is an apparatus, comprising: means for receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in a memory of the programmable atomic unit; means for setting a lock in a lock structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller; means for executing the set of instructions; and means for executing an instruction to terminate the execution of the set of instructions, the instruction to terminate the execution of the set of instructions comprising an operation to clear the lock.

In example 23, the subject matter of example 22 includes, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

In example 24, the subject matter of examples 22-23 includes wherein the instructions to terminate the execution of the instruction set further comprise operations to wait for outstanding store operations to complete before clearing the lock.

In example 25, the subject matter of examples 22-24 includes, wherein the instructions to terminate the execution of the set of instructions further comprises: an operation to wait for an outstanding store operation to complete before clearing the lock; and an operation to send a response to a process that sent the instructions to execute the set of instructions after performing the operation to wait for outstanding store operations to complete and the operation to clear the lock.

In example 26, the subject matter of example 25 includes, wherein the response comprises one or more values stored in a register of the programmable atomic unit.

In example 27, the subject matter of examples 22-26 includes, wherein the lock is a bitmap in a register of the programmable atomic unit.

In example 28, the subject matter of examples 22-27 includes, wherein the memory array comprises one or more Random Access Memory (RAM) banks.

Example 29 is at least one machine readable medium comprising instructions that when executed by processing circuitry cause the processing circuitry to operate to implement any of examples 1-28.

Example 30 is an apparatus comprising means to implement any of examples 1 to 28.

Example 31 is a system to implement any of examples 1-28.

Example 32 is a method to implement any of examples 1-28.

The foregoing detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the inventors also contemplate examples (or one or more aspects thereof) using any combination or permutation of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, regardless of any other instances or uses of "at least one" or "one or more". In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "a or B" may include "a instead of B", "B instead of a", and "a and B". In the appended claims, the terms "including" and "in which" are used as the plain-equivalent terms for the respective terms "comprising" and "in which". Furthermore, in the following claims, the terms "comprising" and "including" are open-ended, that is, a system, apparatus, article, or process that includes elements in addition to those listed in a claim after such term is considered to be within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art, in view of the above description. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the foregoing detailed description, various features may be grouped together to simplify the present disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. An apparatus, comprising:

a memory array;

a memory controller coupled to the memory array, the memory controller comprising an internal memory storing a lock structure for controlling access to one or more memory locations of the memory array;

a programmable atomic unit coupled to the memory controller and comprising:

an instruction memory configured to store one or more instruction sets; and

a processor configured to:

receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in the instruction memory;

setting a lock for a portion of the memory array in the lock structure of the internal memory of the memory controller, the lock preventing subsequent access to the portion of the memory array;

executing the set of instructions; and

executing an instruction to terminate the execution of the set of instructions, the instruction to terminate the execution of the set of instructions comprising an operation to clear the lock.

2. The apparatus of claim 1, wherein the instructions to terminate the execution of the set of instructions further comprises operations to send a response to a process that sent the command to execute the set of instructions.

3. The apparatus of claim 1, wherein the instruction to terminate the execution of the set of instructions further comprises an operation to wait for an outstanding store operation to complete before clearing the lock.

4. The apparatus of claim 1, wherein the instructions to terminate the execution of the set of instructions further comprises:

an operation to wait for an outstanding store operation to complete before clearing the lock; and

an operation to send a response to a process that sent the instructions to execute the set of instructions after performing the operation to wait for outstanding store operations to complete and the operation to clear the lock.

5. The apparatus of claim 4, wherein the response comprises one or more values stored in a register of the programmable atomic unit.

6. The apparatus of claim 1, wherein the lock is a bitmap in a register of the programmable atomic unit.

7. The apparatus of claim 1, wherein the memory array comprises one or more banks of Random Access Memory (RAM).

8. A method, comprising:

at a programmable atomic unit coupled to a memory controller and including a processor:

receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in a memory of the programmable atomic unit;

setting a lock in a lock structure of an internal memory of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller;

executing the set of instructions; and

9. The method of claim 8, wherein the instructions to terminate the execution of the set of instructions further comprises operations to send a response to a process that sent the command to execute the set of instructions.

10. The method of claim 8, wherein the instruction to terminate the execution of the set of instructions further comprises an operation to wait for an outstanding store operation to complete before clearing the lock.

11. The method of claim 8, wherein the instructions to terminate the execution of the set of instructions further comprises:

12. The method of claim 11, wherein the response comprises one or more values stored in a register of the programmable atomic unit.

13. The method of claim 8, wherein the lock is a bitmap in a register of the programmable atomic unit.

14. The method of claim 8, wherein the memory array comprises one or more Random Access Memory (RAM) banks.

15. A non-transitory machine-readable medium storing instructions that, when executed by a machine, cause the machine to perform operations comprising:

receiving a command to execute a set of instructions corresponding to a programmable atomic transaction, the set of instructions stored in a memory of a programmable atomic unit;

setting a lock in a lock structure of a memory controller coupled to the programmable atomic unit, the lock preventing subsequent access to a portion of a memory array of a memory coupled to the memory controller;

executing the set of instructions; and

16. The non-transitory machine-readable medium of claim 15, wherein the instructions to terminate the execution of the set of instructions further comprise operations to send a response to a process that sent the command to execute the set of instructions.

17. The non-transitory machine-readable medium of claim 15, wherein the instructions to terminate the execution of the set of instructions further comprises operations to wait for an outstanding store operation to complete before clearing the lock.

18. The non-transitory machine-readable medium of claim 15, wherein the instructions to terminate the execution of the set of instructions further comprises:

19. The non-transitory machine-readable medium of claim 18, wherein the response comprises one or more values stored in a register of the programmable atomic unit.

20. The non-transitory machine-readable medium of claim 15, wherein the lock is a bitmap in a register of the programmable atomic unit.