JP5279879B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor device, and more particularly to a nonvolatile semiconductor memory device having a memory cell array having a stacked structure.

  Conventionally, as an electrically rewritable nonvolatile memory, a flash memory in which a memory cell array is formed by NAND-connecting or NOR-connecting memory cells having a floating gate structure is well known. A ferroelectric memory is also known as a non-volatile memory capable of high-speed random access.

  On the other hand, as a technique for further miniaturizing a memory cell, a resistance change type memory using a variable resistance element as a memory cell has been proposed. Examples of the variable resistance element include a phase change memory element that changes a resistance value according to a change in state of crystal / amorphization of a chalcogenide compound, an MRAM element that uses a resistance change due to a tunnel magnetoresistance effect, and a polymer in which a resistance element is formed of a conductive polymer. A ferroelectric RAM (PFRAM) memory element, a ReRAM element that causes a resistance change by application of an electric pulse, and the like are known (Patent Document 1).

  In this resistance change type memory, a memory cell can be constituted by a series circuit of a Schottky diode and a variable resistance element instead of a transistor. Therefore, a cross point structure in which a memory cell is arranged at an intersection of upper and lower wirings is adopted. be able to. For this reason, there exists an advantage that it can form easily and can achieve further high integration (patent document 2). Further, the memory cell array using the resistance change type memory has a stacked structure, so that the capacity of the nonvolatile memory can be increased.

  However, if the stacking order of the memory cells in each memory cell array is different in the process of the non-volatile memory having such a stacked structure, the memory cell characteristics vary from one memory cell array to another. Cause.

JP 2006-344349, paragraph 0021 JP-A-2005-522045

  The present invention provides a nonvolatile semiconductor memory device having a stacked structure in which variations in memory cell characteristics occurring between memory cell layers are reduced by making the stacking order of memory cells in each memory cell layer the same.

  A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of first and second wirings that intersect with each other, and memory cells provided at the intersections of the plurality of first and second wirings. A memory cell array formed by stacking a plurality of memory cell layers is provided. The memory cell includes a variable resistance element and a non-ohmic element stacked in the stacking direction of the memory cell array, and the stacking order of the variable resistance element and the non-ohmic element of a memory cell in a predetermined memory cell layer, and the like. The stacking order of the variable resistance element and the non-ohmic element of the memory cell in the memory cell layer is the same.

  According to the present invention, it is possible to provide a non-volatile semiconductor memory device having a stacked structure in which variations in memory cell characteristics occurring between memory cell layers are reduced by making the stacking order of memory cells in each memory cell layer the same. it can.

1 is a block diagram of a nonvolatile memory according to a first embodiment of the present invention. FIG. FIG. 4 is a perspective view of a part of the memory cell array of the nonvolatile memory according to the same embodiment. FIG. 3 is a cross-sectional view of one memory cell taken along line II ′ in FIG. 2 and viewed in the direction of the arrow. It is a typical sectional view showing an example of a variable resistance element in the embodiment. 2 is a circuit diagram of a memory cell array and its peripheral circuits of the nonvolatile memory according to the same embodiment. FIG. FIG. 3 is a cross-sectional view of the nonvolatile memory according to the same embodiment. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. It is the perspective view which showed the formation process of the upper layer part of the non-volatile memory which concerns on the same embodiment. It is the perspective view which showed the formation process of the upper layer part of the non-volatile memory which concerns on the 2nd Embodiment of this invention in process order. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. 2 is a cross-sectional view of a memory cell of the nonvolatile memory according to the same embodiment. FIG. FIG. 4 is a cross-sectional view of another memory cell of the nonvolatile memory according to the same embodiment. It is the perspective view which showed the formation process of the upper layer part of the non-volatile memory which concerns on the 3rd Embodiment of this invention in process order. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. FIG. 4 is a perspective view showing a process of forming an upper layer part of the nonvolatile memory according to the embodiment in order of processes. 2 is a cross-sectional view of a memory cell of the nonvolatile memory according to the same embodiment. FIG. It is sectional drawing of the memory cell of the non-volatile memory which concerns on a comparative example.

  Hereinafter, embodiments of a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.

[First Embodiment]
[overall structure]
FIG. 1 is a block diagram of a nonvolatile memory according to the first embodiment of the present invention.

  This nonvolatile memory includes a memory cell array 1 in which memory cells using ReRAM (variable resistance elements) described later are arranged in a matrix. A bit line BL of the memory cell array 1 is controlled at a position adjacent to the bit line BL direction (hereinafter also referred to as “column direction”) of the memory cell array 1 to erase data in the memory cell and to store data in the memory cell. A column control circuit 2 for writing and reading data from the memory cell is provided. Further, the word line WL of the memory cell array 1 is selected at a position adjacent to the word line WL direction (hereinafter also referred to as “row direction”) which is the first wiring of the memory cell array 1, and the memory cell A row control circuit 3 is provided for applying a voltage necessary for erasing data, writing data to the memory cell, and reading data from the memory cell.

  The data input / output buffer 4 is connected to an external host (not shown) via an I / O line, and receives write data, receives an erase command, outputs read data, and receives address data and command data. The data input / output buffer 4 sends the received write data to the column control circuit 2, receives the data read from the column control circuit 2, and outputs it to the outside. An address supplied from the outside to the data input / output buffer 4 is sent to the column control circuit 2 and the row control circuit 3 via the address register 5. The command supplied from the host to the data input / output buffer 4 is sent to the command interface 6. The command interface 6 receives an external control signal from the host, determines whether the data input to the data input / output buffer 4 is write data, a command, or an address, and if it is a command, transfers it to the state machine 7 as a received command signal. To do. The state machine 7 manages the entire nonvolatile memory, accepts commands from the host, and performs read, write, erase, data input / output management, and the like. An external host can also receive status information managed by the state machine 7 and determine an operation result. This status information is also used for control of writing and erasing.

  Further, the pulse generator 9 is controlled by the state machine 7. By this control, the pulse generator 9 can output a pulse having an arbitrary voltage and arbitrary timing. Here, the formed pulse can be transferred to an arbitrary wiring selected by the column control circuit 2 and the row control circuit 3.

  Peripheral circuit elements other than the memory cell array 1 can be formed on a silicon (Si) substrate immediately below the memory array 1 formed in the wiring layer, so that the chip area of this nonvolatile memory is approximately the memory cell array 1. It is also possible to make it equal to the area.

[Memory cell array and its peripheral circuits]
FIG. 2 is a perspective view of a part of the memory cell array 1, and FIG. 3 is a cross-sectional view of one memory cell taken along the line II ′ in FIG.

  Word lines WL0 to WL2 are arranged in parallel as a plurality of first wirings, and bit lines BL0 to BL2 which are a plurality of second wirings are arranged in parallel to intersect with each other. Memory cells MC are arranged so as to be sandwiched between both wirings. The first and second wirings are preferably made of a material that is resistant to heat and has a low resistance value. For example, W, WSi, NiSi, CoSi, or the like can be used.

  As shown in FIG. 3, the memory cell MC includes a series connection circuit of a variable resistance element VR and a non-ohmic element NO.

As the variable resistance element VR, the resistance value can be changed by applying voltage, through current, heat, chemical energy, etc., and electrodes EL2 and EL3 functioning as a barrier metal and an adhesive layer are arranged above and below. . As the electrode material, Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al, PtIrO _x , PtRhO _x , Rh / TaAlN, or the like is used. It is also possible to insert a metal film that makes the orientation uniform. It is also possible to insert a buffer layer, a barrier metal layer, an adhesive layer, etc. separately.

  As the variable resistance element VR, a compound compound (ReRAM) which is a composite compound containing a cation serving as a transition element and whose resistance value is changed by the movement of the cation can be used.

FIG. 4 is a diagram showing an example of this variable resistance element. This variable resistance element VR has a recording layer 12 disposed between electrode layers 11 and 13. The recording layer 12 is composed of a composite compound having at least two kinds of cationic elements. At least one of the cation elements is a transition element having a d orbital incompletely filled with electrons, and the shortest distance between adjacent cation elements is 0.32 nm or less. Specifically, the formula _A x _M y _X z _(A and M are different elements) is represented by, for example, spinel structure _{(AM 2 O} 4), ilmenite structure _(AMO 3), delafossite structure _(AMO 2) , LiMoN ₂ structure (AMN ₂ ), wolframite structure (AMO ₄ ), olivine structure (A ₂ MO ₄ ), hollandite structure (A _x MO ₂ ), ramsdellite structure (A _x MO ₂ ), perovskite structure (AMO ₃ ) It is composed of a material having a crystal structure such as

  In the example of FIG. 4, A is Zn, M is Mn, and X is O. Small white circles in the recording layer 12 represent diffusion ions (Zn), large white circles represent anions (O), and small black circles represent transition element ions (Mn). The initial state of the recording layer 12 is a high resistance state, but when a fixed potential is applied to the electrode layer 11 and a negative voltage is applied to the electrode layer 13 side, some of the diffused ions in the recording layer 12 move to the electrode layer 13 side. As a result, the diffusion ions in the recording layer 12 decrease relative to the anions. The diffused ions that have moved to the electrode layer 13 side receive electrons from the electrode layer 13 and are deposited as metal, so that the metal layer 14 is formed. Inside the recording layer 12, anions become excessive, and as a result, the valence of transition element ions in the recording layer 12 is increased. As a result, the recording layer 12 has electron conductivity by carrier injection, and the setting operation is completed. For reproduction, it is sufficient to pass a minute current value that does not cause a change in resistance of the material constituting the recording layer 12. In order to reset the program state (low resistance state) to the initial state (high resistance state), for example, a large current is allowed to flow through the recording layer 12 for a sufficient period of time to promote the oxidation-reduction reaction of the recording layer 12. good. The reset operation can also be performed by applying an electric field in the direction opposite to that at the time of setting.

  Non-ohmic elements NO include, for example, (a) Schottky diode, (b) PN junction diode, (c) various diodes such as PIN diode, (d) MIM (Metal-Insulator-Metal) structure, (e) SIS structure (Silicon-Insulator-Silicon) and the like. Also here, electrodes EL1 and EL2 for forming a barrier metal layer and an adhesive layer may be inserted. Further, when a diode is used, a unipolar operation can be performed due to its characteristics, and a bipolar operation can be performed in the case of an MIM structure, an SIS structure, or the like.

  Note that a three-dimensional structure can be obtained by stacking a plurality of the memory structures described above.

  FIG. 5 is a circuit diagram of the memory cell array 1 using the diode SD as the non-ohmic element NO and its peripheral circuits. Here, in order to simplify the description, the description will be made on the assumption that it has a single-layer structure.

  In FIG. 5, the anode of the diode SD constituting the memory cell MC is connected to the word line WL, and the cathode is connected to the bit line BL via the variable resistance element VR. One end of each bit line BL is connected to a selection circuit 2 a that is a part of the column control circuit 2. One end of each word line WR is connected to a selection circuit 3 a that is a part of the row control circuit 3.

  The selection circuit 2a includes a selection PMOS transistor QP0 and a selection NMOS transistor QN0 provided for each bit line BL and having a gate and a drain connected in common. The source of the selection PMOS transistor QP0 is connected to the high potential power supply Vcc. The source of the selection NMOS transistor QN0 is connected to a bit line side drive sense line BDS that applies a write pulse and flows a current to be detected when reading data. A common drain of the transistors QP0 and QN0 is connected to the bit line BL, and a bit line selection signal BSi for selecting each bit line BL is supplied to the common gate.

  The selection circuit 3a includes a selection PMOS transistor QP1 and a selection NMOS transistor QN1 provided for each word line WL and having a gate and a drain connected in common. The source of the selection PMOS transistor QP1 is connected to a word line side drive sense line WDS that applies a write pulse and flows a current to be detected when reading data. The source of the selection NMOS transistor QN1 is connected to the low potential power supply Vss. A common drain of the transistors QP1 and QN1 is connected to the word line WL, and a word line selection signal / WSi for selecting each word line WL is supplied to the common gate.

  In the above, an example suitable for individually selecting memory cells has been described. However, when data of a plurality of memory cells MC connected to the selected word line WL1 are read in a batch, each bit line BL0 is read. Sense amplifiers are individually arranged for .about.BL2, and each bit line BL0.about.BL2 is individually connected to the sense amplifier via the selection circuit 2a with a bit line selection signal BS.

  Further, in the memory cell array 1, the polarity of the diode SD may be reversed from that of the circuit shown in FIG. 5 so that a current flows from the bit line BL side to the word line WL side.

  FIG. 6 is a cross-sectional view of a nonvolatile memory including the above-described memory structure in one stage. On the silicon substrate 21 in which the well 22 is formed, an impurity diffusion layer 23 and a gate electrode 24 of a transistor constituting a peripheral circuit are formed. A first interlayer insulating film 25 is deposited thereon. Vias 26 reaching the surface of the silicon substrate 21 are appropriately formed in the first interlayer insulating film 25. On the first interlayer insulating film 25, a first metal 27 constituting the word line WL which is the first wiring of the memory cell array is formed of a low resistance metal such as W, for example. A barrier metal 28 is formed on the upper layer of the first metal 27. A barrier metal may be formed below the first metal 27. These barrier metals can be formed of Ti and / or TiN. A non-ohmic element 29 such as a diode is formed above the barrier metal 28. On the non-ohmic element 29, a first electrode 30, a variable resistance element 31, and a second electrode 32 are formed in this order. Thereby, the barrier metal 28 to the second electrode 32 are configured as the memory cell MC. A barrier metal may be inserted below the first electrode 30 and above the second electrode 32, or a barrier metal, an adhesive layer, or the like is inserted below the second electrode 32 and above the lower electrode. May be. Further, a stopper such as CMP may be inserted above the second electrode 32. A space between adjacent memory cells MC is filled with a second interlayer insulating film 34 and a third interlayer insulating film 35 (however, the second interlayer insulating film 34 is not shown in FIG. 6). . Further, a second metal 36 constituting a bit line BL that is a second wiring extending in a direction orthogonal to the word line WL is formed on each memory cell MC of the memory cell array. A fourth interlayer insulating film 37 and a metal wiring layer 38 are formed thereon, and a nonvolatile memory that is a resistance change type memory is formed. In order to realize a multilayer structure, the stacking from the barrier metal 28 to the second electrode 32 and the formation of the second and third interlayer insulating films 34 and 35 between the memory cells MC are repeated as many times as necessary. It ’s fine.

[Nonvolatile Memory Manufacturing Method]
Next, a method for manufacturing the nonvolatile memory according to this embodiment shown in FIG. 6 will be described. Here, in order to simplify the description, a case where there is one memory cell layer will be described.

  First, an FEOL (Front End Of Line) process for forming a transistor and the like constituting a necessary peripheral circuit is performed on the silicon substrate 21, and a first interlayer insulating film 25 is deposited thereon. The via 26 is also created here.

  Subsequently, the upper layer portion after the first metal 27 is formed.

  7 to 12 are perspective views showing the upper layer forming process in the order of steps. The upper layer forming process will be described with reference to FIGS.

  As described above, when the first interlayer insulating film 25 and the via 26 are formed, a layer 27a (first wiring material) to be the first metal 27 of the memory cell layer is deposited thereon, and then the memory cell material Formation of the layer 28a to be the barrier metal 28, deposition of the layer 29a to be the non-ohmic element 29, deposition of the layer 30a to be the first electrode 30, deposition of the layer 31a to be the variable resistance element 31, and the second electrode 32 The layer 32a to be formed is sequentially deposited. Through the above steps, the upper layer stack shown in FIG. 7 is formed.

  Subsequently, a hard mask such as TEOS (not shown) is formed on the upper surface of the stacked body, and first anisotropic etching is performed using the hard mask as a mask to form a first groove 41 along the word line WL as shown in FIG. To form a laminate.

  Subsequently, the second interlayer insulating film 34 is embedded in the trench 41. The material of the second interlayer insulating film 34 is preferably a material having good insulation, low capacitance, and good embedding characteristics. Thereafter, a planarization process by CMP or the like is performed, the excess second interlayer insulating film 34 is removed, and the second electrode 32 is exposed to form a block body. FIG. 9 shows the block body after the flattening process.

  Subsequently, a layer 36a (second wiring material) such as W, which becomes the second metal 36, is stacked on the planarized portion of the block body after CMP. The state after this step is shown in FIG.

  Subsequently, a second etching process is performed at L / S in the column direction. As a result, as shown in FIG. 11, the second groove 42 is formed along the bit line BL orthogonal to the word line WL, and at the same time, the memory cell is separated into a columnar shape at the cross point of the word line WL and the bit line BL. MC is formed in a self-aligning manner. Thereafter, by embedding the third interlayer insulating film 35 and planarizing the third interlayer insulating film 35, a cross-point type memory cell layer as shown in FIG. 12 can be formed.

  In this way, by performing the L / S patterning twice orthogonally to each other from the stacking of the solid films, a cross-point cell portion that does not deviate from the wiring is formed in a self-aligning manner.

  In addition, by repeating the formation of the above stacked structure, a multi-layered memory cell array can be formed.

As shown in FIG. 13, after the first etching process and before embedding the second interlayer insulating film 34, a protective film 51 can be formed with an oxide film on the first trench 41. Similarly, after the second etching process and before the third interlayer insulating film 35 is buried, a protective film can be formed from the participating film on the second trench 42. Here, as the oxide film, an oxide of a so-called rare earth element such as Cr, W, or V can be used. Also, Al ₂ O ₃ , CuO, SiO _{2 and the} like can be formed. By forming the protective film 51 in this way, the resistance value at the time of setting can be optimized, and the side wall leakage current of the metal oxide film can be reduced. In addition, data retention characteristics can be improved.

  In the case of the memory cell array manufactured by the above process, the memory cells in all the memory cell layers are non-ohmic elements such as wiring / barrier metal / diode / first electrode / variable resistance from the lower layer to the upper layer as shown in FIG. The device / second electrode / wiring is stacked in this order.

  When forming a memory cell layer, a process in which a large amount of heat is applied, such as film formation and formation of a protective film, is performed. For this reason, the lower the layer, the greater the influence of thermal history.

  According to the present embodiment, the variable resistance element VR is stacked above the non-ohmic element NO, thereby reducing the cross-sectional area of the variable resistance element VR. Therefore, the cell current can be reduced and the power consumption can be reduced. In addition, by stacking the non-ohmic element NO below the variable resistance element VR, the cross-sectional area of the non-ohmic element NO is increased, the forward current is increased, and the allowable maximum value of the current is increased. Can do. On the other hand, when the variable resistance element VR is stacked below the non-ohmic element NO, the cell current can be increased, and an increase in switching probability and durability can be expected. Furthermore, since the size of the diode is reduced, the reverse current of the diode can be reduced.

  As described above, according to the present embodiment, variation in characteristics between the layers of the variable resistance element VR and the non-ohmic element NO is reduced by making the stacking order of the memory cells of the semiconductor memory having the stacked structure the same. It is possible.

[Second Embodiment]
In the second embodiment of the present invention, a non-volatile memory having a stacked memory cell array in the case where the word lines WL or bit lines BL are shared by the memory cell arrays will be described.

  First, a method for manufacturing a nonvolatile memory according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 14, after the first interlayer insulating film 25 is formed, a resist pattern for the word line WL is formed by photolithography in order to form the word line WL by damascene wiring. Thereafter, oxide film etching is performed on the portion without the resist to form a first groove 141 extending in the row direction.

  Subsequently, as shown in FIG. 15, a wiring material to be the first metal 27 such as TiN or W is embedded in the formed first groove 141. Thereafter, the upper surfaces of the first interlayer insulating film 25 and the first metal 27 are planarized by CMP or the like. As a result, a word line WL extending in the row direction is formed.

  Subsequently, as shown in FIG. 16, on the upper surface of the first interlayer insulating film 25 and the first metal 27 planarized by the process of FIG. 15, a layer 28b serving as a barrier metal 28 as a memory cell material, a non-ohmic element A layer 29b to be 29, a layer 30b to be the first electrode 30, a layer 31b to be the variable resistance element 31, and a layer 32b to be the second electrode 32 are sequentially deposited. Here, the non-ohmic element 29 is a PN junction diode made of in-situ doped polysilicon (p-Si) and becoming a P-type semiconductor / N-type semiconductor from the lower layer to the upper layer.

  Subsequently, as shown in FIG. 17, photolithography is performed so that a memory cell is formed at a cross-point portion between the word line WL (first metal 27) and the bit line BL (second metal 36) to be formed later. Create a resist pattern. Thereafter, anisotropic etching is performed until the depth reaches the lower surface of the layer 28a to form columnar memory cells MC. Thereafter, a second interlayer insulating film 134 is stacked so as to cover the exposed first interlayer insulating film 25, the first metal 27, and the memory cell MC. Here, the second interlayer insulating film 134 is deposited higher from the upper surface of the second electrode 32 by the height of the bit line BL formed in a later step.

  Subsequently, as shown in FIG. 18, after depositing a second interlayer insulating film 134, a resist pattern for the bit line BL is formed by photolithography in order to form the bit line BL by damascene wiring. Thereafter, oxide film etching is performed on the portion where there is no resist to expose the upper surface of the second electrode 32. Thereby, the second groove 142 extending in the column direction is formed.

  Subsequently, as shown in FIG. 19, after the wiring material to be the second metal 36 such as TiN or W is embedded in the second trench 142, the upper surfaces of the second interlayer insulating film 134 and the second metal 36 are formed. Is planarized by CMP or the like. As a result, the bit line BL extending in the column direction is formed.

  As another formation method, after depositing the second interlayer insulating film 134, CMP is performed and planarization is performed once. At this time, a CMP stopper may be deposited on the upper electrode. Thereafter, an interlayer insulating film for forming a damascene wiring can be deposited, and lithography, bit line BL deposition, and CMP can be performed to form the bit line BL.

  Thereafter, the memory cell array having a stacked structure can be manufactured by repeating the steps of FIGS. 16 to 19. At this time, the etching direction of the metal wiring is alternately changed to the row direction / column direction, and the diode P The stacking order of the type semiconductor / N type semiconductor needs to be changed alternately.

  FIG. 20 is a sectional view in the column direction of a part of the memory cell array manufactured by the process as described above.

  As shown in FIG. 20, the memory cell MC formed at the cross point of the word line WLj and the bit line BLi has an electrode EL1, a diode composed of a P-type semiconductor / N-type semiconductor that is a non-ohmic element NO, and an electrode EL2 from the lower layer to the upper layer. The variable resistance element VR and the electrode EL3 are stacked in this order.

  On the other hand, the memory cell MC ′ formed at the cross point of the upper bit line BLi and the word line WLj + 1 is also a memory cell except that the diodes are stacked in the order of N-type semiconductor / P-type semiconductor from the lower layer to the upper layer. The stacking order is the same as MC. At this time, the upper and lower electrodes EL3 and EL2 of the variable resistance element VR can be similarly replaced.

  In this way, by reversing the P-type semiconductor / N-type semiconductor of the diode in the upper and lower layers, one wiring (see FIG. 2) is used in two adjacent memory cell layers without changing the stacking order of the basic memory cell layers. In the case of 20, the bit line BLi) can be shared.

  As a comparative example, FIG. 29 shows a cross-sectional view of a part of a memory cell array having a mirror structure centered on a word line WL or a bit line BL.

  In the case of FIG. 29, the memory cell MC formed at the cross point of the word line WLj and the bit line BLi is the same as that of the present embodiment shown in FIG.

  On the other hand, the stacking order of the memory cell MC ′ is completely opposite to that of the memory cell MC. That is, from the lower layer to the upper layer, the electrode EL3, the variable resistance element VR, the electrode EL2, the diode made of an N-type semiconductor / P-type semiconductor that is a non-ohmic element NO, and the electrode EL1.

  Usually, when the memory cell MC is formed by etching, the shape of the memory cell becomes a tapered shape in which the cross-sectional area gradually decreases from the lower layer to the upper layer.

  In that respect, according to the comparative example, the stacking order of the diodes and the variable resistance elements VR is reversed for each layer, so that the memory cell characteristics vary between the memory cell layers.

  However, according to the present embodiment, since the stacking order of the variable resistance element VR and the non-ohmic element such as a diode is the same in all the memory cell layers, the size of the memory cell becomes uniform, and the first embodiment Similar to the embodiment, variation in characteristics occurring between memory cell layers can be reduced. Here, when the variable resistance element VR is arranged in the upper layer, the cell current flowing at the time of switching can be reduced and the power consumption can be reduced due to the size dependency of the cell current during the set / reset operation. In addition, an increase in switching probability and an improvement in durability can be expected. In addition, even when the cell current is increased, the diode size is relatively large, so that the forward current of the diode can be increased, thereby increasing the current withstand voltage of the diode. On the other hand, when the variable resistance element VR is disposed in the lower layer, the cell current can be increased, and an increase in switching probability and durability can be expected. Furthermore, since the size of the diode is reduced, the reverse current of the diode can be reduced.

  Further, this effect can be obtained more prominently by positively forming the memory cell MC in a tapered shape as shown in FIG.

  In the above description, the variable resistance element is stacked on the upper layer of the non-ohmic element such as a diode. On the contrary, even if the non-ohmic element is stacked on the upper layer of the variable resistance element, the memory Variations in memory cell characteristics that occur between cell layers can be reduced. In this case, since the cross-sectional area of the variable resistance element is increased, the switching probability can be improved.

[Third Embodiment]
In the third embodiment of the present invention, a case where L / S processing is simultaneously performed on two memory cell layers by etching will be described. The nonvolatile memory process in this case is shown in FIGS.

  Until the layer 36a serving as the second metal 36 is stacked, the layer 33a serving as the stopper 33 is inserted between the layer 32a serving as the second electrode 32 and the layer 36a serving as the second metal 36. 7 is similar to FIGS. 7 to 10 of the process in the first embodiment. Here, the stopper 33 helps to detect the end point of CMP.

  Then, as shown in FIG. 22, on the upper surface of the layer 36a to be the second metal 36, the layer 28c to be the barrier metal 28 'of the memory cell MC' of the upper memory cell layer and the layer 29c to be the non-ohmic element 29 ' Then, a layer 30c to be the first electrode 30 ′, a layer 31c to be the variable resistance element 31 ′, a layer 32c to be the second electrode 32 ′, and a layer 33c to be the stopper 33 ′ are sequentially deposited.

  Subsequently, as shown in FIG. 23, the second etching process is performed up to the lower surface of the layer 28a to be the barrier metal 28 at L / S in the column direction. As a result, a second trench 242 is formed along the bit line BLi orthogonal to the word line WLj, and at the same time, the lower-layer memory cells MC separated in a columnar shape at the cross points of the word line WLj and the bit line BLi are self-aligned. Formed.

  Subsequently, as shown in FIG. 24, the third interlayer insulating film 235 is buried and the third interlayer insulating film 235 is planarized in the second trench 242.

  Subsequently, as shown in FIG. 25, a layer 27 c to be the third metal 27 ′ is deposited on the planarized layer 33 c and the upper surface of the third interlayer insulating film 235.

  Subsequently, as shown in FIG. 26, a third etching process is performed in the row direction so that the depth reaches the lower surface of the layer 28c. As a result, a third groove 243 is formed along the word line WLj + 1 orthogonal to the bit line BLi, and at the same time, the upper-layer memory cell MC ′ separated into a columnar shape at the cross point between the bit line BLi and the word line WLj + 1 is self-assembled. It is formed consistently.

  Finally, as shown in FIG. 27, the fourth interlayer insulating film 34 ′ is embedded in the third trench 243 and the fourth interlayer insulating film 34 ′ is planarized.

  Through the above process, a nonvolatile memory having two memory cell layers can be manufactured.

  Note that the processes after the deposition of the layer 27c to be the third metal 27 shown in FIG. 24 are the same as the deposition of the metal layer and the memory cell material, the anisotropic etching in the row direction, the deposition of the interlayer insulating film, the metal layer and the memory cell material. The memory cell array having a multi-layer structure can be manufactured by repeatedly performing the deposition, anisotropic etching in the column direction, and deposition of the interlayer insulating film.

  A cross-sectional view in the row direction of a part of the memory cell array manufactured by the above process is shown in FIG.

  In the memory cell array shown in FIG. 28, a lower layer memory cell MC is arranged at the cross point of the word line WLj and the bit line BLi, and an upper layer memory cell MC ′ is arranged at the cross point of the bit line BLi and the word line WLj + 1.

  The memory cell MC is stacked from the word line WLj to the bit line BLi in the order of an electrode EL1, a P-type semiconductor / N-type semiconductor that is a non-ohmic element NO, an electrode EL2, a variable resistance element VR, an electrode EL3, and a stopper ST. It has a structure.

  The memory cell MC ′ is stacked from the bit line BLi to the word line WLj + 1 in the order of an electrode EL1, an N-type semiconductor / P-type semiconductor that is a non-ohmic element NO, an electrode EL2, a variable resistance element VR, an electrode EL3, and a stopper ST. It has a structured.

  In the process shown in FIG. 22, since L / S processing is simultaneously performed for two layers, a taper shape in which the cross-sectional area continuously decreases from the lower surface of the memory cell MC to the upper surface of the memory cell MC ′.

  Even in this case, in all the memory cell layers, since the variable resistance element VR is stacked in an upper layer than the diode that is the non-ohmic element NO, the sectional area of the diode is larger than the sectional area of the variable resistance element VR. Become. As a result, the current flowing through the variable resistance element VR is small, power consumption can be reduced, and the maximum value of the forward current that can flow through the diode can be increased.

  Further, in the above process, since the L / S processing is performed for every two layers, there is a possibility that the characteristics of the odd-numbered memory cell layer and the even-numbered memory cell layer may be different. Variations in memory cell characteristics between memory cell layers or between odd-numbered memory cell layers can be reduced.

  Further, similarly to the above embodiment, when the variable resistance element VR is arranged in the upper layer, the cell current flowing at the time of switching can be reduced and the power consumption can be reduced due to the size dependency of the cell current at the time of the set / reset operation. Can do. In addition, an increase in switching probability and an improvement in durability can be expected. In addition, even when the cell current is increased, the diode size is relatively large, so that the forward current of the diode can be increased, thereby increasing the current withstand voltage of the diode. On the other hand, when the variable resistance element VR is disposed in the lower layer, the cell current can be increased, and an increase in switching probability and durability can be expected. Furthermore, since the size of the diode is reduced, the reverse current of the diode can be reduced.

[Others]
Note that the present invention is not limited to the memory cell including the variable resistance element and the diode as described above, but a memory having various cross-point type multilayer structures such as a phase change memory element, an MRAM element, and a PFRAM. Applicable to the device.

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Column control circuit, 2a ... Selection circuit, 3 ... Row control circuit, 3a ... Selection circuit, 4 ... Data input / output buffer, 5 ... Address register, 6 ... command interface, 7 ... state machine, 9 ... pulse generator, 11, 13 ... electrode layer, 12 ... recording layer, 14 ... metal layer, 21 ... ..Silicon substrate, 22 ... well, 23 ... impurity diffusion layer, 24 ... gate electrode, 25 ... first interlayer insulating film, 26 ... via, 27, 36 ... metal, 28 ... Barrier metal, 29 ... Non-ohmic element, 30, 32 ... Electrode, 31 ... Variable resistance element, 34, 35, 37, 134, 235 ... Interlayer insulating film, 38 ... Metal wiring layer 41, 42, 141, 14 , 242, 243 ... groove, 51 ... protective layer.

Claims (5)

A memory cell array comprising a plurality of memory cell layers having a plurality of first and second wirings intersecting each other and memory cells provided at each intersection of the plurality of first and second wirings,
The memory cell includes a variable resistance element and a non-ohmic element stacked in the stacking direction of the memory cell array,
The stacking order of the variable resistance element and the non-ohmic element of the first memory cell that is the memory cell of the predetermined memory cell layer, and the variable resistance of the second memory cell that is the memory cell of the other memory cell layer stacking order of elements and the non-ohmic element Ri same der,
The first and second memory cells have a tapered shape in which a cross-sectional area gradually decreases from a lower layer to an upper layer of the memory cell array,
A non-volatile semiconductor memory device, wherein the first and second memory cells have a uniform size . The nonvolatile semiconductor memory device according to claim 1, wherein the first or second wiring is shared by two memory cell layers adjacent in the stacking direction. The non-ohmic element is a diode including a P-type semiconductor and an N-type semiconductor stacked in the stacking direction of the memory cell array,
3. The nonvolatile semiconductor memory device according to claim 2, wherein a predetermined stacking order of the P-type semiconductor and the N-type semiconductor is reversed between the predetermined diode in the memory cell layer and the adjacent diode in the memory cell layer. . 4. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell is stacked in the order of the non-ohmic element and the variable resistance element from a lower layer to an upper layer of the memory cell array. . 4. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell is stacked in order of the variable resistance element and the non-ohmic element from a lower layer to an upper layer of the memory cell array. .

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