JP5277500B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor memory device having a two-terminal structure using SiC.

  In recent years, semiconductor memory devices have been used in various fields as information storage devices. As a conventional semiconductor memory device, a flash memory, a RAM, a ROM, or the like is used, which is a three-terminal memory that requires three electrodes for control. In recent years, a two-terminal memory that can be controlled by two electrodes is expected in accordance with a request for expansion of stored information. Since the number of electrodes of the two-terminal memory is smaller than that of the three-terminal memory, the occupied area per memory on the circuit board is reduced. Therefore, the number of memories per unit area of the circuit board can be increased, and the amount of information per area, that is, the stored information density can be increased. This makes it possible to manufacture a storage device with a large amount of information that can be handled on a small-sized substrate.

As a two-terminal memory, Suda et al. Reported a nonvolatile resistance change type memory using SiC (see Non-Patent Document 1). As shown in FIG. 14, the two-terminal memory 100 includes a SiC layer 102 formed on an n-type Si substrate 101, a Si oxide layer 103 formed on the SiC layer 102, and a back surface of the n-type Si substrate 101. The pair of electrodes 104 and 105 are formed on the surface of the Si oxide layer 103. The Si oxide layer 103 is formed by thermally oxidizing the upper part of the SiC layer 102 at 1000 ° C., whereby C is removed as CO or CO ₂ by the ingress of oxygen (O), and the remaining Si is combined with oxygen (O). Formed. The SiC on the Si substrate 101 side remains as SiC without being oxidized.

The general operation of the two-terminal memory 100 will be described. Since the oxidation temperature of the Si oxide layer 103 is as low as 1000 ° C., the complete oxide SiO ₂ and the incomplete oxide SiOx (x <2) are mixed. Since this Si oxide was formed through the process of removing SiC from SiC, Si having dangling bonds not bonded to other atoms exists as crystal defects when the temperature is low. Emits electrons and remains as positively charged Si ⁺ . Therefore, such a donor type defect exists in the Si oxide region and the interface between the Si oxide and SiC. In particular, many donor type defects exist at the interface between the Si oxide and SiC.

  When a voltage is applied between the electrodes 104 and 105 so that the Si oxide layer 103 side is positive, the applied voltage is mainly applied to the Si oxide layer 103 and the SiC layer 102 because the resistance of the Si substrate 101 is low. Take it. However, since the Si oxide layer 103 becomes a barrier, almost no current flows. That is, the entire memory device is in a state of high resistance (OFF state).

The band gap of Si is 1.1 eV, and the band gap of SiC is 2.3 eV in the case of a cubic structure. When the voltage is further increased, there is a band gap difference between the SiC layer 102 and the Si substrate 101. Therefore, when a certain voltage is exceeded, electrons are injected from the Si substrate 101 to the SiC layer 102 side, and Si oxide and SiC Electrons are trapped by Si ⁺ , which is a donor-type defect, which is present at a large amount at the interface. At this time, it is difficult to apply a voltage from the Si substrate 101 to the region where the electrons are captured, a strong electric field is generated in the Si oxide having a small amount of electron capture, and electrons tunnel through the Si oxide layer 103 so that a current is generated. Flowing. Therefore, the resistance of the entire memory device is reduced (ON state).

  Transition from the OFF state to the ON state corresponds to writing of information “1”.

When a voltage is applied between the electrodes 104 and 105 so that the Si oxide layer 103 side is negative when the memory device is in the ON state, the electrons remain secured in the donor-type defect Si ⁺ , so the voltage is mainly The Si oxide is applied, and then electrons tunnel through the Si oxide layer 103 and a current flows. However, when a more negative voltage is applied to the Si oxide layer 103, the trapped electrons are emitted and become Si ⁺ , and the electrons are returned to the Si substrate 101 side. Therefore, the voltage is applied to both Si oxide and SiC again. As a result, the electric field of the Si oxide is weakened, so that electrons cannot tunnel through the Si oxide layer 103 and are turned off.

  Transition from the ON state to the OFF state corresponds to erasure of information or writing of information “0”.

That is, this memory operation utilizes donor type defects formed in the Si oxide. When electrons are trapped by Si-type oxide and donor-type defects Si ⁺ generated at the interface between Si oxide and SiC, they are turned on, and when electrons are emitted from donor-type defects, they are turned off. Therefore, it is possible to correspond to a memory operation in which the ON state is stored as a logical value “1” and the OFF state is stored as a logical value “0”.

  If the voltage applied to the Si oxide is sufficiently increased to the plus side, it can be changed from the OFF state to the ON state, and conversely if it is sufficiently increased to the minus side, the ON state can be changed to the OFF state. Further, by checking whether a current flows at a low voltage or not, it is possible to read “0 (OFF state)” or “1 (ON state)” which is a stored value of the memory device.

K.Takada, M.Fukumoto, Y.Suda, “Memory Function of a SiO2 / β-SiC / Si MISDiod” Ext. Abs. 1999 Intrenational Conference on Solid State and Materials, p.132-133 (1999)

In a conventional memory device having a Si oxide / SiC / Si substrate structure, SiC is formed by low-temperature oxidation at 1000 ° C., so that a large amount of SiOx exists in addition to SiO ₂ in the Si oxide. Since the SiOx ratio of this Si oxide exceeds 10%, donor-type defects are distributed throughout the Si oxide, and once electrons are trapped by these defects, the voltage on the Si oxide side becomes negative. Even if it is sufficiently large, a phenomenon occurs in which electrons are not emitted from the defect, and as a result, it does not operate as a memory. For use as memory, ON depending on the application, since the repetitive operation of the OFF is needed more than 10 ⁴ times, electron trapping in Si ^+, release is necessary structure becomes easy.

On the other hand, the present inventors have previously formed a SiO ₂ / SiO _{2 layer} formed by two-stage oxidation in which a SiC layer is laminated on an n-type Si substrate by CVD and thermal oxidation at 1200 ° C. followed by thermal oxidation at 1000 ° C. A two-terminal memory device having a Six / SiC / n-Si structure has been proposed. In this manufacturing method, a SiO ₂ layer is formed on the surface of the SiC layer by thermal oxidation at 1200 ° C. in the first stage, and a SiO x layer is formed on the surface of the SiC layer below the SiO ₂ layer by thermal oxidation at 1000 ° C. in the second stage. The The memory device as SiO ₂ layer tunnel layer of the electron, SiOx layer functions respectively as the trapping layer of the electron, ON, repeated operation of the OFF is obtained more than 10 ⁴ times.

  By the way, in order to operate the memory device, it is configured as a semiconductor integrated circuit on which a drive circuit such as a MOS transistor is mounted in order to control voltage and write, read and erase information.

  In recent years, as the element structure of a semiconductor integrated circuit becomes finer and more complicated, the manufacturing process temperature tends to be lowered more and more, for example, manufactured at a low temperature of 850 ° C. to 950 ° C. A semiconductor device formed by two-stage thermal oxidation at 1200 ° C. and 1000 ° C. cannot be mounted on a semiconductor integrated circuit using such a low temperature process.

Further, even when the SiO ₂ layer and the SiO x layer are formed by two-step thermal oxidation, as described later, since SiO x is distributed also in the SiO ₂ layer, it is possible to completely release trapped electrons at the time of erasing. In some cases, trapped electrons may remain. For this reason, complete OFF cannot be obtained, and the ON / OFF ratio may be reduced.

An object of the present invention is to provide a method for manufacturing a semiconductor memory device with an improved ON / OFF ratio in view of the above points.
It is another object of the present invention to provide a method for manufacturing a semiconductor memory device that can improve the ON / OFF ratio and can be manufactured by a low-temperature process.

The method of manufacturing a semiconductor memory device according to a first aspect of the present invention includes the steps of laminating sequentially SiC layer and the Si layer on a Si substrate, a thermal oxidation process by a predetermined temperature of the first stage, SiO ₂ layers of stacked Si layer And an SiO ₂ layer / SiO x layer / SiC layer / Si substrate structure is formed by changing the vicinity of the interface in contact with the laminated Si layer to the SiO x layer.

  A method for manufacturing a semiconductor memory device according to a second aspect of the present invention is characterized in that, in the above manufacturing method, the predetermined temperature is set in a range of 950 ° C. to 800 ° C.

In the first aspect of the present invention, a SiC layer and a Si layer are sequentially laminated on a Si substrate, and the vicinity of the interface between the Si layer laminated by thermal oxidation treatment at a predetermined temperature in one step and the Si layer where the SiC layer is laminated are simultaneously formed. It is oxidized. At this time, since changing the stacked Si layer SiO ₂ layer, a tunnel layer by layer of SiO ₂ complete oxidation is formed. Further, since the interface in contact with the Si layer on which the SiC layer is laminated is changed to an incompletely oxidized SiOx layer, an electron trapping layer having a high SiOx ratio is formed.

In the second aspect of the present invention, the SiO ₂ layer / SiOx layer / SiC layer / Si substrate structure is formed by a low temperature process by setting the temperature of the one-stage thermal oxidation treatment within a range of 800 ° C. to 950 ° C. can do.

According to the method of manufacturing a semiconductor memory device of the first aspect of the present invention, a SiO ₂ layer / SiO x layer / SiC layer having a tunnel layer formed by a completely oxidized SiO ₂ layer and an incompletely oxidized SiO x layer having a large proportion of SiO x / Si substrate structure can be formed. As a result, a semiconductor memory device having an improved ON / OFF ratio can be manufactured.

  According to the method of manufacturing a semiconductor memory device of the second aspect of the present invention, the ON / OFF ratio is improved and the temperature is lowered by setting the temperature during the thermal oxidation process within the range of 800 ° C. to 950 ° C. Enable manufacturing in process.

  Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment]
First, FIG. 1 shows an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device 1 according to the present embodiment is formed by sequentially forming a SiC layer 3, a SiOx layer 4 and a SiO ₂ layer 5 on a Si substrate 2. One electrode 6 is formed on the back surface of the Si substrate 2, and the other electrode 7 is formed on the surface of the SiO ₂ layer 5. The semiconductor memory device 1 is a two-terminal memory and is configured as a nonvolatile resistance change memory.

The SiO ₂ layer 5 is formed as a fully oxidized electron tunnel layer. SiOx layer 4 is formed as an electron trapping layer of incomplete oxidation of some SiO ₂ are mixed. The film thickness t ₁ of the SiO ₂ layer 5 can be 2 nm to 20 nm, preferably 3 nm to 15 nm, for example 5 nm. When the film thickness t ₁ is less than 2 nm, trapped electrons are lost, and when it exceeds 20 nm, current hardly flows. Thickness _{t 2} of the SiOx layer 4 is thinner than the thickness of the SiO ₂ layer 5 can be 1 nm to 10 nm, for example, 3 nm. And the thickness t ₂ becomes less thin and trapped electron number than 1 nm, the memory device is sufficiently longer turned ON, it is not possible to release completely trapped electrons upon erasure exceeds 10 nm, it remains trapped electrons There is a case.

The Si substrate 2 is formed of an n-type Si substrate doped with an n-type impurity, for example, with the plane orientation of the main surface being the (100) plane. This n-type Si substrate functions as an electron supply source. When an n-type Si substrate having a high electron concentration is used, memory operation can be efficiently expressed. When the semiconductor memory device of the present invention is integrated together with a bipolar transistor or the like, a SiC layer is formed on a p-type Si substrate, and n-type Si is brought into contact with the p-type Si substrate. Thus, it is possible to supply electrons from the n-type Si to the SiC layer side through the p-type Si substrate. Further, since the amount of Si ⁺ defects is controlled in the SiOx layer 4 and at the interface between the SiOx layer 4 and the SiC layer 3, the SiC layer 3 itself formed on the Si substrate 2 has fewer defects and higher crystallinity. Is good. Alternatively, if there are few defects, the SiC layer may have a polycrystalline structure.

  When the plane orientation of the Si substrate 2 is the (100) plane, this memory is suitable for incorporation into a semiconductor integrated circuit. Usually, in a semiconductor integrated circuit having a MOS transistor or the like, a substrate having a (100) plane orientation of the main surface is used as the semiconductor substrate. Therefore, the Si substrate 2 of the memory device 1 has the same (100) plane. It is preferable to use a certain substrate. When a (100) plane substrate is used, the SiC layer 3 having high crystallinity can be formed to such an extent that good memory characteristics can be obtained.

  As the Si substrate 2, it is also possible to use a substrate whose main surface has another plane orientation. For example, a Si substrate having a (111) plane as the main surface can be used, and if it is the (111) plane, the SiC layer 3 having higher crystallinity can be formed.

The electrodes 6 and 7 can be formed of a metal film. The electrode 7 on the surface of the SiO ₂ layer 5 is preferably made of a metal having a high work function, such as Ni, Pt, or Au, and is formed of Au in this example. The electrode 6 on the back surface of the Si substrate 2 may be any metal as long as it is a conductor capable of obtaining ohmic contact with Si, and is formed of Al in this example.

[Description of operating principle]
The operation principle of the semiconductor memory device 1 according to the present embodiment will be described with reference to the energy band diagrams of FIGS. First, FIG. 2A shows a state in which no voltage is applied between the electrodes 6 and 7, and the memory device 1 is in an OFF state. That is, in this state, the trap level (donor type defect) 10 exists at the SiOx layer 4 and the interface between the SiOx layer 4 and the SiC layer 3. The trap level 10 is schematically illustrated as a square region.

Next, as shown in FIG. 2B, when a positive voltage is applied between the electrodes 6 and 7 so that the electrode 7 side on the surface of the SiO ₂ layer 5 is positive, the resistance of the Si substrate 2 is low. The applied voltage is mainly applied to the Si oxide layer including the SiO ₂ layer 5 and the SiOx layer 4 and the SiC layer 3. However, the voltage applied to the Si oxide layer (4, 5) is insufficient, and the Si oxide layer (4, 5) acts as a barrier so that almost no current flows. The memory device 1 as a whole is in a high resistance state and in an OFF state.

Next, as shown in FIG. 2C, when the positive voltage is further increased, there is a band gap difference between the SiC layer 3 and the Si substrate 2 as described above. e is trapped at the interface between the SiC layer 3 and the SiOx layer 4 and the trap level 10 in the SiOx layer 4. Thereby, the energy band of SiC layer 3 becomes flat (not completely flat but close to flat), and voltage is not applied to SiC layer 3 very much. Accordingly, much voltage is applied to the fully oxidized SiO ₂ layer 5 without electron capture. Therefore, a strong electric field is generated in the SiO ₂ layer 5, electrons e flow current increases the probability of tunneling of the SiO ₂ layer 5. As a result, the entire memory device 1 is brought into a low resistance state and turned on.
Transition from the OFF state to the ON state corresponds to writing of information “1”.

Next, as shown in FIG. 3D, when the memory device 1 is in the ON state, a negative voltage is applied between the electrodes 6 and 7 so that the electrode 7 side on the surface of the SiO ₂ layer 5 is negative. At this time, since the electrons e remain trapped in the trap level 10, the voltage is applied mainly to the SiO ₂ layer 5 and current continues to flow. It is in the ON state.

However, as shown in FIG. 3E, when the negative voltage is further increased, the trapped electrons e are emitted, and the electrons e are returned to the Si substrate 2 side. Again, a voltage is distributed and applied to both SiC layer 3 and SiO ₂ layer 5. As a result, the electric field of the SiO ₂ layer 5 is weakened, and the electrons e cannot tunnel through the SiO ₂ layer 5, that is, the tunnel probability is reduced, and almost no current flows. The entire memory device 1 is in a high resistance state and is in an OFF state.
Transition from the ON state to the OFF state corresponds to erasure of information or writing of information “0”.

[Manufacturing Method of Embodiment]
An embodiment of a method for manufacturing the semiconductor memory device 1 will be described with reference to FIG.
First, as shown in FIG. 4A, for example, an n-type Si substrate 2 having a (100) plane orientation of the main surface and doped with an n-type impurity is prepared. The n-type Si substrate 2 of this example is a Si substrate having a specific resistance of 0.01 Ω-cm.

  Next, as shown in FIG. 4B, the SiC layer 3 is formed on the n-type Si substrate 2 by a CVD (chemical vapor deposition) method or a sputtering method. The SiC layer 3 is, for example, SiC (3C—SiC) having a cubic symmetry as a crystal structure. Hexagonally symmetric 4H—SiC or 6H—SiC may be used. Further, it may be polycrystalline or amorphous with few defects, for example, dangling bonds terminated with hydrogen. The SiC layer 3 may be either doped or not doped with impurities. In this example, an intrinsic (i-type) SiC layer not doped with impurities is used. The p-type doped SiC layer 3 may be formed on the n-type Si substrate 2. A heterojunction is formed between the Si substrate 2 and the SiC layer 3.

  Next, as shown in FIG. 4C, a Si layer 11 is formed on the SiC layer 3 by using a single crystal growth method. For example, the Si layer 11 is grown by GS-MBE (gas source molecular beam epitaxy) method, CVD (chemical vapor deposition) method or sputtering method. The Si layer 11 is preferably a single crystal layer. However, since the crystal state of the Si layer 11 is influenced by the crystallinity of the underlying SiC layer 3, it may not be a single crystal depending on the crystallinity of the SiC layer 3. The film thickness t3 of the Si layer 11 can be in the range of 1 nm to 10 nm, preferably 1.5 nm to 7.5 nm, and is 2.5 nm in this example.

Next, as shown in FIG. 4D, a one-step low-temperature thermal oxidation treatment is performed to change the Si layer 11 into a fully oxidized SiO ₂ layer 5 and the interface between the SiC layer 3 and the Si layer 11 is incompletely oxidized. The SiOx layer 4 is changed. As the thermal oxidation treatment, dry oxidation treatment is used. Further, the thermal oxidation treatment is performed in an atmospheric pressure (1 atm) with 100% oxygen. The term “low temperature” as used herein means that when a semiconductor device, for example, a MOS transistor is mounted together with the memory device of the present embodiment, the semiconductor element, for example, the MOS transistor is not thermally affected. Temperature. The temperature of this one-stage thermal oxidation treatment is preferably 800 ° C. to 950 ° C. When the temperature is lower than 850 ° C., it takes too much oxidation time. Therefore, the thermal oxidation temperature is more preferably in the range of 850 ° C. to 950 ° C. in consideration of practical use.

Since the SiO ₂ layer 5 formed by thermally oxidizing the Si layer 11 has a film thickness approximately twice that of the Si layer 11, the thickness t ₁ of the SiO ₂ layer 5 is preferably ₂ nm to ₂₀ nm. Can be in the range of 3 nm to 15 nm, and is 5 nm in this example. As the thickness _{t 2} of the SiOx layer 4 can be within the range of 1 nm to 10 nm, in this example is set to 3 nm.

Here, the relationship between the thermal oxidation temperature and the thermal oxidation time when forming the SiO ₂ layer 5 of 5 nm and forming the SiO x layer 4 of 3 nm, for example, by one-step thermal oxidation treatment is shown. About 22 minutes at 950 ° C. About 48 minutes at 900 ° C. It takes about 1 hour 49 minutes at 850 ° C. It takes about 4 hours and 43 minutes at 800 ° C.

Next, as shown in FIG. 4E, for example, an Au electrode 7 is formed on the surface of the SiO ₂ layer 5 and an Al electrode 6 is formed on the back surface of the Si substrate to obtain the target semiconductor memory device 1.

[Example of semiconductor integrated device with this memory device]
FIG. 13 shows an example of a semiconductor integrated device in which this memory device and other transistors are integrated. In the semiconductor integrated device 21 according to the present embodiment, for example, a p-type silicon semiconductor substrate 22 is used as a silicon substrate. An n-type semiconductor well region 23 is formed on the substrate 22 by impurity doping. Further, a p ⁺ type semiconductor well region 24 and an n ⁺ type semiconductor well region 25 doped with impurities at a high concentration are formed. Further, the element isolation region 41 is formed. The element isolation region can be formed of a buried insulating film, for example.

The n-type semiconductor well region 23, the p ⁺ -type semiconductor well region 24, and the n ⁺ -type semiconductor well region 25 constitute a bipolar transistor 26. Each semiconductor well region 23, 24, 25 functions as a collector, a base, and an emitter.

On the other hand, a p-channel MOS transistor 27 is also configured. The n semiconductor well region 23 functions as a channel layer, and the p ⁺ type semiconductor well region 24 functions as a source region 29 and a drain region 30.

After forming and patterning the gate insulating film 31, a window is opened in the gate insulating film 31. In other regions, the SiC layer 3 and the Si layer are selectively formed on the p ⁺ type semiconductor well region 24 facing the window by the CVD method. The film forming temperature at this time is 850 ° C.

Next, one-step thermal oxidation treatment is performed at a low temperature of 800 ° C. to 950 ° C. to change the stacked Si layer to the SiO ₂ layer 5 and change the interface region between the SiC layer 3 and the Si layer to the SiO x layer 4. Next, using the interlayer insulating film 32, electrodes are formed on the SiO ₂ layer 5 of the memory device 1, the n ⁺ type semiconductor well region 25 serving as the emitter of the bipolar transistor 26, the source region 29 and the drain region 30 of the MOS transistor 27, respectively. Form. That is, the electrode 33 is formed on the SiO ₂ layer 5 of the memory device 1. An emitter electrode 34 is formed in the emitter region 25. A source electrode 36 is formed in the source region 29, a drain electrode 37 is formed in the drain region 30, and a gate electrode 38 is formed in the gate insulating film 31. In addition, a base electrode 35 is formed in the p ⁺ type semiconductor well region 24 serving as a base region.

Further, although not shown, a multilayer wiring structure is formed on the interlayer insulating layer 32, and these elements (memory device 1, bipolar transistor 26, p-channel MOS transistor 27) are connected. The memory device 1 is connected to a p ⁺ type semiconductor well region 24 that serves as a base of the bipolar transistor 26. In this memory device 1, when a positive voltage is applied to the SiO ₂ layer 5 side via the electrode 33 to write data, electrons are emitted from the emitter region 25 via the p ⁺ type semiconductor well region 24 serving as a base. Supplied.

  Unlike this example, depending on the configuration of the integrated circuit, the SiC layer 3 of the memory device 1 of the present embodiment may be formed on the n-type semiconductor well region 23. In this manner, the semiconductor integrated device 21 in which the memory device 1 of the present embodiment and the bipolar transistor 26 and the MOS transistor 27 are integrated is manufactured.

  Next, the semiconductor memory device obtained by the one-step thermal oxidation according to this embodiment is compared with the semiconductor memory device obtained by the two-step thermal oxidation of the comparative example, and the superiority of this embodiment is shown. explain.

[Comparative example]
9 to 12 show comparative examples of two-stage thermal oxidation. As shown in the schematic diagram of FIG. 9, an SiC layer 23 is formed on an n-type Si substrate 22 (A in FIG. 9). Next, two-stage thermal oxidation is performed on the SiC layer 23 after thermal oxidation at 1200 ° C. and thermal oxidation at 1000 ° C. That is, the SiO ₂ layer 25 is formed on the surface of the SiC layer 23 by one-step thermal oxidation at 1200 ° C., and the SiOx layer 24 is formed at the interface between the SiC layer 23 and the SiO ₂ layer 25 by two-step thermal oxidation at 1000 ° C. (Fig. B). FIG. 11 shows a composition distribution in the substrate depth direction in 1000 ° C. thermal oxidation, and FIG. 12 shows a composition distribution in the substrate depth direction in 1200 ° C. thermal oxidation. Based on the composition distributions of FIGS. 11 and 12, the proportions of the structures of the oxides SiO ₂ and SiOx when the SiC layer 23 is thermally oxidized in two stages are schematically shown in FIGS. Finally, as shown in FIG. 10C, the SiO ₂ layer 25 is not completely oxidized, and some SiOx is mixed. Also in SiOx layer 24, a small proportion of the proportion of SiO ₂ is much SiOx.

[This embodiment]
5 to 7 show an embodiment of one-stage thermal oxidation. As shown in the schematic diagram of FIG. 5, the SiC layer 3 and the Si layer 11 are laminated on the n-type Si substrate 2 (A in FIG. 5). Next, one-step heat treatment is performed on the Si layer 11 and the SiC layer 3. In this example, the Si layer 11 is completely oxidized by one-step thermal oxidation at 950 ° C. to form the SiO ₂ layer 5, and the SiC layer 3 is incompletely oxidized to form the SiO x layer 4. Then, an Au electrode 7 is formed on the surface of the SiO ₂ layer, and an Al electrode 6 is formed on the back surface of the n-type Si substrate 2 (FIG. B). FIGS. 6A and 6B schematically show the composition ratios of the oxides SiO ₂ and SiOx when this one-step thermal oxidation is performed. Finally, as shown in FIG. 6B, the proportion of SiO ₂ in the SiO ₂ layer 5 increases, and a nearly complete SiO ₂ layer is obtained. The ratio of SiOx in the interface region (corresponding to the SiOx layer 4) of the SiC layer 3 is increased. An increase in the capture defect density in the SiOx layer 4 is observed. Further, defects in the SiO ₂ layer 5 are reduced more than defects in the SiO ₂ layer formed by oxidizing the SiC layer. Since the SiO ₂ layer 5 is formed by thermally oxidizing the Si layer 11, the film quality is dense and high quality compared to the deposited SiO ₂ .

The solid line (a) in FIG. 7 uses the substrate structure of the Si / SiC / 0.01 Ω-cm n-Si (100) plane, and this embodiment is manufactured by one-step thermal oxidation at 950 ° C. for 30 minutes. The IV characteristic of the memory device 1 is shown.
This embodiment manufactured by one-step thermal oxidation at 850 ° C. for 120 minutes using the substrate structure of the Si / SiC / 0.01Ω-cm n-Si (100) surface in the broken line (b) of FIG. The IV characteristic of the memory device 1 is shown.
Hysteresis, which is a memory characteristic, appears in the I-V characteristic and shows good characteristics.

  FIG. 8 shows the relationship between the number of erase / write operations and the ON / OFF current ratio when the memory device 1 of the present embodiment and the memory device of the comparative example are compared. Line a is a characteristic of the memory device of this embodiment in which Si / SiC is thermally oxidized at 950 ° C. in one step. Line b is a characteristic of the memory device of the comparative example in which SiC is thermally oxidized in two stages at 1200 ° C. and 1000 ° C. Line c is the characteristic of the memory device of the comparative example in which SiC is thermally oxidized at 1000 ° C. in one step.

As apparent from FIG. 8, the memory device (line a) obtained by thermally oxidizing Si / SiC in this embodiment at 950 ° C. in one step is a memory device obtained by thermally oxidizing SiC in two steps. from (line b), improved ON / OFF ratio, 10 ⁴ or more rewriting count is obtained. This is presumably because the film quality of the SiO ₂ layer 5 is improved, the electron tunnel layer and the electron capture layer are effectively separated, the captured electrons are easily removed, and the repetition characteristics are improved. In the comparative example (line c), the ON / OFF ratio decreases and the number of rewrites is as low as about 10 ³ or less.

According to the manufacturing method of the present embodiment described above, it is possible to form a SiO ₂ layer / SiO x layer / SiC layer / Si substrate structure by one-step low-temperature thermal oxidation treatment of Si / SiC. Then, a completely oxidized SiO2 layer is formed, and an incompletely oxidized SiOx layer having a large proportion of SiOx is formed. Therefore, the ON / OFF ratio is improved and the number of practical rewrites is improved compared to the manufacturing method in which two-step thermal oxidation is performed. A two-terminal semiconductor memory device can be manufactured. In addition, since such a semiconductor memory device can be manufactured by low-temperature thermal oxidation, integration with, for example, a MOS transistor formed by a low-temperature process that constitutes a memory drive circuit becomes possible. Therefore, a low-temperature process semiconductor integrated device incorporating this type of semiconductor memory device can be manufactured.

In the present embodiment, when performing thermal oxidation, dry oxidation is preferable because finer and higher quality oxidation can be obtained than wet oxidation and the film quality of the SiO ₂ layer 5 is improved. Furthermore, when performed in 100% oxygen at atmospheric pressure, a dense oxide film having a higher oxidation rate than oxidation under reduced pressure can be obtained.

1 is a configuration diagram showing an embodiment of a semiconductor memory device according to the present invention. (A)-(c) It is an energy band figure (the 1) which shows the operation | movement principle of the semiconductor memory device based on this invention. (D)-(e) It is an energy band figure (the 2) which shows the operation | movement principle of the semiconductor memory device based on this invention. A to E are manufacturing process diagrams showing an embodiment of a method of manufacturing a semiconductor memory device according to the present invention. A to B are schematic views of a memory device obtained by the manufacturing method of the present embodiment. It is a schematic diagram of the order of the process which shows the ratio of the structure of AB. It is an IV characteristic view of the semiconductor memory device according to the present embodiment. 6 is a graph showing the relationship between the ON / OFF current ratio and the number of erase / write operations, comparing the semiconductor memory device according to the present embodiment and the semiconductor memory device according to the comparative example. It is a schematic diagram of the memory device obtained by the manufacturing method of AB comparative example. It is a schematic diagram of the order of the process which shows the ratio of the structure of the comparative example by AC two-step thermal oxidation. It is a composition distribution map which shows the composition distribution of the depth direction when a SiC layer is thermally oxidized at 1000 degreeC. It is a composition distribution map which shows the composition distribution of the depth direction when a SiC layer is thermally oxidized at 1200 degreeC. 1 is a schematic configuration diagram showing an embodiment of a semiconductor integrated device on which a semiconductor memory device according to the present invention is mounted. It is a block diagram which shows the example of the conventional non-volatile resistance change memory.

Explanation of symbols

1 .. Semiconductor memory device, 2 .. n-type Si substrate, 3 .. SiC layer, 4 .. SiOx layer, 5 .. SiO ₂ layer, 6, 7.

Claims (6)

Sequentially stacking a SiC layer and a Si layer on a Si substrate;
The step of changing the laminated Si layer to a SiO ₂ layer and changing the vicinity of the interface of the SiC layer in contact with the laminated Si layer to a SiOx layer by thermal oxidation treatment at a predetermined temperature in one step,
A method of manufacturing a semiconductor memory device, comprising: forming a SiO 2 layer / SiO x layer / SiC layer / Si substrate structure. The method of manufacturing a semiconductor memory device according to claim 1, wherein the predetermined temperature is set within a range of 950 ° C. to 800 ° C. The method for manufacturing a semiconductor memory device according to claim 1, wherein a dry oxidation process is used as the thermal oxidation process. The method of manufacturing a semiconductor memory device according to claim 1, wherein the oxidation treatment is performed in an atmospheric pressure of 100% oxygen. The method of manufacturing a semiconductor memory device according to claim 1, wherein an underlying Si substrate on which the SiC layer is formed is n-type. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the underlying Si substrate on which the SiC layer is formed is p-type, and the p-type Si substrate is in contact with the n-type.

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