JP5273828B2 - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the scale of hardware to be used by an FIFO or the like is increased in the case of trying to achieve data transfer by byte units. <P>SOLUTION: A byte enable holding circuit 10 for write is configured to hold the byte enable of data written in the latest write address of an FIFO 40, and a byte enable holding circuit 20 for read is configured to hold the byte enable of write data before one timing or the logical sum of the byte enable and self-holding content before one timing or self-holding content before one timing. A byte reading determination flag 50 indicates the presence/absence of full byte reading for one word of the FIFO by decrypting the byte enable of read data. In the case of the absence of the full byte reading, a selector 503 selects the holding content of the circuit 20, and in the case of the presence of the full byte reading, the selector 503 selects and sets the byte enable held by the circuit 10 as the byte enable of read data. <P>COPYRIGHT: (C)2013,JPO&amp;INPIT

Description

  The present invention relates to a data transfer device, and more particularly to a data transfer device capable of transferring data in units of bytes using a FIFO.

  In general, when data is transferred between a memory device and an arbitrary interface in units of bytes that do not match the data width of the memory device, it is necessary for the CPU or the like to take the data once and then combine the data by matching the data width. . In this case, in order to avoid the load on the CPU, a technique that enables input / output in units of bytes to the memory device is known.

  First, in order to realize writing and reading in byte units, individual FIFOs are provided in byte units, and the write address and read address for the FIFO are controlled differently for each FIFO. However, this complicates the circuit if one word is a FIFO of 4 bytes or more. For example, when a marketable and large-capacity DDR memory is used as a FIFO, it is necessary to have a DDR memory controller and a DDR physical interface for each byte, resulting in a large scale.

  The second is to provide a transmission FIFO for storing transmission data from the upper apparatus to the lower apparatus and a reception FIFO for storing reception data from the lower apparatus to the upper apparatus. Detects that the byte width is less than the data, and notifies the host device. The host device then transmits the transmission data to be transmitted to the transmission FIFO or the next reception data to be received from the reception FIFO. Data transmission / reception with the FIFO is permitted depending on the size.

JP 2002-050172 A JP 2003-296264 A

  The problem to be solved is that hardware to be used such as FIFO becomes large in order to realize data transfer in units of bytes.

  In the present invention, in order to enable writing / reading of less than one word with a small circuit, enable data indicating a valid byte position is managed by a register on the write side and the read side, and is selected and given to the read data. This is the main feature.

  The data transfer apparatus of the present invention employs a configuration in which enable data is managed by the registers on the write side and the read side, and is selected at the time of reading and given to the read data. Therefore, the circuit configuration (logic Therefore, there is an advantage that write / read operations in byte units can be realized even if a FIFO having a byte width of 1 word or less is used. Therefore, even when using a FIFO in which the byte width of one word is expanded, if only the circuit related to byte enable is expanded, the same circuit configuration (logic) is sufficient, and the increase in the gate scale is small. .

It is a block diagram which shows one Example of the data transfer apparatus of this invention. It is a figure which shows the truth table of the selector 103. It is a figure which shows the truth table of the byte read determination flag. It is a figure which shows the truth table of the decoder 104. FIG. 6 is a diagram showing a truth table of a write address counter 12. FIG. It is a first time chart illustrating the operation of the writing system. 12 is a second time chart illustrating the operation of the writing system. It is a figure which shows the truth table of the selector 203. FIG. It is a figure which shows the truth table of a lead solvent and the enable determination circuit. It is a figure which shows the truth table of the decoder 204. FIG. 4 is a diagram showing a truth table of a read address counter 22. FIG. 3 is a diagram showing a truth table of the address comparator 30. FIG. It is a figure which shows the truth table of the byte read determination flag. It is a figure which shows the truth table of the selector 503. 4 is a diagram showing a truth table of a memory EMPTY flag 60. FIG. It is a first time chart illustrating the operation of the read system. 6 is a second time chart illustrating the operation of the read system. 6 is a first time chart for explaining a method of generating a lead BE. 12 is a second time chart for explaining a method of generating a lead BE. 12 is a third time chart for explaining a method of generating a lead BE. 10 is a fourth time chart for explaining a method of generating a lead BE. FIG. 10 is a fifth time chart for illustrating a method for generating a lead BE.

  The data transfer apparatus of the present invention writes write data corresponding to binary information (byte enable) indicating a valid byte position in response to a write request, reads the read data from the FIFO in response to a read request, Attach enable. On the write side, there is provided a write byte enable holding circuit for holding the byte enable of the data written in the latest write address of the FIFO, and on the read side, the data written in the latest write address of the FIFO is stored. There is provided a byte enable, a logical sum of the byte enable and the self-held content before one timing, or a read byte enable holding circuit for holding the self-held content before one timing.

  On the read side, a byte read determination flag and a selector for read data are further provided. The byte read determination flag decodes the byte enable of the read data, stores that the read is performed with a byte enable of less than one word when the FIFO write address matches the read address, and reads to the position where one word has been reached Sometimes erased.

  When the byte read determination flag is set, the selector selects the byte enable held by the read byte enable holding circuit, the byte read determination flag is reset, and the FIFO write address matches the read address. When byte enable is selected, the byte enable held by the write byte enable holding circuit is selected. When the byte read determination flag is reset and the FIFO write address does not match the read address, the byte enable indicating all byte read is selected. In this case, each byte of read data is enabled. Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of the data transfer apparatus of the present invention. In this data transfer device, when the write REQ is input, the write DATA at the write byte position indicated by the enable data (write BE) is written to the FIFO 40, and when the read REQ is input, the read DATA is read from the FIFO 40 to indicate the read byte position. Enable data (read BE) is output. Write BE and read BE are specified by binary information. The FIFO 40 is a first-in first-out memory for storing data in which one word is composed of a plurality of bytes, and has a plurality of bytes of write data I / F and a plurality of bytes of read data I / F. Note that the memory EMPTY indicates that there is no data stored in the FIFO 40. In the following description, it is assumed that the FIFO 40 stores a 4-byte word.

(1) Configuration of Write System First, the write system shown on the left side of FIG. 1 will be described. The write system includes a gate circuit 401, a write address counter 12, a write byte enable holding circuit 10, a write byte enable determination circuit 11, an OR circuit 102, a selector 103, a decoder 104, and an AND circuit 101.

  The gate circuit 401 inputs only the byte (valid byte) designated by the write BE in the write DATA to the FIFO 40 as W DATA. W DATA is stored in the memory area indicated by the write address (W ADD) of the FIFO 40 output from the write address counter 12 at the same time as the write REQ (= W REQ) “1” is asserted.

  When writing to all bytes constituting one word in the FIFO 40 is performed, the write address counter 12 is updated by +1 and the next W DATA is stored in W ADD updated by +1. That is, the write address counter 12 designates W ADD to write W DATA at the next timing.

  The write byte enable holding circuit 10 holds the effective byte position of W DATA written in the latest W ADD of the FIFO 40 as binary information. For example, since one word consists of 4 bytes, the binary information is “0001” if the effective byte is only the first byte, and the binary information is “0111” if the effective byte is the first to third bytes.

  The write byte enable determination circuit 11 is in an initial state (“0000” in the above example) or the data written in WADD is 1 based on the binary information held by the write byte enable holding circuit 10. Whether it has reached the number of words ("1111" in the above example) and whether the data written in the FIFO 40 is less than one word ("0001", "0011" or "0111" in the above example) Is output (“0” for the former, “1” for the latter).

  The OR circuit 102 outputs a logical sum of the binary information held by the write BE and the write byte enable holding circuit 10. That is, a new input write BE is added to the current valid byte position.

  The selector 103 uses the determination result in the write byte enable determination circuit 11 as a select signal, selects the output of the write BE or OR circuit 102, and outputs it to the write byte enable holding circuit 10.

  When the decoder 104 decodes the output of the selector 103 and detects from the W DATA to be written to the FIFO 40 that one word (the output of the selector 103 is “1xxx”) reaches the address of the FIFO 40, the decoder 104 assumes the “1” asserted state. Become. The AND circuit 101 asserts “1” an enable signal EN for updating the write address counter 12 by +1 based on the logical product of the write REQ and the decoder 104.

  FIG. 2 shows a truth table of the selector 103 for setting the write byte enable holding circuit 10. The write byte enable holding circuit 10 stores write BE if the output of the write byte enable determination circuit 11 is “0” (case 1), and write BE if the output of the write byte enable determination circuit 11 is “1”. The binary information held by the write byte enable holding circuit 10 is logically ORed and stored (case 2).

  At this time, the initial value “0000” or 1 word “1111” is stored in the write byte enable holding circuit 10, and if it is less than 1 word, “1” is asserted from the LSB side (or MSB side) and logical OR is performed. Therefore, there are five types of “0001”, “0011”, “0111” (or “1000”, “1100”, “1110”).

  FIG. 3 shows a truth table of the write byte enable determination circuit 11. The write byte enable determination circuit 11 outputs “0000” or “1xxx”, that is, outputs “0” when the initial value or the number of bytes for one word is written. If the output of the write byte enable holding circuit 10 is a write other than “0000” or “1xxx”, that is, a write with the number of bytes less than one word, “1” is output. Here, “X” indicates “don't care”.

  FIG. 4 shows a truth table of the decoder 104. The decoder 104 outputs “1” if the output of the selector 103 is “1xxx”, and outputs “0” otherwise. FIG. 5 shows a truth table of the write address counter 12. The write address counter 12 is +1 only when the write REQ asserts “1” via the AND circuit 101 and the output of the decoder 104 is “1”, that is, byte enable for one word is reached during the write operation. Update the count.

(2) Operation of Write System FIGS. 6 and 7 are time charts illustrating the operation of the write system described above. FIG. 6 shows a state transition of each circuit when the write DATA is sequentially written to the FIFO 40 in units of 1 byte. FIG. 7 shows the state transition of each circuit when the write DATA is sequentially written to the FIFO 40 in units of 1 to 4 bytes. The write BE is composed of 4 bits, and the position of the bit asserting “1” corresponds to the position of the valid byte of the write DATA. Initially, it is assumed that the address counter 12 holds “0” and the write enable holding circuit 10 holds “0000”.

  When the write BE is less than 4 bits and “1” is asserted, for example, “1” is asserted from the LSB side, and at the next write timing, the bit that was asserted “1” at the previous write timing is set to “0” and the MSB When "1" is asserted to the side, it is permitted to assert the LSB side to "1" again. This is for writing to the next address after writing to all the bytes constituting one word. Note that the direction of assertion of “1” to the write BE may be performed from the MSB side to the LSB side, contrary to the above.

(2.1) 1-byte Write Operation In FIG. 6, the write data “01” to “07” are continuously written seven times. At timing 3 when the write REQ in which “1” assertion continues until timing 10 rises, the write DATA “01” accompanied by the write BE “0001” is input. That is, the operation for writing the write DATA “01” to the first byte of W ADD “0” of the FIFO 40 starts. Since the write enable determination circuit 11 outputs “0”, the selector selects the write BE “0001” (case 1 in FIG. 2). However, in order for the write enable holding circuit 10 to hold “0001”, it is necessary to wait for the next timing.

  At timing 4, write DATA “02” accompanied by write BE “0010” is input. The writing of the write DATA “01” to the W ADD “0” of the FIFO 40 is completed, and the operation for writing the write DATA “02” to the second byte of the W ADD “0” is started. Since the write enable holding circuit 10 holds “0001”, the write enable determination circuit 11 asserts “1” (see FIG. 3), and the selector 103 selects the output “0011” of the OR circuit 102 (see FIG. 3). Case 2 in FIG. The write enable holding circuit 10 holds “0011” at the next timing.

  At timing 5, write DATA “03” accompanied by write BE “0100” is input. Writing of the write DATA “02” to the W ADD “0” of the FIFO 40 is completed, and an operation for writing the write DATA “03” to the third byte of the W ADD “0” is started. Since the write enable holding circuit 10 holds “0011”, the write enable determination circuit 11 asserts “1” (see FIG. 3), and the selector 103 selects the output “0111” of the OR circuit 102 (see FIG. 3). Case 2 in FIG. The write enable holding circuit 10 holds “0111” at the next timing.

  At timing 6, the write DATA “04” accompanied by the write BE “1000” is input. The writing of the write DATA “03” to the W ADD “0” of the FIFO 40 is completed, and the operation for writing the write DATA “04” to the fourth byte of the W ADD “0” is started. Since the write enable holding circuit 10 holds “0111”, the write enable determination circuit 11 asserts “1” (see FIG. 3), and the selector 103 selects the output “1111” of the OR circuit 102 (see FIG. 3). Case 2 in FIG. The write enable holding circuit 10 holds “1111” at the next timing. In this case, the decoder 104 outputs “1” (see FIG. 4).

  At timing 7, the write DATA “05” accompanied by the write BE “0001” is input. The writing of the write DATA “04” to the W ADD “0” of the FIFO 40 is completed, and the operation for writing the write DATA “05” to the first byte of the FIFO 40 is started. Since the decoder 104 outputs “1”, the write address counter 12 is updated by +1 (see FIG. 5) and becomes “1”. Therefore, the write DATA “05” is written by W ADD “1”. To be done. Since the write enable holding circuit 10 holds “1111”, the write enable determination circuit 11 asserts “0” (see FIG. 3), and the selector 103 selects the write BE “0001” (see FIG. 2). Case 1). The write enable holding circuit 10 holds “0001” at the next timing.

  At timing 8, the write DATA “06” accompanied by the write BE “0010” is input. The writing of the write DATA “05” to the W ADD “1” of the FIFO 40 is completed, and the operation for writing the write DATA “06” to the second byte of the W ADD “1” of the FIFO 40 starts. Since the write enable holding circuit 10 holds “0001”, the write enable determination circuit 11 asserts “1” (see FIG. 3), and the selector 103 selects the output “0011” of the OR circuit 102 (see FIG. 3). Case 2 in FIG. The write enable holding circuit 10 holds “0011” at the next timing.

  At timing 9, write DATA “07” accompanied by write BE “0100” is input. Writing of the write data “06” to W ADD “1” of the FIFO 40 is completed, and all 4 bytes of the address “0” of the FIFO 40 are filled with the write DATA. The operation for writing the write DATA “07” to the third byte of W ADD “1” of the FIFO 40 starts. Since the write enable holding circuit 10 holds “0011”, the write enable determination circuit 11 asserts “1” (see FIG. 3), and the selector 103 selects the output “0111” of the OR circuit 102 (see FIG. 3). Case 2 in FIG. The write enable holding circuit 10 holds “0111” at the next timing. Note that the current state at the timing 9 is maintained since the write REQ is “0” after the timing 10.

(2.2) At-Random Write Operation FIG. 6 shows a simple write pattern in which 1-byte write is repeated, but FIG. 7 presents a more complicated write pattern. That is, as an example of an at-random write pattern, a mode is presented in which two 2-byte writes, one 1-byte write, and two 3-byte writes are sequentially performed following two one-word width writes. .

  In FIG. 7, at timing 3 at which the write REQ in which “1” assertion continues until timing 10 rises, the write DATA “01 to 04” accompanied by the write BE “1111” is input. That is, the operation for writing the write data “01 to 04” into the first to fourth bytes of W ADD “0” of the FIFO 40 starts. Since the write enable holding circuit 10 holds “0000”, the write enable determination circuit 11 asserts “0” (see FIG. 3), and the selector 103 selects the write BE “1111” (see FIG. 2). Case 1). However, in order for the write enable holding circuit 10 to hold “1111”, it is necessary to wait for the next timing. In this case, the decoder 104 outputs “1”.

  At timing 4, the write DATA “05 to 08” accompanied by the write BE “1111” is input. Since the decoder 104 outputs “1”, the write address counter 12 is updated by +1 to become “1” (see FIG. 5), so that writing is performed in the first to fourth bytes of WADD “1” of the FIFO 40. The operation for writing DATA “05-08” starts. Since the write enable holding circuit 10 holds “1111”, the write enable determination circuit 11 asserts “0” (see FIG. 3), and the selector 103 selects the write BE “1111” (see FIG. 2). Case 1). The write enable holding circuit 10 continues to hold “1111” at the next timing. Also in this case, the decoder 104 continues to output “1”.

  At timing 5, the write DATA “0910” accompanied by the write BE “0011” is input. Since the decoder 104 outputs “1”, the write address counter 12 is updated by +1 to become “2” (see FIG. 5), so that the write is performed on the first and second bytes of WADD “2” of the FIFO 40. The operation for writing DATA “0910” starts. Since the write enable holding circuit 10 holds “1111”, the write enable determination circuit 11 asserts “0” (see FIG. 3), and the selector 103 selects the write BE “0011” (see FIG. 2). Case 1). The write enable holding circuit 10 holds “0011” at the next timing. In this case, the decoder 104 outputs “0”.

  At timing 6, the write data “1112” accompanied by the write BE “1100” is input. Since the decoder 104 outputs “0”, the write address counter 12 + 1 is not updated and remains “2” (see FIG. 5), so the third to fourth bytes of WADD “2” of the FIFO 40 The operation for writing the write DATA “1112” starts. Since the write enable holding circuit 10 holds “0011”, the write enable determination circuit 11 asserts “1” (see FIG. 3), and the selector 103 selects the output “1111” of the OR circuit 102 (see FIG. 3). Case 2). The write enable holding circuit 10 holds “1111” at the next timing. In this case, the decoder 104 outputs “1”.

  At timing 7, the write DATA “13” accompanied by the write BE “0001” is input. Since the decoder 104 outputs “1”, the write address counter 12 is updated by +1 to “3” (see FIG. 5), so that the write DATA “1” is written in the first byte of W ADD “3” of the FIFO 40. The operation for writing "13" begins. Since the write enable holding circuit 10 holds “1111”, the write enable determination circuit 11 asserts “0” (see FIG. 3), and the selector 103 selects the write BE “0001” (see FIG. 2). Case 1). The write enable holding circuit 10 holds “0001” at the next timing. In this case, the decoder 104 does not output “1”.

  At timing 8, the write data “14 to 16” accompanied by the write BE “1110” is input. Since the decoder 104 outputs “0”, the write address counter 12 + 1 is not updated and remains “3” (see FIG. 5), so the second to fourth bytes of WADD “3” in the FIFO 40 The operation for writing the write data “14 to 16” starts. Since the write enable holding circuit 10 holds “0001”, the write enable determination circuit 11 asserts “1” (see FIG. 3), and the selector 103 selects the output “1111” of the OR circuit 102 (see FIG. 3). Case 2). In this case, the decoder 104 outputs “1”.

  At timing 9, write data “17 to 19” accompanied by write BE “0111” is input. Since the decoder 104 outputs “1”, the write address counter 12 is updated by +1 to “4” (see FIG. 5), so that the write is performed on the first to third bytes of WADD “4” of the FIFO 40. The operation for writing DATA “17-19” starts. Since the write enable holding circuit 10 holds “1111”, the write enable determination circuit 11 asserts “0” (see FIG. 3), and the selector 103 selects the write BE “0111” (see FIG. 2). Case 1). The write enable holding circuit 10 holds “0111” at the next timing. In this case, the decoder 104 does not output “1”. Note that the current state at the timing 9 is maintained since the write REQ is “0” after the timing 10.

  From the above series of operations, the write operation of less than one word stores data in the FIFO 40 in units of 1 byte with the FIFO address held, updates the FIFO address when it reaches 1 word, and writes the write DATA to the FIFO 40. It can be seen that alignment is performed in units of one word.

(3) Configuration of Read System Next, the read system shown on the right side of FIG. 1 will be described including the address comparator 50 and the memory EMPTY flag 60. When the read REQ (= R REQ) is “1” asserted, the read DATA (R DATA) is read from the read address (R ADD) of the FIFO 40. At this time, the byte specified by the read BE is valid in the read DATA.

  The read system includes a read address counter 22, a decoder 204, an AND circuit 201, an address comparator 30, a read byte enable holding circuit 20, a read byte enable determination circuit 21, an OR circuit 202, a selector 203, an AND circuit 501, and an AND circuit. A circuit 502, a byte read determination flag 50, and a selector 503 are included.

  The read address counter 22 indicates R ADD of R DATA, and is updated by +1 when one word of R DATA is read from the FIFO 40. That is, the decoder 204 asserts “1” if the fourth byte of the read BE is “1”, and the AND circuit 201 updates the read address counter 22 by +1 according to the read REQ and the decoder 204 “1” asserted state. The enable signal EN is asserted “1”.

  The address comparator 30 compares the output of the write address counter 12 and the output of the read address counter 22, and outputs “1” when the output values of these two counters match, and outputs “1” when they do not match. 0 ”is output. A carry flag is provided between the two counters, and control is performed so that the relationship between the two counters does not become free run after the counter exceeds the maximum value.

  The AND circuit 601 sets the memory EMPTY flag 60 when the output values of the two counters match with each other as a result of the comparison in the address comparator 30, and there is no write REQ and there is a read REQ. In other words, the memory EMPTY flag 60 outputs an EMPTY signal asserted to “1” when the data held in the FIFO 40 becomes empty, and is reset when there is a write REQ.

  The read byte enable holding circuit 20 holds either the write BE, the logical sum of the write BE and the output of the read byte enable holding circuit 20, or the output of the read byte enable holding circuit 20.

  The read byte enable determination circuit 21 is in an initial state based on the binary information held by the read byte enable holding circuit 20, or whether the read data has reached one word of data, Assert the determination result whether it is less than one word ("0" for the former, "1" for the latter).

  The OR circuit 202 outputs a logical sum of the binary information held by the write BE and the read byte enable holding circuit 20. That is, a new input write BE is added to the output of the current read byte enable holding circuit 20.

  The selector 203 uses the write REQ, read REQ, output of the address comparator 30 and output of the read byte enable determination circuit 21 as a select signal, and outputs the write BE or OR circuit 202 or read byte enable holding circuit 20. One of the outputs is selected and output to the read byte enable holding circuit 20.

  The AND circuit 501 sets the byte read determination flag 50 when the read REQ is asserted “1”, the output of the address comparator 30 is “1”, and the output of the decoder 204 is “0”, that is, byte read. To do. The AND circuit 502 resets the byte read determination flag 50 when the read REQ is asserted to “1” and the output of the decoder 204 is “1”, that is, when the read has reached one word.

  The byte read determination flag 50 is used to select a byte enable held in the write byte enable holding circuit 10 or the read byte enable holding circuit 20.

  The selector 503 uses the output of the byte read determination flag 50, the read REQ, and the output of the address comparator 30 as a select signal, and holds the value of All “0”, the value of the read byte enable holding circuit 10 or the read byte enable. The value of the circuit 20 or the value of All “1” is selected and output as the read BE.

  FIG. 8 shows a truth table of the selector 203 for setting the read byte enable holding circuit 20. If the output of the address comparator 30 is “0”, the selector 203 stores (holds) the output of the read byte enable holding circuit 20 (case 2).

  On the other hand, if the output of the address comparator 30 is “1” and the write REQ and read REQ are “1”, the value of the write BE is selected (case 3).

  If the output of the address comparator 30 is “1”, the write REQ is “1”, the read REQ is “0”, and the output of the read byte enable determination circuit 21 is “0”, the write BE Select an output (Case 4). At this time, however, if the output of the read byte enable determination circuit 21 is “1”, the read byte enable holding circuit 20 selects a value obtained by logically ORing the value of the write BE with the value stored in the previous write (case). 5).

  If not all of the above cases, the output of the read byte enable holding circuit 20 is stored (held) (case 1).

  FIG. 9 shows a truth table of the read byte enable determination circuit 21. The read byte enable determination circuit 21 asserts “0” when the output of the read byte enable holding circuit 20 reaches “0000”, that is, an initial value, or “1xxx”, that is, one word (4 bytes). When the output of the read byte enable determination circuit 20 is other than “0000” or “1111”, that is, indicates the number of bytes less than one word, “1” is output. The logic of the read byte enable determination circuit 21 is the same as the logic of the write byte enable determination circuit 11 shown in FIG.

  FIG. 10 shows a truth table of the decoder 204. The decoder 204 outputs “1xxx” when the output of the selector 503 is “1xxx”, that is, when the read DATA reaches one word, and outputs “0” when the output of the selector 503 is other than “1xxx”.

  FIG. 11 shows a truth table of the read address counter 22. The read address counter 22 is updated by +1 after one clock when the output of the decoder 204 is “1” and there is a read REQ. In other cases, the read address counter 22 holds the current output.

  FIG. 12 shows a truth table of the address comparator 30. The address comparator 30 outputs “1” when the count value of the write address counter 12 is equal to the count value of the read address counter 22, and outputs “0” otherwise.

  FIG. 13 shows a truth table of the byte read determination flag 50. The byte read determination flag 50 is set to “1” when there is a read REQ when the output of the address comparator 30 is “1” and the output of the decoder 204 is “0”, that is, the read DATA does not reach one word. Is done. When the output of the decoder 204 is “1”, that is, when the read DATA reaches one word, if there is a read REQ, it is reset to “0”.

  FIG. 14 shows a truth table of the selector 503. The selector 503 outputs “0000” if the read REQ is “0” (case 1).

  On the other hand, if the read REQ is “1” and the output of the byte read determination flag 50 is “1”, the output of the read byte enable holding circuit 20 is selected (case 2).

  If the read REQ is “1”, the output of the byte read determination flag 50 is “0”, and the output of the address comparator 30 is “1”, the output of the write byte enable holding circuit 10 is selected (case). 3). However, if the output of the address comparator 30 is “0” at this time, “1111” is selected (case 4).

  FIG. 15 shows a truth table of the memory EMPTY flag 60. The memory EMPTY flag 60 is set to “1” when the output of the address comparator 30 is “1”, the write REQ is “0”, and the read REQ is “1”. This is because data less than one word written last is read in a state where there is no newly written data. If the write REQ is “1”, “0” is reset.

(4) Operation of Read System FIGS. 16 and 17 are time charts illustrating the operation of the read system described above. FIG. 16 shows the state transition of each circuit when reading DATA from the FIFO 40 sequentially in units of 1 byte. FIG. 17 shows the state transition of each circuit when reading DATA consisting of one or more bytes is read at random. Initially, it is assumed that the write address counter 12 and the read address counter 22 are “0”, and the write byte enable holding circuit 10 and the read byte enable holding circuit 20 hold “0000”. Therefore, the address comparator 30 outputs “1”, and the memory EMPTY flag 60 also outputs “1”. The byte read determination flag 50 is in a reset state.

(4.1) 1-byte read operation FIG. 16 shows a case where the read REQ is input during the write operation shown in FIG. 6 and the data is read one byte at a time, and the waveform of the write system is a copy of FIG. . The read REQ can be set to “1” when the memory EMPTY is “0”, that is, when data of 1 byte or more is stored in the FIFO 40. The read REQ is “1” between the timing 4 and the timing 11, and during this time, the write DATA “01” to “07” sequentially written in the FIFO 40 is sequentially read as the read DATA “01” to “07”.

  At timing 3, since the read byte enable holding circuit 20 holds “0000”, the read enable determination circuit 21 outputs “1” (see FIG. 9). Since the address comparator 30 outputs “1” (see FIG. 12), the write REQ is “1”, and the read REQ is “0”, the selector 203 selects the write BE “0001” (FIG. 8). Case 4). Since the read REQ has not yet been input, the selector 503 outputs “0000” (case 1 in FIG. 14).

  At timing 4, since the write REQ is asserted by “1” at timing 3, the memory EMPTY flag 60 outputs “0” and continues until timing 11 (see FIG. 15). The read byte enable holding circuit 20 holds “0001” selected by the selector 203 at timing 3, and the read byte enable determination circuit 21 outputs “1” (see FIG. 9). Since the read REQ is asserted by “1”, the selector 203 outputs the write BE “0010” (case 3 in FIG. 8). The selector 503 selects “0001” held by the write byte enable holding circuit 10 (case 3 in FIG. 14). That is, the first byte write DATA “01” input at timing 3 and written to the FIFO 40 at timing 4 is read as the first byte read DATA “01”. In this case, since the decoder 204 outputs “0”, the output of the AND circuit 501 is “1”.

  At timing 5, the byte read determination flag 50 is set to “1” in response to the final sentence setting condition being satisfied (FIG. 13). Accordingly, the selector 503 selects “0010” held by the read byte enable holding circuit 20 (case 2 in FIG. 14). That is, the second byte write DATA “02” input at the timing 4 and written to the FIFO 40 at the timing 5 is read as the second byte read DATA “02”.

  Timing 6 changes in the same manner as timing 5. At timing 7, the address comparator 30 outputs “0” because of a mismatch between the write address counter 12 and the read address counter 22 (see FIG. 12). Therefore, the output of the AND circuit 501 is “0”. Since the read BE is “1000”, the output of the AND circuit 502 is “1”, and the reset condition of the byte read determination flag 50 is satisfied (FIG. 13). Further, the decoder 204 outputs “1”. Further, since the read byte enable holding circuit 20 holds “1000”, the byte read determination circuit 21 becomes “0” (see FIG. 9).

  At timing 8, the byte read determination flag 50 is reset to “0”. Since the decoder 204 outputs “1”, the read address counter 22 is updated to “1” (see FIG. 11), and the address comparator 30 outputs “1” again (see FIG. 12). . Therefore, the selector 503 selects “0001” held by the write enable holding circuit 10 (case 3 in FIG. 14). As a result, the output of the AND circuit 501 is “1”, and the output of the AND circuit 502 is “0”. The selector 203 selects the write BE “0010” (case 3 in FIG. 8).

  At timing 9, the output of the byte read determination flag 50 becomes “1” (see FIG. 13), and the selector 503 selects “0010” held by the read solvent and the enable holding circuit 20 (case 2 in FIG. 14). . The selector 203 selects the write BE “0100” (case 3 in FIG. 8).

  The operation at the timing 10 is the same as that at the timing 9. At this time, since the write REQ becomes “0”, the setting condition of the memory EMPTY flag 60 is satisfied (see FIG. 15).

  At timing 11, the output of the memory EMPTY flag 60 becomes “1”. Since the read REQ also becomes “0”, the selector 503 continues to center “0000” thereafter (case 1 in FIG. 14).

(4.2) At-random read operation FIG. 17 shows an example of an at-random read pattern, in which 1 byte, 2 bytes, 1 byte, 4 bytes, 4 bytes, and 2 bytes are sequentially written 6 times, and 1 after 5 timings. Write only bytes, read only one byte during the first continuous write, and read all remaining data written in the first continuous write between the first continuous write and the second write Reading the data after the second writing.

  Even with such a complicated writing / reading pattern, the operation of each circuit is considered to be easily understood based on the fact that it has been learned by the detailed description so far, so that further description is omitted. However, at timing 9, the read BE is “1110” because the write DATA “0203” at the timing 4 and the write DATA “04” at the timing 5 are combined to become the read DATA “020304”. Indicates that In this way, reading from the FIFO 40 is performed at word breaks.

(4.3) Generation of Lead BE Here, a method of generating a read BE signal will be described with reference to timing charts from FIG. 18 to FIG. In these drawings, the write operation is the same, but the read operation shows a plurality of cases in which the timing at which the read REQ is asserted to “1” is changed. Depending on the timing at which the read REQ is asserted to “1”, FIGS. 18, 19, 20, and 22 are cases of a read operation of less than one word, and FIG. 21 is a case of a read operation of one word. Further, in all cases, unlike the read operation of the timing chart of FIG. 16, data written by 1 byte is combined and read by a plurality of bytes.

  In the case of FIG. 18, the write operation starts from timing 3, and at the read operation at timing 4, the write byte enable holding circuit 10 and the read byte enable holding circuit 20 hold the same “0001”. The flag 50 remains at the initial value “0”, and “0001” in the write byte enable holding circuit 10 is selected as the read BE (case 3 in FIG. 14).

  After timing 5, the byte read determination flag 50 is set to “1”. This means that the read operation has been performed with less than one word, and in the next read operation, it is used for the function of selecting the remaining byte data that reaches one word. The write byte enable holding circuit 10 newly stores the write BE output by the selector 103 at timing 3 (case 1 in FIG. 2), and then writes the write BE and write byte enable holding circuit from timing 4 to timing 6. The values obtained by logically ORing the ten held contents are sequentially stored (case 2 in FIG. 2).

  On the other hand, the read byte enable holding circuit 20 newly stores the write BE output from the selector 203 at timing 3 (case 3 in FIG. 8), and stores the write BE again at the fourth clock ( In case 4) in FIG. 8, from timing 5 to timing 6, values obtained by logically ORing the write BE to values excluding “0001” are sequentially stored (case 5 in FIG. 8). This is because at the timing 4, the read BE is “0001” and the processing is completed, so that data excluding the first byte is validated in the next read operation.

  Next, at timing 7, the read byte enable holding circuit 20 is “1110”, and the first bit is delimited by “1”, that is, one word, but the address comparator 30 is next time from the condition of “0”. In order to secure the lead BE that is output by the read operation, the “1110” is held (case 2 in FIG. 5). After timing 8, the write byte enable holding circuit 10 continues to be updated and operates independently of the read byte enable holding circuit 20.

  In the read operation at the timing 10, “1110” of the read byte enable holding circuit 20 is selected as the read BE by the output “1” of the byte read determination flag 50 (case 2 in FIG. 14). At the timing 11 when the read process is completed, none of the conditions is satisfied, so the read byte enable holding circuit 20 holds “1110” (case 1 in FIG. 8).

  FIG. 19 shows a case where the initial read operation is delayed by one timing with respect to FIG. The write byte enable holding circuit 10 and the read byte enable holding circuit 20 are updated to the same value until the timing 5 at which the read operation is performed, the read BE “0011” is output by the read operation at the timing 5, and the address comparison is performed at the timing 7. The device 30 holds “1100” of the read byte enable holding circuit 20 from the condition “0” (case 2 in FIG. 8). The read BE “1100” is output in the next read operation (timing 10).

  FIG. 20 shows a case where the initial read operation is delayed by 2 clocks with respect to FIG. The write byte enable holding circuit 10 and the read byte enable holding circuit 20 are updated to the same value until the timing 6 at which the read operation is performed, the read BE “0111” is output by the read operation at the timing 6, and the address comparison is performed at the timing 7. The device 30 holds “1000” of the read byte enable holding circuit 20 from the condition of “0” (case 2 in FIG. 8). The read BE “1000” is output in the next read operation (timing 10).

  FIG. 21 shows a case where a read operation is never performed while a write operation of one word or more is performed. At timing 7, the write operation reaches one word, and the write address counter 12 updates +1 count. Since the read address counter 22 remains at the initial value, the output of the address comparator 30 becomes “0” at timing 7. Since the read operation of less than one word is not performed, the byte read determination flag 50 remains “0”, and the write byte enable hold circuit 10 and the read byte enable hold circuit 20 are updated to the same value. At timing 7, the address comparator 30 holds “1111” of the read byte enable holding circuit 20 from the condition “0” (case 2 in FIG. 8).

  Since the first read operation is performed at timing 10, the byte read determination flag 50 is “0”, and the address comparator 30 is “0”, “1111”, which is valid for one word, is selected as the read BE (see FIG. 14 cases 4). This is because there is no condition for reading the remaining byte data of less than one word, and there is a difference between the values of the write address counter 12 and the read address counter 22, so that the memory area of the address where the read operation is performed is equivalent to one word. This is because the data is stored. At this time, “1111” of the read byte enable holding circuit 20 and the output “1111” selected by the selector 503 are the same, but the read byte enable holding circuit 20 side may not be “1111” (FIG. 17 timing 10, 11).

  In FIG. 22, the first read operation of less than one word is performed at the fifth clock, and the read BE “0011” is output (case 3 in FIG. 14). Since the output of the address comparator 30 is “0” from timing 8 to timing 9, it is held at “1100” of the read byte enable holding circuit 20 (case 2 in FIG. 8). A second read operation is performed at timing 8 to output the read BE “1100” (case 2 in FIG. 14). At timing 9, since the read operation of the remaining byte data reaching one word is completed, the byte read determination flag 50 is reset to “0”. Up to this point, there is no significant difference from the cases of FIGS.

  However, at timing 9, the selector 203 writes the write byte enable determination circuit 21 to “0” (because the value of the read byte enable holding circuit 20 is “1100”), the address comparator 30 is “1”, and the write Since REQ is “1” and read REQ is “0”, write BE “0100” is selected (case 4 in FIG. 8). At the 10th clock, “0100” is stored in the read byte enable holding circuit 20, but is “invalid data that cannot be used as byte enable”.

  A third read operation is performed at timing 10. Based on the condition that the byte read determination flag 50 is “0” and the address comparator 30 is “1”, the value of the write byte enable holding circuit 10 is selected and the read BE “0111” is output (case 3 in FIG. 14). ). At the same time, the selector 203 selects the write BE “1000” from the condition that the address comparator 30 is “1”, the write REQ signal is “1”, and the read REQ signal is “1” (FIG. 8). Case 3). This is a function of selecting a new write BE excluding the byte enable because a read operation of less than one word was performed at timing 10, and the above-mentioned “invalid data that cannot be used as byte enable” is shown here. Disappear.

  From the condition that the decoder 204 is “0” (other than the third bit of the read BE signal is not applicable to “1”), the address comparator 30 is “1”, and the read REQ is “1”. At timing 11, the byte read determination flag 50 is set to “1”, and the write byte enable holding circuit 20 newly stores the write BE “1000”. This write BE “1000” is held until the next read operation (case 2 in FIG. 8).

  In the case of FIG. 22, the output of the address comparator 30 is “1” at the time of the third read operation at timing 10, but when the output of the address comparator 30 is “0”, the above-described FIG. The value of the read BE “1111” is output as in the case, and the end of the read operation ends in the case of FIG.

  The above is an explanation covering all cases in each truth table. The combination of these cases makes it easy to understand the operation of each circuit in any other write / read pattern.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

  (Supplementary note 1) Write data corresponding to binary information (byte enable) indicating a valid byte position is written to the FIFO in response to a write request, read data is read from the FIFO in response to a read request, and the byte enable is attached. A write byte enable holding circuit for holding the byte enable of data written at the latest write address of the FIFO, and the byte of data written at the latest write address of the FIFO. Enable, or the logical sum of the byte enable and the self-held content one timing before, or the read byte enable holding circuit for holding the self-held content one timing before, and decoding the byte enable of the read data FIFO write address and read A byte read determination flag that is erased when reading is performed with a byte enable of less than one word when the dress matches, and the position that has reached one word is read, and the byte read determination flag is set When the byte enable held by the read byte enable holding circuit is selected, and when the byte read determination flag is reset and the write address of the FIFO coincides with the read address, the write byte enable is selected. The byte enable held by the holding circuit is selected, and when the byte read determination flag is reset and the write address of the FIFO does not match the read address, the byte enable indicating all byte read is selected, Each read data Data transfer apparatus characterized by comprising a selector to the byte enable.

  (Supplementary Note 2) A write byte that outputs a determination result as to whether or not the FIFO is in an initial state or the write data has reached one word by the byte enable held by the write byte enable holding circuit. An enable determination circuit and when the write request is present and the FIFO is in an initial state or when the write data reaches one word, the byte enable of the write data is selected, and the write request has the write byte enable. When the determination result in the determination circuit is negative, when there is no write request, the logical select between the byte enable of the write data and the content held by the write byte enable holding circuit is selected, and the write byte enable holding circuit The supplementary note 1 has a selector that outputs to The data transfer device.

  (Additional remark 3) It has a decoder which decodes the output of the selector and detects that the write data reaches one word, and a write address counter which designates the latest write address and counts up by the detection The data transfer apparatus according to appendix 2, characterized by:

  (Supplementary Note 4) A read byte that outputs a determination result as to whether or not the FIFO is in an initial state or the read data has reached one word by the byte enable held by the read byte enable holding circuit. When the enable determination circuit and the write address and the read address do not match, the byte enable held by the read byte enable holding circuit, while the write address and the read address match, and the read When there is a request or when there is no read request and the FIFO is in an initial state or when the read data reaches one word, the byte enable of the write data, the write address and the read address match, And there is no read request and for the lead And a selector that selects a logical sum of the byte enable of the write data and the byte enable held by the read byte enable holding circuit when the determination result in the write enable determination circuit is negative. The data transfer apparatus according to Supplementary Note 1.

  (Additional remark 5) It has a decoder which detects that the read data for 1 word was read from said FIFO, and the read address counter which shows the address of the said read data and is updated +1 by the said detection, It is characterized by the above-mentioned. The data transfer apparatus according to appendix 4.

  (Supplementary Note 6) An address comparator that compares the content held in the write address counter with the content held in the read address counter has an address that matches the result of the comparison, and there is no write request and the read 6. The data transfer apparatus according to appendix 5, characterized by having a memory EMPTY flag for outputting an EMPTY signal indicating that the FIFO is empty when requested.

  For example, when streaming data is transferred via this data transfer device, the streaming data can be transferred even if the capacity of the streaming data is not delimited by one word (including one word or more), and is separated in byte units. Can also be transferred.

DESCRIPTION OF SYMBOLS 10 Write enable holding circuit 11 Write enable determination circuit 12 Write address counter 20 Read enable hold circuit 21 Read enable determination circuit 22 Read address counter 30 Address comparator 40 FIFO
50 byte read determination flag 60 memory EMPTY flag 101 AND circuit 102 OR circuit 103 selector 104 decoder 201 AND circuit 202 OR circuit 203 selector 204 decoder 401 gate circuit 501 AND circuit 502 AND circuit 503 selector 601 AND circuit

Claims (6)

Data transfer device for writing write data corresponding to binary information (byte enable) indicating valid byte position in response to write request to FIFO, reading read data from FIFO in response to read request, and attaching byte enable In
A write byte enable holding circuit for holding the byte enable of data written to the latest write address of the FIFO;
The byte enable of the data written in the latest write address of the FIFO, the logical sum of the byte enable and the self-holding content one timing before, or the read byte enable that holds the self-holding content one timing before A holding circuit;
Decodes the byte enable of the read data, stores the read with byte enable of less than one word when the write address of the FIFO matches the read address, and erases when read to the position reaching one word Read byte determination flag,
When the byte read determination flag is set, the byte enable held by the read byte enable holding circuit is selected, the byte read determination flag is reset, and the write address and read address of the FIFO Is selected, the byte enable held by the write byte enable holding circuit is selected, and if the byte read determination flag is reset and the write address of the FIFO does not match the read address, all bytes are selected. A data transfer apparatus, comprising: a selector that selects the byte enable indicating reading and sets the byte enable of the read data. A write byte enable determination circuit for outputting a determination result as to whether or not the FIFO is in an initial state or the write data has reached one word by the byte enable held by the write byte enable holding circuit; ,
When the write request is present and the FIFO is in the initial state or when the write data reaches one word, the byte enable of the write data is selected, and the determination result in the write byte enable determination circuit is the write request. A selector that selects a logical sum of the byte enable of the write data and the content held by the write byte enable holding circuit and outputs the logical sum to the write byte enable holding circuit. The data transfer device according to claim 1. A decoder for decoding the output of the selector and detecting that the write data reaches one word;
3. The data transfer apparatus according to claim 2, further comprising: a write address counter that designates the latest write address and counts up by the detection. A read byte enable determination circuit for outputting a determination result as to whether or not the FIFO is in an initial state or the read data has reached one word by the byte enable held by the read byte enable holding circuit; ,
When the write address and the read address do not match, the byte enable held by the read byte enable holding circuit, while when the write address and the read address match and there is the read request or When there is no read request and the FIFO is in an initial state or when the read data reaches one word, the byte enable of the write data, the write address and the read address match, and the read request If the determination result in the read byte enable determination circuit is negative, the logical sum of the byte enable of the write data and the byte enable held in the read byte enable holding circuit is selected. And having a selector to Data transfer apparatus according to claim 1 that. A decoder for detecting that one word of read data has been read from the FIFO;
5. The data transfer apparatus according to claim 4, further comprising a read address counter that indicates an address of the read data and is updated by +1 by the detection. An address comparator that compares the content held in the write address counter with the content held in the read address counter;
The memory has an EMPTY flag that outputs an EMPTY signal indicating that the FIFO is empty when the addresses match according to the comparison result and there is no write request and there is the read request. 5. The data transfer device according to 5.

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