JP5273535B2 - Analog signal comparator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To compare a value of an analog signal with a predetermined value by a comparatively simple circuit and in a short period of time. <P>SOLUTION: An analog signal comparator includes: an oscillator 21A which produces a first pulse signal; a VCO 22 which inputs an analog signal, converts the analog input signal to a second pulse signal, and outputs it; a first shift resistor 241 which inputs the first pulse signal from the oscillator 21; a second shift resistor 242 which inputs the second pulse signal from the VCO 22; and the number-of-pulses comparing circuit which detects the values of all bits or some bits of the first and second shift resistors 241, 242, and based on those detected values, compares the number of first pulse signals produced by the oscillator 21A with the number of second pulse signals produced by VCO 22. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an analog signal comparator capable of comparing an analog signal value with a predetermined value in a relatively simple circuit and in a short time.

  FIG. 12A shows a conventional analog comparator 200 used for signal level detection. In the comparator 8, the reference signal V1 is set to one input terminal (−), the analog voltage V2 is input to the other input terminal (+), and the voltage Vo (+15 [V]) as a comparison result is output from the output terminal. Or, -15 [V]) is output.

In the comparator 200 of FIG.
When V2 <V1, Vo = -15 [V]
When V2 = V1, Vo = 0 [V]
When V2> V1, Vo = + 15 [V]
It becomes.

  However, as shown in FIG. 12B, when the output of Vo changes, a time delay Td of several tens to several hundreds ns occurs even at high speed. This time delay corresponds to one cycle of a digital signal on the order of several tens of MHz. For this reason, the comparator 200 shown in FIG. 12A is not suitable for signal level comparison of digital signals on the order of several hundred MHz to several GHz.

  FIG. 13 shows a conventional digital comparator 300 used for signal level detection. The comparator 300 includes an A / D converter 301 (4 bits in FIG. 13) and a digital value comparison unit 302 that can set a set value (reference voltage V1). The A / D converter 301 inputs the analog signal to be measured V2 and outputs it to the digital value comparison unit 302 as 4-bit data.

  The digital value comparison unit 302 compares the preset digital value of the reference voltage V1 with the digital value input from the A / D converter 301, and the measured analog signal V2 is larger than the reference voltage V1. Whether V2 <V1, V2 = V1, V2> V1 can be determined.

  By the way, the comparator 302 of FIG. 13 requires a certain time from the input of the analog signal V2 to be measured to obtain the comparison result, and can only compare the signal levels of digital signals on the order of several tens of MHz.

  An object of the present invention is to provide an analog signal comparator capable of comparing the value of an analog signal with a predetermined value in a relatively simple circuit and in a short time.

  An analog signal comparator according to a first aspect of the present invention is a first oscillation circuit that generates a first pulse signal, and a second oscillation that receives the analog signal, converts the analog input signal into a second pulse signal, and outputs the second pulse signal. A circuit, a first shift register that inputs a first pulse signal from the first oscillation circuit, a second shift register that inputs a second pulse signal from the second oscillation circuit, and The values of all or some bits of the first and second shift registers are detected, and based on these detected values, the number of first pulse signals generated by the first oscillation circuit and the second oscillation And a pulse number comparison circuit for comparing the number of second pulse signals generated by the circuit.

  An analog signal comparator according to a second aspect of the present invention is a first oscillation circuit that generates a first pulse signal, and a second oscillation that receives the analog signal, converts the analog input signal into a second pulse signal, and outputs the second pulse signal. A first counter for inputting a first pulse signal from the first oscillation circuit, a second counter for inputting a second pulse signal from the second oscillation circuit, and the first counter. And a pulse number comparison circuit for comparing the number of pulses from the first oscillation circuit with the number of pulses from the second oscillation circuit by comparing the values of the second counter and the second counter. .

  The analog signal comparators of the first and second inventions can be configured to be synchronously driven by an external clock or a clock generated from the pulse number comparison circuit.

  In the analog signal comparators of the first and second inventions, the first oscillation circuit can input an analog signal, convert the analog signal into the first pulse signal, and output the first pulse signal. In this case, the first oscillation circuit and the second oscillation circuit can be voltage controlled oscillators or current controlled oscillators.

  In the analog signal comparator according to the sixth aspect of the invention, the reference pulse generator may be configured to input an analog signal, convert the analog signal into a pulse signal, and output the pulse signal.

  According to the present invention, analog signals can be compared with a simple circuit in a short time. The analog signal comparator of the present invention can also be formed on one IC chip.

1A and 1B are functional block diagrams illustrating an embodiment of an analog signal comparator according to the first invention.
In FIG. 1A, an analog signal comparator 2A includes an oscillator (first oscillation circuit in the first invention) 21A, a VCO 22 (second oscillation circuit in the first invention), a pulse number comparison circuit 23, It consists of two shift registers 241,242.

  The oscillator 21A generates a pulse signal Pf1 (first pulse signal in the first invention: corresponding to the reference signal S1), and the VCO 22 inputs an analog signal S2 to be compared, which is input to the pulse signal Pf2 (first invention). To the second pulse signal).

  In FIG. 1A, a common clock CLCK 1 is input to the oscillators 21 A, VCO 22 and pulse number comparison circuit 23. At the rise of CLCK1, the oscillator 21A, VCO 22 and pulse number comparison circuit 23 are reset. In addition, at the timing synchronized with the fall of CLCK1, the oscillator 21A generates the pulse signal Pf1, and the VCO 22 generates the pulse signal Pf2.

The pulse number comparison circuit 23 detects the last bit of the shift register 241 and the last bit of the shift register 241 at a timing synchronized with the clock CLCK2 (not shown in FIG. 1A). The clock CLCK2 is a multiplied clock of the clock CLCK1, but is not shown in FIG.
The shift registers 241 and 242 receive the pulse signal Pf1 from the oscillator 21A and the pulse signal Pf2 from the VCO 22, and store the number of pulses, respectively.

  When the number of bits of the shift registers 241 and 242 is small, the oscillator 21A and the VCO 22 generate the first pulse signals Pf1 and Pf2 in synchronization (in the case of being synchronized in FIGS. 4A and 4B described later). However, when the number of bits of the shift registers 241 and 242 is large, the first pulse signals Pf1 and Pf2 need not be generated in synchronization. The shift registers 241 and 242 can be at least 2 bits.

  As shown in FIG. 3 (detailed explanatory diagram of the shift register in FIG. 1B), the pulse number comparison circuit 23 detects the value of each bit of the shift registers 241 and 242. Although all the bits of the shift registers 241 and 242 are detected in FIG. 3, some of the bits may be detected.

  By detecting only the value of each last bit, the number of pulses Pf1 and Pf2 can be compared. For example, the difference between S1 and S2 can be detected by detecting a plurality of bits of the shift registers 241 and 242. Specifically, when the sixth bit of the shift register 241 is 0 and the fifth bit is 1, and the third bit of the shift register 242 is 0, and the second bit is 1, S2 is approximately 2 / S1. It turns out that it is five.

  Further, the shift registers 241 and 242 are used by using the values of predetermined bits (one or more) of the shift registers 241 and 242 or by using signals (for example, outputs from the terminals X1 and X2) generated by the pulse number comparison circuit 23. Operations such as maintaining the state of 242 can be performed. FIG. 3 shows a circuit that uses the output generated by the pulse number comparison circuit 23 to turn off the gates G1 and G2, thereby holding the states of the shift registers 241 and 242.

  Although not shown, the pulse number comparison circuit 23 compares the two consecutive bits of the shift register 241 with the two consecutive bits of the shift register 242 to obtain “1, 1”, “0, 0” or “ When there is a combination of “0, 0” and “1, 1”, “1”, “0” or “0”, “1” can be output from the terminals X1 and X2.

  As shown in FIGS. 4A and 4B, the pulse number comparison circuit 23 sets the last bit of the shift register 241 to “1” before the pulse signal Pf2 when S1 is larger than S2. Set to 1 ”. At this time, “1” is output from the terminal X1 (the output of the terminal X2 is maintained at “0”). When S1 is smaller than S2, the last bit of the shift register 242 is set to the pulse signal pf2 before the pf1. Set to “1”. At this time, “1” is output from the terminal X2. When the pulse signal Pf2 and the pulse signal Pf1 simultaneously set the last bit of each shift register to 1, the same value (both “1” or both “0”) is output from the output terminals X1 and X2. Can be.

  FIG. 1B is a block diagram showing an analog signal comparator using a VCO 21B in place of the oscillator 21A of FIG. In FIG. 1B, the VCO 21B can receive an analog signal S1, convert it to a frequency signal (pulse signal) corresponding to the magnitude of the analog signal S1, and output it to the pulse number comparison circuit 23. . The outputs X1 and X2 of the pulse number comparison circuit 23 in FIG. 1B are the same as the outputs of the pulse number comparison circuit 23 in FIG.

  In the analog signal comparator 2A in FIG. 1A, the oscillator 21A, the VCO 22, the pulse number comparison circuit 23, and the shift registers 241, 242 are driven by the common CLCK1, but the present invention is not limited to this. For example, the oscillator 21A, the VCO 22, and the shift registers 241, 242 may be driven by a clock generated by the pulse number comparison circuit 23, or the oscillator 21A, the VCO 22 may be driven by a clock generated from appropriate bits of the shift registers 241, 242. The pulse number comparison circuit 23 may be driven (the oscillators 21A and VCO22, the pulse number comparison circuit 23, and the shift registers 241 and 242 are driven according to timing when both or one of the shift registers 241 and 242 overflows). You may do it). Similarly, in the analog signal comparator 2B of FIG. 1B, the VCO 21B, VCO 22, pulse number comparison circuit 23, and shift registers 241, 242 are driven by a common CLCK1, but the present invention is not limited to this. For example, the VCO 21B, the VCO 22, and the shift registers 241, 242 may be driven by a clock generated by the pulse number comparison circuit 23, or the VCO 21B, the VCO 22, The pulse number comparison circuit 23 may be driven (the VCO 21B and VCO 22, the pulse number comparison circuit 23, and the shift registers 241 and 242 are driven according to the timing when both or one of the shift registers 241 and 242 overflows). It may be)

  2A shows an analog signal comparator 2C that drives the oscillator 21C, VCO 22, and pulse width comparison circuit 23 by the output of the pulse number comparison circuit 23. FIG. 2B shows the pulse number comparison circuit 23. An analog signal comparator 2D that drives the VCO 21D, VCO 22, and pulse width comparison circuit 23 by the generated clock is shown. In these circuits, when one of the two output terminals X1 and X2 of the pulse number comparison circuit 23 becomes “1”, the rise of this “1” is used as a drive signal.

  In the analog signal comparator 2A of FIG. 1A, as shown in FIG. 4A, when the number of pulses of the pulse signal Pf1 reaches a predetermined number (here, 6), “1” is output from the terminal X1. Although the terminal X1 is returned to “0” when the number of pulses of the pulse signal Pf2 reaches the predetermined number, the timing for returning the terminal X1 to “0” is limited to FIG. For example, the output of the terminal X1 can be maintained at "1" until the next clock CLCK1 is input. Similarly, in the analog signal comparator 2B of FIG. 1B, as shown in FIG. 4B, when the number of pulses of the pulse signal Pf2 reaches a predetermined number (here, 6), the terminal X2 “ 1 "is output, and when the number of pulses of the pulse signal Pf1 reaches the predetermined number, the output of the terminal X2 is returned to" 0 ". The timing for returning the output of the terminal X2 to" 0 "is shown in FIG. For example, the output of the terminal X2 can be maintained at “1” until the next clock CLCK1 is input. In FIGS. 1A and 1B, two outputs (X1, X2) are obtained from the output terminal of the pulse number comparison circuit 23. However, the present invention is not limited to this, and one output or Three or more outputs may be obtained.

  An application example of the first invention will be described with reference to FIGS. In FIG. 5A, the bits of the first shift register 241 are indicated by a0 to an-1, and the bits of the second shift register 242 are indicated by b0 to bn-1.

  In FIG. 5B, the first shift register 241 is a0 to a7, the second shift register 242 is b0 to b7, a0 to a6 = 1, a7 = 0, b0 to b2 = 1, b3 to b7. The case of = 0 is shown. In this case, it can be expressed as S2 = (3/7) · S1. It can also be expressed as the difference between S1 and S2 (7-3) = 4.

  Further, for example, the value of the second shift register 242 is not compared with the value of the first shift register 241 as it is, and the value of the second shift register 242 added with 1 and the value of the first shift register 241 By comparing the values, it is possible to obtain the same effect as when S1 is compared with S1 plus a bias of (1/8) S2.

  6A and 6B are functional block diagrams showing an embodiment of the analog signal comparator of the second invention. 6A, an analog signal comparator 3A includes an oscillator (first oscillation circuit in the second invention) 31A, a VCO 32 (second oscillation circuit in the second invention), a pulse number comparison circuit 33, It consists of two counters 341 and 342.

  The oscillator 31A generates a pulse signal Pf1 (first pulse signal in the first invention: corresponding to the reference signal S1), and the VCO 32 inputs an analog signal S2 to be compared, which is supplied as a pulse signal Pf2 (second invention). To the second pulse signal).

  In FIG. 6A, a common clock CLCK1 is input to the oscillator 31A, the VCO 32, and the pulse number comparison circuit 33. At the rise of CLCK1, the oscillator 31A, the VCO 32, and the pulse number comparison circuit 33 are reset. Further, the oscillator 31A generates a pulse signal Pf1 and the VCO 32 generates a pulse signal Pf2 at a timing synchronized with the falling edge of CLCK1.

  The counters 341 and 342 receive the pulse signal Pf1 from the oscillator 31A and the pulse signal Pf2 from the VCO 32 and store the number of pulses, respectively. The pulse number comparison circuit 33 sets the value of the counter 341 (the number of pulse signals Pf1). ) And the value of the counter 342 (number of pulse signals Pf2) at a timing synchronized with the clock CLCK2 (not shown in FIG. 6A). The clock CLCK2 is a multiplied clock of the clock CLCK1, but is not shown in FIG. In FIG. 6A, the pulse number comparison circuit 33 checks the count values of the counters 341 and 342, and when one of the count values reaches a predetermined count value MAX, which counter is set to the value. Depending on whether or not it reaches, “0” or “1” is output from the terminals X1 and X2.

  The oscillator 31A and the VCO 32 may be driven synchronously when the predetermined count value MAX is small and asynchronously driven when the predetermined count value MAX is large.

  That is, the oscillator 31A and the VCO 32 generate the first pulse signal Pf1 and the pulse signal Pf2 synchronously when the predetermined count value MAX is small (in FIGS. 8A and 8B described later, synchronously). When the predetermined count value MAX is large, the first pulse signals Pf1 and Pf2 can be generated asynchronously.

  As shown in FIGS. 8A and 8B, the pulse number comparison circuit 33 sets “1” from the output terminal X1 when the counter 341 reaches a predetermined count value MAX before the counter 342. When the counter 342 reaches the predetermined count value MAX earlier than the counter 341, “1” is output from the terminal X2 (output of the terminal X2). Is maintained at “0”).

  In FIG. 8A, after the counter 341 reaches the predetermined count value MAX and the output of the terminal X1 becomes “1”, the counter 342 reaches the predetermined count value MAX, whereby the output terminal X1 becomes “0”. Shows the case. Similarly, in FIG. 8B, after the counter 342 reaches the predetermined count value MAX and the output terminal X2 becomes “1”, the counter 341 reaches the predetermined count value MAX. The case of “0” is shown.

  Although not shown, the pulse number comparison circuit 33 compares the count value of the counter 341 with the count value of the counter 342, and when the difference becomes 2 or -2, the output terminals X1 and X2 output “ “1”, “0” or “0”, “1” can also be output.

  When the counters 341 and 342 simultaneously reach the count value MAX, the same value (both “1” or both “0”) can be output from the output terminals X1 and X2.

  FIG. 6B is a block diagram showing an analog signal comparator using a VCO 31B in place of the oscillator 31A of FIG. In FIG. 6B, the VCO 31B can receive the analog signal S1, convert it to a frequency signal (pulse signal) corresponding to the magnitude of the analog signal S1, and output it to the pulse number comparison circuit 33. . The outputs X1 and X2 of the pulse number comparison circuit 33 in FIG. 6B are the same as the outputs of the pulse number comparison circuit 33 in FIG.

  In the analog signal comparator 3A shown in FIG. 6A, the oscillator 31A, the VCO 32, the pulse number comparison circuit 33, and the shift registers 341 and 342 are driven by the common CLCK1, but the present invention is not limited to this. For example, the oscillator 31A, the VCO 32, and the counters 341 and 342 may be driven by a clock generated by the pulse number comparison circuit 33, or the oscillator 31A, the VCO 32, and the pulse number comparison circuit 33 may be driven by a clock generated from the counters 341 and 342. (The oscillator 31A, the VCO 32, the pulse number comparison circuit 33, and the counters 341, 342 may be driven according to the timing when both or one of the counters 341, 342 overflows). Similarly, in the analog signal comparator 3B of FIG. 6B, the VCO 31B, the VCO 32, the pulse number comparison circuit 33, and the shift registers 341 and 342 are driven by the common CLCK1, but the present invention is not limited to this. For example, the VCO 31B, the VCO 32, and the counters 341 and 342 may be driven by a clock generated by the pulse number comparison circuit 33, or the VCO 31B, the VCO 32, and the pulse number comparison circuit 33 may be driven by a clock generated from the counters 341 and 342. (The VCO 31B and VCO 32, the pulse number comparison circuit 33, and the counters 341 and 342 may be driven according to the timing when both or one of the counters 341 and 342 overflows).

    7A shows an analog signal comparator 3C that drives the oscillator 31C, the VCO 32, and the pulse width comparison circuit 33 by the output of the pulse number comparison circuit 33. FIG. 7B shows the pulse number comparison circuit 33. An analog signal comparator 3D that drives the VCO 31D, the VCO 32, and the pulse width comparison circuit 33 by the generated clock is shown. In these circuits, when one of the two output terminals X1 and X2 of the pulse number comparison circuit 33 becomes “1”, the rise of this “1” is used as a drive signal.

  In the analog signal comparator 3A of FIG. 6A, as shown in FIG. 8A, when the number of pulses of the pulse signal Pf1 reaches a predetermined number (here, 6), “1” is output from the output terminal X1. When the number of pulses of the pulse signal Pf2 reaches the predetermined number, the output terminal X1 is returned to “0”. The timing for returning the output terminal X1 to “0” is shown in FIG. For example, the output of the output terminal X1 can be maintained at “1” until the next clock CLCK1 is input. Similarly, in the analog signal comparator 3B in FIG. 6B, as shown in FIG. 8B, when the number of pulses of the pulse signal Pf2 reaches a predetermined number (here, 6), the output terminal X2 When “1” is output and the number of pulses of the pulse signal Pf1 reaches the predetermined number, the output terminal X2 is returned to “0”. The timing for returning the output terminal X2 to “0” is shown in FIG. For example, the output of the output terminal X2 can be maintained at “1” until the next clock CLCK1 is input.

  In FIGS. 6A and 6B, two outputs (X1, X2) are obtained from the output terminal of the pulse number comparison circuit 33. However, the present invention is not limited to this, and one output or Three or more outputs may be obtained.

  An application example of the first invention will be described with reference to FIGS. In FIG. 9A, the first counter 341 is indicated by p0 to pn-1, and the second counter 342 is indicated by q0 to qn-1. By shifting the value of the second counter 342 to the left by x bits, the value can be raised to the power of 2 by x, and by shifting the value of the second counter 342 to the right by y bits, the value can be changed. 2 to the power of −y. FIG. 9B shows a case where the value of the second counter 342 is shifted by 1 bit to the left to square the value. In FIG. 9C, the value of the second counter 342 is shifted to the right. A case where the value is raised to the (1/2) th power by shifting by 1 bit is shown. A value obtained by calculating the difference between the first counter 341 and the second counter 342 is stored in a predetermined register, and further shifted to the right or left by z bits to further reduce this value to the 2 z power (or -Z).

  Of course, although not shown, the number of pulses can be compared using the shift register described in FIGS. 1 to 4, or the number of pulses can be compared using the counter described in FIGS. .

FIG. 10 is a functional block diagram showing a related technique of the analog signal comparator of the present invention. In FIG. 10, an analog signal comparator 7 includes first to kth oscillation circuits 71, 72/1, 72/2,..., 72 / k−1 that generate first to kth pulse signals. , 74 / k to which the first to kth pulse signals from the first to kth oscillation circuits are inputted, and the first to kth shift registers 74/1, 74/2,. The values of all or some bits of the k-th shift register are detected, and the number of the first to k-th pulse signals generated by the first to k-th oscillation circuits based on these detected values. And a pulse number comparison circuit 73 for comparing. Here, at least one of the first to kth oscillation circuits can be configured to input an analog signal, convert the analog signal into a pulse signal, and output the pulse signal. The pulse number comparison circuit 73 can perform various processes using outputs from the first to kth oscillation circuits.

FIG. 11 is a functional block diagram showing another related technique of the analog signal comparator of the present invention. In FIG. 11, an analog signal comparator 8 includes first to kth oscillation circuits 81 1 , 82/1, 82/2,..., 82 / k−1 that generate first to kth pulse signals. , 84 / k to which the first to kth pulse signals from the first to kth oscillation circuits are inputted, and the first to kth counters 84/1, 84/2,. A pulse number comparison circuit 83 that compares the number of pulses from the first to kth oscillation circuits by comparing the values of the counters of k with each other is provided. Here, at least one of the first to kth oscillation circuits can be configured to input an analog signal, convert the analog signal into a pulse signal, and output the pulse signal. The pulse number comparison circuit 83 can perform various processes using outputs from the first to kth oscillation circuits.

  In the above embodiments, the case where the analog signal is a voltage has been described. However, the present invention can also be applied when the analog signal is a current. In this case, a current controlled oscillator is used instead of the VCO.

(A), (B) is a functional block diagram which shows embodiment of the analog signal comparator of 1st invention. (A), (B) is a functional block diagram which shows other embodiment of the analog signal comparator of 1st invention. FIG. 2 is a detailed explanatory diagram of the shift register of FIG. (A), (B) is operation | movement explanatory drawing of the analog signal comparator of 1st invention. (A), (B) is explanatory drawing which shows the application example of 1st invention. (A), (B) is a functional block diagram which shows embodiment of the analog signal comparator of 2nd invention. (A), (B) is a functional block diagram which shows other embodiment of the analog signal comparator of 2nd invention. (A), (B) is operation | movement explanatory drawing of the analog signal comparator of 2nd invention. (A), (B) is explanatory drawing which shows the application example of 2nd invention. It is a functional block diagram which shows embodiment of the analog signal comparator of 4th invention. It is a functional block diagram which shows embodiment of the analog signal comparator of 5th invention. (A) is a figure which shows the conventional analog type comparator, (B) is explanatory drawing which shows the operation | movement. It is a functional block diagram showing a conventional digital comparator.

Explanation of symbols

2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D Analog signal comparator 21A, 21C, 31A, 31C Oscillator 21B, 21D, 22, 31B, 31D, 32 VCO
23, 33 Pulse number comparison circuit 241, 242 Shift register 341, 342 Counter

Claims (5)

A first oscillation circuit for generating a first pulse signal;
A second oscillation circuit that inputs an analog signal, converts the analog input signal into a second pulse signal, and outputs the second pulse signal;
A first shift register for inputting a first pulse signal from the first oscillation circuit;
A second shift register for inputting a second pulse signal from the second oscillation circuit;
Detecting all bits or values of some bits of said first and said second shift register, based on these detected values, the number of the first pulse signal of the first oscillator circuit generates said a pulse number comparison circuit for comparing the number of the second pulse signal the second oscillation circuit generates,
An analog signal comparator comprising: A first oscillation circuit for generating a first pulse signal;
A second oscillation circuit that inputs an analog signal, converts the analog input signal into a second pulse signal, and outputs the second pulse signal;
A first counter for inputting a first pulse signal from the first oscillation circuit;
A second counter for inputting a second pulse signal from the second oscillation circuit;
By comparing the values of said first and said second counter, and the pulse number from the first oscillation circuit, and the pulse number comparison circuit for comparing a pulse number from the second oscillator circuit,
An analog signal comparator comprising:   3. The analog signal comparator according to claim 1, wherein the analog signal comparator is synchronously driven by an external clock or a clock generated from the pulse number comparison circuit.   4. The analog signal comparator according to claim 1, wherein the first oscillation circuit receives an analog signal, converts the analog signal into the first pulse signal, and outputs the first pulse signal. 5.   The analog signal comparator according to claim 4, wherein the first oscillation circuit and the second oscillation circuit are voltage controlled oscillators or current controlled oscillators.

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