JP5271287B2 - インタフェース・プロセッサ - Google Patents

インタフェース・プロセッサ Download PDF

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Publication number
JP5271287B2
JP5271287B2 JP2009553206A JP2009553206A JP5271287B2 JP 5271287 B2 JP5271287 B2 JP 5271287B2 JP 2009553206 A JP2009553206 A JP 2009553206A JP 2009553206 A JP2009553206 A JP 2009553206A JP 5271287 B2 JP5271287 B2 JP 5271287B2
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JP
Japan
Prior art keywords
thread
port
activity
processor
indication
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JP2009553206A
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English (en)
Japanese (ja)
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JP2010521730A (ja
JP2010521730A5 (https=
Inventor
メイ，デービット
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xmos Ltd
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Xmos Ltd
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Publication of JP2010521730A5 publication Critical patent/JP2010521730A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
JP2009553206A 2007-03-14 2008-03-13 インタフェース・プロセッサ Active JP5271287B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/717,622 2007-03-14
US11/717,622 US8219789B2 (en) 2007-03-14 2007-03-14 Interface processor
PCT/GB2008/000870 WO2008110799A1 (en) 2007-03-14 2008-03-13 Interface processor

Publications (3)

Publication Number Publication Date
JP2010521730A JP2010521730A (ja) 2010-06-24
JP2010521730A5 JP2010521730A5 (https=) 2013-02-21
JP5271287B2 true JP5271287B2 (ja) 2013-08-21

Family

ID=39433789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009553206A Active JP5271287B2 (ja) 2007-03-14 2008-03-13 インタフェース・プロセッサ

Country Status (6)

Country Link
US (1) US8219789B2 (https=)
EP (1) EP2137616B1 (https=)
JP (1) JP5271287B2 (https=)
KR (1) KR101501181B1 (https=)
CN (1) CN101681274B (https=)
WO (1) WO2008110799A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5173714B2 (ja) 2008-09-30 2013-04-03 ルネサスエレクトロニクス株式会社 マルチスレッドプロセッサ及びその割り込み処理方法
US8447960B2 (en) * 2010-01-08 2013-05-21 International Business Machines Corporation Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition
US20110173420A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Processor resume unit
JP2014211890A (ja) * 2014-06-25 2014-11-13 ルネサスエレクトロニクス株式会社 マルチスレッドプロセッサ及びその割り込み処理方法
CN110908491B (zh) * 2018-08-28 2023-08-08 上海忆芯实业有限公司 功耗控制方法、控制部件及其电子系统
US11288072B2 (en) * 2019-09-11 2022-03-29 Ceremorphic, Inc. Multi-threaded processor with thread granularity

Family Cites Families (22)

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US5515538A (en) 1992-05-29 1996-05-07 Sun Microsystems, Inc. Apparatus and method for interrupt handling in a multi-threaded operating system kernel
US5944816A (en) 1996-05-17 1999-08-31 Advanced Micro Devices, Inc. Microprocessor configured to execute multiple threads including interrupt service routines
US6985431B1 (en) * 1999-08-27 2006-01-10 International Business Machines Corporation Network switch and components and method of operation
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6976095B1 (en) * 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US6952824B1 (en) * 1999-12-30 2005-10-04 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US7480706B1 (en) * 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US6799317B1 (en) 2000-06-27 2004-09-28 International Business Machines Corporation Interrupt mechanism for shared memory message passing
US20020091956A1 (en) * 2000-11-17 2002-07-11 Potter Scott T. Methods and systems for reducing power consumption in computer data communications
JP3698987B2 (ja) * 2000-12-18 2005-09-21 エヌイーシーコンピュータテクノ株式会社 バッファ制御装置、汎用ポート制御装置、入出力システム、情報処理装置
US20020161957A1 (en) 2001-02-09 2002-10-31 Guillaume Comeau Methods and systems for handling interrupts
US20030065741A1 (en) * 2001-09-29 2003-04-03 Hahn Vo Concurrent bidirectional network communication utilizing send and receive threads
JP2003167748A (ja) * 2001-11-30 2003-06-13 Fujitsu Ltd マルチスレッド計算機
KR100429543B1 (ko) * 2002-05-25 2004-04-29 삼성전자주식회사 네트워크 프로세서에서 다양한 개수의 포트들을 처리하기위한 방법
JP2004220070A (ja) * 2003-01-09 2004-08-05 Japan Science & Technology Agency コンテキスト切り替え方法及び装置、中央演算装置、コンテキスト切り替えプログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体
US7496915B2 (en) 2003-04-24 2009-02-24 International Business Machines Corporation Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes
US7350060B2 (en) * 2003-04-24 2008-03-25 International Business Machines Corporation Method and apparatus for sending thread-execution-state-sensitive supervisory commands to a simultaneous multi-threaded (SMT) processor
JP4740851B2 (ja) * 2003-08-28 2011-08-03 ミップス テクノロジーズ インコーポレイテッド 仮想プロセッサリソースの動的構成のための機構体
US7203100B2 (en) * 2004-11-01 2007-04-10 Sun Mircosystems, Inc. Efficient implementation of a read scheme for multi-threaded register file
US7149832B2 (en) 2004-11-10 2006-12-12 Microsoft Corporation System and method for interrupt handling
US8745627B2 (en) * 2005-06-27 2014-06-03 Qualcomm Incorporated System and method of controlling power in a multi-threaded processor
US8074026B2 (en) * 2006-05-10 2011-12-06 Intel Corporation Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems

Also Published As

Publication number Publication date
US20080229311A1 (en) 2008-09-18
JP2010521730A (ja) 2010-06-24
US8219789B2 (en) 2012-07-10
CN101681274A (zh) 2010-03-24
CN101681274B (zh) 2014-12-17
WO2008110799A1 (en) 2008-09-18
EP2137616B1 (en) 2013-10-30
KR101501181B1 (ko) 2015-03-18
KR20090122992A (ko) 2009-12-01
EP2137616A1 (en) 2009-12-30

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