JP5262487B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device constituted by sticking a first substrate having an element region and a second substrate for sealing the element region together, wherein the substrates is excellently joined together to improve the sealing property for the element region. <P>SOLUTION: The method of manufacturing the semiconductor device 1 constituted by joining the second substrate 200 to the first substrate 100 having the element region 110 to seal the element region 110 includes feeding electricity to a heating metal layer 150 when the first substrate 100 and second substrate 200 are joined together with a substrate joining member 160 interposed. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A semiconductor device having a first substrate having an element region and a second substrate for sealing the element region and bonding the first substrate and the second substrate is known. For example, Patent Document 1 discloses that when manufacturing such a semiconductor device, a first substrate and a second substrate are bonded to each other through a joint portion made of solder and a reflow process is performed. A technique for sealing each element by joining a second substrate via solder is disclosed.

JP 2005-251898 A

  However, when the first substrate and the second substrate are bonded through the reflow process as in the prior art, each substrate is deformed due to the influence of heat applied in the reflow process, and the bonding between the substrates is As a result, there is a problem that the sealing performance of the element is lowered.

  The problem to be solved by the present invention is that a semiconductor device in which a first substrate having an element region and a second substrate for sealing the element region are bonded together can satisfactorily bond each substrate, It is an object of the present invention to provide a method for manufacturing a semiconductor device with improved sealing performance in an element region.

A method of manufacturing a semiconductor device in which a second substrate is bonded to a first substrate having an element region in order to seal the element region, wherein the extraction electrode is provided on the first substrate or the second substrate. Forming a first insulating film in a region other than the element region on the first substrate, forming a second heating metal member on the first insulating film, and the first (2) forming a second insulating film so as to cover the heating metal member, forming a wiring from the element region on the second insulating film, and forming a first heating on the second insulating film. A step of forming a metal member, a step of forming a substrate bonding member on the first heating metal member, a step of electrically connecting the lead electrode and the wiring via the electrode bonding member, The first substrate and the second substrate are opposed to each other, and the substrate bonding member is To, bonded to the first substrate and the second substrate, to provide a method of manufacturing a semiconductor device having a step of energizing the first heating metal member.

  According to the present invention, the heat generated by energizing the heated metal member causes the substrate bonding member to be in a molten state, and the first substrate and the second substrate are bonded via the substrate bonding member. Heat can be prevented from diffusing to the whole and the second substrate, the first substrate and the second substrate can be satisfactorily bonded, and the element region can be appropriately sealed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a cross-sectional view of a semiconductor device 1 according to the first embodiment.

  As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a first substrate 100 and a second substrate 200, and is configured by bonding the second substrate 200 to the first substrate 100.

  The first substrate 100 is, for example, silicon, and a plurality of elements 111 are formed in the element region 110 by using a semiconductor manufacturing technique. The plurality of elements 111 are sealed from the outside air by bonding the second substrate 200 to the first substrate 100.

  Specifically, a first heating metal layer 150 and a substrate bonding layer 160 are formed on the first substrate 100. As shown in FIG. 2, the first heating metal layer 150 and the substrate bonding layer 160 are: It is formed along the circumferential direction of the first substrate 100. Then, the first substrate 100 is bonded to the metal pattern layer 230 of the second substrate 200 via the substrate bonding layer 160, whereby the first substrate 100 and the second substrate 200 are bonded to each other, and the plurality of elements 111. However, it will be sealed from outside air. FIG. 2 is a top view of the first substrate 100 constituting the semiconductor device 1 according to the first embodiment (that is, a top view in a state where the second substrate 200 is removed from the semiconductor device 1).

  Although it does not specifically limit as the some element 111 formed in the 1st board | substrate 100, For example, an infrared sensor etc. are mentioned. When the plurality of elements 111 are infrared sensors, the second substrate 200 is preferably made of a material that can pass through the infrared wavelength region. Examples of such a material include ZnS, ZnSe, Examples thereof include Ge and chalcogenide glass. In addition, a cavity is formed in the first substrate 100 below the element region 110 where the plurality of elements 111 are formed in order to improve the characteristics of the elements 111. The cavity of the first substrate 100 can be formed by, for example, wet etching.

  As shown in FIGS. 1 and 2, four pairs of wirings 120 electrically connected to the element region 110 are formed on the first substrate 100. The wiring 120 is made of a conductive metal material such as copper (Cu). Further, metal bumps 130 are formed on the wirings 120 in the vicinity of the end portions.

  On the other hand, the through electrode 210 is formed on the second substrate 200, and the through electrode 210 maintains a hermetic structure by filling the through hole formed in the second substrate 200 with a metal such as Cu. Formed with. Further, the second substrate 200 is provided with an electrode pad 220 made of a metal such as gold, copper, or aluminum at the end of the through electrode 210.

  Then, each wiring 120 formed on the first substrate 100 is electrically connected to the electrode pad 220 and the through electrode 210 formed on the second substrate 200 via the metal bumps 130 formed on each wiring 120. Thus, power is supplied to the element region 110 from the through electrode 210 and an electric signal from the element region 110 is taken out.

  Note that the metal bumps 130 formed on each wiring 120 electrically connect the wiring 120 and the electrode pad 220 by making contact with the electrode pad 220 of the second substrate 200. The metal bump 130 is preferably made of a deformable material having a low Young's modulus such as gold or solder such as Sn—Pb. By configuring the metal bump 130 with a deformable material having a low Young's modulus, the stress applied between the first substrate 100 and the second substrate 200 can be relaxed by the metal bump 130.

Further, as shown in FIG. 1, an insulating film 140 is formed on the surface of the first substrate 100 on the portion where the wiring 120 is formed and the portion where the first heating metal layer 150 is formed. . The insulating film 140 is formed to thermally and electrically insulate the first substrate 100 from the wiring 120 and the first heating metal layer 150. For example, when the first substrate is made of silicon, the insulating film 140 can be made of a silicon oxide film (SiO ₂ ) by performing a thermal oxidation process on the first substrate. . Alternatively, the insulating film 140 may be an organic insulating film other than the silicon oxide film.

  FIG. 3 is an enlarged view of a portion A in FIG. As shown in FIG. 3, the first heating metal layer 150 formed on the insulating film 140 includes a heating metal layer intermediate layer formed on the upper surface and the lower surface of the first heating member layer 151 and the first heating member layer 151. 152, 153. The material of the first heating member layer 151 is not particularly limited, but is preferably a metal having a melting point of 1000 ° C. or higher. For example, platinum (Pt), molybdenum (Mo), tungsten (W), nickel (Ni) And tantalum (Ta).

  The heating metal layer intermediate layer 152 is a layer formed to ensure adhesion between the first heating member layer 151 and the insulating film 140, and is made of, for example, titanium (Ti), chromium (Cr), or the like. The Similarly, the heating metal layer intermediate layer 153 is a layer formed to ensure adhesion between the first heating member layer 151 and the bonding layer intermediate layer 162 constituting the substrate bonding layer 160. , Titanium (Ti), chromium (Cr) and the like.

  The first heating metal layer 150 is formed on the insulating film 140 in the order of the heating metal layer intermediate layer 152, the first heating member layer 151, and the heating metal layer intermediate layer 153 (that is, the metal material (that is, the heating metal layer intermediate layer 153). , Cr, Ti, Pt, Mo, W, Ni, Ta, etc.).

  The substrate bonding layer 160 includes a bonding member layer 161 and a bonding layer intermediate layer 162. If the joining member layer 161 is made into a molten state by heating, the first heating metal layer 150 of the first substrate 100 and the metal pattern layer 230 of the second substrate 200 can be joined thereby. Although it is good and is not particularly limited, it is preferably composed of a metal having a melting point of 700 ° C. or lower. Specific examples of the material constituting the bonding member layer 161 include solder, aluminum (Al), lead (Pb), tin (Sn), and the like. Alternatively, the bonding member layer 161 may be made of a conductive resin that softens when heated.

  The bonding layer intermediate layer 162 is a layer formed in order to ensure adhesion between the bonding member layer 161 and the heating metal layer intermediate layer 153 of the first heating metal layer 150, such as gold (Au). Consists of

  Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. FIG. 4 is a perspective view for explaining the method for manufacturing the semiconductor device 1 of the first embodiment. As shown in FIG. 4, the semiconductor device 1 according to the first embodiment manufactures a first substrate 100 on which a plurality of elements 111 are formed and a second substrate 200 for sealing the plurality of elements 111, The first substrate 100 and the second substrate 200 are manufactured by bonding them with the substrate bonding layer 160 interposed therebetween. In FIG. 4, the members constituting the first substrate 100 and the second substrate 200 other than the first heating metal layer 150 and the substrate bonding layer 160 are not shown.

  FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device 1 of the first embodiment. As shown in FIG. 5, when manufacturing the semiconductor device 1, first, using the wafer 300, a plurality of first regions having element regions 110 including a plurality of elements 111 are formed on the wafer 300 by a semiconductor manufacturing technique. The substrate 100 is manufactured. Then, the plurality of second substrates 200 are attached to the plurality of first substrates 100 formed on the wafer 300 to form the plurality of semiconductor devices 1 on the wafer 300. Next, the wafer 300 is manufactured by separating the plurality of semiconductor devices 1 formed on the wafer 300 by performing a dicing process.

  Hereinafter, the manufacturing process of the semiconductor device 1 of the first embodiment will be described in detail. 6A to 6E are views for explaining a manufacturing process of the semiconductor device 1 of the first embodiment. 6A to 6E correspond to enlarged views of a portion A of the semiconductor device 1 shown in FIG.

First, an element region 110 including a plurality of elements 111 shown in FIG. 1 is formed on the first substrate 100 by a semiconductor manufacturing technique, and then an insulating film 140 is formed on the surface of the first substrate 100 as shown in FIG. 6A. To do. When the first substrate 100 is a silicon substrate, a silicon oxide film (SiO ₂ ) as the insulating film 140 can be formed by performing a thermal oxidation process. Alternatively, when the insulating film 140 is formed using an organic material, the insulating film 140 can be formed by a method of applying an organic material.

  Next, as shown in FIG. 6B, after forming the insulating film 140 on the first substrate 100, the wiring 120 for supplying power to the element region 110 and extracting electric signals from the element region 110 is formed. The wiring 120 can be formed, for example, by sputtering a metal that forms the wiring 120.

  Further, as shown in FIG. 6B, before or after or simultaneously with this, the heating metal layer intermediate layer 152, which forms the first heating metal layer 150, on the insulating film 140 of the first substrate 100, the first One heating member layer 151, a heating metal layer intermediate layer 153, and a bonding layer intermediate layer 162 that constitutes the substrate bonding layer 160 are formed in this order. Each layer 152, 151, 153, 162 can be formed by sputtering each metal constituting these layers in this order.

  Next, as illustrated in FIG. 6C, the bonding member layer 161 that forms the substrate bonding layer 160 is formed on the bonding layer intermediate layer 162. When aluminum, lead, or tin is used as the material constituting the bonding member layer 161, the bonding member layer 161 can be formed by sputtering these metals on the bonding layer intermediate layer 162. Alternatively, when solder is used as a material constituting the bonding member layer 161, the bonding member layer is formed on the bonding layer intermediate layer 162 by laminating sheet solder on the bonding layer intermediate layer 162 or using paste solder. 161 is formed.

  In addition, after the bonding member layer 161 is formed, metal bumps 130 are formed on the wiring 120 as shown in FIG. 6C. The metal bump 130 may be formed using, for example, a wire bond.

  On the other hand, as shown in FIG. 6D, an electrode pad 220 is formed at the end of the through electrode 210 for the second substrate 200 on which the through electrode 210 is formed. The electrode pad 220 can be formed by sputtering using a metal that forms the electrode pad 220, electroless plating, electrolytic plating, or the like. In addition, before or after this, or simultaneously, the metal pattern layer 230 is formed on the second substrate 200. The metal pattern layer 230 may be formed by sputtering using a metal that will form the metal pattern layer 230 at a position corresponding to the position where the first heating metal layer 150 and the substrate bonding layer 160 are formed on the first substrate 100, or without any metal. It can be formed by electrolytic plating or electrolytic plating.

  Next, as shown in FIG. 6E, the metal bumps 130 of the first substrate 100, the electrode pads 220 of the second substrate 200, the first heating metal layer 150 of the first substrate 100, and the metal pattern of the second substrate 200. The first substrate 100 and the second substrate 200 are aligned so that the layers 230 are in corresponding positions, and the layers 230 are overlaid and pressed from above.

  In the first embodiment, when the first substrate 100 and the second substrate 200 are overlapped and pressed, the first heating metal layer 150 is energized by applying a pulse voltage, and the energization by applying the pulse voltage is performed. The first heating metal layer 150 is heated by this, and the temperature of the first heating metal layer 150 is raised, thereby melting the bonding member layer 161. Thus, the first heating metal layer 150 of the first substrate 100 and the metal pattern layer 230 of the second substrate 200 are bonded via the bonding member layer 161. That is, the first substrate 100 and the second substrate 200 are bonded via the bonding member layer 161, whereby the first substrate 100 and the second substrate 200 are bonded together, and the plurality of elements 111 are sealed from the outside air. Stop.

  The timing for applying the pulse voltage to the first heating metal layer 150 and energizing the first heating metal layer 150 is preferably when the first substrate 100 and the second substrate 200 are superposed and pressurized, but is not particularly limited. It may be after the substrate 100 and the second substrate 200 are overlapped. The heating temperature of the first heating metal layer 150 may be a temperature between the melting point of the first heating member layer 151 constituting the first heating metal layer 150 and the melting point of the bonding member layer 161, and is not particularly limited. The temperature is usually 200 to 700 ° C, preferably 200 to 300 ° C.

  When energizing the first heating metal layer 150, for example, as shown in FIG. 7, a plurality of semiconductor devices 1 before dicing are laid out on the wafer 300, and the first heating metal layer of each semiconductor device 1 is laid out. For example, the first heating metal layer 150 of each semiconductor device 1 may be energized while the 150 is electrically connected in series or in parallel. Here, FIG. 7 is a figure for demonstrating an example of the electricity supply method of the 1st heating metal layer 150 in 1st Embodiment.

  In the example shown in FIG. 7, a power input electrode pad 310 and a lead wiring 320 are provided in the wafer 300 in order to pass a current through each first heating metal layer 150 of each semiconductor device 1. A voltage is applied to each first heated metal layer 150 of each semiconductor device 1 from the power supply 400 via these. Note that the connection mode and the number of connections when the first heating metal layer 150 of the semiconductor device 1 is electrically connected in series or in parallel are appropriately adjusted according to the current value and the voltage value applied to the first heating metal layer 150. do it. For example, when a material having a high resistance value is used as the material constituting the first heating metal layer 150, it is difficult to increase the voltage value setting value for reasons of dielectric breakdown. It is desirable to increase the number.

  FIG. 8 is a graph showing the relationship between the pulse voltage applied to the first heating metal layer 150, the temperature of the first heating metal layer 150, the temperature of the substrate bonding layer 160, and the temperature of the element region 110. As shown in FIG. 8, according to the first embodiment, by applying a pulse voltage to the first heating metal layer 150, the first heating metal layer 150 and the substrate bonding layer 160 are made to have a melting point higher than that of the substrate bonding layer 160. Can be heated. On the other hand, the temperature of the element region 110 also increases as the temperature of the first heating metal layer 150 increases, and continues to increase even after the application of the pulse voltage, but the temperature rise of the element region 110 itself is small. Can do.

  According to the first embodiment, the first heating metal layer 150 is energized, the first heating metal layer 150 is heated, and the heat generated from the first heating metal layer 150 brings the substrate bonding layer 160 into a molten state. Thus, the first heating metal layer 150 of the first substrate 100 and the metal pattern layer 230 of the second substrate 200 are bonded via the substrate bonding layer 160, whereby the first substrate 100 and the second substrate 200 are bonded. It is what is pasted together. Therefore, according to the first embodiment, it is possible to effectively prevent heat from diffusing over the entire first substrate 100 and the entire second substrate 200, and the first substrate 100 and the second substrate due to heat diffusion. The deformation of the substrate 200 can be prevented. As a result, the bonding in the surface direction of the bonding portion constituted by the first heating metal layer 150, the substrate bonding layer 160, and the metal pattern layer 230 can be made sufficient. Can be secured.

<< Second Embodiment >>
Next, a second embodiment of the present invention will be described. 9 is an enlarged view of a main part of the semiconductor device 1a according to the second embodiment, FIG. 10 is a top view of the first substrate 100 constituting the semiconductor device 1a according to the second embodiment, and FIGS. 11A to 11F are the second embodiment. It is a figure for demonstrating the manufacturing process of the semiconductor device 1a which concerns on a form. In addition, FIG. 9, FIG. 11A-FIG. 11F are equivalent to the figure which expanded and showed the A section of FIG. 1 in 1st Embodiment. FIG. 10 corresponds to a top view of the semiconductor device 1a with the second substrate 200 removed.

  As shown in FIG. 8, in the semiconductor device 1 a according to the second embodiment, the first insulating film 141 and the second insulating film 142 are formed on the surface of the first substrate 100, and the second insulating film 142 is formed. The semiconductor device 1 has the same configuration as that of the semiconductor device 1 according to the first embodiment except that the second heating metal layer 170 is formed therein.

  As shown in FIG. 9, the second heating metal layer 170 is disposed in the second insulating film 142 and directly below the metal bumps 130, and includes the second heating member layer 171 and the second heating member. It consists of intermediate layers 172 and 173 for heating metal layers formed on the upper and lower surfaces of the layer 171. The second heating metal layer 170 is heated by energization, and thereby heats the metal bumps 130 formed on the wiring 120. The second heating metal layer 170 is disposed immediately below the metal bumps 130, and at least the metal bumps are disposed. It has a width of 130 or more diameters.

  As shown in FIG. 10 which is a top view of the first substrate constituting the semiconductor device 1a, the second heating metal layer 170 is formed corresponding to the formation position of each metal bump 130, and the metal bump 130 is also formed. In the vicinity, the formation width is narrowed, so that the resistance value is increased in the vicinity of the metal bump 130. And by setting it as such a structure, the metal bump 130 can be heated effectively, making resistance value in another part small. In the example shown in FIG. 10, the width of the second heating metal layer 170 is changed to change the resistance value between the vicinity of the metal bump 130 and the other portions. It is also possible to adopt a configuration in which the resistance value is varied by changing the thickness of the metal layer 170.

  Next, a method for manufacturing the semiconductor device 1a of the second embodiment will be described with reference to FIGS. 11A to 11F.

First, in the same manner as in the first embodiment, an element region 110 including a plurality of elements 111 shown in FIG. 1 is formed by a semiconductor manufacturing technique, and then a first insulating film 141 is formed as shown in FIG. 11A. When the first substrate 100 is a silicon substrate, the first insulating film 141 can be made of a silicon oxide film (SiO ₂ ) by performing a thermal oxidation process. Alternatively, the insulating film 140 may be formed of an organic material. In this case, the insulating film 140 can be formed by a method of applying an organic material.

  Next, as shown in FIG. 11A, the heating metal layer intermediate layer 172, the second heating member layer 171, and the heating metal layer intermediate that constitute the second heating metal layer 170 are formed on the first insulating film 141. Layer 173 is formed in this order. Each of the layers 172, 171 and 173 can be formed by sputtering the respective metals constituting them in this order. Specifically, the intermediate layer 172 for heating metal layers can be composed of, for example, titanium (Ti), chromium (Cr), or the like, and can be formed by sputtering these metals. The second heating member layer 171 can be made of, for example, platinum (Pt), molybdenum (Mo), tungsten (W), nickel (Ni), tantalum (Ta), etc., and these metals are sputtered. Can be formed. Further, the heating metal layer intermediate layer 173 can be made of, for example, titanium (Ti), chromium (Cr), or the like, and can be formed by sputtering these metals.

  Next, as shown in FIG. 11B, a second insulating film 142 is formed on the first insulating film 141 on which the second heated metal layer 170 is formed.

  Here, since the second heated metal layer 170 is heated by being energized, and thereby heats the metal bump 130 shown in FIG. 9, the heat generated by the second heated metal layer 170 is as much as possible. It is preferable to adopt a configuration that does not dissipate heat. Therefore, it is preferable to adjust the heat dissipation characteristics by using the first insulating film 141 and the second insulating film 142, and thereby to prevent the heat generated by the second heating metal layer 170 from being dissipated as much as possible.

For example, by adjusting the thermal conductivity of the first insulating film 141 and the second insulating film 142, by making the thermal conductivity of the second insulating film 142 higher than the thermal conductivity of the first insulating film 141, The heat dissipation characteristics can be adjusted. In this case, the first insulating film 141 is preferably formed of a silicon oxide film (SiO ₂ ) or an organic material having insulating properties and low thermal conductivity, and the second insulating film 142 has insulating properties. It is preferably formed of a material having a high thermal conductivity (for example, a Poly-Dia layer). Alternatively, the thickness of the first insulating film 141 and the second insulating film 142 is adjusted, and the thickness of the second insulating film 142 is made thinner than the thickness of the first insulating film 141, thereby adjusting the heat dissipation characteristics. Also good.

  Next, as in the first embodiment, as shown in FIG. 11C, the wiring 120 is formed on the second insulating film 142, and the first heating metal layer 150 is formed before, after, or simultaneously with the wiring 120. The intermediate layer for heating metal layer 152, the first heating member layer 151, the intermediate layer for heating metal layer 153, and the bonding layer intermediate layer 162 that constitutes the substrate bonding layer 160 are formed in this order. To do.

  Next, as in the first embodiment, as illustrated in FIG. 11D, a bonding member layer 161 that forms the substrate bonding layer 160 is formed on the bonding layer intermediate layer 162. In addition, after the bonding member layer 161 is formed, the metal bump 130 is formed on the wiring 120. In the second embodiment, the metal bump 130 is preferably made of a material that is easily melted by being heated by the second heating member layer 171, and is preferably made of, for example, solder having a low melting point. . In addition, when copper is used as a material constituting the wiring 120, Ni—Au or the like is used between the wiring 120 and the metal bump 130 from the viewpoint of wettability of solder to the wiring 120 and prevention of oxidation of the wiring 120. A plating film or a metal vapor deposition film may be formed.

  Next, as in the first embodiment, as shown in FIG. 11E, the electrode pad 220 and the metal pattern layer 230 are formed on the second substrate 200 on which the through electrode 210 is formed.

  Next, as in the first embodiment, as shown in FIG. 11F, the first substrate 100 and the second substrate 200 are aligned, overlapped, and pressurized from above. Further, similarly to the first embodiment, the first heating metal layer 150 is energized, the first heating metal layer 150 is heated, and the temperature of the first heating metal layer 150 is increased, so that the bonding member layer 161 is formed. The first substrate 100 and the second substrate 200 are bonded to each other through the bonding member layer 161, and the plurality of elements 111 are sealed from the outside air.

  In the second embodiment, when the first heated metal layer 150 is energized and heated, or before or after that, the second heated metal layer 170 is also energized to heat it. Thereby, the temperature of the 2nd heating metal layer 170 is raised, and the metal bump 130 is melted. Then, by melting the metal bump 130, the wiring 120 of the first substrate 100 and the electrode pad 220 of the second substrate 200 can be bonded via the metal bump 130.

  When energizing the first heating metal layer 150 and the second heating metal layer 170, a plurality of semiconductor devices 1a before dicing are laid out on the wafer 300 as shown in FIG. With the first heating metal layer 150 and the second heating metal layer 170 being electrically connected in series or in parallel, respectively, the first heating metal layer 150 and the second heating metal layer 170 of each semiconductor device 1a are respectively The method of energizing is mentioned. Here, FIG. 12 is a diagram for explaining an example of a method of energizing the first heating metal layer 150 and the second heating metal layer 170 in the second embodiment.

  In the example shown in FIG. 12, in order to pass a current through each first heating metal layer 150 of each semiconductor device 1a, a power input electrode pad 310 and a lead wiring 320 are provided in the wafer 300. A voltage is applied from the power source 400 to each first heated metal layer 150 of each semiconductor device 1a via the power source 400. Similarly, in order to allow a current to flow through each second heating metal layer 170 of each semiconductor device 1a, a power input electrode pad 330 and a lead wiring 340 are provided in the wafer 300, and the power source 500 is connected thereto. Thus, a voltage is applied to each second heating metal layer 170 of each semiconductor device 1a. That is, in the example shown in FIG. 12, a voltage can be applied to the first heating metal layer 150 and the second heating metal layer 170 by the power source 400 and the power source 500 which are separate power sources, respectively. Note that when the first heating metal layer 150 and the second heating metal layer 170 of the semiconductor device 1a are electrically connected in series or in parallel, the connection mode and the number of connections are the first heating metal layer 150 and the second heating metal layer. What is necessary is just to adjust suitably with the electric current value and voltage value which are each applied to the metal layer 170. FIG.

  According to 2nd Embodiment, in addition to the effect of the above-mentioned 1st Embodiment, there exist the following effects. That is, according to the second embodiment, the second heating metal layer 170 for heating the metal bump 130 is further provided, and the metal bump 130 is melted by the heating of the second heating metal layer 170, so that the first substrate 100 The wiring 120 and the electrode pad 220 of the second substrate 200 are joined. Therefore, according to the second embodiment, the height variation between the plurality of metal bumps 130 formed on the plurality of wirings 120 can be suppressed, and the first substrate 100 and the second substrate 200 are separated. The reaction force can be reduced. As a result, in addition to ensuring the airtightness of the joint composed of the first heating metal layer 150, the substrate bonding layer 160, and the metal pattern layer 230, the crack resistance of the joint is improved. It is possible to suppress the destruction of the sealing structure of the element region 110 by the second substrate 200.

  In addition, according to the second embodiment, since the conductive second heating metal layer 170 is formed in the second insulating film 142, in addition to the effects of the first embodiment described above, the wafer 300 is formed. After dicing to obtain the semiconductor device 1a, the noise reduction effect can be achieved by connecting the second heating metal layer 170 to the ground.

<< Third Embodiment >>
Next, a third embodiment of the present invention will be described. FIG. 13 is an enlarged view of a main part of the semiconductor device 1b according to the third embodiment, and FIGS. 14A to 14C are diagrams for explaining a manufacturing process of the semiconductor device 1b according to the third embodiment. In addition, FIG. 13, FIG. 14A-FIG. 14C are equivalent to the figure which expanded and showed the A section of FIG. 1 in 1st Embodiment.

  As shown in FIG. 13, the semiconductor device 1 b according to the third embodiment has a configuration in which the metal pads 130 b are formed on the electrode pads 220 of the second substrate 200 and then the electrode pads 220 and the wirings 120 are joined. Except for this, it has the same configuration as the semiconductor device 1a of the second embodiment.

  Hereinafter, a method for manufacturing the semiconductor device 1b according to the third embodiment will be described with reference to FIGS. 14A to 14C.

  First, in the same manner as in the second embodiment, the element region 110 including the plurality of elements 111 shown in FIG. 1 is formed by the semiconductor manufacturing technique, and then the first substrate 100 is heated by the first heating as shown in FIG. 14A. The metal layer 150, the second heating metal layer 170, and the substrate bonding layer 160 are formed (see FIGS. 11A to 11C of the second embodiment).

  Next, as in the second embodiment, as shown in FIG. 14B, the electrode pad 220 and the metal pattern layer 230 are formed on the second substrate 200 on which the through electrode 210 is formed. In the third embodiment, metal bumps 130 b are further formed on the electrode pads 220. In the third embodiment, since the metal bumps 130b are formed on the electrode pads 220 of the second substrate 200, they can be formed by electroless plating or electrolytic plating in addition to a method using wire bonding or the like. When the metal bump 130b is formed by electroless plating or electrolytic plating, it is preferable to mask other than the plated portion.

  Next, in the same manner as in the second embodiment, as shown in FIG. 14C, the first substrate 100 and the second substrate 200 are aligned, overlapped, and pressurized from above. Further, in the same manner as in the second embodiment, the first heating metal layer 150 and the second heating metal layer 170 are energized and heated to melt the bonding member layer 161 and the metal bumps 130b. And thereby, the 1st board | substrate 100 and the 2nd board | substrate 200 are bonded together via the joining member layer 161, while sealing the several element 111 from external air, the wiring 120 of the 1st board | substrate 100, and 2nd The electrode pad 220 of the substrate 200 is bonded via the metal bump 130b.

  According to 3rd Embodiment, in addition to the effect of the above-mentioned 1st, 2nd embodiment, there exists the following effect. That is, according to the third embodiment, in order to melt the metal bump 130 by heating the second heating metal layer 170, the bonding portion constituted by the first heating metal layer 150, the substrate bonding layer 160, and the metal pattern layer 230. In addition to ensuring the airtightness, the crack resistance of the joint can be improved, and the destruction of the sealing structure of the element region 110 by the second substrate 200 can be suppressed. Furthermore, according to the third embodiment, it is possible to reduce noise by connecting the second heating metal layer 170 to the ground.

<< 4th Embodiment >>
Next, a fourth embodiment of the present invention will be described. 15 is an enlarged view of a main part of the semiconductor device 1c according to the fourth embodiment, FIG. 16 is a top view of the first substrate 100 constituting the semiconductor device 1c according to the fourth embodiment, and FIGS. 17A to 17D are the fourth embodiment. It is a figure for demonstrating the manufacturing process of the semiconductor device 1c which concerns on a form. 15 and 17A to 17D correspond to enlarged views of the portion A of FIG. 1 in the first embodiment. FIG. 16 corresponds to a top view of the semiconductor device 1c with the second substrate 200 removed.

  As shown in FIGS. 15 and 16, in the semiconductor device 1 c according to the fourth embodiment, a metal thin film 130 c is formed on the wiring 120 instead of the metal bump 130, and the first substrate 100 is interposed via the metal thin film 130 c. The wiring 120 and the electrode pad 220 of the second substrate 200 are bonded together, and the same structure as that of the semiconductor device 1a of the second embodiment is provided except that the step in the metal pattern layer 230 forming portion of the second substrate 200 is eliminated. It is what you have.

  Hereinafter, a method for manufacturing the semiconductor device 1c of the fourth embodiment will be described with reference to FIGS. 17A to 17D.

  First, in the same manner as in the second embodiment, an element region 110 including a plurality of elements 111 shown in FIG. 1 is formed by a semiconductor manufacturing technique, and then a first heating is applied to the first substrate 100 as shown in FIG. 17A. The metal layer 150, the second heating metal layer 170, and the substrate bonding layer 160 are formed (see FIGS. 11A to 11C of the second embodiment).

  Next, as illustrated in FIG. 17B, a metal thin film 130 c is formed on the wiring 120. As a material for forming the metal thin film 130c, for example, a low melting point metal such as solder, lead (Pb), tin (Sn), aluminum (Al), or the like can be used. The metal thin film 130c can be formed by sputtering these metals on the wiring 120 when lead, tin, or aluminum is used as a material constituting the metal thin film 130c. Alternatively, when solder is used as the material constituting the metal thin film 130c, the metal thin film 130c is formed on the wiring 120 by laminating sheet solder on the wiring 120 or using paste solder.

  Next, as in the second embodiment, as illustrated in FIG. 17C, the electrode pad 220 and the metal pattern layer 230 are formed on the second substrate 200 on which the through electrode 210 is formed.

  Next, as in the second embodiment, as shown in FIG. 17D, the first substrate 100 and the second substrate 200 are aligned, overlapped, and pressurized from above. Further, similarly to the second embodiment, the first heating metal layer 150 and the second heating metal layer 170 are energized and heated to melt the bonding member layer 161 and the metal thin film 130c. And thereby, the 1st board | substrate 100 and the 2nd board | substrate 200 are bonded together via the joining member layer 161, while sealing the several element 111 from external air, the wiring 120 of the 1st board | substrate 100, and 2nd The electrode pad 220 of the substrate 200 is bonded via the metal thin film 130c.

  According to 4th Embodiment, in addition to the effect of the above-mentioned 1st-3rd embodiment, there exists the following effect. That is, according to the fourth embodiment, since the metal thin film 130c is used instead of the metal bump 130, the heat capacity necessary for melting the metal thin film 130c is compared with the case where the metal bump 130 is used. The energy required for melting can be reduced. Moreover, according to the fourth embodiment, since the metal bumps 130 are not used, it is possible to reduce the digging process for providing a step in the portion of the second substrate 200 where the metal pattern layer 230 is formed.

<< 5th Embodiment >>
Next, a fifth embodiment of the present invention will be described. FIG. 18 is an enlarged view of a main part of the semiconductor device 1d according to the fifth embodiment, and FIGS. 19A to 19E are diagrams for explaining a manufacturing process of the semiconductor device 1d according to the fifth embodiment. 18 and 19A to 19E correspond to enlarged views of the portion A of FIG. 1 in the first embodiment.

  As shown in FIG. 18, the semiconductor device 1 d according to the fifth embodiment is the fourth except that the first heating metal layer 150 d is formed in the second insulating film 142 and immediately below the substrate bonding layer 160. It has the same configuration as the semiconductor device 1c of the embodiment. As can also be seen from FIG. 18, in the semiconductor device 1d according to the fifth embodiment, the height of the metal thin film 130d is set to the height of the metal thin film 130c in the semiconductor device 1c according to the fourth embodiment. In comparison with this, it can be set low.

  Next, a method for manufacturing the semiconductor device 1d according to the fifth embodiment will be described with reference to FIGS. 19A to 19E.

  First, in the same manner as in the fourth embodiment, an element region 110 including a plurality of elements 111 shown in FIG. 1 is formed by a semiconductor manufacturing technique, and then a first insulating film 141 is formed as shown in FIG. 19A.

  Next, as shown in FIG. 19A, the heating metal layer intermediate layer 172, the second heating member layer 171, and the heating metal layer intermediate that constitute the second heating metal layer 170 are formed on the first insulating film 141. Layer 173 is formed in this order. Further, at the same time or at the same time, the heating metal layer intermediate layer 152, the first heating member layer 151, and the heating metal layer that constitute the first heating metal layer 150 are formed on the first insulating film 141. The intermediate layer 153 for forming is formed in this order. The layers 172, 171 and 173 and the layers 152, 151 and 153 can be formed by sputtering the respective metals constituting them in this order.

  Next, as shown in FIG. 19B, a second insulating film 142 is formed on the first insulating film 141 on which the second heated metal layer 170 and the first heated metal layer 150 are formed.

  Next, as illustrated in FIG. 19C, the wiring 120 is formed on the second insulating film 142, and the metal thin film 130 d is formed on the wiring 120. Further, at the same time, or simultaneously, the bonding layer intermediate layer 162 and the bonding member layer 161 that form the substrate bonding layer 160 are formed on the first insulating film 141 in this order.

  Next, as in the fourth embodiment, as shown in FIG. 19D, the electrode pad 220 and the metal pattern layer 230 are formed on the second substrate 200 on which the through electrode 210 is formed.

  Next, as in the fourth embodiment, as shown in FIG. 19E, the first substrate 100 and the second substrate 200 are aligned, overlapped, and pressurized from above. Further, as in the fourth embodiment, the first heated metal layer 150 and the second heated metal layer 170 are energized and heated to melt the bonding member layer 161 and the metal thin film 130d. And thereby, the 1st board | substrate 100 and the 2nd board | substrate 200 are bonded together via the joining member layer 161, while sealing the several element 111 from external air, the wiring 120 of the 1st board | substrate 100, and 2nd The electrode pad 220 of the substrate 200 is bonded via the metal thin film 130d.

  According to the fifth embodiment, the first heating metal layer 150, the substrate bonding layer 160, and the metal pattern layer 230 are used to melt the metal thin film 130c by heating the second heating metal layer 170, as in the second embodiment. In addition to being able to ensure the airtightness of the joint composed of the above, it is possible to improve the crack resistance of the joint, and to suppress the destruction of the sealing structure of the element region 110 by the second substrate 200 Can do.

  According to 5th Embodiment, in addition to the effect of the above-mentioned 1st-4th embodiment, there exists the following effect. That is, according to the fifth embodiment, since the first heating metal layer 150 and the second heating metal layer 170 are both formed on the first insulating film 141, the first heating metal layer 150 and the second heating metal layer are formed. 170 can be formed simultaneously or in succession, and the number of steps can be reduced.

  In addition, according to the fifth embodiment, since the first heating metal layer 150 is formed in the second insulating film 142 and thereby electrically insulated from the substrate bonding layer 160, the first heating metal layer 150 is formed on the first heating metal layer 150. When energizing, there is no possibility of current flowing into the substrate bonding layer 160, and energization loss can be reduced. As a result, the temperature of the first heating metal layer 150 when the first heating metal layer 150 is energized to heat the first heating metal layer 150 can be controlled relatively easily, and the substrate bonding layer 160 can be controlled. When the substrate is melted, the molten state of the substrate bonding layer 160 can be stabilized, and as a result, the bondability of the bonded portion can be improved.

<< 6th Embodiment >>
Next, a sixth embodiment of the present invention will be described. 20 is an enlarged view of a main part of the semiconductor device 1e according to the sixth embodiment, FIG. 21 is a top view of the first substrate 100 constituting the semiconductor device 1e according to the sixth embodiment, and FIGS. 22A to 22D are the sixth embodiment. It is a figure for demonstrating the manufacturing process of the semiconductor device 1e which concerns on a form. 20 and 22A to 22D correspond to enlarged views of the portion A of FIG. 1 in the first embodiment. FIG. 21 corresponds to a top view of the semiconductor device 1e with the second substrate 200 removed.

  As shown in FIGS. 20 and 21, the semiconductor device 1e according to the sixth embodiment includes the first substrate 100 via the bonding portion between the wiring 120 and the electrode pad 220 via the metal thin film 130d and the substrate bonding layer 160. The semiconductor device 1d has the same configuration as that of the semiconductor device 1d of the fifth embodiment, except that the coating portions 181 to 184 for preventing the spread of solder leakage are formed at the joint between the first and second substrates 200, respectively.

  That is, in the semiconductor device 1e according to the sixth embodiment, a coating portion 181 is formed on the wiring 120 and a coating portion is formed on the metal pad 220, which forms a bonding portion between the wiring 120 and the electrode pad 220 via the metal thin film 130d. 182 are formed respectively. Similarly, a coating portion 183 is formed on the bonding layer intermediate layer 162 and a coating portion 184 is formed on the metal pattern layer 230, which constitutes a bonding portion between the first substrate 100 and the second substrate 200 via the bonding member layer 160. , Each is formed.

  Hereinafter, a method for manufacturing the semiconductor device 1e according to the sixth embodiment will be described with reference to FIGS. 22A to 22D.

  First, in the same manner as in the fifth embodiment, an element region 110 including a plurality of elements 111 shown in FIG. 1 is formed by a semiconductor manufacturing technique, and then, as shown in FIG. The metal layer 170, the first heating metal layer 150, the wiring 120, and the bonding layer intermediate layer 162 are formed.

  Next, as shown in FIG. 22A, coat portions 181 and 183 for preventing spread of solder leakage are formed on the wiring 120 and the bonding layer intermediate layer 162, respectively. The coat portions 181 and 183 are formed as the metal thin film 130d and the bonding member layer 161 as shown in FIGS. 21 and 22A, which are top views of the first substrate 100 constituting the semiconductor device 1e. Is formed so as to surround. By making the coating portions 181 and 183 have such a configuration, the effect of preventing the spread of solder leakage can be enhanced.

  Next, as illustrated in FIG. 22B, a metal thin film 130 d is formed in a portion surrounded by the coat portion 181 on the wiring 120. Also, before or after this, or simultaneously, the bonding member layer 161 is formed in a portion surrounded by the coating portion 183 on the bonding layer intermediate layer 162.

  Next, as in the fifth embodiment, as shown in FIG. 22C, the electrode pad 220 and the metal pattern layer 230 are formed on the second substrate 200 on which the through electrode 210 is formed.

  Next, as shown in FIG. 22C, coat portions 182 and 184 for preventing the spread of solder leakage are formed on the electrode pad 220 and the metal pattern layer 230, respectively. As shown in FIG. 22C, the coating portions 182 and 184 are formed so as to surround a portion where the metal thin film 130d is formed and a portion where the bonding member layer 161 is formed.

  Next, as in the fifth embodiment, as shown in FIG. 22D, the first substrate 100 and the second substrate 200 are aligned, overlapped, and pressurized from above. Further, as in the fifth embodiment, the first heating metal layer 150 and the second heating metal layer 170 are energized and heated to melt the bonding member layer 161 and the metal thin film 130d. And thereby, the 1st board | substrate 100 and the 2nd board | substrate 200 are bonded together via the joining member layer 161, while sealing the several element 111 from external air, the wiring 120 of the 1st board | substrate 100, and 2nd The electrode pad 220 of the substrate 200 is bonded via the metal thin film 130d.

  According to 6th Embodiment, in addition to the effect of the above-mentioned 1st-5th embodiment, there exists the following effect. That is, according to the sixth embodiment, the bonding portion between the wiring 120 and the electrode pad 220 via the metal thin film 130d, and the bonding portion between the first substrate 100 and the second substrate 200 via the substrate bonding layer 160, Since the coating portions 181 to 184 for preventing the spread of solder leakage are formed, it is possible to prevent the leakage of solder when the metal thin film 130d and the substrate bonding layer 160 are formed of solder. As a result, the distance between the junction between the wiring 120 and the electrode pad 220 via the metal thin film 130d and the junction between the first substrate 100 and the second substrate 200 via the substrate junction layer 160 are reduced. Thus, the semiconductor device can be miniaturized. Further, since the spread of solder leakage can be prevented, the height of the metal thin film 130d and the height of the substrate bonding layer 160 after melting can be stabilized, and as a result, the first substrate 100 And the second substrate 200 can be stably joined.

<< 7th Embodiment >>
Next, a seventh embodiment of the present invention will be described. 23 is a cross-sectional view of the semiconductor device 1f according to the seventh embodiment, FIG. 24 is a cross-sectional view for explaining a method for manufacturing the semiconductor device 1f according to the seventh embodiment, and FIG. 25 is a first heating metal according to the seventh embodiment. 6 is a diagram for explaining an example of a method for energizing a layer 150. FIG. FIG. 25 corresponds to a top view of the semiconductor device 1f viewed from the second substrate 200 side.

  As shown in FIG. 23, the semiconductor device 1f according to the seventh embodiment includes the first heating metal layer 150 and the substrate bonding layer 160 formed on the second substrate 200 side. Except that the heating through electrode 240 for heating the 1 heating metal layer 150 is formed, it has the same configuration as the semiconductor device 1 of the first embodiment.

  Hereinafter, a method for manufacturing the semiconductor device 1 f according to the seventh embodiment will be described with reference to FIGS. 24 and 25.

  First, as shown in FIG. 24, on the wafer 300, as in the first embodiment, an element region 110 including a plurality of elements 111, wirings 120, metal bumps 130, an insulating film 140, and the like are formed on the first substrate 100. A metal pattern layer 230 is formed. On the other hand, unlike the first embodiment, the through electrode 210, the heating through electrode 240, the electrode pad 220, the first heating metal layer 150, and the substrate bonding layer 160 are formed on the second substrate 200.

  In the seventh embodiment, the first heating metal layer 150 includes the first heating member layer 151 and the heating metal layer formed on the upper surface and the lower surface of the first heating member layer 151, as in the first embodiment. The intermediate layers 152 and 153 may be used. Further, the substrate bonding layer 160 may be composed of the bonding member layer 161 and the bonding layer intermediate layer 162 as in the first embodiment. Here, in the seventh embodiment, in order to form the first heating metal layer 150 and the substrate bonding layer 160 on the second substrate 200, the layers constituting the first heating metal layer 150 and the substrate bonding layer 160 are formed. In this case, as in the first embodiment, in addition to the method of forming by sputtering, it is also possible to form by electroless plating or electrolytic plating. When forming each layer by electroless plating or electrolytic plating, it is preferable to mask other than the plated portion.

  Then, as shown in FIG. 25, on the wafer 300, the first heating metal layer 150 is energized for each semiconductor device 1 f by using a pair of heating through electrodes 240 provided on the second substrate 200. Do. That is, as shown in FIG. 25, the first heating metal layer 150 is heated by energizing the first heating metal layer 150 through a pair of heating through electrodes 240 provided on the second substrate 200. Thereby, the substrate bonding layer 160 is melted, and the first substrate 100 and the second substrate 200 are bonded together. In the seventh embodiment, as shown in FIG. 25, it is preferable that the distance between the pair of through electrodes 240 for heating is arranged at an equal distance so that the resistance values are equal.

  According to the seventh embodiment, in addition to the effects in the first embodiment, the following effects can be obtained. That is, according to the seventh embodiment, since the first heating metal layer 150 is energized for each semiconductor device 1f, the current value when energizing the first heating metal layer 150 is relatively large. It can be. In addition, according to the seventh embodiment, since the first heating metal layer 150 is energized for each semiconductor device 1f, the influence of the wire breakage even when the wire breakage occurs in a specific semiconductor device. Therefore, the manufacturing yield can be improved.

<< Eighth Embodiment >>
Next, an eighth embodiment of the present invention will be described. 26 is a cross-sectional view of a semiconductor device 1g according to the eighth embodiment, FIG. 27 is a cross-sectional view for explaining a method for manufacturing the semiconductor device 1g according to the eighth embodiment, and FIG. 28 is a first heating metal in the eighth embodiment. 6 is a diagram for explaining an example of a method for energizing a layer 150. FIG. FIG. 28 corresponds to a top view of the semiconductor device 1g as viewed from the first substrate 100 side.

  As shown in FIG. 26, the semiconductor device 1 g according to the eighth embodiment is the first except that a heating through electrode 240 g for heating the first heating metal layer 150 is formed on the first substrate 100. The semiconductor device 1 has the same configuration as that of the embodiment.

  Hereinafter, a method for manufacturing the semiconductor device 1g according to the eighth embodiment will be described with reference to FIGS. First, as shown in FIG. 27, on the wafer 300, a heating through electrode 240g, an element region 110 composed of a plurality of elements 111, a wiring 120, a metal bump 130 and an insulating film 140, and a heating substrate are formed on the first substrate 100. The first heating metal layer 150 and the substrate bonding layer 160 bonded to the through electrode 240g are formed. Meanwhile, the through electrode 210, the electrode pad 220, and the metal pattern layer 230 are formed on the second substrate 200. 27 shows the first substrate 100 and the second substrate 200 upside down as compared with FIG.

  In the eighth embodiment, the first heating metal layer 150 includes the first heating member layer 151 and the heating metal layer formed on the upper surface and the lower surface of the first heating member layer 151, as in the first embodiment. The intermediate layers 152 and 153 may be used. Further, the substrate bonding layer 160 may be composed of the bonding member layer 161 and the bonding layer intermediate layer 162 as in the first embodiment.

  As shown in FIG. 28, as in the seventh embodiment, the first through-electrodes 240g for heating provided on the first substrate 100 are used on the wafer 300 for each semiconductor device 1g. Energization of the heating metal layer 150 is performed. That is, as shown in FIG. 28, the first heating metal layer 150 is heated by energizing the first heating metal layer 150 through a pair of heating through electrodes 240g provided on the first substrate 100, Thereby, the substrate bonding layer 160 is melted, and the first substrate 100 and the second substrate 200 are bonded together.

  According to the eighth embodiment, in addition to the effects in the first embodiment, the following effects can be obtained. That is, according to the seventh embodiment, since the first heating metal layer 150 is energized for each semiconductor device 1g, the current value when energizing the first heating metal layer 150 is relatively large. It can be. In addition, according to the seventh embodiment, since the first heating metal layer 150 is energized for each semiconductor device 1g, the influence of the wire breakage even when the wire breakage occurs in a specific semiconductor device. Therefore, the manufacturing yield can be improved.

<< Ninth Embodiment >>
Next, a ninth embodiment of the present invention will be described. FIG. 29 is a cross-sectional view of a semiconductor device 1h according to the ninth embodiment.

  As shown in FIG. 29, the semiconductor device 1h according to the ninth embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment except that the porous structure portion 101 is formed on the first substrate 100.

  As shown in FIG. 29, the porous structure portion 101 is a porous portion formed by making the material constituting the first substrate 100 porous, and below the insulating film 140 in the first substrate 100, The first heating metal layer 150 is formed directly below the heating metal layer 150 along the portion where the first heating metal layer 150 is formed.

  According to 9th Embodiment, in addition to the effect in 1st Embodiment, there exist the following effects. That is, according to the ninth embodiment, by providing the porous structure portion 101, it is possible to prevent the heat generated by the first heating metal layer 150 from diffusing in the thickness direction of the first substrate 100. It is possible to efficiently prevent thermal diffusion when the heated metal layer 150 is energized to heat the first heated metal layer 150.

<< 10th Embodiment >>
Next, a tenth embodiment of the present invention will be described. FIG. 30 is a cross-sectional view of a semiconductor device 1i according to the tenth embodiment.

  In the semiconductor device 1 i according to the tenth embodiment, as shown in FIG. 30, the porous structure portion 101 provided on the first substrate 100 is covered with insulating grooves 141 and 142 formed continuously from the insulating film 140. Except for this, it has the same configuration as that of the semiconductor device 1h according to the ninth embodiment.

  According to 10th Embodiment, in addition to the effect in 1st Embodiment, there exist the following effects. That is, according to the tenth embodiment, the porous structure portion 101 is provided, and the porous structure portion 101 is covered with the insulating grooves 141 and 142, so that the heat generated by the first heating metal layer 150 is reduced. In addition to diffusion in the thickness direction of the one substrate 100, diffusion in the lateral direction of the first substrate 100 can also be prevented. Therefore, the effect of preventing thermal diffusion when the first heated metal layer 150 is energized to heat the first heated metal layer 150 can be further enhanced.

  Each embodiment described above is described in order to facilitate understanding of the present invention, and is not described in order to limit the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

  For example, in the above-described embodiment, an example in which the through electrode 210 for supplying power to the element region 110 and taking out an electric signal from the element region 110 is formed on the second substrate 200 side is shown. The electrode 210 may be formed on the first substrate 100 side.

  In the above-described embodiment, the metal bump 130 and the metal thin films 130c and 130d are the electrode bonding member of the present invention, the first heating metal layer 150 is the first heating metal member of the present invention, and the substrate bonding layer 160 is the present invention. The second heating metal layer 170 corresponds to the first heating metal member of the present invention.

FIG. 1 is a cross-sectional view of a semiconductor device 1 according to the first embodiment. FIG. 2 is a top view of the first substrate constituting the semiconductor device according to the first embodiment. FIG. 3 is an enlarged view of a portion A in FIG. FIG. 4 is a perspective view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 6A is a drawing for explaining the manufacturing process for the semiconductor device of the first embodiment. FIG. 6B is a diagram showing a step subsequent to FIG. 6A. FIG. 6C is a diagram showing a step subsequent to FIG. 6B. FIG. 6D is a diagram showing a step subsequent to FIG. 6C. FIG. 6E is a diagram showing a step subsequent to FIG. 6D. FIG. 7 is a diagram for explaining an example of a method for energizing the first heated metal layer. FIG. 8 is a graph showing the relationship between the pulse voltage applied to the first heated metal layer, the temperature of the first heated metal layer, the temperature of the bonding layer, and the temperature of the element region. FIG. 9 is an enlarged view of a main part of the semiconductor device according to the second embodiment. FIG. 10 is a top view of the first substrate constituting the semiconductor device according to the second embodiment. FIG. 11A is a diagram for explaining a manufacturing process of the semiconductor device of the second embodiment. FIG. 11B is a diagram showing a step subsequent to FIG. 11A. FIG. 11C is a diagram showing a step subsequent to FIG. 11B. FIG. 11D is a diagram showing a step subsequent to FIG. 11C. FIG. 11E is a diagram showing a step subsequent to FIG. 11D. FIG. 11F is a diagram showing a step subsequent to FIG. 11E. FIG. 12 is a diagram for explaining an example of a method for energizing the first heated metal layer and the second heated metal layer in the second embodiment. FIG. 13 is an enlarged view of a main part of the semiconductor device according to the third embodiment. FIG. 14A is a drawing for explaining the manufacturing process for the semiconductor device of the third embodiment. FIG. 14B is a diagram showing a step subsequent to FIG. 14A. FIG. 14C is a diagram showing a step subsequent to FIG. 14B. FIG. 15 is an enlarged view of a main part of the semiconductor device according to the fourth embodiment. FIG. 16 is a top view of the first substrate constituting the semiconductor device according to the fourth embodiment. FIG. 17A is a drawing for explaining the manufacturing process for the semiconductor device of the fourth embodiment. FIG. 17B is a diagram showing a step subsequent to FIG. 17A. FIG. 17C is a diagram showing a step subsequent to FIG. 17B. FIG. 17D is a diagram showing a step subsequent to FIG. 17C. FIG. 18 is an enlarged view of a main part of the semiconductor device according to the fifth embodiment. FIG. 19A is a drawing for explaining the manufacturing process for the semiconductor device of the fifth embodiment. FIG. 19B is a diagram showing a step subsequent to FIG. 19A. FIG. 19C is a diagram showing a step subsequent to FIG. 19B. FIG. 19D is a diagram showing a step subsequent to FIG. 19C. FIG. 19E is a diagram showing a step subsequent to FIG. 19D. FIG. 20 is an enlarged view of a main part of the semiconductor device according to the sixth embodiment. FIG. 21 is a top view of the first substrate constituting the semiconductor device according to the sixth embodiment. FIG. 22A is a diagram for explaining a manufacturing process for the semiconductor device of the sixth embodiment. FIG. 22B is a diagram showing a step subsequent to FIG. 22A. FIG. 22C is a diagram showing a step subsequent to FIG. 22B. FIG. 22D is a diagram showing a step subsequent to FIG. 22C. FIG. 23 is a cross-sectional view of the semiconductor device according to the seventh embodiment. FIG. 24 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the seventh embodiment. FIG. 25 is a diagram for explaining an example of a method for energizing the first heated metal layer in the seventh embodiment. FIG. 26 is a cross-sectional view of the semiconductor device according to the eighth embodiment. FIG. 27 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the eighth embodiment. FIG. 28 is a view for explaining an example of a method for energizing the first heated metal layer in the eighth embodiment. FIG. 29 is a cross-sectional view of the semiconductor device according to the ninth embodiment. FIG. 30 is a cross-sectional view of the semiconductor device according to the tenth embodiment.

Explanation of symbols

1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i ... Semiconductor device 100 ... First substrate 110 ... Element region 111 ... Element 120 ... Wiring 130 ... Metal bump 130c, 130d ... Metal thin film 140 ... Insulation Film 141 ... 1st insulating film 142 ... 2nd insulating film 150 ... 1st heating metal layer 151 ... 1st heating member layer 152,153 ... Intermediate | middle layer 160 for heating metal layers ... Substrate joining layer 161 ... Joining member layer 162 ... Joining Layer intermediate layer 170 ... second heating metal layer 171 ... second heating member layer 172,173 ... heating metal layer intermediate layer 200 ... second substrate 210 ... through electrode 220 ... electrode pad 230 ... metal pattern layer 300 ... wafer

Claims (6)

A method of manufacturing a semiconductor device in which a second substrate is bonded to a first substrate having an element region to seal the element region,
Forming an extraction electrode on the first substrate or the second substrate;
Forming a first insulating film in a region other than the element region on the first substrate;
Forming a second heating metal member on the first insulating film;
Forming a second insulating film so as to cover the second heating metal member;
Forming a wiring from the element region on the second insulating film;
Forming a first heating metal member on the second insulating film ;
Forming a substrate bonding member on the first heating metal member;
Electrically connecting the extraction electrode and the wiring via an electrode bonding member;
A step of causing the first substrate and the second substrate to face each other, bonding the first substrate and the second substrate through the substrate bonding member, and energizing the first heating metal member;
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device in which a second substrate is bonded to a first substrate having an element region to seal the element region,
Forming an extraction electrode on the first substrate or the second substrate;
Forming a first insulating film in a region other than the element region on the first substrate;
Forming a first heating metal member on the first insulating film;
Forming a second heating metal member on the first insulating film;
Forming a second insulating film so as to cover the first heating metal member and the second heating metal member;
Forming a wiring from the element region on the second insulating film;
Forming a substrate bonding member on the second insulating film;
Electrically connecting the extraction electrode and the wiring via an electrode bonding member;
A step of causing the first substrate and the second substrate to face each other, bonding the first substrate and the second substrate through the substrate bonding member, and energizing the first heating metal member;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1 or 2 ,
The method of manufacturing a semiconductor device, wherein the electrode joining member is a bump shape. In the manufacturing method of the semiconductor device according to claim 1 or 2 ,
The method for manufacturing a semiconductor device, wherein the electrode bonding member is a sheet shape. In the manufacturing method of the semiconductor device in any one of Claims 1-4 ,
A step of energizing the second heating metal member after the first substrate and the second substrate are made to face each other and the first substrate and the second substrate are bonded together via the substrate bonding member; A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5 ,
A method for manufacturing a semiconductor device, comprising forming a diffusion prevention layer around the substrate bonding member and the electrode bonding member.

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