JP5258188B2 - Thyristor - Google Patents

Description

  The present invention relates to a thyristor.

  As disclosed in Patent Document 1, the conventional thyristor includes an n ++ layer 3 (hereinafter referred to as an emitter layer) as an emitter layer, a p ++ layer 2 (hereinafter referred to as a base layer) as a base layer, and a bulk. An n− layer 1 (hereinafter referred to as a bulk layer) as a layer and a p ++ layer 5 (hereinafter referred to as a facing base layer) as a facing base layer are disposed, and an n layer 6 (hereinafter referred to as a buried layer) is further disposed. (Referred to as a buried layer).

  The buried layer is disposed between the base layer and the bulk layer, and has a bonding surface with the base layer as a first bonding surface (pn bonding surface) and a bonding surface with the bulk layer as a second bonding surface. That is, the buried layer is buried in the bulk layer so that the end of the second joint surface has a predetermined inclination toward the end of the first joint surface, and the angle formed by the first joint surface and the second joint surface. θ has a pseudo acute bevel angle (θ <90 degrees, where θ is a bevel angle).

  By the way, the general bevel angle indicates an angle formed by the wall surface of the formed groove and the pn junction surface in contact with the groove. When there is a difference in concentration between the buried layer and the bulk layer, that is, the buried layer has a high concentration. When the bulk layer has a low concentration, the low concentration bulk layer can be regarded as a pseudo groove. Accordingly, the angle θ formed by the first bonding surface and the second bonding surface in the buried layer is considered to have an acute bevel angle smaller than 90 degrees by regarding the bulk layer as a pseudo groove. be able to.

Here, regarding the bevel angle, the relationship between the bevel angle and the current path due to the expansion of the depletion layer will be described.
As shown in FIG. 4, when a groove is formed and the pn junction surface is in contact with the groove, the bevel angle θ formed by the groove wall surface and the pn junction surface is an obtuse bevel indicated by θ> 90 degrees. It becomes a corner. In such a case, as shown in FIG. 4, the relationship between the depletion layer Ws extending at the groove wall surface and the depletion layer Wc extending inside the buried layer having the pn junction surface is a relationship represented by Ws <Wc. Thus, before the depletion layer fully expands in the buried layer, electric field concentration is caused on the groove side and breakdown occurs. As a result, the current follows a path that bypasses the groove side. The breakdown voltage is preferably determined mainly by the pn junction (base layer 3 / buried layer 4), but the breakdown voltage is greatly reduced by the electric field concentration in the groove. In the obtuse bevel angle, the pressure resistance depends not only on the semiconductor junction but also on the groove shape.

  On the other hand, as shown in FIG. 5, when the buried layer is formed so that the groove and the pn junction surface are separated from each other, as described above, the bevel angle θ formed by the first joint surface and the second joint surface in the buried layer is , Θ <90 degrees, resulting in an acute bevel angle. In such a case, as shown in FIG. 5, the relationship between the depletion layer Ws extending at the second junction surface and the depletion layer Wc extending inside the buried layer is expressed as Ws> Wc. Prior to the depletion layer extending from the joint surface fully expanding, the electric field concentration is caused on the inner side, and the inner side first yields. As a result, the current follows the internal path without bypassing the end of the buried layer. That is, at an acute bevel angle, a desired high breakdown voltage can be obtained by a pn junction regardless of the shape of the groove.

As described above, when the buried layer is formed so that the groove and the pn junction surface are separated and has an acute bevel angle, the current path is not detoured, and the dV / dt-VCL characteristic shown in FIG. 6 is obtained. be able to.
US Pat. No. 4,967,256

  Recently, however, further improvements in dV / dt-VCL characteristics have been desired, and an invention for that purpose has been desired.

  Accordingly, the present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a thyristor capable of obtaining a good dV / dt-VCL characteristic.

The present invention has been devised to achieve the above object, and includes a first conductivity type emitter layer, a second conductivity type base layer opposite to the first conductivity type, and the first conductivity type. and the bulk layer, the second conductivity type facing the base layer are sequentially parallel arranged, on the base layer and the bulk layer, the buried layer of the first conductivity type high concentration than the bulk layer is disposed In the thyristor in which a groove is provided between the emitter layer and the emitter layer and the channel stopper ,
In the buried layer, when a surface in contact with the base layer is a first bonding surface and a surface in contact with the bulk layer is a second bonding surface, an end of the second bonding surface is inclined toward the first bonding surface. And the end portion of the first joint surface has a predetermined inclination toward the end of the second joint surface, and the concentration of the end portion formed by contact of the first joint surface and the second joint surface is Formed lower than the concentration on the inner side of the buried layer ,
The groove is provided in contact with the base layer and the bulk layer, and not in contact with the joint surface between the base layer and the buried layer and the joint surface between the bulk layer and the buried layer. It is characterized by.

The groove is embedded with glass mainly composed of silicon.

  The first conductivity type emitter layer, the second conductivity type base layer opposite to the first conductivity type, the first conductivity type bulk layer, and the second conductivity type facing base layer are in parallel in this order. In the thyristor in which a buried layer of the first conductivity type having a higher concentration than the bulk layer is disposed between the base layer and the bulk layer, the buried layer has a surface in contact with the base layer as a first bonding surface. When the surface in contact with the bulk layer is the second bonding surface, the end of the second bonding surface is in contact with the first bonding surface with an inclination, and the end of the first bonding surface is the first bonding surface. The concentration of the end portion having a predetermined inclination toward the end of the two bonding surfaces and the contact between the first bonding surface and the second bonding surface is lower than the concentration on the inner side of the buried layer.

In the thyristor of the present invention, the end of the first bonding surface of the buried layer has a predetermined inclination toward the end of the second bonding surface, so that the current path transitions toward the inside of the buried layer,
Since the current path follows the inner side of the buried layer, the current path can be further shortened, and dV / dt-VCL characteristics better than those of the conventional thyristor can be obtained.

  Furthermore, in another thyristor of the present invention, the concentration of the end portion at the end portion where the first bonding surface and the second bonding surface of the buried layer are in contact with each other is lower than the concentration inside the buried layer. The amount of acceptor is larger on the inner side than on the end side. Since the extension of the depletion layer is inversely proportional to the amount of carriers, the end side is extended more than the inner side. As a result, the current path transitions from the end side toward the inner side, so that the current path follows the inner side of the buried layer, so that the current path can be further shortened, compared to the conventional thyristor. Good dV / dt-VCL characteristics can be obtained.

Hereinafter, embodiments of the thyristor of the present invention will be described in detail with reference to the drawings. In the following description, the same constituent elements are assigned the same reference numerals and overlapped in the drawings used in the embodiments. The description is omitted as much as possible. In the embodiment, a two-way two-terminal thyristor will be described as an example of a surge protection thyristor.
In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type.

  As shown in FIG. 1, the thyristor 1 of the present invention includes an emitter layer 2 shown as an n ++ layer, a base layer 3 shown as a p + layer, and a buried layer shown as an n + layer in order from the front surface to the back surface. It comprises a layer 4, a bulk layer 5 shown as an n− layer, and a facing base layer 6 shown as p + and p ++ layers.

  By the way, the thyristor 1 of the present invention has electrodes on the front surface side and the back surface side, respectively, and in order to obtain electrical characteristics in the opposite direction between these electrodes, the emitter layer 2, the base layer 3, A configuration including the buried layer 4, the bulk layer 5, and the facing base layer 6 is also provided from the back side, and these components are arranged adjacent to each other. In the thyristor 1 of the present invention, the electrode of the emitter layer of one configuration and the electrode of the facing base layer of the other configuration are made common, and the electrode of the facing base layer of one configuration and the emitter layer of the other configuration are further combined. These electrodes are also shared. Accordingly, the thyristor 1 of the present invention is a thyristor structure of a type called a so-called Sidac (registered trademark) having a two-way two-terminal structure.

  As described above, the thyristor 1 having the two-way two-terminal structure includes two sets of the emitter layer, the base layer, the buried layer, the bulk layer, and the facing base layer. The configuration will be described as a representative example. In the following description, the configuration on the left side in FIG. 1, that is, the configuration including the emitter layer 2, the base layer 3, the buried layer 4, the bulk layer 5, and the facing base layer 6 in order from the surface side will be described as a representative example. Do.

  As shown in FIG. 1, the thyristor 1 includes a channel stopper 7 shown as an n ++ layer at both ends of the surface. The channel stopper prevents pn inversion of the bulk layer 5 and an undesirable leakage current as a function of the thyristor. (Channel current) can be suppressed.

  A groove is formed inside the surface facing each channel stopper, and glass 8 mainly composed of silicon for suppressing leakage current and ensuring a desired breakdown voltage is embedded in the groove. In addition, a structure including the emitter layer 2, the base layer 3, the buried layer 4, the bulk layer 5, and the facing base layer 6 is formed in order from the front surface where each glass 8 faces, and the structure is also formed from the back surface side. .

  By the way, the bulk layer 5 shown as an n− layer is a so-called semiconductor wafer containing, for example, phosphorus (P) as an n-type impurity at a concentration of the 14th power (eg, 1E14 cm ^ −3). A facing base layer 6 is formed in the vicinity of the back surface.

  The facing base layer 6 is formed by first doping a back surface of the bulk layer 5 (semiconductor wafer) with, for example, boron (B) as a P-type impurity to provide a region indicated as p + having a concentration of the 18th power. On the other hand, it is formed by doping a P-type impurity and providing a region (ohmic layer) shown as p ++ having a concentration of the 20th power.

On the other hand, a base layer 3 is formed in the vicinity of the surface of the bulk layer 5.
Specifically, the surface of the bulk layer 5 is doped with, for example, boron (B) as a p-type impurity, and a region indicated as p + having a concentration of the 18th power is formed as the base layer 3. The base layer 3 can be formed simultaneously with the facing base layer 6. An emitter layer 2 is formed near the surface of the base layer 3.

  Specifically, the surface of the formed base layer 3 is doped with, for example, phosphorus (P) or arsenic (As) as an n-type impurity, and a region indicated as n ++ having a concentration of the 20th order is formed as the emitter layer 2. Is done.

  On the emitter layer 2, a nickel layer 9 is applied by plating, and then a solder layer 10 is formed on the nickel layer, thereby forming an electrode for the emitter layer 2. The electrodes formed as described above are also formed on the facing base layer 6.

Prior to the formation of the base layer 3, the buried layer 4 is buried in the bulk layer 5.
Specifically, the bulk layer 5 is doped with, for example, phosphorus (P) or arsenic (As), and a region indicated as n + having a concentration in the range of 15 to 16 is formed as the buried layer 4. After the buried layer 4 is formed in this manner, doping for the base layer 5 and the emitter layer is sequentially performed, and a groove for embedding the glass 8 is formed.

  In the buried layer 4 to be formed, when the surface in contact with the base layer on the upper surface side is the first bonding surface and the surface in contact with the bulk layer on the lower surface side is the second bonding surface, the end of the first bonding surface and the second The ends of the joining surfaces are in contact with each other with a predetermined inclination angle. In the following description, a portion of the buried layer 4 where the end of the first joint surface and the end of the second joint surface are in contact with each other is referred to as an end portion.

  Incidentally, as shown in FIG. 1, the buried layer 4 has a pseudo acute bevel angle at an angle θ formed by the first joint surface and the second joint surface.

  A general bevel angle indicates an angle formed by a groove wall surface and a pn junction surface in contact with the groove. In this embodiment, since the buried layer 4 has a higher concentration than the bulk layer 5, the bevel angle is low due to the concentration difference. The bulk layer 5 having a concentration can be regarded as a pseudo groove. Thus, when the bulk layer 5 is regarded as a pseudo-groove, it can be considered that the angle θ formed by the end of the first joint surface and the end of the second joint surface in the buried layer 4 has an acute bevel angle. it can.

  By the way, the 2nd junction surface in the embedding layer 4 of this invention has a predetermined inclination toward the 1st junction surface unlike the past. Thereby, a depletion layer generated by applying a voltage difference to the electrode of the emitter layer 2 and the electrode of the facing base layer 6 spreads as shown in FIG.

  Therefore, the relationship between the depletion layer Ws extending at the second junction surface and the depletion layer Wc extending at the inner side of the buried layer is Ws> Wc ′> Wc, and the depletion layer extending from the second junction surface is fully expanded. First, electric field concentration is caused on the inner side, and the inner side yields before the end side. That is, a desired breakdown voltage can be obtained without being affected by the groove. Thus, in the conventional thyristor, the current path bypasses the end of the buried layer, but in the thyristor of the present invention, the current flows through the inner side inside the end without bypassing the end. Therefore, by shortening the current path, the thyristor 1 of the present invention can obtain better dV / dt-VCL characteristics as compared with the conventional case as shown in FIG.

  Further, in the conventional thyristor shown in FIGS. 4 and 5, since the current flows so as to bypass the end of the buried layer, electric field concentration is caused at the end of the buried layer. Since the end of the layer 4 is not bypassed, the path width of the current path can be made uniform, and electric field concentration can be prevented.

  Furthermore, the buried layer 4 of the thyristor of the present invention is set so that the impurity concentration gradually decreases from the inner side toward the end as shown in FIG. 7, for example, the inner side concentration is 1E15 cm ^ -3. The concentration is set so that the concentration gradually decreases toward the end portion, and the concentration at the end portion is on the 14th power level.

  Therefore, a depletion layer generated by applying a voltage difference to the electrode of the emitter layer and the electrode of the facing base layer spreads inward depending on the concentration distribution. Thus, the current path flowing from the facing base side to the emitter side by the expanding depletion layer does not bypass the end of the buried layer where the first junction surface and the second junction surface are in contact. As a result, the thyristor 1 of the present invention can obtain better dV / dt-VCL characteristics than the conventional thyristor as shown in FIG.

  As described above, according to the thyristor 1 of the present invention, the end of the first bonding surface of the buried layer 4 has a predetermined inclination toward the end of the second bonding surface, and further, the end of the buried layer 4 Since the concentration of the end portion is lower than the concentration on the inner side of the buried layer, the current path transitions toward the inner side of the buried layer, so that the current path follows the inner side of the buried layer. And dV / dt-VCL characteristics better than those of conventional thyristors can be obtained.

  In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this, and the first conductivity type is p-type and the second conductivity type is n-type. The present invention may be applied to.

  In the embodiment, a thyristor that combines the distribution of the impurity concentration in the buried layer 4 and the shape of the end portion in the buried layer 4 has been described as an example, but in order to obtain good dV / dt-VCL characteristics, It is sufficient if at least one of the configurations is satisfied.

  FIG. 3B shows the dV / dt-VCL characteristics of a thyristor in which only the impurity concentration distribution in the buried layer 4 is changed, and dV / dt-VCL of the thyristor in which only the impurity concentration distribution in the buried layer 4 is changed. The characteristics are shown in FIG.

  In the embodiment, the description has been given of the example in which the groove for embedding the glass is formed shallower than the joint surface (main joint) between the base layer 3 and the buried layer 4, but the present invention is not limited to this and is shown in FIG. Thus, the present invention can be applied to a thyristor having a groove deeper than the position of the main junction. Further, the groove can be omitted.

  In this case, when the main joint comes into contact with the groove, an obtuse bevel angle as shown in FIG.

  In the embodiment, the thyristor having a bidirectional two-terminal structure has been described as an example. However, the present invention is not limited to this, and the present invention may be applied to a thyristor having a unidirectional two-terminal structure.

  The specific numerical values disclosed in the examples only disclose one embodiment of the present invention. Therefore, if the same effect as the present invention can be achieved, the value may be appropriately changed.

It is a figure which shows the thyristor of this invention. It is a figure which shows the breadth of a depletion layer, and an electric current path | route in the thyristor of this invention. It is a graph which shows the characteristic of the thyristor of this invention. It is a figure which shows the breadth of a depletion layer in a conventional thyristor, and a current pathway (there is a groove). It is a figure which shows the breadth of a depletion layer in a conventional thyristor, and a current path (no groove). It is a graph which shows the characteristic of the conventional thyristor. It is a figure which shows distribution of the impurity concentration in the embedding layer of the thyristor of this invention. It is the figure which applied this invention to the thyristor in which the groove | channel was formed deeper than the main junction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Thyristor 2 Emitter layer 3 Base layer 4 Buried layer 5 Bulk layer 6 Face-to-face base layer 7 Channel stopper 8 Glass 9 Nickel layer 10 Solder layer

Claims (2)

The first conductivity type emitter layer, the second conductivity type base layer opposite to the first conductivity type, the first conductivity type bulk layer, and the second conductivity type facing base layer are in parallel in this order. In the thyristor, the buried layer of the first conductivity type having a higher concentration than the bulk layer is disposed between the base layer and the bulk layer, and a groove is provided between the emitter layer and the channel stopper . ,
In the buried layer, when a surface in contact with the base layer is a first bonding surface and a surface in contact with the bulk layer is a second bonding surface, an end of the second bonding surface is inclined toward the first bonding surface. And the end portion of the first joint surface has a predetermined inclination toward the end of the second joint surface, and the concentration of the end portion formed by contact of the first joint surface and the second joint surface is Formed lower than the concentration on the inner side of the buried layer ,
The groove is provided in contact with the base layer and the bulk layer, and not in contact with the joint surface between the base layer and the buried layer and the joint surface between the bulk layer and the buried layer. Thyristor characterized by 2. The thyristor according to claim 1, wherein the groove is embedded with glass mainly composed of silicon.