JP5256477B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus that performs correction processing (black level correction, white balance correction, etc.) unique to an image sensor having a plurality of image data readout channels.

  FIG. 23 is a block diagram schematically showing a configuration of an image processing LSI for a digital (still, video) camera in the prior art. In this apparatus, the image data reading channel RCH0 of the image sensor PIS is one channel, and as a result, the image data in each pixel is raster-scanned in line order and sequentially read out. The arrangement (color arrangement) of the color filters provided in each pixel in the effective pixel area of the image sensor PIS is a so-called RGB Bayer (RGB Bayer) arrangement.

  Image data sequentially read out from the image sensor PIS according to a pixel clock (not shown) is first A / D converted by the A / D converter 300P, and then the image data before the image sensor data on the C-MOS LSI. Input to a processing unit (hereinafter referred to as SPU (sensor processing unit)) 100P. The SPU 100P is not a circuit that performs original image processing, but performs processing caused by problems peculiar to the image sensor PIS, that is, black level correction, white balance correction, and defective pixel correction are input image data from the image sensor PIS. Is a unit that executes on to obtain a normalized RGB Bayer signal.

  FIG. 24 is a diagram schematically showing normalization processing of RGB Bayer signals input from the image sensor PIS, and FIG. 24 is also used in the first embodiment described later. Each color signal of R (red), G (green), and B (blue) shown in FIG. 24 (a) is assumed to have linearity, and each color signal is subjected to black level correction. Are aligned (see FIG. 24B). Further, each color signal is subjected to white balance correction, and their characteristics are overlapped and normalized (see FIG. 24C).

  The normalized RGB Bayer signal is then input to the RPU 200P and subjected to original image processing such as γ correction.

  FIG. 25 is a block diagram schematically showing the configuration of the main part of the SPU 100P in the prior art. In the figure, the global H counter 1 generates a count value HCNT by counting the number of receptions using the pixel clock CLK as an input signal, and reads out the image data from the image sensor PIS in the horizontal direction. It is a global horizontal direction counter that defines or manages. The global V counter 2 increments the count value VCNT by 1 each time a reset signal output from the carry-out CO of the global H counter 1 is received in synchronization with the pixel clock CLK, thereby causing the image sensor PIS. This is a global vertical direction counter that defines or manages the readout timing of image data from the vertical direction. Both counters 1 and 2 are components applied in the first embodiment to be described later. In the SPU 100P, since the readout channel of the image sensor PIS is one channel, the repetition range of the timing signal for readout of correction data may be 2 × 2 under the RGB Bayer array. Therefore, a 2-bit color selection timing signal COLSEL is generated by combining the least significant bit HCNT (0) of the count value HCNT of the global H counter 1 and the least significant bit VCNT (0) of the count value VCNT of the global V counter 2. Is done. In addition, a black level correction value register BLR is provided in advance in the SPU 100P. Here, the black level correction value register BLR is a register BL0 for storing black level correction values at each location in the 2 × 2 repetition range to which each color (all four colors) under the RGB Bayer array is assigned. ~ BL3. That is, the register BL0 stores the black level correction value of the color R at the 00 position within the repeat range, and the register BL1 stores the black level correction value of the color Gr at the 01 position within the repeat range. The register BL2 stores the black level correction value of the color Gb at the 10 position within the repeat range, and the register BL3 stores the color B at the 11 position within the repeat range. Stores the black level correction value. Similarly, a white balance correction value register WBR is also provided in the SPU 100P. Further, as shown in FIG. 25, the SPU 100P has a special point that both the black level correction value and the white balance correction value at each location of each color are selected via the corresponding selectors 11P and 12P. It is directly selected by the timing signal COLSEL. Reference numerals 13P and 14P denote a black level correction processing unit and a white balance correction processing unit, respectively.

<Problem 1>
In search of higher quality image generation, there is a demand for higher definition of image sensors (CCD sensors, CMOS sensors, etc.), and hence an increase in the number of pixels. In response to such a demand, an image sensor having 8M pixels or 10M pixels or more has been realized. In response to such an increase in the number of pixels of an image sensor, a digital still camera manufacturer using such an image sensor seeks to maintain or further improve the number of frames per unit time, that is, the continuous shooting speed. ing. Therefore, for example, if the continuous shooting speed is 10 frames / second when the number of pixels is 3M pixels, the data rate or the image data reading rate is 30M pixels / second, and this continuous shooting speed is maintained. For example, when the number of pixels is 5M pixels, the image data readout rate is 50M pixels / second, when the number of pixels is 8M pixels, the image data readout rate is 80M pixels / second, and when the number of pixels is 10M pixels. The image data read rate reaches 100M pixels / second. Nevertheless, the maximum value of the operating speed of the CCD sensor is about 35 MHz, and in the case of the CMOS sensor, the maximum value is about 50 MHz to 100 MHz. The operation speed of the C-MOS LSI is about 100 MHz. When an image sensor is to be produced at low cost and low power consumption, the maximum value of the operation speed of the image sensor is preferably about 40 MHz. As a result, as long as image data is read from the image sensor in one channel, it is impossible to maintain and realize the continuous shooting speed at which the reading rate described above is 50 Mpixels / second or more. In order to fundamentally solve such problems, it is necessary to increase the number of image data read channels of the image sensor. In response to such a need, an image sensor having a plurality of readout channels has recently been realized.

  With such an increase in the number of read channels, various image data read patterns have been proposed and realized, and new ways to deal with such diversification of image data read patterns have been proposed. There is a problem. In this regard, the case where the number of read channels is 2 will be briefly considered below.

  For example, the pattern shown in FIG. 26 can be considered as an example of a read pattern when the number of read channels is 2 under the RGB Bayer array. In this readout pattern, only the R color image data belonging to an even line with an image sensor is read out from the first readout channel RCH0, while the Gr color image belonging to the even line from the second readout channel RCH1. Read data only. In the next odd line, only Gb color image data is read from the first read channel RCH0, and only B color image data is read from the second read channel RCH1. Alternatively, as a modification thereof, the R and Gr color image data belonging to an even line with an image sensor is read from the first read channel RCH0, while the Gb and B color image data belonging to the next odd line is read. There may be a pattern example of reading from the second read channel RCH1.

  As a further example under the RGB Bayer arrangement, the pattern shown in FIG. 27 can be considered. Furthermore, as shown in FIG. 28, the RGB Bayer array of the image sensor is divided into two from the center to the left and right, and a reading pattern is also proposed in which reading is sequentially performed from the left side in a certain line, while also sequentially reading from the right side.・ It is realized. Furthermore, a reading pattern has been proposed in which reading is performed in the vertical direction in a certain region of the RGB Bayer array of the image sensor, while reading is performed in the horizontal direction in other regions.

  Thus, even when the number of read channels is 2, various read patterns have been proposed as described above. Then, when the number of read channels increases further, the read pattern becomes more complicated, and the number increases ascending.

  As described above, it can be said that there are various reading patterns from the image sensor for each manufacturer of the image sensor, or for each product number even if the product is in the same manufacturer. Therefore, from the viewpoint of designing and manufacturing a general-purpose LSI (image processing apparatus) that performs image processing on image data read from the image sensor, the image sensor employed by the digital camera manufacturer has any image reading pattern. Even so, it can be said that there is a need to provide a versatile image processing LSI that can always cope with the image reading pattern. Such problems are issues that require immediate attention.

<Problem # 2>
As described above, since the effective pixel area of the image sensor is the same as the number of pixels in the image sensor increases, the size of each cell in the image sensor must be further reduced. As described above, with the miniaturization of each cell of the image sensor, the level of the output signal of each cell becomes relatively small, and therefore the linearity of the output signal is also impaired. For this reason, cells having different characteristics frequently appear for each location in the effective pixel region of the image sensor or for each line. Therefore, the black level correction value and the white balance correction value necessary for normalizing the RGB Bayer signal of each pixel differ for each location in the effective pixel region of the image sensor. It is required to correct the RGB Bayer signal of each pixel with high accuracy by overcoming the above-described problems caused by the miniaturization of each cell of such an image sensor.

  The present invention has been made to cope with the above-described concerns, and a first object of the present invention is to provide an image processing apparatus that overcomes the first problem, and a second object of the present invention. Is to provide an image processing apparatus which overcomes the second problem.

The invention according to claim 1 is an image processing apparatus, wherein each image signal read in synchronization from each of a plurality of image data read channels of the image sensor is input to an input channel corresponding to the image data read channel. A plurality of pipeline-type image sensors that receive each pixel clock and execute predetermined image processing on the received image data in parallel for each pixel clock due to a problem peculiar to the image sensor. Independently for each input channel of the processing unit and the plurality of image sensor preprocessing units, a color selection timing signal for designating the color of a pixel at a certain time point is generated, and each image sensor preprocessing unit is generated. A color timing arrangement unit that outputs a corresponding color selection timing signal, and each image sensor pre-processing The knit executes the predetermined image processing according to the color selection timing signal corresponding to the unit, and each image sensor pre-processing unit is provided for each color, and the brightness and output of the color for each color. A plurality of linearization table registers having linearization characteristics for correcting non-linear characteristics with values, and outputs of the plurality of linearization table registers corresponding to the color selection timing signal corresponding to the unit. and first selector, said Bei example a linearization processing section for correcting process nonlinearity of the input image data by using the linearization characteristic first selector selects and outputs, each image sensor preprocessing unit, the plurality of The output of the linearization table register A register having a fixed linearization parameter for designating a specific output corresponding to the second output, and a second selector for selecting / outputting either the output of the register or the color selection timing signal corresponding to the unit; The first selector selects outputs of the plurality of linearization table registers according to an output value of the second selector .

The invention according to claim 2 is the image processing apparatus according to claim 1, wherein the linearization characteristics held in each of the plurality of linearization table registers included in each of the image sensor pre-processing units are: Each of the image sensor preprocessing units is provided for each color, and each of the image sensor pre-processing units has a level of a broken line among the plurality of broken lines corresponding to the color for each color. A plurality of limiter registers held as limit values; and a third selector that selects outputs of the plurality of limiter registers according to an output value of the second selector, and the linearization processing unit includes: When the input image data exceeds the limit value given by the output of the third selector, the correction process is clipped. And wherein the Rukoto.

  Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

  According to the first aspect of the present invention, there is provided an image processing apparatus capable of corresponding to various readout patterns from an image sensor having a plurality of image data readout channels and executing predetermined image processing caused by the image sensor. I can do it.

  According to the first aspect of the present invention, regardless of the pattern of reading data from the image sensor, the brightness of the color caused by the miniaturization of the image sensor for each input channel and for each color. Non-linear characteristics with the output value can be corrected.

According to the first aspect of the present invention, not only correction of nonlinear characteristics due to miniaturization of the image sensor but also nonlinear characteristics due to other causes such as the circuit system on the output side of the image sensor are provided for each input channel. It can be corrected selectively.

According to the invention of claim 2 , linearization processing can be clipped for each input channel and for each color.

It is a block diagram which shows the relationship between the read-out channel of an image sensor, and the input channel of the image processing apparatus which concerns on this Embodiment. It is a block diagram which shows the structural example of the SPU circuit of an image processing apparatus. It is a block diagram which shows the principle of operation of a color timing arrangement part. It is a block diagram which shows the structural example of the principal part of a color timing arrangement part. It is a block diagram which shows the structure of a part of color timing arrangement part. FIG. 5 is a diagram illustrating an example of a repetition range of an arbitrary size that can be set by the local H counter and the local V counter of the circuit of FIG. 4. It is a figure which shows three types of repeating ranges. It is a figure which illustrates typically the offset drift of the black level signal generated over the whole screen. It is a block diagram which shows an example of a structure of a black level correction process part. It is a block diagram which shows the other example of a structure of a black level correction process part. It is a figure which shows the principle of the method of calculating | requiring the modulation data in a modulation circuit. It is a figure which shows the principle of the other method which calculates | requires the modulation | alteration data in a modulation circuit. It is a figure which shows an example of the linear interpolation (interpolation interpolation) in one dimension. It is a figure which shows the practical method which calculates | requires the modulation | alteration data in a modulation circuit. It is a block diagram which shows the structural example of a modulation circuit. FIG. 16 is a diagram showing a practical method for obtaining modulation data when the modulation range is set to 256 × 256 in the modulation circuit of FIG. 15. FIG. 16 is a diagram showing a method for changing the physical width of a modulation range in the modulation circuit of FIG. 15. It is a figure which shows the method of a tail correction. It is a figure which shows the method of a linearization process. It is a block diagram which shows the structural example of the linearization processing circuit in the SPU circuit of each input channel. It is a figure which shows the case where the linearization characteristic is divided | segmented by the broken line. It is a block diagram which shows the example of a part of main implementation of the SPU circuit of each input channel. It is a block diagram which shows the relationship between the read-out channel of the image sensor in the prior art, and the input channel of an image processing apparatus. It is a figure which shows the normalization process of a RGB Bayer signal. It is a block diagram which shows the structural example of the SPU circuit in a prior art. It is a figure which shows an example of an image data read-out pattern. It is a figure which shows an example of an image data read-out pattern. It is a figure which shows an example of an image data read-out pattern.

(Embodiment 1)
<Programmable configuration of color selection timing signal under multiple input channels>
FIG. 1 is a block diagram schematically showing a configuration of an image processing LSI for a digital (still, video) camera according to the present embodiment. In the example of FIG. 1, the number of image data readout channels RCH0 to RCH3 of the image sensor (for example, a solid-state imaging device such as a CCD sensor or a CMOS sensor) IS is four. The arrangement (color arrangement) of the color filters provided in each pixel in the effective pixel area of the image sensor IS is the RGB Bayer arrangement described above. In the RGB Bayer array, as indicated by a thick line in FIG. 1, the G (green) color arranged next to the R (red) color is affected by the R color, and is therefore displayed as a Gr color. The G color arranged immediately below is affected by the B (blue) color located next to it, so that it is displayed as the Gb color.

  Image data read in parallel from the image data read channels RCH0 to RCH3 in accordance with a pixel clock (not shown here) is read by the A / D converters 300 to 303 corresponding to the image data read channel. After A / D conversion, it is input to an SPU (image sensor data preprocessing unit) 100 on the C-MOS LSI. Here, as with the SPU 100P in FIG. 23, the SPU 100 performs a predetermined image processing such as correction of image data (black level correction, white balance correction, defective pixel correction, etc.) caused by problems peculiar to the image sensor IS. ) To normalize the input RGB Bayer signal (10-bit to 16-bit data) (see FIG. 24 described above in this regard). In addition, the RPU 200 on the C-MOS LSI, like the RPU 200P in FIG. 23, performs original image processing (gamma correction, color space conversion) on the RGB Bayer signal normalized for each image data read channel RCH0 to RCH3. 2 is a second image processing unit for performing processing and the like. In FIG. 1, for convenience of illustration, the output of the four channels of the SPU 100 is shown as a single signal in a pseudo manner. Since the core part of the present embodiment is in the internal configuration of the SPU 100, the configuration and operation of the SPU 100 will be described in detail below.

  FIG. 2 is a block diagram schematically showing the main part of the configuration of the SPU 100. The SPU 100 is roughly divided into (1) first to fourth channel correction processing units SPU-C0 to SPU-C3 including four units corresponding to the number of image data read channels of the image sensor, and (2) 3 Common to each of the color timing arrangement unit 10 that generates and outputs the color selection timing signals C0CS to C3CS for each channel, which is a bit signal, and (3) the first to fourth channel correction processing units SPU-C0 to SPU-C3 The SPU register 9 stores the black level correction data DL0 to DL7 (18-bit signal) for each of the eight types and the white balance correction data WB0 to WB7 (18-bit signal) for each of the eight types. Here, in the Bayer array, although the color of each pixel is basically specified by four colors of R, Gr, Gb, and B, in this embodiment, the SPU 100 can support eight types of colors. This is because the readout pattern shown in FIG. 28 described above can be supported.

  Among these components, the first to fourth channel correction processing units SPU-C0 to SPU-C3 are read out in synchronization with the pixel clock from each of a plurality of image data readout channels of the image sensor IS. Each image signal is received for each pixel clock through an input channel corresponding to the image data readout channel, and the received image data (C0Input to C3Input) is received according to the color selection timing signal (C0CS to C3CS). This corresponds to a pipeline-type image sensor pre-processing unit for a plurality of input channels that executes the predetermined image processing in parallel for each pixel clock.

  The color timing arrangement unit 10 is one of the characteristic components of the present embodiment. A horizontal counter and a vertical counter (both at this stage) that define and manage the timing of reading image data from the image sensor IS. (Not shown)), color selection timing signals C0CS to C3CS for designating the color of the pixel at a certain point of time independently for each input channel are generated, and the image sensor before each input channel is generated. It is a circuit that outputs corresponding color selection timing signals to the processing units SPU-C0 to SPU-C3.

  The image data C0Input to C3Input read in accordance with the pixel clock from the image sensor IS are input in parallel to the input channels of the first to fourth channel correction processing units SPU-C0 to SPU-C3. . Further, since the internal configurations of the correction processing units SPU-C0 to SPU-C3 for each channel are equivalent to each other, the description of the internal configuration of each correction processing unit is the same as the internal configuration of the first channel correction processing unit SPU-C0. It will be represented by the description. As shown in FIG. 2, the first selector 11C0 selects the black level corresponding to the color at the pixel position to which the image data C0Input input at this time is selected from among the eight types of black level correction data DL0 to DL7 input. The correction data is selected and output based on the designated value of the input first channel color selection timing signal C0CS. Then, the black level correction processing unit 13C0 performs black level correction on the input image data C0Input based on the black level correction data selected from the black level correction data DL0 to DL7. Further, the second selector 12C0 similarly selects the white balance correction data corresponding to the color at the pixel position to which the image data C0Input inputted at this time is input from among the eight types of white balance correction data WB0 to WB7 inputted. Selection / output is performed based on the designated value of the color selection timing signal C0CS for the first channel. As a result, the white balance correction processing unit 14C0 applies the white balance correction data to the input image data C0Input based on the white balance correction data selected from the white balance correction data WB0 to WB7, and the input image data C0Input. Is normalized. Note that other processes such as a defective pixel correction process executed thereafter are omitted in FIG.

  As shown in FIG. 2, another feature point of the SPU 100 is that the SPU register 9 is not provided in the correction processing units SPU-C0 to SPU-C3 for each channel. The fourth channel correction processing units SPU-C0 to SPU-C3 are separately provided outside. By sharing the correction data held by the SPU register 9 as described above, the number of gates constituting the register can be significantly reduced, and the power consumption of the SPU 100 can be reduced.

  Hereinafter, the configuration and operation of the color timing arrangement unit 10 which is one of the core units will be described.

  First, from the viewpoint of facilitating understanding of the basic configuration and operation of the color timing arrangement unit 10, the number of image readout channels is set to 2, and 2 pixels in the horizontal direction and 2 in the vertical direction under the Bayer array. Assume that the image data is read out in a 2 × 2 repetition range or period composed of pixels. FIG. 3 is a diagram illustrating the configuration and repeating range of the color timing arrangement unit in such a case.

  In FIG. 3, a global H counter 1 and a global V counter 2 correspond to the global H counter 1 and the global V counter 2 described above with reference to FIG. In the case of FIG. 3, the image reading repetition range is a 2 × 2 region, and therefore the color base timing signal CLBASET for specifying the pixel position within the repetition range at a certain time may be a 2-bit signal. Therefore, in the basic example of FIG. 3, the color base timing signal CLBASET includes the least significant bit signal HCNT (0) of the count value HCNT of the global H counter 1 and the least significant bit signal VCNT (0) of the count value VCNT of the global V counter 2. ). Also, the black level correction data for each of the four colors under the Bayer arrangement is stored in advance in the registers BL0 to BL3, and the black level correction data register unit BLR including the four registers BL0 to BL3 It is commonly used for each input channel CH0, CH1. 3 is notable in that the timing registers TRCH0 and TRCH1 and the timing register selectors TSELCH0 and TSELCH1 are provided separately for each of the input channels CH0 and CH1. Here, the timing register TRCH0 for the first channel CH0 corresponding to the first image data readout channel has colors (in four colors under the Bayer array) at each location within the above-described repetition range of the color base timing signal CLBASET. 4 registers T01 to T04 (the values are stored by a CPU (not shown)) for giving any color. That is, the timing register TRCH0 selects the position of each register T01 to T04 with the least significant bit of each counter, and then selects the color value corresponding to each position in the register. This is a so-called “index register” stored by the CPU. Further, the timing register TRCH1 for the second channel CH1 corresponding to the second image data read channel has the same configuration as the timing register TRCH0 independently of the timing register TRCH0. Then, the selector TSELCH0 for the first channel CH0 sets the command value of the color base timing signal CLBASET output from the registers T01 to T04 in the timing register TRCH0 according to the input to the counters 1 and 2 of the pixel clock CLK. The corresponding register value is selected, and the selected signal (2 bits) is output as the color selection timing signal C0CS for the first channel CH0 to the selector BLSELCH0 in the correction processor SPU-C0 for the first channel CH0. . The color selection timing signal C0CS designates the color of the pixel from which the image data is read from the first image data read channel at a certain time. Similarly, for the second channel CH1, independently of the first channel CH0, the second channel CH1 selector TSELCH1 sets the command value of the color base timing signal CLBASET from the registers T11 to T14 in the timing register TRCH1. The corresponding register value is selected, and the selected signal (2 bits) is output to the selector BLSELCH1 in the correction processor SPU-C1 for the second channel CH1 as the color selection timing signal C1CS for the second channel CH1. . The color selection timing signal C1CS also specifies the color of the pixel from which the image data is read from the second image data read channel in parallel at the certain time point, independently of the first channel CH0.

  The feature of the circuit of FIG. 3 is that, as described above, once the corresponding register is selected from a plurality of registers in the timing register by the color base timing signal CLBASET, the color generated by the selection is selected. The black level correction data corresponding to the color of the pixel at a certain point in time is appropriately selected by the selection timing signal. In other words, the circuit of FIG. 3 employs a configuration in which the timing for reading image data is first selected, and then black level correction data at the selected timing is selected. With this configuration, the SPU 100 can cope with various image reading patterns by allowing the repetition range to be arbitrarily set. On the other hand, in the conventional configuration shown in FIG. 25 described above, the black level correction data for each channel is directly read from the register BLR by the color selection signal COLSEL generated from both counters 1 and 2, so that the SPU 100P has various images. The read pattern can no longer be supported.

  Based on the understanding of the above description, an implementation example of the color timing arrangement unit 10 of FIG. 2 will be examined next.

  4 and 5 are block diagrams illustrating an example of mounting the color timing arrangement unit 10. 4 is provided with a local H counter 5 and a local V counter 6 in addition to the global H counter 1 and the global V counter 2 of FIG. The timing signal CLBASET is generated. Here, the global H counter 1 and the global V counter 2 in FIG. 5 correspond to the global H counter 1 and the global V counter 2 described in FIGS. 25 and 3, respectively, and the effective pixel area of the image sensor IP. The position of the readout target pixel in the whole is determined.

  Among these components, the local H counter 5 includes a horizontal reset signal HRESET output from the carry-out terminal CO of the global H counter 1 in FIG. 5 and a reset signal HVRESET for the entire effective pixel area of the image sensor IS. And a horizontal horizontal counter that determines the period in the horizontal direction of the repetition range of the color base timing signal CLBASET within a range of a maximum of n bits (n ≧ 1). Here, as shown in FIG. 5, the reset signal HVRESET is output from the AND circuit 3 using the horizontal direction reset signal HRESET and the vertical direction reset signal VRESET output from the carry-out terminal CO of the global vertical direction counter 2 as its input signals. Signal. As described above, the local H counter 5 can set the period in the horizontal direction of the repetition range to an arbitrary value within a range of maximum n bits. That is, as shown in FIG. 4, the local H counter 5 has data in the horizontal direction of the repetition range that can be designated up to the maximum value n bits (stored in advance by the CPU). In this implementation example, the data stored in the register 5R is n = 3 bits, that is, 8 (= 07). Therefore, the local H counter 5 has a repeat range. For the horizontal period, a 3-bit count value is output (HC (0), HC (1), HC (2)). On the other hand, the local V counter 6 is reset by the output signal HVRESET of the AND circuit 3, and the period of the color base timing signal CLBASET in the vertical direction of the repetition range is within a maximum m bits (m ≧ 1). The vertical vertical counter of the repetition range can be set to an arbitrary value within a range of maximum m bits. That is, as shown in FIG. 4, the local V counter 6 has data in a cycle in the vertical direction of the repeat range that can be designated up to the maximum value m bits (stored in advance by the CPU). In this implementation example, the data stored in the register 5R is m = n = 3 bits, that is, 8 (= 07). Therefore, the local V counter 6 is For the vertical period of the repeat range, a 3-bit count value is output (VC (0), VC (1), VC (2)).

  For example, if the values in the registers 5R and 6R are set to 2 and 2 respectively by the CPU, the repetition range of the color base timing signal CLBASET generated by the count values of both the local H counter 5 and the local V counter 6 is as shown in FIG. This is the 3 × 3 area shown in 6 (a). If the values in the registers 5R and 6R are set to 2 and 3, respectively, by the CPU, the repetition range becomes a 3 × 4 area shown in FIG. 6B. In this manner, by appropriately determining the values to be set in the registers 5R and 6R, the user of the SPU 100 can repeat any size or any pattern within a maximum range of 8 × 8. The range can be easily realized, and it is possible to deal with various image data read patterns by using such an arbitrary pattern repetition range.

  As described above, the local H counter 5 and the local V counter 6 are incorporated in the circuit of FIG. 4 in order to generate a repetition range of a local arbitrary cycle. That is, the AND circuit 3 uses the horizontal direction reset signal HRESET and the vertical direction reset signal VRESET output from the carry-out terminal CO of the global V counter 2 as its input signals. The local H counter 5 is reset in synchronization with the reset of the global H counter 1, that is, reset by the horizontal reset signal HRESET and the output signal HVRESET of the AND circuit 3, and the horizontal range of the color base timing signal is repeated. The period in the direction is determined within a range of at most n bits (n ≧ 1). Further, the local V counter 6 is reset in synchronization with the reset of the global V counter 2, that is, reset by the output signal HVRESET of the AND circuit 3, and the period in the vertical direction of the repetition range of the color base timing signal is set. It is determined within a range of maximum m bits (m ≧ 1).

  As described above, in the repetition range of the maximum size 8 × 8 that can be realized by both count values of the local H counter 5 and the local V counter 6 (when using the lower 3 bits of each local counter) 64 locations that define the color value are given, but such a large location of 64 is not necessary in view of the actual readout pattern. In practice, in a read pattern that extends long in the horizontal direction and repeats, the repetition length or cycle in the vertical direction is relatively short. Similarly, in a read pattern that extends long and repeats in the vertical direction, the repeat length or cycle is relatively short in the horizontal direction. In consideration of such a structural feature of the readout pattern, the inventor of the present application considered that the number of locations included in the repetition range of the color base timing signal CLBASET is 16 is sufficient. When the number of locations included in the repeat range is 16, only three types of repeat ranges of 4 × 4, 8 × 2, and 2 × 8 can be set. Therefore, in the circuit of FIG. 4, the first selector 7 using both count values HC (1) and VC (2) as input signals and the signal VLEN set by the CPU as its select signal, and both count values HC, respectively. (2) and VC (1) are input signals, respectively, and a second selector 8 having a signal HLEN set by the CPU as its select signal is provided on the output side of the local H counter 5 and the local V counter 6, Four count signals CLBASET (0) = HC (0), output signal CLBASET (1) of the first selector 7, output signal CLBASET (3) of the second selector 8, and count signal CLBASET (2) = VC (0) Are combined to generate an 8-bit color base timing signal CLBASET. Therefore, the color base timing signal CLBASET is a timing signal indicating a place at a certain point in time within a repeating range of 16 places.

  The combination of select signals VLEN and HLEN set by a CPU (not shown) based on the actual image data read pattern of the image sensor IS used by the user is shown in FIG. 7 in the circuit of FIG. Street. That is, as shown in FIG. 7A, VLEN = 0 and HLEN = 0, and therefore, a repetition range of 4 × 4 size is obtained by combining the lower 2 bits of each of the local H counter 5 and the local V counter 6. Can be realized. Alternatively, as shown in FIG. 7B, by setting VLEN = 0 and HLEN = 1, the pixel is repeated by 8 pixels in the horizontal direction and repeated by 2 pixels or 2 lines in the vertical direction. A repeatable size range can be realized. Alternatively, as shown in FIG. 7C, by setting VLEN = 1 and HLEN = 0, the pixel is repeated 2 pixels in the horizontal direction and 8 pixels in the vertical direction. Can be realized. In this way, by selectively assigning the lower 2 bits of each of the local H counter 5 and the local V counter 6, the repetition range of the color base timing signal CLBASET can be changed as appropriate. Of course, when a very complicated read pattern is required, the bit length of the horizontal and vertical counters of the present invention may be expanded to realize a repetition range of 8 × 8, 16 × 16, or the like.

  By appropriately selecting and setting the repetition range of the three types of color base timing signals CLBASET as described above, the SPU 100 having the circuit of FIG. 4 can cope with various image data reading patterns of the image sensor IS. Become.

  As shown in FIG. 4, timing registers TR0 to TR3 and timing register selectors TRS0 to TRS3 are provided independently for each of the input channels CH0, CH1, CH2, and CH3. As described above with reference to FIG. 3, each of the timing registers TR0 to TR3 is an index register and has 16 registers because the number of locations within the repetition range of the color base timing signal CLBASET is 16. Therefore, the user selects the position of each of the 16 registers by the signal obtained by combining the lower 2 bits of both counters 1 and 2 and then corresponds to the register at each position selected by the CPU. Stores color data for each location within the repeat range. As a result, each of the timing registers TR0 to TR3 outputs the outputs of 16 registers that determine the color type at the corresponding place within the repetition range at a certain reading time point (the output has 8 types of color types). Therefore, it is an 8-bit signal. Each selector TRSX (X: 0 to 3) reads out each of the 16 outputs of the corresponding timing register TRX (X: 0 to 3) according to the level of the input color base timing signal CLBASET. Select the output of the register that gives the type of color at the corresponding location in the repetition range at the time, and select the output of the selected register as the color selection timing signal in each input channel CHX (X: 0 to 3) Output as CXCS (X: 0 to 3). The color selection timing signal CXCS output from each selector TRSX is the color selection timing signal C0CS, C1CS, C2CS, C3CS (3-bit signal) in FIG.

  As is apparent from the above description, the circuit portion composed of the constituent elements 1, 2, 3, 4, 5, 6, 7, and 8 includes the least significant bits (1 A color base timing signal CLBASET that defines a repetitive range by combining at least the least significant bit (at least one bit) of the output signal of the vertical counter with the least significant bit (one bit or more). Part ". In addition, as long as the pattern of the repeating range of (a), (b), and (c) of FIG. 7 is adopted, there is no necessity to apply the local H counter 5 and the local V counter 6, and instead, FIG. Using the count values of the global H counter 1 and the global V counter 2, the color base timing signal CLBASET that realizes the pattern of the repetition range of (a), (b), and (c) of FIG. 7 can be generated. In that sense, the “horizontal counter” mentioned above is a technical term that encompasses both the case where only the global H counter 1 is used and the case where the local H counter 5 is also used. Similarly, the “vertical counter” mentioned above is a technical term encompassing both the case where only the global V counter 2 is used and the case where the local V counter 6 is also used. Further, the selectors 7 and 8 in FIG. 4 are collectively referred to as “selector section”.

  The functions or advantages that can be realized by the SPU 100 of FIG. 2 are, as is apparent from the above description, 8 colors can be supported, and the timing signal that gives the colors is independent for each input channel. The color type within the range can be set independently for each channel. Accordingly, eight black level correction data (or eight white balance correction data) stored in the SPU register 9 provided outside each input channel correction processing unit SPU-CX (X: 0 to 3). Will be selected for each place in the repeat range. In other words, the SPU 100 can execute a process of assigning a color corresponding to a read pattern independently to each of the correction processing units of the four input channels at an arbitrary timing.

<Black level two-dimensional modulation correction>
As described above, the first stage of normalization processing of the RGB Bayer signal due to the influence of miniaturization accompanying the increase in the number of pixels of the image sensor IS or the influence of the location where the chip of the image sensor IS is cut out from the semiconductor wafer. The black level correction data of each color in the black level correction cannot be regarded as a constant value throughout the entire screen. In other words, the black level correction data of each color is slightly distorted (not uniform) over the entire screen of the image sensor IS. In other words, offset drift occurs in the black level correction data of each color over the entire screen. For example, as illustrated in FIG. 8, in the effective pixel area EPR, black level correction data DLix in the x direction and the y direction of each color i in four colors (R, Gr, Gb, B), In DLiy, offset values ΔMx and ΔMy are generated, and the offset values ΔMx and ΔMy slightly change over the entire effective pixel region EPR. In order to remove such an offset drift of the black level correction data of each color, the offset value ΔMx, ΔMy of the black level correction data DLix, DLy at the position of the pixel is set to a constant value for every pixel. The black level correction data DLix and DLiy may be subtracted one by one. However, such sequential correction for each pixel and for each color must be said to be an unrealistic method in view of the number of pixels of the image sensor IS. Therefore, there is a demand for a practical measure that can effectively reduce the offset drift of black level correction data that occurs over the entire screen as illustrated in FIG.

  Therefore, in the present embodiment, the black level correction processing unit 13CX (X: 0 to 3) in the SPU circuit SPU-CX (X: 0 to 3) of each input channel shown in FIG. 1 and a plurality of black level modulation data discretely arranged in the position coordinates defined by the global vertical counter 2 are stored, and the black level correction data at the pixel position corresponding to the input image signal is stored. The modulation data is obtained by interpolation using the plurality of black level modulation data. According to this approximation method, it is sufficient that each SPU circuit SPU-CX has the plurality of black level modulation data.

  As the circuit configuration of the black level correction processing unit 13CX (X: 0 to 3) of each input channel CHX, two types can be considered. As the first type, for example, as illustrated in FIG. 9, the selector 11CX is selected from the input image data CXInput (X: 0 to 3) according to the command value of the color selection timing signal CXCS (X: 0 to 3). A subtractor 28 subtracts a fixed value of black level correction data DLi (i: 0 to 3) relating to the color of the pixel corresponding to the input image data CXInput selected by (X: 0 to 3), and then a modulation circuit. The subtractor 29 may subtract the modulation data MDLi (i: 0 to 3) of the pixel calculated by 2DCOR by interpolation. In this case, even if the front and rear of the subtracters 28 and 29 are reversed, the modulation result of the black level signal is the same. In FIG. 9, for the sake of convenience, the SPU register 9 has four registers 91 to 94 for storing black color correction data DL0, DL1, DL2, DL3 of four colors (R, Gr, Gb, B), respectively. It is said.

  Alternatively, as the second type, for example, as illustrated in FIG. 10, the black level correction processing unit 13CX (X: 0 to 3) of each input channel CHX may be configured. In this example, the multiplier 30 has the color of the pixel selected by the modulation data MDLiP (i: 0 to 3) and the selector 11CX (X: 0 to 3) of the pixel calculated by the interpolation circuit 2DCOR by interpolation. The black level correction data (constant value) DLi is multiplied to obtain modulation data MDLi (i: 0 to 3), and the value is subtracted from the input image data CXInput in the subtractor 31.

  In any type, the black level correction processing unit 13CX (X: 0 to 3) of each input channel CHX has a color corresponding to the input image signal according to the position of the pixel corresponding to the input image signal. It can be said that constant black level correction data is modulated and the modulation data is subtracted from the input image signal. In the following description, for the sake of convenience, the configuration of the type shown in FIG. 9 is considered.

  FIG. 11 is a diagram schematically showing a method of calculating modulation data in the modulation circuit 2DCOR, where the horizontal axis is the count value HCNT (X of the global H counter (hereinafter simply referred to as H (horizontal) counter) 1). The vertical axis represents the count value VCNT (Y) of the global V counter (hereinafter simply referred to as V (vertical) counter) 2. Moreover, in FIG. 11, for convenience, as a best case, black level modulation data P (00), P (01), P (10), P (10), P at each pixel position at the four corners of the effective pixel region EPR of the image sensor IS. P (11) is arranged. Here, the four black level modulation data P (00), P (01), P (10), and P (11) are stored in advance in a register (not shown) of the modulation circuit 2DCOR by a CPU (not shown). Z.) is stored. The black level modulation data P (00), P (01), P (10), and P (11) are respectively stored in the image sensor IS having a non-uniform two-dimensional offset value by the digital camera manufacturer. A black level signal at each pixel position is measured with respect to the screen, and each pixel position (10, 10), (2058, 10), (10, 1510), (2058, 1510) is measured based on the measurement result. After calculating data corresponding to the offset value (see offset values ΔMx, ΔMy in FIG. 8), the calculated value is set in the corresponding register.

  In FIG. 11, the modulation circuit 2DCOR converts black level modulation data P (X, Y) at a certain pixel position (X, Y) into black point modulation data P (00 at four preset points). ), P (01), P (10), and P (11), and has an interpolation unit that calculates by interpolation, that is, linear interpolation. For example, when the black level signal has an offset drift such that the black level modulation data P (00), P (01), P (10), and P (11) are 100, 20, 20, and 10, respectively. The value of the modulation data P (X, Y) at the center position of the effective pixel region EPR is 37.5 when approximated by linear interpolation. In this way, the modulation circuit 2DCOR according to the present embodiment, in the case of FIG. 11, has four pieces of preset black level modulation data P (00), P (01), P (10), P ( The value of the modulation data P (X, Y) at each pixel position is determined by interpolation using 11). In this case, the modulation circuit 2DCOR needs to hold only four pieces of black level modulation data P (00), P (01), P (10), and P (11) as data. Then, the modulation data P (X, Y) at each pixel position can be obtained.

  FIG. 12 is a diagram illustrating another example of obtaining the modulation data P (X, Y) at each pixel position by interpolation interpolation. In FIG. 12, the number of black level modulation data set in advance by the digital camera manufacturer is nine, and four black level modulation data are provided at each corner of the effective pixel area EPR as in FIG. P (00), P (02), P (20), P (22) are arranged, and four black level modulation data P (01), P (10) are also arranged in the middle of each side of the effective pixel region EPR. ), P (21), P (12), and black level modulation data P (11) is also arranged at the center position of the effective pixel region EPR. As a result, the effective pixel region EPR is divided into four blocks <R0>, <R1>, <R2>, and <R3> by the nine black level modulation data. In the case of FIG. 12, the modulation circuit 2DCOR outputs the modulation data P (X, Y) at the pixel position (X, Y) belonging to each block <Ri> (i: 0 to 3) to the block <Ri. > Is obtained by interpolation using four black level modulation data arranged at the four corners. For example, the modulation data P (X, Y) at the pixel position (X, Y) belonging to the block <R0> is four black level modulation data P (00), P (01), P (10), It is obtained by interpolation calculation using P (11). Also, the modulation data P (X, Y) at the pixel position (X, Y) belonging to the block <R1> is four black level modulation data P (01), P (02), P (11), It is obtained by an interpolation calculation using P (12). The same applies to the other blocks <R2> and <R3>. As described above, the modulation circuit 2DCOR according to the present embodiment, in the example of FIG. 12, has nine black level modulation data P (00), P (01), P (10), Modulation data P (X, Y) at each pixel position is obtained by interpolation using P (11), P (02), P (12), P (20), P (21), and P (22). Determine the value of. In this case, since the modulation circuit 2DCOR only needs to hold the nine black level modulation data as data, similarly, the modulation data P (X, Y) can be obtained.

  The principle of the method of calculating the modulation data (offset value) at each pixel position in the modulation circuit 2DCOR according to the present embodiment is as described above, but there are the following problems.

  That is, when interpolation data of each pixel position is interpolated from a plurality of black level modulation data, division processing is always included in the interpolation interpolation equation. For example, as can be seen in the one-dimensional interpolation shown in FIG. 13, an operation that gives an arbitrary point P (X, Y) located between two points (0, A), (L, B). The formula is Y = A + (B−A) / L × X, and this formula also includes a division process of 1 / L. In such division processing (division), when designing and manufacturing the SPU 100 with LSI, the circuit scale increases with the increase in the number of gates, and division is generally a troublesome process for LSI circuits. It can be said that.

However, since division cannot be excluded from the interpolation equation, if the division equation that appears in the interpolation equation can be given in the form of 1/2 ⁿ instead. The LSI circuit can easily cope with the shift processing using a shift register (for example, binary number 100 is 4 in decimal number and binary number 100 is shifted to the right by 1 bit). Since the decimal number 010 is 2 in decimal, the process of shifting binary data to the right by 1 bit corresponds to 1/2 in decimal.)

Therefore, in the modulation circuit 2DCOR of the present embodiment, as shown in FIG. 14, the modulation range defined by a plurality of preset black level modulation data is excluded except when adjacent on a diagonal line. The interval between the black level modulation data adjacent to each other is set to a range in which the interval is always 2 ⁿ (n is a positive integer). Due to the arrangement of the black level modulation data, the modulation range has a position interval 2 in the horizontal direction and the vertical direction from the center position of the modulation range corresponding to the position where the black level modulation data M2DR11 is arranged as shown in FIG. Each black level modulation data is symmetrically arranged at each position separated by ⁿ , and each of them is divided into four zones or small areas defined by four black level modulation data. It becomes an area. In the example of FIG. 14, the modulation range in which the nine black level modulation data are arranged is a square having a size of 4096 × 4096. Therefore, the number of pixels in the effective pixel region EPR of the image sensor IS is about 10 M pixels. Become.

  It should be noted that the center position coordinates of the modulation range in which nine black level modulation data are arranged as shown in FIG. 14 and the center position coordinates of the effective pixel region EPR of the image sensor IS are generally Does not match. In the case where there is such a wrinkle between the center position coordinates, the correction accuracy is lowered. Therefore, the position coordinate axes defined by the count value HCNT (X) of the H counter 1 and the count value VCNT (Y) of the V counter 2 are reduced. The physical origin “Poriginal” is shifted so that the center position coordinates of the modulation range and the center position coordinates of the effective pixel region EPR of the image sensor IS to be used coincide with each other. In FIG. 14, the virtual origin of the position coordinate axis after such a shift process is represented as a point P (0, 0). Such shift processing of the origin of the position coordinate axes is defined by the nine black level modulation data shown in FIG. 14 (in other words, the count value HCNT (X) of the H counter 1 and the V counter 2 After obtaining the position coordinates of the center of the modulation range (defined by the upper bits of the count value VCNT (Y)) and the position coordinates of the center of the effective pixel area of the image sensor to be used, the position coordinates of both centers are mutually This is achieved by calculating an offset value that can take a positive value and a negative value that match, and then independently adding the calculated offset value to each output value of the H counter 1 and the V counter 2. As a result, as shown in FIG. 14, at a pixel position separated from the virtual origin P (0, 0) after the shift (after adding the offset value) by x in the horizontal direction and y by the vertical direction. The modulation data M2DRES, which is the black level offset value, is obtained by interpolation from the black level correction data M2DROO, M2DR01, M2DR10, and M2DR11 arranged at the four corners of the upper left zone. Similarly, the calculation of the modulation data at the pixel positions belonging to other zones is also obtained by interpolating from the black level correction data at the four corners of the zone.

  FIG. 15 is a block diagram showing a specific configuration example of the modulation circuit 2DCOR that executes the method of interpolating modulation data shown in FIG. In FIG. 15, the register 1OR modulates the physical origin “Poriginal” of the position coordinate axis defined by the count value HCNT (X) of the H counter 1 and the count value VCNT (Y) of the V counter 2 described above. The shift amount in the horizontal direction when shifting so that the center position coordinates of the range and the center position coordinates of the effective pixel region EPR of the image sensor IS to be used coincide with each other, that is, the offset value Hoff (+/−) (FIG. 14 offset value M2DHCOF). The adder 32 adds the offset value Hoff (+/−) to the count value HCNT (13-bit signal) of the H counter 1. Similarly, the register 2OR performs vertical shift when shifting the physical origin of the position coordinate axis so that the center position coordinate of the modulation range and the center position coordinate of the effective pixel region EPR of the image sensor IS to be used coincide with each other. The shift amount in the direction, that is, the offset value Voff (+/−) (corresponding to the offset value M2DVCOF in FIG. 14) is held. The adder 33 then adds the offset value Voff (+/−) to the count value VCNT (13-bit signal) of the V counter 2.

  In the circuit example of FIG. 15, the count value HCNT of the 13-bit signal added with the offset value Hoff (+/−) is the three counter output signals HCNT [12: 4], HCNT [11: 3], and HCNT [ 10: 2]. Here, for convenience of explanation, the three counter output signals HCNT [12: 4], HCNT [11: 3], and HCNT [10: 2] are all 8-bit signals. Then, the selector 34 has three counter output signals HCNT [12: 4], HCNT [11: 3], HCNT [10: 2] in accordance with a command value of a select signal SELH issued by a CPU (not shown). Select. This selection defines the physical width of the modulation range in the horizontal direction, as will be described later. Similarly, the count value VCNT of the 13-bit signal to which the offset value Voff (+/−) is added is an 8-bit signal, and three counter output signals VCNT [12: 4] and VCNT [11: 3] ], VCNT [10: 2]. Then, the selector 35 has three counter output signals VCNT [12: 4], VCNT [11: 3], VCNT [10: 2] in accordance with a command value of a select signal SELV issued by a CPU (not shown). Select. Similarly, this selection defines the physical width of the modulation range in the vertical direction, as will be described later.

Here, for convenience, the counter output signal HCNT [12: 4] is selected as the output signal AHC (8-bit signal) of the selector 34, and the counter output signal VCNT [12] is selected as the output signal AVC (8-bit signal) of the selector 35. : 4] is selected. In such a selection, the modulation range defined by both counter output signals HCNT [12: 4], VCNT [12: 4] is a 256 × 256 square as illustrated in FIG. In this example, the 256 × 256 modulation range includes a total of nine black level modulation data, that is, black level modulation data P11 at the center position of the modulation range, and 4 at each of the four corner positions. The black level modulation data P00, P02, P20, and P22, and four black level modulation data P01, P10, P12, and P21 at the center positions of the sides. As a result, the modulation range is divided into four zones or regions <R0> to <R3> each of which is a square having a width of 128 (2 ⁷ ) × 128 (2 ⁷ ).

  In the circuit of FIG. 15, the nine black level modulation data P11, P00, P02, P20, P22, P01, P10, P12, and P21 are previously stored in CPUs (not shown) in the corresponding registers MR1 to MR9. ) Is stored. Then, the most significant bit AHC (7) of the output signal AHC of the selector 34 (corresponding to the counter output signal HCNT [12: 4]) and the output signal AVC of the selector 35 (corresponding to the counter output signal VCNT [12: 4]). The most significant bit AVC (7) is combined, and the combined 2-bit signal becomes a select signal for each selector 36, 37, 38, 39. Therefore, the position of the combined signal of the most significant bit AHC (7) of the output signal AHC and the most significant bit AVC (7) of the output signal AVC is defined by the H counter 1 and the V counter 2. It defines which of the four regions <R0> to <R3> shown in FIG. That is, when the value of 0 of each selector 36, 37, 38, 39 is selected, it is determined that the target pixel is located in the region <R0> in FIG. When the value of 1 of each selector 36, 37, 38, 39 is selected, it is determined that the target pixel is located in the region <R1> in FIG. When the two values of the selectors 36, 37, 38, and 39 are selected, it is determined that the pixel of interest is located in the region <R2> in FIG. When the three values of the selectors 36, 37, 38, and 39 are selected, it is determined that the pixel of interest is located in the region <R3> in FIG.

  The remaining lower bit signal AHC [6: 0] of the output signal AHC is the local origin of the region <Rj> (j: 0 to 3) to which the pixel of interest belongs, that is, the position of the upper left corner of the region. A position separated by x in the horizontal direction is defined. Similarly, the remaining lower bit signal AVC [6: 0] of the output signal AVC is the local origin of the region <Rj> (j: 0 to 3) to which the pixel of interest belongs, that is, the upper left corner of the region. A position separated by y in the vertical direction is defined.

The modulation range shown in FIG. 16, except when adjacent diagonally, as composed to the black level modulation data always 2 ⁷ interval position is adjacent to each other, it is arranged nine black level modulation data Therefore, when the pixel of interest belongs to a region <Rj> (j: 0 to 3) among the four regions <R0> to <R3>, the interpolation / interpolation calculation unit 40 in FIG. Is

The modulation data Pout at the local pixel position (x, y) of the pixel of interest is calculated on the basis of the expression given in (5), and the calculation result Pout is output to the subtractor 29 as data MDLi (see FIG. 9). At that time, the interpolation interpolation unit 40 performs division in the equation given by Equation 1 by shift processing. Therefore, an increase in circuit scale, which is a problem when performing division in LSI, is avoided. As a result of calculation / output by the interpolation unit 40, the offset value of the black level signal at the local pixel position (x, y) is removed or reduced.

  When the modulation range in FIG. 16 is set to 16 divisions, the 2-bit signal consisting of the most significant bit AHC (7) of the output signal AHC and the next higher bit AHC (6) and the most significant of the output signal AVC. A combined signal of a 2-bit signal composed of the upper bit AVC (7) and the next higher bit AVC (6) may be used as a select signal for each selector.

  In the circuit of FIG. 15, the CPU (not shown) selects the select signal SELH so that the selector 34 selects the signal HCNT [11: 3] and the selector 35 selects the signal VCNT [11: 3]. , SELV is controlled, the modulation range is reduced to a second modulation range <R0A> corresponding to a quarter of the first modulation range <R>, as shown in FIG. Further, when the selector 34 selects the signal HCNT [10: 2] and the selector 35 selects the signal VCNT [10: 2], the modulation range is 1/4 of the second modulation range <R0A>. Is further reduced to the third modulation range <R0AA> corresponding to the region. Further, if the count values HCNT [12: 0] and VCNT [12: 0] are finely separated, a modulation range in which the physical range is further narrowed can be realized. Alternatively, if the number of bits of the signal separated from the count values HCNT [12: 0] and VCNT [12: 0] is increased, the physical range becomes wider than the first modulation range <R> in FIG. Range can be realized. Thus, by appropriately selecting the upper bits of the count values HCNT [12: 0] and VCNT [12: 0] according to the size or size of the effective pixel region EPR of the image sensor IS to be used, The physical width of the modulation range can be changed.

<White balance gain two-dimensional modulation correction>
As described above, the miniaturization of the image sensor IS for increasing the number of pixels has an effect that the correction data causes drift over the entire screen even in the white balance correction. Therefore, the solution described in the column of <Black level two-dimensional modulation correction> is also adopted for white balance correction data. That is, the white balance correction processing unit 14Ci (i: 0 to 3) (see FIG. 2) of each input channel has a constant color corresponding to the input image signal according to the position of the pixel corresponding to the input image signal. The white balance correction data is modulated and the input image signal is multiplied by the modulation data.

More specifically, the white balance correction processing unit has a plurality of white balance modulation data discretely arranged within the position coordinates defined by the horizontal counter 1 and the vertical counter 2 and corresponds to the input image signal. The modulation data at the position of the pixel to be determined is obtained by interpolation using a plurality of white balance modulation data. At that time, the white balance correction processing unit is arranged so that the interval between the arrangement positions of the adjacent white balance modulation data is always 2 ⁿ (n is a positive integer), except when adjacent on the diagonal line. The interpolation is performed using a plurality of white balance modulation data. In the interpolation, the white balance correction processing unit selects the upper bits of the horizontal counter 1 and the vertical counter 2 to define the physical width of the modulation range and can take positive and negative values. The offset value is independently added to the output values of the horizontal counter 1 and the vertical counter 2 so that the center of the modulation range defined by the plurality of white balance modulation data matches the center of the effective pixel area EPR of the image sensor IS. After that, the interpolation interpolation is performed.

  Since the configuration and modulation method of the white balance correction processing unit are basically the same as the configuration and operation of the modulation circuit for black level correction data, illustration thereof is omitted.

<Tailing correction gain two-dimensional modulation correction>
As shown in FIG. 18, due to the deterioration of the characteristics accompanying the increase in the number of pixels of the image sensor IS, the image input to each input channel SPU circuit SPU-Ci (i: 0 to 3) of the SPU circuit 100 (FIG. 2). The data waveform is tailed. Each input channel SPU circuit SPU-Ci (i: 0 to 3) corrects the rising and falling rounds of such a waveform with reference to a tail correction processing unit (see FIG. 22 of an implementation example described later). ). That is, for each pixel clock CLK, the tail correction processing unit outputs a difference signal (P _n−1 −P) between the image signal P _n of a certain target pixel and the image signal P _n−1 of the same color pixel near the target pixel. _The tail correction value αΔ obtained by multiplying _n ) by a constant tail correction gain α is added to the received image data P _n (see FIG. 18), and the tail correction processing is executed. However, like the black level correction data, the tail correction gain α itself used in such a tail correction process also drifts over the entire screen due to the effect of miniaturization.

  Therefore, in the present embodiment, the solving means described in the column of <Black level two-dimensional modulation correction> is fully adopted for the tail correction gain α. That is, the tail correction processing unit modulates the tail correction gain of the color corresponding to the input image signal according to the position of the target pixel corresponding to the input image signal, and converts the modulated correction gain into the difference. A tail correction value is obtained by multiplying the signal.

More specifically, the tail correction processing unit has a plurality of tail correction gain modulation data discretely arranged in the position coordinates defined by the horizontal counter 1 and the vertical counter 2, and the input image signal The modulation correction gain at the position of the pixel of interest corresponding to is obtained by interpolation using a plurality of tail correction gain modulation data. In particular, in order to enable division in the interpolation equation to be executed by LSI shift processing, the tail correction processing unit performs a correction between adjacent tail correction correction modulation data except for cases adjacent to each other on a diagonal line. The interpolation is performed using a plurality of tail correction gain modulation data arranged so that the interval between the arrangement positions is always 2 ⁿ (n is a positive integer). At that time, the tailing correction processing unit defines the physical width of the modulation range by selecting the upper bits of the horizontal counter 1 and the vertical counter 2. The tail correction processing unit independently adds an offset value that can take a positive value and a negative value to the output values of the horizontal counter 1 and the vertical counter 2, and is defined by a plurality of tail correction gain modulation data. After the center of the modulation range to be matched with the center of the effective pixel region EPR of the image sensor IS, the interpolation interpolation is performed.

<Linearization processing>
The main points of the processing described below are that linearization characteristics that differ for each color are defined for each input channel, and linearization processing can be executed by switching the linearization characteristics according to the color selection timing signal described above. There is in point to do. In this regard, the explanation of the linearization process will be developed with reference to the drawings.

  As described above, with the miniaturization of the image sensor for realizing an increase in the number of pixels of the image sensor, a portion having a relatively low level in the characteristics of the semiconductor element constituting each pixel of the image sensor. It is a situation that must be used. For this reason, the brightness and output value characteristics of each color have been linear in the past, but recently the brightness and output value characteristics of each color are nonlinear.

  For example, as schematically illustrated in FIG. 19A, the characteristic R0 between the brightness of the R color and the output value is actually nonlinear. For other colors (Gr, Gb, B colors), the characteristics of brightness and output value are also non-linear.

  Therefore, as schematically illustrated in FIG. 19B, a curve RC having a reverse characteristic relationship to the characteristic R0 for the R color is defined as the linearization characteristic. If the linearization characteristic RC having such a definition is used as a correction characteristic, the two characteristics R0 and Rc cancel each other, and the resulting characteristic has linearity as shown in FIG. It becomes a straight line R. Such a principle is basically used here to perform the linearization process. The specific circuit configuration is as follows.

  FIG. 20 is a block diagram illustrating a configuration of a circuit portion that executes linearization processing included in the correction processing unit SPU-CX for each input channel X (X: 0 to 3) (such a circuit configuration is the input channel X). (X is provided every 0 to 3).) The linearization table register LTR forms the core of the linearization processing unit. As shown in FIG. 20, the linearization table register LTR has linearization table registers 17, 18, 19, and 20 for each color for each of four types (R, Gr, Gb, and B). . For example, the R linearization table register 17 holds data of linearization characteristics RC as shown in FIG. 19B (written in advance by a CPU (not shown)). Actually, as illustrated in FIG. 21, the R linearization table register 17 corrects the non-linearity between the brightness of the R color and the output value in the image sensor IS with an inverse characteristic. The curve of the characteristic RC is held as 33 line data RCA divided by, for example, 32 line graphs. The same applies to the linearization table registers 18 to 20 for other colors. The output data (16-bit signal) of the linearization table registers 17 to 20 for each color is input to the first selector 21.

  As a basic operation, the first selector 21 receives the color selection timing signal CXCS (X: 0 to 3) corresponding to the input channel X (CH0 to CH3) described above as the selection signal SEL1, and performs linearization. Among the outputs of the table registers 17 to 20, the linearization table registers 17 to 20 corresponding to the color of the pixel at a certain time point instructed by the color selection timing signal CXCS are selected and output. As a result, the linearization processing unit 26 uses the 33 linearization characteristic data selected and output by the first selector 21 in accordance with the correction principle described with reference to FIG. 19 to input image data CXInput (X: 0). -3) is corrected, and then linearized input image data CXInput is output to a white balance correction unit (not shown).

  As a result, regardless of the read pattern of the image data from the image sensor IS, nonlinear characteristics between color brightness and output value due to the miniaturization of the image sensor IS for each input channel and for each color. Can be reliably corrected.

  As additional components, a fixed linearization parameter register 15 and a second selector 16 may be provided as shown in FIG. The viewpoint here is that the non-linearity of the image data input to each input channel is due to the characteristics of an amplifier or the like provided on each readout channel side of the image sensor IS, in addition to those caused by miniaturization of the image sensor IS. There is also a cause. In particular, the latter non-linear characteristics due to other causes such as the circuit system on the output side of the image sensor IS differ for each readout channel. Therefore, the fixed linearization parameter register 15 has one of the four linearization table registers 17 to 20 described above as a value unique to each of the four channels CH0 to CH3. A value that designates the characteristic as the linearization characteristic for the channel for correcting the nonlinear characteristic due to the latter cause is stored in advance by a CPU (not shown). The second selector 16 then (1) selects the level (command) of the select signal SEL2 issued by the CPU (not shown) when correcting the non-linear characteristics due to the former (miniaturization of the image sensor IS). The color selection timing signal CXCS of the channel is selected according to the value (the linearization correction described above is performed), and (2) the cause of the latter (characteristics of the component on the readout path) When correcting the non-linear characteristic caused by the above, the select signal SEL2 issued by the CPU (not shown) instructs to select the output value of the fixed linearization parameter register 15, and as a result, the fixed linearization parameter register Since the output value (parameter) of 15 becomes the select signal SEL1 of the first selector 21, linear Among the outputs of the initialization table registers 17 to 20, the output of the linearization table register specific to the channel selected by the select signal SEL1 is input to the linearization processing unit 26, which is caused by the latter. A process for correcting the nonlinear characteristic is executed.

  As described above, (1) “register 15” having a fixed linearization parameter for designating a specific output corresponding to the unit among outputs of the plurality of linearization table registers 17 to 20, and (2) a register The image processing device SPU-CX further includes a “second selector 16” that selects and outputs one of the 15 outputs and the color selection timing signal CXCS corresponding to the unit. In addition to the correction of the non-linear characteristic caused by the conversion, the non-linear characteristic caused by other causes such as the circuit system on the output side of the image sensor can be selectively corrected for each input channel.

  As a further additional component, as shown in FIG. 20, a limit unit LMIP including limiter registers 22 to 25 for each color and a third selector 27 may be provided. The viewpoint here is as shown in FIG. 21 (the horizontal pitch of each line is equal), and a limit value is provided for the linearization characteristic divided by 32 line graphs, and the value is If it exceeds, the linearization process is terminated. That is, as shown in FIG. 20, (1) four limiter registers 22 to 25 are provided for each color, and each of the 32 limiter registers 22 to 25 divides the linearization characteristic of the color for each color. A level with a broken line within a broken line is held as a limit value. (2) The third selector 27 selects the outputs of the four limiter registers 22 to 25 in accordance with the output value of the second selector 16, and linearly selects the selected limit value (16-bit signal) LMI. The data is output to theization processing unit 26. As a result, the linearization processing unit 26 clips the correction process when the input image data CXIput is equal to or greater than the limit value given by the output LMI of the third selector 27.

<Example of implementation>
FIG. 22 is a block diagram illustrating an implementation example of a main part of the SPU circuit SPU-CX (X: 0 to 3) of each input channel. In FIG. 22, the preceding circuit C1 is a tailing correction processing unit, the next circuit C2 is a black level correction processing unit, and the next circuit C3 is a linearization processing execution circuit. Although not provided, a white balance correction processing unit is disposed after the circuit C3.

(Appendix)
While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

  The present invention, for example, performs image processing for each pixel clock without buffering data read out on a large-capacity memory for image data read from each read channel of an image sensor included in a digital (still, video) camera. It is suitable for application to an LSI for an image processing apparatus of a complete real-time pipeline type that is executed in parallel.

100 SPU
IS image sensor 9 SPU register 10 color timing arrangement unit C0Input image data SPU-C0 first input channel SPU circuit unit 13C0 black level correction processing unit 14C0 white balance correction processing unit 1 global H counter 2 global V counter CLBASET color base timing signal TR0 First input channel timing register TRS0 Timing register selector C0CS First input channel color selection timing signal 5 Local H counter 6 Local V counter

Claims (2)

Each image signal read synchronously from each of a plurality of image data read channels of the image sensor is received for each pixel clock at an input channel corresponding to the image data read channel, and the received image data A plurality of pipeline-type image sensor pre-processing units that execute predetermined image processing due to problems peculiar to the image sensor in parallel for each pixel clock;
A color selection timing signal for designating a color of a pixel at a certain time point is independently generated for each input channel of the plurality of image sensor preprocessing units, and a color corresponding to each image sensor preprocessing unit is generated. A color timing arrangement unit that outputs a selection timing signal;
Each of the image sensor pre-processing units executes the predetermined image processing according to the color selection timing signal corresponding to the unit,
Each of the image sensor pre-processing units is
A plurality of linearization table registers having a linearization characteristic that is provided for each color and corrects a nonlinear characteristic between the brightness and output value of the color for each color;
A first selector that selects outputs of the plurality of linearization table registers in accordance with the color selection timing signal corresponding to the unit;
A linearization processing unit that corrects nonlinearity of input image data using the linearization characteristics selected and output by the first selector ;
Each of the image sensor pre-processing units is
A register having a fixed linearization parameter for designating a specific output corresponding to the unit among the outputs of the plurality of linearization table registers;
A second selector for selecting and outputting either the output of the register or the color selection timing signal corresponding to the unit;
The first selector selects outputs of the plurality of linearization table registers according to an output value of the second selector .
Image processing device. The image processing apparatus according to claim 1 ,
The linearization characteristic held in each of the plurality of linearization table registers included in each image sensor preprocessing unit is a characteristic composed of a plurality of broken lines,
Each of the image sensor pre-processing units is
Provided for each color, each of which has a plurality of limiter registers each having a level of a broken line of the plurality of broken lines corresponding to the color as a limit value;
A third selector for selecting outputs of the plurality of limiter registers according to an output value of the second selector;
The linearization processing unit clips the correction processing when the input image data is equal to or greater than the limit value given by the output of the third selector,
Image processing device.

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