JP5255389B2 - Storage device and memory control method - Google Patents

Description

  The present invention relates to a technique for extending the life of a storage device using a nonvolatile semiconductor memory.

  In recent years, as an auxiliary storage device for information equipment, in addition to a magnetic disk storage device, a storage device using a semiconductor memory excellent in vibration resistance and access speed as a storage medium has been used. Among them, in particular, those using an electrically erasable and rewritable nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) such as a flash memory is an auxiliary storage device of information equipment. It has become mainstream.

  In general, the nonvolatile semiconductor memory has an upper limit (for example, about 100,000 times) in the number of data rewrites (erase times) due to the characteristics of the element. In the nonvolatile semiconductor memory, since data is erased for each physical block, it is devised not to reach the upper limit number of erase times only for a specific block, that is, to equalize the number of erase times of a block (hereinafter referred to as the block erase number). Simply called “leveling”). This is because the life of the storage device is extended by leveling.

For example, in the technique of Patent Document 1, when any one of data blocks that are physical blocks in use is replaced with a replacement block that is a waiting physical block, leveling is performed by using a replacement block with a small number of erasures. I am trying.
JP 2005-196634 A

  However, although the technique of Patent Document 1 has a certain level of effect on leveling, when a specific data block is dedicated to reading (a state in which rewriting is not performed for a long time), the number of times of erasing the data block However, there was a situation in which other blocks reached the upper limit of the number of erasures with a small amount, and leveling was not sufficient.

  Therefore, the present invention has been made in view of the above problems, and an object thereof is to perform more effective leveling with respect to the nonvolatile semiconductor memory.

In order to solve the above problems, the present invention provides a nonvolatile semiconductor memory that performs data writing to a storage area in a predetermined unit and erases data in units of physical blocks that have a larger data amount than the predetermined unit. A memory control unit that controls writing and reading of data to and from the nonvolatile semiconductor memory in accordance with an instruction from an external host device. Memory control unit, the physical block of the nonvolatile semiconductor memory, at least, a data block is a physical block during use, a replacement block is a physical block waiting, separately managed, this time, the data block The data block is managed in a first-in first-out data structure queue, the replacement block is managed in a separate replacement block queue for each predetermined number of rewrites, the number of rewrites in each physical block is managed, in timing, compared to the number of times of rewriting of the leading data block of the data block queue, when the predetermined lower range limit the replacement to the replacement block queue block more large number of rewrites of are present, for the data block For the first data block in the queue and the replacement block With any of the replacement block existing in-menu, it is alternated. Other means will be described later.

  According to the present invention, more effective leveling can be performed with respect to the nonvolatile semiconductor memory.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings (refer to drawings other than the referenced drawings as appropriate). FIG. 1 is an explanatory diagram including the hardware configuration of the storage device of this embodiment.

  As shown in FIG. 1, the storage device 6 is a device that stores data based on an instruction from the host device 3, and is connected to the host device 3 via the data bus 4 so as to be accessible. As the data bus 4, for example, a small computer system interface (SCSI) or an advanced technology attachment (ATA) is used, but another data bus such as a USB (Universal Serial Bus) may be used.

  The storage device 6 includes a memory control unit 1 and a semiconductor memory 2. Data exchange between the semiconductor memory 2 and the memory control unit 1 is performed via the data bus 5.

  The memory control unit 1 includes a microprocessor 11 (arithmetic unit), a memory I / F (interface) control unit 12, a host I / F control unit 13, and a memory 14.

The microprocessor 11 controls writing and reading of data with respect to the semiconductor memory 2 in accordance with instructions from the host device 3.
The memory I / F control unit 12 performs access control with the semiconductor memory 2 according to an instruction from the microprocessor 11. Note that the memory I / F control unit 12 is not necessarily required if the microprocessor 11 can directly control the semiconductor memory 2.

  The host I / F control unit 13 controls data transmission / reception with the host device 3 in accordance with data write / read requests (instructions) from the host device 3. Note that data write and read requests from the host device 3 are made to a logical storage area (details will be described later) constructed for the semiconductor memory 2.

  The memory 14 is a work area of the microprocessor 11 and can be realized by a memory element such as an SRAM (Static Random Access Memory), a DRAM (Dynamic RAM), or an MRAM (Magneto-resistive RAM). The memory 14 stores storage information 141, logical / physical conversion table 142, data block queue 143, replacement block queue 144, erase wait block queue 145, erase count information 146, and bad block information 147 as management information of the semiconductor memory 2. Is remembered. Each information in the memory 14 is constructed by the microprocessor 11 reading data from the semiconductor memory 2 when the storage device 6 is powered on.

  Here, it is assumed that the semiconductor memory 2 stores the same information as the logical / physical conversion table 142 and the erase count information 146. The storage information 141 is information of a block number in which such information (the same information as the logical / physical conversion table 142 and the erase count information 146) is stored in the semiconductor memory 2. In the semiconductor memory 2, data writing and reading are performed in page units (predetermined units), and data erasing is performed in block units including a plurality of pages. The block includes a data block in which data is already stored, a replacement block in which data is not stored and is waiting, and an erasure waiting block in a state waiting for data erasure (details will be described later).

  The logical / physical conversion table 142 is a table that stores correspondence information between a logical address indicated at the time of access from the host device 3 and a physical address (block number and page number) on the semiconductor memory 2 (details are shown in FIG. 4). (Postscript).

The data block queue 143 is information for storing (managing) data blocks in the semiconductor memory 2 in a queue (first-in first-out data structure) format.
The replacement block queue 144 is information for storing (managing) replacement blocks of the semiconductor memory 2 in a queue format.
The erase waiting block queue 145 is information for storing (managing) the erase waiting blocks of the semiconductor memory 2 in a queue format.
Instead of the data block queue 143, the replacement block queue 144, and the deletion waiting block queue 145, information stored (managed) in another format such as a table may be used.

The erase count information 146 is information on the erase count for each physical block of the semiconductor memory 2.
The bad block information 147 is information on the address of a write-prohibited bad block. As the defective block information 147, information on the congenital defective blocks existing from the time of manufacture of the semiconductor memory 2 and information on acquired defective blocks generated during use of the semiconductor memory 2 are stored separately. May be.

  In addition to the above information, the memory 14 may have a table for managing the next write page for each physical block, but these are not directly related to the features of the present invention. The illustration and detailed description are omitted.

  The semiconductor memory 2 is non-volatile and is a storage medium to be controlled by the memory control unit 1 in accordance with instructions from the host device 3 and can be realized by, for example, a flash memory. The semiconductor memory 2 is the same as the logical / physical conversion table 142 and the erase count information 146 stored in the memory 14 as described above, in addition to the data (actual data) written by the memory control unit 1 in accordance with an instruction from the host device 3. It also stores at least a part of the management information related to itself such as the above information.

  FIG. 2 is a diagram showing an internal configuration of the semiconductor memory according to the present embodiment. FIG. 2 shows a logical storage area related to the semiconductor memory 2. The host device 3 shown in FIG. 1 recognizes this logical storage area with respect to the storage device 6.

  The block 21 is a minimum unit for erasing data. The page 211 is a unit for reading and writing data. In FIG. 2, the logical storage area of the semiconductor memory 2 is composed of a plurality of blocks 21, and the block 21 is composed of a plurality of pages 211. That is, the logical storage area of the semiconductor memory 2 has m blocks 21 from block 1 to block m (integer), and each block includes n blocks from page 1 to page n (integer). Has a page.

FIG. 3 is a diagram showing a logical storage area constructed for the flash memory under the control of the memory control unit.
As logical storage areas related to the semiconductor memory 2, there are a data block 22 and a replacement block 23.
The data block 22 is a block (set of blocks) made up of one or a plurality of blocks for storing data, and has logical blocks from block 1 to block p (integer). Each block includes a data page 222 and a replacement page 223 as shown in the figure.

  The data page 222 has pages that hold data from page 1 to page q (integer), and the replacement page 223 has pages (q + 1) to page n (integer). The replacement page 223 is an erased rewritable page.

  The replacement block 23 is an erased replacement block from the block (p + 1) to the block m (integer), and each block includes erased pages 232 from page 1 to page n (integer). ing.

  The data page 222 is an area where the user can read and write data according to instructions from the host device 3. Since the data page 222 cannot be overwritten due to restrictions of the semiconductor memory 2, the overwritten data after the overwriting process under the control of the memory control unit 1 is stored in the replacement page 223.

  When the replacement page 223 cannot be stored, a replacement block 23 is newly allocated and written. At this time, the overwritten data of the replacement page 223 and the non-overwritten data of the data page 222, which are valid portions after the overwriting process, are copied and replaced in the replacement block 23. Further, the replacement page 223 and the data page 222 after replacement are erased to be candidates for the replacement block 23.

  Note that the values of “p” and “q” in FIG. 3 are set as initial values when the storage device 6 is manufactured in this embodiment. The method of setting the values of “p” and “q” is not particularly limited, but may be set by connecting a debugger to the microprocessor 11 in addition to setting in advance. Alternatively, a predetermined command may be issued from the host device 3 and set. Further, it is possible to manage the table with the values of “p” and “q” being variable, but in the present embodiment, they are handled as fixed values for easy explanation.

  FIG. 4 is a diagram illustrating a configuration example of a logical / physical conversion table. The logical / physical conversion table 142 includes a logical address indicated at the time of access from the host device 3 and a physical address (block number and page number) of the semiconductor memory 2.

  In principle, the logical address is unchanged from the initial setting state, but the physical address is rewritten by the microprocessor 11 in accordance with a write operation to the semiconductor memory 2 by the memory control unit 1.

  FIG. 5 is a conceptual diagram of the data block queue. The data block queue 143 indicates a connection of (identifiers) of data blocks managed in a queue format. Data blocks are concatenated and managed from the head to the tail, and the latest rewritten data block is concatenated to the tail.

  In such a data block queue 143, the data block with the longest unrewritten time up to that point exists at the head, and the unrewritten time up to that point becomes shorter as it approaches the end. Further, in the data block queue 143, it is considered statistically that there is a tendency that there is a data block with a smaller number of rewrites as it is closer to the head and with a greater number of rewrites as it is closer to the end.

  FIG. 6 is a conceptual diagram of the replacement block queue. The replacement block queue 144 indicates a connection of replacement blocks (identifiers) managed in a queue format. The replacement block queue 144 is a separate queue for every 10,000 times, such as less than 10,000 times, 10,000 times or more and less than 20,000 times, ..., 90,000 times or more, less than 100,000 times, or 100,000 times or more. Managed. Here, the management unit “every 10,000 times” is merely an example, and another management unit may be used.

  Next, the leveling process for the semiconductor memory 2 will be described with reference to FIG. FIG. 7 is a flowchart showing the leveling process related to the semiconductor memory.

  First, the microprocessor 11 determines whether or not there is a replacement block whose rewrite count is 90,000 (predetermined) or more (step S1). This determination can be made by referring to the replacement block queue 144 in the memory 14. In addition, the timing of this determination may be regular, or may be when the replacement block is registered in the replacement block queue 144 in a queue of 90,000 times or more and less than 100,000 times, Furthermore, it may be a time when the processing operation of the microprocessor 11 occurs. If it is determined that there is no replacement block (No in step S1), the process returns to step S1.

  If it is determined that there is the replacement block (Yes in step S1), the microprocessor 11 determines whether the number of rewrites of the first data block in the data block queue 143 is less than 90,000 times (predetermined number) (step). S2).

  If it is determined that the number is less than 90,000 times (Yes in step S2), the microprocessor 11 replaces the replacement block (replacement block whose rewrite count is 90,000 times or more) and the first data block in the data block queue 143 ( The data is exchanged) (step S3), and the process ends after updating the logical / physical conversion table 142 and the like.

  If it is determined that the number of times is 90,000 times or more (No in step S2), the microprocessor 11 notifies the administrator to that effect by display or the like, and ends the process. The administrator who received the notification recognizes that there are replacement blocks with 90,000 or more rewrites and that the number of rewrites of the first data block in the data block queue 143 is 90,000 or more. can do.

  FIG. 8 is a graph showing how the number of block rewrites changes when the leveling process is performed. Here, two physical blocks of block A and block B will be described as representatives among the plurality of physical blocks.

  As shown in FIG. 8, in the block A, the number of rewrites sequentially increases with time in the first half. On the other hand, in the block B, after the number of rewrites is slightly increased at first, data that is hardly rewritten (read-only data) is stored, so that the number of rewrites is maintained as it is.

  Under such circumstances, at the time T, the microprocessor 11 determines that the number of rewrites of the block A that is the replacement block is 90,000 times or more (Yes in step S1), and the first in the data block queue It is determined that the number of rewrites of the block B that is a data block is less than 90,000 times (Yes in step S2). Thereafter, the microprocessor 11 replaces the data of the block A and the block B (step S3), and updates the logical / physical conversion table 142 and the like.

  By this process, the block A stores the read-only data, so that the possibility that the number of rewrites will increase after time T is kept low. Further, the block B stores data that is frequently rewritten rather than read-only data, so that the possibility that the number of rewrites will increase after time T increases.

  As described above, according to the storage device 6 of the present embodiment, a replacement block having a rewrite count of 90,000 times or more and a data block of data blocks whose unwritten time until that point is longer than a predetermined value (managed in a queue format). By replacing the first data block), more effective leveling can be performed. Of the data blocks, the data block whose unwritten time until that point is longer than a predetermined value may be, for example, a data block having the longest unwritten time, or a predetermined length of time. It may be a data block that has not been rewritten for a long time.

  Also, by managing data blocks in a queue format that is a first-in first-out data structure, the top data block can be extracted as a replacement block with a replacement block with 90,000 or more rewrites, and leveled Processing can be simplified and the burden can be reduced.

  Furthermore, when the number of rewrites of the first data block in the data block queue is 90,000 times or more, it is not necessary to replace the data block with a replacement block having the number of rewrites of 90,000 or more. Processing can be avoided.

As mentioned above, although embodiment of this invention was described, this invention is not limited to this, It can implement in the range which does not change the meaning.
For example, the predetermined number of times may not be 90,000, and any number can be set as long as it is close to the upper limit number of times of rewriting of the semiconductor memory 2 (which is not constant because it is based on the manufacturer's specifications). .

Further, the leveling process of the present embodiment and the conventional leveling process may be used in combination.
Furthermore, when the number of rewrites of the first data block in the data block queue is 90,000 times or more, it is determined whether the number of rewrites of the second and subsequent data blocks is less than 90,000 times, and less than 90,000 times If there is a data block, the data block may be used for replacement.
In addition, specific configurations of hardware and software can be appropriately changed without departing from the gist of the present invention.

It is explanatory drawing containing the hardware constitutions of the memory | storage device of this embodiment. It is the figure which showed the internal structure of the semiconductor memory of this embodiment. It is the figure which showed the logical storage area constructed | assembled regarding the flash memory by control of a memory control part. It is the figure which showed the structural example of the logical / physical conversion table. It is a conceptual diagram of a data block queue. It is a conceptual diagram of a replacement block queue. It is the flowchart which showed the leveling process regarding a semiconductor memory. It is the graph which showed the mode of the change of the rewrite frequency of a block at the time of performing a leveling process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory control part 2 Semiconductor memory 3 Host apparatus 4,5 Data bus 6 Memory | storage device 11 Microprocessor (arithmetic part)
12 Memory I / F Control Unit 13 Host I / F Control Unit 14 Memory 21 Block 22 Data Block 23 Alternate Block

Claims (2)

A nonvolatile semiconductor memory that performs data writing to a storage area in a predetermined unit and erases data in a unit of a physical block having a data amount larger than the predetermined unit;
In accordance with an instruction from an external host device, a memory control unit that controls writing and reading of data to and from the nonvolatile semiconductor memory;
A storage device comprising:
The memory control unit
The physical block of the non-volatile semiconductor memory is managed separately at least as a data block that is a physical block that is in use and a replacement block that is a physical block that is on standby, in which case the data block is a first-in first-out data structure Are managed in a data block queue, and the replacement block is managed in a separate replacement block queue for each predetermined number of rewrites,
Managing the number of rewrites for each physical block;
If a replacement block exists in the replacement block queue, the number of rewrites at the lower limit of the predetermined range is larger than the number of rewrites of the first data block of the data block queue at a predetermined timing , the relevant data A storage device , wherein a data block at a head of a block queue is replaced with one of replacement blocks existing in the replacement block queue . A nonvolatile semiconductor memory that performs data writing to a storage area in a predetermined unit and erases data in a unit of a physical block having a data amount larger than the predetermined unit;
In accordance with an instruction from an external host device, a memory control unit that controls writing and reading of data to and from the nonvolatile semiconductor memory;
A memory control method using a storage device comprising:
The memory control unit
The physical block of the non-volatile semiconductor memory is managed separately at least as a data block that is a physical block that is in use and a replacement block that is a physical block that is on standby, in which case the data block is a first-in first-out data structure Are managed in a data block queue, and the replacement block is managed in a separate replacement block queue for each predetermined number of rewrites,
Managing the number of rewrites for each physical block;
If a replacement block exists in the replacement block queue, the number of rewrites at the lower limit of the predetermined range is larger than the number of rewrites of the first data block of the data block queue at a predetermined timing , the relevant data A memory control method comprising: exchanging a head data block in a block queue and any of the replacement blocks existing in the replacement block queue .

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