JP5245797B2 - Signal transmission method, receiver, transmitter, and semiconductor device - Google Patents

Signal transmission method, receiver, transmitter, and semiconductor device Download PDF

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JP5245797B2
JP5245797B2 JP2008319700A JP2008319700A JP5245797B2 JP 5245797 B2 JP5245797 B2 JP 5245797B2 JP 2008319700 A JP2008319700 A JP 2008319700A JP 2008319700 A JP2008319700 A JP 2008319700A JP 5245797 B2 JP5245797 B2 JP 5245797B2
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signal
transmission
coil
receiving coil
receiver
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JP2010147557A (en
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源洋 中川
正之 水野
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日本電気株式会社
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  The present invention relates to a signal transmission method and a semiconductor device, and more particularly to a signal transmission method suitable for noise resistance and low power consumption, a receiver, a transmitter, and a semiconductor device.

  Recently, along with the high integration of circuits incorporated in a semiconductor device, a semiconductor device has been proposed that realizes data transmission by electromagnetic induction between coils formed by stacking a plurality of semiconductor chips on each semiconductor chip.

  In these semiconductor devices, the coil formed on one semiconductor chip generates a magnetic field signal, and the coil formed on the other semiconductor chip has a signal proportional to the differential value of the current signal input to the transmission coil. Is induced and signal transmission between the chips is performed in a non-contact manner by receiving the induced signal.

  Each will be described in detail below.

  FIG. 9 is a diagram schematically showing a cross-sectional configuration of the semiconductor device described in Patent Document 1. In FIG. In this semiconductor device, coils 102 and 103 are formed on the surfaces of the semiconductor chips 100 and 101, and the semiconductor chip 100 and the semiconductor chip 101 are electromagnetically coupled by the coils 102 and 103.

FIG. 10 is a diagram schematically showing a cross-sectional configuration of the semiconductor device described in Patent Document 2. In FIG. This semiconductor device is formed by stacking a semiconductor chip Ln in which a transmission device S and a transmission coil SP S connected thereto are arranged, and a semiconductor chip Ln + x in which a reception device E and a reception coil SP E connected thereto are arranged. Yes, signal transmission is performed between the transmission coil SP S and the reception coil SP E. In Patent Document 2, a signal can be directly and reliably connected from the inside of one chip to the inside of a vertically adjacent chip without imposing extremely high requirements on mutual adjustment and surface flatness between semiconductor chips. The effect is described.

  FIG. 11 is a perspective view schematically showing the configuration of the semiconductor device described in Non-Patent Document 1. As shown in FIG. In this semiconductor device, a plurality of semiconductor chips 300, 301, 302, and 303 are stacked, and coils 304, 305, and 307 respectively formed on the semiconductor chips 300, 301, 302, and 303 are arranged at the same position in the vertical direction. Further, the transmitter circuit Tx and the receiver circuit Rx are arranged in the vicinity of each other to perform signal transmission between the upper and lower semiconductor chips. Non-Patent Document 1 describes that a low-power consumption, wide-band interface can be realized.

  In Patent Document 3, the waveform of the magnetic field signal received by the receiving coil in the prior art described in each of the above documents is very similar to the waveform of noise mixed in the receiving coil from inside and outside the semiconductor device. Therefore, it is described that the problem that it is difficult to separate the signal and noise is that data transmission can be facilitated by making the waveform of the current signal input to the transmission coil a triangular wave.

FIG. 12 shows waveforms of input / output signals of the transmission device S and the reception device E (see FIG. 10) described in Patent Document 2. Symbols U201, I L , U203, and U204 in FIG. 12 correspond to the input / output terminals shown in FIG. Code U201 is the input voltage signal waveform of the transmitter S, reference numeral I L is the current signal waveform that flows through the transmission coil SP S, code U203 is a voltage signal waveform induced in the receiving coil SP E, code U204 is 6 is a voltage signal waveform output from the receiving device E. The transmitting device S, a digital clock signal, data signal, etc., the signal of the rectangular wave is inputted, it is induced by the current waveform I L and receiving coil SP E through the transmission coil SP S as code U201 The voltage signal waveform U203 is a waveform having a narrow pulse width and a sharp peak.

Current signal waveform I L flowing through the transmitter coil SP S, such as current flows only when rising and trailing of the square wave input to the transmitter S, becomes narrow waveform with steep pulse width. This can be understood from the circuit configuration of the transmission device S.

FIG. 13 shows a transmission device S described in Patent Document 2. Ahead of an inverter 205, transmission coil SP S inverters 206 and 207 constitute a loop. Although the output voltage of the inverter 205 and the output voltage of the inverter 207 are in phase, a shift corresponding to the delay time of the inverters 206 and 207 occurs. Designed to reduce the current flow to the transmitter coil SP S during this displacement, the current waveform, such as I L.

On the other hand, the receiving coil SP E, since the differential value of the received magnetic field is induced as a voltage by the Faraday's law of electromagnetic induction, as shown in FIG. 12, the differential signals I L
Will be induced.

  As a result, the voltage signal U203 having a sharp peak with a narrow pulse width is input to the receiving device E.

  Similarly, in the semiconductor device described in Non-Patent Document 1, a voltage signal having a steep peak with a narrow pulse width is input to the receiving circuit.

FIG. 14 shows a current signal waveform or a voltage signal waveform at the transmission / reception circuit described in Non-Patent Document 1 and its respective input / output points. Similar to Patent Document 2, the transmission data Txdata is a rectangular wave by the digital signal, the current I T flowing through the transmitter coil is adapted to waveform current flows only when rising and trailing of the rectangular wave.

FIG. 15 is a diagram showing a configuration of the transmission circuit Tx. When the transmission data Txdata 308 is input to the transmission circuit Tx, a time lag between the signal and the signal input to the coil via the delay buffer 310 is generated. It has a configuration in which current flows I T to transmission coil during this displacement. Although not explicitly stated in Non-Patent Document 1, that the received voltage VR is differentiated value of the current I T through the transmission coil it can be easily inferred from the waveform of VR in FIG.

  Moreover, in patent document 4, it is not the semiconductor device which laminated | stacked the several semiconductor chip like patent document 1-3, but as shown in FIG. 16, it uses electromagnetic induction between the different coils formed in the same semiconductor device. That the signal is transmitted.

  Furthermore, Non-Patent Document 2 describes that a signal is transmitted using electromagnetic induction between a coil formed on a semiconductor device and a coil formed on an induction substrate, as shown in FIG. .

Japanese Patent Laid-Open No. 7-212260 JP-A-8-236696 International Publication No. 2007/29435 Pamphlet U.S. Pat. No. 4,785,345 Noriyuki Miura, et al., "Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect", IEEE 2004 Symposium on VLSI Circuits Digest of Technical Papers, pp.246-249 (2004). Hiroki Ichikuro, et al., "An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based Inductive-Coupling through LSI Package", IEEE International Solid State Circuits Conference 2007 Digest of Technical Papers, pp. 360-361, 608 (2007) .

  The following is an analysis of the related art according to the present invention.

  In the related art, since the polarity of the differential value of the current flowing through the transmission coil always has an inflection point, the polarity of the signal induced at both ends of the reception coil also changes from positive to negative or from negative to positive.

  The signal receiver determines whether the polarity of the induced signal is positive or negative, and performs signal transmission. Transmission is not possible.

  In addition, in order to realize stable signal transmission, sufficient received signal strength is required, so that the area occupied by the transmission / reception coil increases and the power consumption of the receiver increases. Alternatively, the signal transmission distance is limited.

  An object of the present invention is to provide a signal transmission method, a receiver, a transmitter, and a semiconductor device that enable stable signal transmission when performing non-contact signal transmission by electromagnetic induction.

  The invention disclosed in the present application is generally configured as follows.

  ADVANTAGE OF THE INVENTION According to this invention, the receiver which takes the difference between the signals in a mutually different timing about the signal induced in a receiving coil by electromagnetic induction, and restores a signal is provided.

  According to the present invention, there is provided a transmitter including a transmission coil that is electromagnetically coupled to the reception coil of the receiver, and supplies a current in a direction corresponding to a value of transmission data to the transmission coil in synchronization with a transmission clock. Provided.

  According to the present invention, there is provided a signal transmission system including the transmitter and the receiver.

  According to the present invention, a semiconductor device including the transmitter and the receiver is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the signal transmission method which performs signal transmission by taking the difference between the signals of mutually different timing about the signal induced in a receiving coil by electromagnetic induction, and restoring a signal is provided.

  According to the present invention, stable signal transmission is possible when signal transmission is performed in a non-contact manner by electromagnetic induction.

  Embodiments of the present invention will be described. In the present invention, the difference between the signal induced in the receiving coil and the induced signal is taken, and the signal transmission is realized using the difference calculation result, thereby obtaining a signal having a larger amplitude, which is stable. Signal transmission is possible.

Further, in the present invention, by setting the signal delay amount in accordance with the shape of the current waveform input to the transmission coil, it is possible to distinguish from noise induced in the reception coil due to factors other than the electromagnetic signal emitted from the transmission coil. This simplifies the realization of the S / N (signal-to-noise) ratio necessary for signal reception. For this reason,
Reduction of the area occupied by the transmitter / receiver coil,
Reduction of power required for transmission and reception,
Expansion of signal transmission distance,
At least one of the above can be realized.

  With reference to FIG. 8, the configuration of the semiconductor device of this embodiment will be described. Referring to FIG. 8, the semiconductor chips (1, 2) that perform non-contact signal transmission by electromagnetic induction are arranged so that the reception coil (11) and the transmission coil (25) face each other. In the chip (1), a receiver (10) that inputs a reception clock is connected to the reception coil (11), and reception data is output from the receiver (10). In the chip (2), a transmission coil (25) is connected to a transmitter (20) for inputting transmission data and a transmission clock.

  In FIG. 8, the transmission coil (25) and the transmitter (20) are provided in the semiconductor chip (2), and the reception coil (11) and the receiver (10) are provided in the semiconductor chip (1). Although shown, it is needless to say that the present invention is not limited to such a configuration. For example, a transmission coil (25), a transmitter (20), and a reception coil (11) may be provided on the semiconductor chip (2), and a receiver (10) may be provided on the semiconductor chip (1). Alternatively, the transmitter (20) may be provided on the semiconductor chip (2), and the transmitter coil (25), the reception coil (11), and the receiver (10) may be provided on the semiconductor chip (1). Good. In addition, it is not always necessary to provide the semiconductor chip (1, 2) with the transmission / reception coil. For example, at least one of the transmission coil and the reception coil is provided on a substrate different from the semiconductor chip. The transmitter (20) or receiver (10) formed on the semiconductor chip (1,2) is electrically connected to the transmission coil (25) or the reception coil (11) to transmit The coil (25) and the receiving coil (11) may be opposed to transmit a signal using electromagnetic induction.

  In the present invention, a differential amplifier that takes a difference between a signal induced in the receiving coil (11) by electromagnetic induction and a delayed signal obtained by delaying a signal induced in the receiving coil (11) by electromagnetic induction for a predetermined time. (13), and the signal is restored based on the difference calculation result. That is, a delay circuit (12) having an input connected to one end of the receiving coil (11), and a differential amplifier (13) for differentially inputting a signal at one end of the receiving coil and an output signal of the delay circuit (12) And a latch (14) for sampling the output of the differential amplifier in response to a clock signal (see FIG. 1). In FIG. 1, a transmission signal is restored from an analog signal to a digital signal by a latch that samples the output of the differential amplifier in response to a clock signal. However, the signal restoration means is a sampling latch that responds to a clock signal. The present invention is not limited, and an asynchronous amplifier or other general signal restoration means may be used. In the present embodiment, the example of the single-ended configuration in which the delay device at one end of the receiving coil and the differential amplifier are connected is shown in FIG. 1, but the present invention is limited to the single-ended configuration. Instead, the delay device and the differential amplifier may be connected to both ends of the receiving coil.

  Alternatively, in another aspect of the present invention, a signal obtained by sampling a signal induced in the receiving coil (11) by electromagnetic induction with the first clock signal and a signal induced in the receiving coil by electromagnetic induction are A differential amplifier (13) that takes a difference between the first clock signal and a signal sampled by a second clock signal delayed by a predetermined delay time is provided, and the signal is restored based on the difference calculation result. In the present invention, the delay circuit (12) that delays the first clock signal to generate the second clock signal, and one end connected to one end of the receiving coil are turned on / off based on the first clock signal. A first switch (sampling switch) (17-1) to be controlled, and a second switch (sampling switch) that is connected to one end of the receiving coil and controlled to be turned on / off based on the second clock signal. (17-2), a differential amplifier (13) having a differential input connected to the other ends of the first and second switches, and a latch for sampling the output of the differential amplifier in response to a clock signal (14) (see FIG. 4).

  In still another embodiment of the present invention, a delay circuit (12) for delaying a first clock signal to generate the second clock signal, a signal at one end of the receiving coil, and a predetermined comparison signal are input. A first comparator (14-1) for outputting a comparison result in response to the first clock signal; a signal at one end of the receiving coil and a predetermined comparison signal; And a second comparator (14-2) for outputting a comparison result in response to (see FIG. 6). Embodiments of a receiver and a transmitter in a semiconductor device of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a receiver according to an embodiment of the present invention. Referring to FIG. 1, in this embodiment, a receiving coil 11 having one end connected to GND (ground) via a resistor, a delay circuit 12 having an input connected to the other end of the receiving coil 11, and the receiving coil 11. Are provided with a differential amplifier 13 having a differential input connected to the other end thereof and the output of the delay circuit 12, and a sampling latch 14 for restoring a digital signal from the differential output signal of the differential amplifier 13. The output of the sampling latch 14 is input to an SR (set / reset) flip-flop composed of two-input NAND (NAND) circuits 15-1 and 15-2 in which the inputs and outputs are connected in a cascade manner, and the output of the SR flip-flop. Is inverted by inverters 16-1 and 16-2. Note that the delay time of the delay circuit 12 is variably set by a delay time control signal. In this embodiment, the delay time of the delay circuit 12 is, for example, about half the width of the transmission current input to the transmission coil (25 in FIG. 8) that is electromagnetically coupled to the reception coil 11. In FIG. 1, for simplicity of explanation, a single-ended configuration in which one end of the receiving coil 11 is connected to the GND, and the other end of the receiving coil 11 is connected to the delay circuit 12 and the differential amplifier 13. Although an example has been shown, it is needless to say that a differential configuration in which a delay circuit and a differential amplifier are connected to one end and the other end of the receiving coil, respectively, may be used.

FIG. 2 is a timing waveform diagram for explaining the operation of the circuit of FIG. FIG. 2 shows transmission data, current input from the transmitter (20 in FIG. 8) to the transmission coil (25 in FIG. 8), voltage V rx induced in the reception coil 11, delayed signal V delay , Vout = V The timing waveform of the reception signal received by rx− V delay , the reception clock, the sampling latch output, and the reception clock is shown.

As shown in FIG. 2, when a current flows through the transmitting coil (25 in FIG. 8), the receiving coil 11 has a positive orientation while the value of the current flowing through the transmitting coil increases according to Faraday's law. A voltage V rx is induced in the receiving coil 11. At this time, the magnitude of the voltage V rx induced in the receiving coil 11 is a value proportional to the amount of time change of the current. Thereafter, when the current flowing through the transmission coil becomes I max , the current flowing through the transmission coil changes from increasing to decreasing. At this time, since the amount of change in current becomes negative, a negative voltage is induced in the receiving coil 11. The magnitude of the signal at this time is proportional to the amount of time variation of the current, as described above. The signal V rx induced in the reception coil 11 is input to the differential amplifier 13 and the delay circuit 12. In the delay circuit 12, the voltage V rx input delay time T delay is delayed, outputs a delay signal V delay. The output of the delay circuit 12 is input to the differential amplifier 13.

The differential amplifier 13 takes the difference between the voltage V rx induced in the receiving coil 11 and the delay signal V delay and outputs a difference calculation result V rx −V delay . The delay signal V delay output from the delay circuit 12 is equivalent to a voltage induced in the receiving coil 11 by the delay time T delay before the voltage V rx .

By sampling the difference calculation result Vout = V rx −V delay by the sampling latch 14, the transmission signal is restored. The output of the NAND 15-1 of the SR flip-flop is set at the transition of the normal signal of the differential output of the sampling latch 14 from High to Low, and from the High of the inverted signal of the differential output of the sampling latch 14 At the transition to Low, the output of the NAND 15-1 of the SR flip-flop is reset.

Since the polarity of the voltage induced in the receiving coil 11 continuously changes from positive to negative or from negative to positive, the polarities of V rx and V delay are reversed. Vout = V rx −V delay can obtain a larger amplitude than V rx and facilitates signal reception. Further, noise signals such as white noise generated due to factors other than electromagnetic signals emitted from the transmission coil to the reception coil 11 are reduced by the delay circuit 12 and the differential amplifier 13 (differential amplifier 13). Common mode signal removal), noise resistance is improved, and signal transmission is stabilized and facilitated.

  In this embodiment, an example in which a signal is restored using the synchronous sampling latch 14 is shown, but the present invention is not limited to the sampling latch 14. A signal restoration circuit such as an asynchronous comparator or a signal amplifier may be used.

  FIG. 3 is a diagram illustrating an example of the configuration of the transmitter (20 in FIG. 8) in the present embodiment. Referring to FIG. 3, the transmission circuit includes a transmission coil 25, a pMOS transistor 27-1, an nMOS transistor 26-1, a pMOS transistor 27-2, and an nMOS transistor 26-2 that supply current to the transmission coil 25. The transistors 27-1, 26-1, 27-2, and 26-2 are composed of logic circuits that control ON / OFF.

  The pMOS transistor 27-1 and the nMOS transistor 26-1 are connected in series between the power supply and the ground, the drains are connected to each other and connected to one end of the transmission coil 25, and the pMOS transistor 27-2 and the nMOS transistor 26-2 are connected to the power supply. The drains are connected in series between the grounds, and are connected to the other end of the transmission coil 25.

  A delay circuit 21 that receives a transmission clock and varies the delay time according to the delay time control signal, a transmission clock, a logic gate 22 that performs a negative logical product of the inversion of the delay signal of the delay circuit 21, and an inversion of transmission data An inverter 23-1 supplied to the gate of the pMOS transistor 27-1, and a negative OR circuit (NOR) for supplying the negative OR of the transmission data and the output of the logic circuit (gate) 22 to the gate of the nMOS transistor 26-1. 24-1, the inverter 23-2 that inverts the transmission data inversion signal and supplies the inverted signal to the gate of the pMOS transistor 27-2, and the negative OR of the transmission data inversion signal and the output of the logic circuit (gate) 22 And a NOR circuit (NOR) 24-2 for supplying to the second gate.

When the delay amount T delay of the delay circuit 21 is half of the width in the time direction of the current waveform flowing through the transmission coil 25, signal transmission is most effective.

  When the transmission data has a timing waveform as shown in FIG. 2, when the transmission data is 0 (Low), the rising edge of the clock signal is received, and the pulse width of the delay time of the delay circuit 21 from the logic circuit (gate) 22 , The output of the inverter 23-1 is High, the output of the NOR circuit 24-1 is High, and the nMOS transistor 26-1 is turned on. Since the transmission data inversion signal is High and the output of the inverter 23-2 is Low, the pMOS transistor 27-2 is turned on, and since the transmission data inversion signal is High, the output of the NOR circuit 24-2 is Low. The nMOS transistor 26-2 is turned off. Current flows through the power supply, the pMOS transistor 27-2, the transmission coil 25, the nMOS transistor 26-1, and the ground.

  When the transmission data changes from 0 (Low) to 1 (High), a rising edge of the clock signal is received, and a one-shot Low pulse having a pulse width corresponding to the delay time of the delay circuit 21 is generated from the logic circuit (gate) 22. The output of the inverter 23-1 is Low, the output of the NOR circuit 24-1 is Low, and the pMOS transistor 27-1 is turned on. Since the transmission data inversion signal is Low and the output of the inverter 23-2 is High, the pMOS transistor 27-2 is turned off, and the one-shot Low pulse having the pulse width of the delay time of the delay circuit 21 from the logic circuit (gate) 22 The output of the NOR circuit 24-2 that receives the transmission data inverted signal becomes High, and the nMOS transistor 26-2 is turned on. Current flows through the power supply, the pMOS transistor 27-1, the transmission coil 25, the nMOS transistor 26-2, and the ground.

Next, a description will be given of a second embodiment of the present invention. In the above embodiment, the signal V rx induced in the receiving coil is delayed and sampled. However, instead of delaying the signal V rx , the signal V rx is delayed by the sampling clock and another sampling clock that is delayed by a phase equal to the delay time. rx may be sampled.

FIG. 4 is a diagram showing the configuration of the second exemplary embodiment of the present invention. The present embodiment includes first and second switches 17-1 and 17-2 made of analog sampling switches, and the delay circuit 12 generates a reception clock 2 obtained by delaying the reception clock. The first switch 17-1 receives the signal V rx induced in the receiving coil 11 at the reception clock 1 and outputs the reception signal 1 (V rx ). The second switch 17-2 receives the signal V rx induced in the reception coil 11 and outputs the reception signal 2 (V delay ) with the reception clock 2. The delay time of the delay circuit 12 is variably set by a delay control signal. The differential amplifier 13, the subsequent sampling latch 14, the SR flip-flops (NANDs 15-1 and 15-2), and the inverters 16-1 and 16-2 are the same as those in the above embodiment.

FIG. 5 is a timing waveform diagram for explaining the operation of the second embodiment of the present invention. As shown in FIG. 5, the basic operation is almost the same as the timing waveform diagram of FIG. 2 showing the operation of the embodiment. The signal V rx induced in the reception coil 11 is used as a signal sampled by the reception clock 1 and the reception clock 2 having the reception clock 1 and the delay T delay . A delay between the reception clock 1 and the reception clock 2 can be generated similarly to the delay circuit 12 of the first embodiment. The first switch 17-1 and the second switch 17-2 capture the signal V rx induced in the reception coil 11 with the reception clock 1 and the reception clock 2, and output the reception signal 1 and the reception signal 2. To do. The differential amplifier 13 obtains a difference between the received signal 1 and the received signal 2 and restores the received signal.

Next, a third embodiment of the present invention will be described. FIG. 6 is a diagram showing the configuration of the third exemplary embodiment of the present invention. In this embodiment, comparators 14-1 and 14-2 are provided. That is, a comparator 14-1 that compares the voltage at one end of the receiving coil 11 with a comparison signal (reference voltage for comparison) in response to the receiving clock 1, a delay circuit 12 that delays the receiving clock 1, and a receiving coil 11 is provided with a comparator 14-2 that compares the voltage at one end of 11 and the comparison signal in response to the reception clock 2 from the delay circuit 12. The output of the comparator 14-1 is input to the arithmetic unit 18 as the received signal 1 through the SR flip-flop composed of the NAND circuits 15-1 and 15-2 and the inverters 16-1 and 16-2. The output of the comparator 14-2 is input to the arithmetic unit 18 as the received signal 2 via the SR flip-flop composed of the NAND circuits 15-3 and 15-4 and the inverters 16-3 and 16-4. Comparators 14-1 and 14-2 are configured by the same circuit as the sampling latch 14 of FIGS. 1 and 4, and receive a signal V rx induced in the receiving coil 11 at one input and a comparison signal at one input. It is good also as composition which receives.

The voltage V rx induced in the receiving coil 11 is converted into digital data by a comparison signal and voltage comparison in response to the reception clocks 1 and 2, and the converted data is subjected to differential processing by the arithmetic unit 18, thereby obtaining an analog signal. The same effect as in the case of the delay / arithmetic unit can be obtained.

FIG. 7 is a timing waveform diagram for explaining the operation of the third embodiment. In FIG. 7, transmission data to reception clocks 1 and 2 are the same as in FIG. The received data 1 and 2 in FIG. 7 are the outputs of the inverters 16-1 and 16-3 in FIG. The output signal is the output of the arithmetic unit 18. The comparator 14-1, 14-2 converts the voltage V rx induced in the reception coil 11 into digital data by comparing the voltage with the comparison signal in response to the reception clocks 1, 2, respectively. A difference calculation process is performed on the reception data 1 and the reception data 2 by the calculation device 18, whereby the signal (transmission data) received by the reception coil 11 is restored.

  According to the above-described embodiment, it is possible to amplify the signal induced by electromagnetic induction, and it is possible to reduce noise components other than the signal induced by electromagnetic induction. It is possible to reduce the power required for the transmission and / or increase the signal transmission distance.

  In each of the embodiments shown in FIGS. 1, 4, and 6, a single-ended configuration example in which a delay circuit and a differential amplifier are connected to one end of the receiving coil is shown. However, the present invention is limited to the single-ended configuration. Of course, a differential type configuration in which a delay circuit and a differential amplifier are connected to both ends of the receiving coil may be used.

  The disclosures of Patent Documents 1-4 and Non-Patent Documents 1 and 2 are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

It is a figure which shows the structure of the receiver of 1st Example of this invention. It is a timing waveform diagram for demonstrating operation | movement of the receiver of 1st Example of this invention. It is a figure which shows the structure of the transmitter of one Example of this invention. It is a figure which shows the structure of the receiver of the 2nd Example of this invention. It is a timing waveform diagram for demonstrating operation | movement of the receiver of 2nd Example of this invention. It is a figure which shows the structure of the receiver of the 3rd Example of this invention. It is a timing waveform diagram for demonstrating operation | movement of the receiver of the 3rd Example of this invention. It is a figure which shows the structure of the semiconductor device of the Example of this invention. It is a figure of the semiconductor device indicated in patent documents 1 (Drawing 4). It is a figure of the semiconductor device described in patent document 2 (FIG. 1). It is a perspective view of a semiconductor device indicated in nonpatent literature 2. FIG. 6 is a signal waveform diagram of an input device and an output device described in Patent Document 2 (FIG. 2). This is a transmission circuit described in Patent Document 2 (FIG. 3). It is the current waveform or voltage waveform in the transmission / reception circuit described in the nonpatent literature 2, and its each input-output point. This is a transmission circuit described in Non-Patent Document 2. This is a signal transmission device described in Patent Document 4. This is a signal transmission device described in Non-Patent Document 2.

Explanation of symbols

1 chip 2 chip 10 receiver 11 receiving coil 12 delay circuit 13 differential amplifier 14 sampling latch 14-1, 14-2 comparator 15-1, 15-2, 15-3, 15-4 NAND
16-1, 16-2, 16-3, 16-4 Inverter 17-1 First switch 17-2 Second switch 18 Arithmetic device 20 Transmitter 21 Delay circuit 22 Logic gate 23-1, 23-2 Inverter 24-1, 24-2 NOR
25 Transmitting coil 26-1, 26-2 nMOS transistor 27-1, 27-2 pMOS transistor

Claims (14)

  1. Input a signal induced in the receiving coil by electromagnetic induction in response to a transmission current flowing in the transmitting coil according to transmission data, and a signal obtained by delaying the signal induced in the receiving coil by electromagnetic induction by a delay circuit and comprises a preparative Ru differential amplifier the difference between the input the signal on the basis of the difference calculation result in the differential amplifier, have rows to restore the signal,
    A receiver in which a delay time of the delay circuit is equivalent to a half of an active period of a transmission current pulse flowing in the transmission coil .
  2. The receiver according to claim 1 , further comprising a sampling latch that samples an output signal of the differential amplifier in response to a clock signal.
  3. And signal a signal induced in the receiving coil by electromagnetic induction in response sampled at a first clock signal to the transmission current flowing in the transmission coil in accordance with transmission data, the signal induced in the receiving coil by electromagnetic induction the signal and sampled at a second clock signal delayed by the first clock signal delay circuit, type, comprising a differential amplifier for taking the difference between the input the signal at the differential amplifier based on the difference calculation result, and restores the signal,
    A receiver in which a delay time of the delay circuit is equivalent to a half of an active period of a transmission current pulse flowing in the transmission coil .
  4. A first switch having one end connected to at least one end of the receiving coil and controlled to be turned on / off based on the first clock signal;
    A second switch having one end connected to at least one end of the receiving coil and controlled to be turned on / off based on the second clock signal ;
    The receiver according to claim 3 , wherein the differential amplifier has a differential input connected to the other ends of the first and second switches.
  5. 4. The receiver according to claim 3 , further comprising a sampling latch that samples the output signal of the differential amplifier in response to a clock signal.
  6. A signal induced in the receiving coil by electromagnetic induction in response to a transmission current flowing in the transmission coil according to the transmission data and a predetermined comparison signal are input, and a first comparison result is obtained in response to the first clock signal. A first comparator to output;
    Type the said signal with a predetermined comparison signal induced in the receiving coil by electromagnetic induction and outputs a second comparison result in response to a second clock signal obtained by delaying the first clock signal in the delay circuit A second comparator that
    A first latch circuit that latches a first comparison result that is an output of the first comparator;
    A second latch circuit that latches a second comparison result that is an output of the second comparator;
    An arithmetic unit for restoring a signal from the first and second comparison results;
    With receiver.
  7. The receiver of claim 1 or 3 with an SR flip-flop for receiving the differential output of the sampling latch.
  8. Comprising the receiving coil and the transmitting coil electromagnetically coupled receiver according to any one of claims 1 to 7,
    A transmitter for supplying a current in a direction corresponding to a value of transmission data to the transmission coil in synchronization with a transmission clock.
  9. A signal transmission system comprising the transmitter according to claim 8 and the receiver according to any one of claims 1 to 7 .
  10. Semiconductor device comprising a receiver according to any one of claims 1 to 7.
  11. A semiconductor device comprising the transmitter according to claim 8 and the receiver according to any one of claims 1 to 7 .
  12. Wherein the with a transmitter chip, a chip with the receiver, the semiconductor device according to claim 1 1, wherein a separate chip.
  13. A signal induced in the receiving coil by electromagnetic induction in response to a transmission current flowing in the transmitting coil in accordance with transmission data, a signal obtained by delaying the signal induced in the receiving coil by electromagnetic induction by a delay circuit, and a differential amplifier type in, taking the difference between said signals, based on the difference calculation result, by restoring the signal, have row signal transmission,
    The signal transmission method , wherein the delay time of the delay circuit is equivalent to half the active period of a transmission current pulse flowing through the transmission coil .
  14. A signal obtained by sampling a signal induced in the receiving coil by electromagnetic induction in response to a transmission current flowing in the transmitting coil in accordance with transmission data with the first clock signal, and the signal induced in the receiving coil by electromagnetic induction , A signal sampled with a second clock signal obtained by delaying the first clock signal by a delay circuit , and input to a differential amplifier, taking a difference between the signals , based on the difference calculation result, By restoring the signal , signal transmission is performed,
    A signal transmission method in which a delay time of the delay circuit is equivalent to a half of an active period of a transmission current pulse flowing in the transmission coil .
JP2008319700A 2008-12-16 2008-12-16 Signal transmission method, receiver, transmitter, and semiconductor device Expired - Fee Related JP5245797B2 (en)

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