JP5243499B2 - Space equipment synchronization system and space equipment used therefor - Google Patents

Description

  The present invention relates to a synchronization system for synchronizing a plurality of space devices connected according to the SpaceWire standard and a space device used therefor, and in particular, when a Timecode packet cannot be transmitted from a main device to a subordinate device, It is related with the system etc. which complement.

  SpaceWire (based on IEEE-1355) is known as a communication standard for connecting a plurality of space devices mounted on an artificial satellite or the like. In this system using SpaceWire, as shown in FIG. 8, a master device (for example, a controller or a central processing unit) 31 and other slave devices (for example, sensors or masters) are connected via a SpaceWire network. Devices that operate according to instructions of the system devices) 32-1 to 32-n (n is an integer of 2 or more), and the slave devices 32-1 to 32-n are controlled under the control of the master device 31. Make it work. At this time, the master device 31 also functions as a device for managing time, and always synchronizes the master device 31 and the slave devices 32-1 to 32-n.

  The synchronization between the master device 31 and the slave devices 32-1 to 32-n is performed using a Timecode packet including synchronization information. The Timecode packet is periodically transmitted from the master device 31 and is simultaneously arranged with respect to the plurality of slave devices 32-1 to 32-n. At this time, if a problem occurs in a part or a plurality of transmission paths, and the Timecode packet does not reach the slave devices 32-1 to 32-n, synchronization with the master device 31 is not possible, and the operation of the master / slave system operates. Disturbed.

  For this reason, in the above system, when transmission of the Timecode packet fails for some reason, it is necessary to take measures to compensate for the loss of the Timecode packet and maintain synchronization. Although not using SpaceWire, for example, Patent Documents 1 to 5 reclaim the missing synchronization information when time information (synchronization information) is missing, as a technique for compensating for the missing synchronization signal. Or a technique for ensuring synchronization with the master device by mounting a PLL on the slave device side.

JP 2003-298630 A JP 2009-198245 A JP-A-9-46325 JP-A-9-198158 JP 2009-182659 A

  As described above, in a system in which space devices are connected according to the SpaceWire standard, it is necessary to always synchronize the master device 31 and the slave devices 32-1 to 32-n. For this reason, the slave devices 32-1 to 32-n are required to maintain synchronization with the master device 31 even when the Timecode packet from the master device 31 cannot be temporarily received. It is necessary that when a Timecode packet is lost, the loss can be complemented immediately.

  On the other hand, all of the techniques described in Patent Documents 1 to 5 recover the synchronization gradually by re-requesting the synchronization information or free-running the PLL after the synchronization is once lost due to the loss of the synchronization information. . For this reason, when these technologies are applied to a system based on SpaceWire, when a timecode packet is lost, it is possible to recover from lost synchronization, but it is not possible to maintain it without removing synchronization. Disturbance of operation cannot be avoided.

  Therefore, the present invention has been made in view of the above-described problems in the prior art, and even when a failure occurs in the transmission of the Timecode packet, the master device and the slave device maintain a synchronized state, An object of the present invention is to provide a space equipment synchronization system capable of continuing the operation of the master-slave system.

In order to achieve the above object, the present invention provides a synchronization of a space device in which a master device and a plurality of slave devices are connected according to the SpaceWire standard, and the slave devices are operated in synchronization with the master device. The slave device decodes a Timecode packet periodically output from the master device and generates a first synchronization signal pulse and first synchronization signal data; and the Timecode A reference timing signal generation unit that generates a dummy pulse that rises in the same cycle as the packet; a synchronization signal pulse complementing unit that inputs the first synchronization signal pulse and the dummy pulse and outputs a second synchronization signal pulse; A synchronization signal data complementing unit that inputs first synchronization signal data and an instruction signal from the synchronization signal pulse complementing unit and outputs second synchronization signal data; When the dummy pulse rises before the first synchronization signal pulse is received, the complementing unit supplements the synchronization signal pulse using the dummy pulse, and the complemented synchronization signal pulse is transferred to the second synchronization signal pulse. In addition to outputting as a sync signal pulse, the sync signal data complementing unit is instructed to increment the value of the first sync signal data received immediately before, and the incremented sync signal data is sent to the second sync signal data. Output from the SpaceWire decoder when the first synchronization signal pulse is received from the SpaceWire decoder after the complemented synchronization signal pulse is output as the second synchronization signal pulse. The value of the first synchronization signal data is compared with the value of the second synchronization signal data output from the synchronization signal data complement unit If the codes match is characterized by ignoring the first sync pulse from the SpaceWire decoder.

According to the present invention, the dummy pulse rising at the same cycle as the transmission cycle of the Timecode packet is generated inside the slave device, and the synchronization signal pulse complementing unit precedes the reception of the first synchronization signal pulse. Since the second synchronization signal pulse is generated using the dummy pulse when the dummy pulse rises, the synchronization signal pulse can be complemented immediately upon transmission failure of the Timecoed packet. Complementary processing can be performed while maintaining the slave device in a synchronized state. When the second synchronization signal pulse is generated using the dummy pulse, the synchronization signal data complementing unit increments the first synchronization signal data received immediately before, and the slave device voluntarily synchronizes the synchronization signal data. Therefore, the synchronization signal data can be complemented simultaneously with the complement of the synchronization signal pulse.
Further, when the synchronization signal pulse complementing unit outputs the complemented synchronization signal pulse as the second synchronization signal pulse and then receives the first synchronization signal pulse from the SpaceWire decoder, the first output from the SpaceWire decoder The value of the synchronization signal data is compared with the value of the second synchronization signal data output from the synchronization signal data complementing unit, and if both match, the first synchronization signal pulse from the SpaceWire decoder is ignored. Therefore, it is possible to prevent the system from malfunctioning due to the second synchronization signal pulse rising twice in a short period.

  The space device synchronization system may include a cycle setting register for setting the rising cycle of the dummy pulse, and the rising cycle of the dummy pulse may be configured to be extendable. According to this, even when the transmission period of the Timecode packet is changed on the main device side, it is possible to flexibly cope with it.

Further, the present invention is a space device that is connected to the main device according to the SpaceWire standard and operates in synchronization with the main device, decodes a Timecode packet periodically output from the main device, A SpaceWire decoder that generates one synchronization signal pulse and first synchronization signal data; a reference timing signal generation unit that generates a dummy pulse that rises in the same cycle as the Timecode packet; and the first synchronization signal pulse and the dummy pulse. The synchronization signal pulse complementing unit that outputs the second synchronization signal pulse, the first synchronization signal data and the instruction signal from the synchronization signal pulse complementing unit are input, and the second synchronization signal data is output. A synchronizing signal data complementing unit, wherein the synchronizing signal pulse complementing unit is configured to start up the dummy pulse before receiving the first synchronizing signal pulse. , Supplementing the synchronization signal pulse using the dummy pulse, outputting the complemented synchronization signal pulse as the second synchronization signal pulse, and receiving the first signal received immediately before from the synchronization signal data complement unit After instructing to increment the value of the sync signal data, causing the sync signal data after the increment to be output as the second sync signal data , and outputting the complemented sync signal pulse as the second sync signal pulse When the first synchronization signal pulse is received from the SpaceWire decoder, the value of the first synchronization signal data output from the SpaceWire decoder and the second output from the synchronization signal data complementing unit. the comparator compares the value of the synchronization signal data, if they match, ignores the first sync pulse from the SpaceWire decoder And wherein the door.

  As described above, according to the present invention, even when a failure occurs in the transmission of the Timecode packet, the master device and the slave device can be maintained in a synchronized state, and the operation of the master / slave system can be continued. .

It is a block diagram which shows 1st Embodiment of the synchronization system of the space equipment concerning this invention. It is a figure which shows the structure of a Timecode packet. It is a flowchart which shows the procedure of a synchronous signal data and a complementary process of a pulse. It is a flowchart which shows the procedure at the time of returning from self-running mode to Sync mode after execution of a complementation process. FIG. 2 is a timing chart showing the operation of the complementary circuit of FIG. 1 in time series. It is a figure which shows the operation | movement transition of the complementary circuit of FIG. It is a block diagram which shows 2nd Embodiment of the synchronization system of the space equipment concerning this invention. It is a block diagram which shows the conventional space equipment system using a SpaceWire network.

  Next, modes for carrying out the invention will be described in detail with reference to the drawings.

  FIG. 1 shows a first embodiment of a space device synchronization system according to the present invention. The synchronization system 1 is roughly divided into a main system device (for example, a controller and a central processing unit) 2 and a SpaceWire. A slave device (for example, a sensor that transmits a detection value to the master device 2 or a device that operates according to an instruction of the master device 2) 3 connected to the master device 2 via the network 4 is configured. . In FIG. 1, only one slave device 3 is illustrated, but actually, a plurality of slave devices 3 are installed.

  The main device 2 functions as a device for managing time within the synchronization system 1 and is equipped with a high-precision oscillator (not shown). The master device 2 distributes the Timecode packet as a signal for synchronizing the slave device 3 with the master device 2.

  As shown in FIG. 2, the Timecode packet is composed of a 14-bit code string including 6-bit synchronization signal data. In the synchronization signal data, numerical values “0” to “63” are sequentially set, and the value of the synchronization signal data is incremented by 1 each time a Timecode packet is transmitted. For this reason, for example, a Timecode packet including synchronization signal data having a value “1” is transmitted next to a Timecode packet including synchronization signal data having a value “0”. The Timecode packet is periodically transmitted at a period of 1 / 64s (frequency: 64 Hz).

Returning to FIG. 1, the slave device 3 is a device controlled by the master device 2 and operates in synchronization with the master device 2. The slave device 3 extracts the synchronization signal data SD from the Timecode packet and generates a synchronization signal pulse SP that rises in response to the reception of the Timecode packet, and a dummy pulse (Dummy). pulse), a complement circuit 7 for complementing the synchronization signal data and the synchronization signal pulse when the Timecode packet is not transmitted, and the synchronization signal data SD ′ output from the complement circuit 7 In addition, a processing circuit 8 or the like that performs a predetermined process upon receiving the synchronization signal pulse SP ′ is provided.

  In the present specification, the former is referred to as “first synchronization signal data SD” in order to distinguish the synchronization signal data SD output from the SpaceWire decoder 5 from the synchronization signal data SD ′ output from the complementary circuit 7. And the latter is referred to as “second synchronization signal data SD ′”. Similarly, the synchronization signal pulse SP output from the SpaceWire decoder 5 is referred to as “first synchronization signal pulse SP”, and the synchronization signal pulse SP ′ output from the complementing circuit 7 is “second synchronization signal pulse SP ′”. Called.

  The reference timing signal generator 6 includes an oscillator 6a and a counter 6b that counts clocks from the oscillator 6a and measures elapsed time. The maximum count value (time-up time) of the counter 6b is preset in accordance with the transmission period (1/64 s) of the Timecode packet. In the reference timing signal generation unit 6, the count value of the counter 6b is the maximum value (time-up value). ) Raise a dummy pulse as it reaches. For this reason, the dummy pulse is a signal that rises at the same cycle as the transmission cycle of the Timecode packet. Note that the oscillator 6a is not necessarily the same as the oscillator mounted on the main device 2, and may be any one that can generate a clock necessary for measuring 1 / 64s by the counter 6b.

  The complement circuit 7 includes a synchronization signal data complementing unit 11 that complements the synchronization signal data, and a synchronization signal pulse complementing unit 12 that complements the synchronization signal pulse.

  The synchronization signal data complementing unit 11 inputs the first synchronization signal data SD from the SpaceWire decoder 5 to the Data1 terminal, and receives either the received first synchronization signal data SD or the complementary synchronization signal data complemented by itself. The second synchronization signal data SD ′ is output from the Data2 terminal.

  The synchronization signal pulse complementing unit 12 inputs the first synchronization signal pulse SP from the SpaceWire decoder 5 and the dummy pulse from the reference timing signal generation unit 6, and outputs any of these as the second synchronization signal pulse SP ′. To do.

When receiving the first synchronization signal pulse SP prior to the dummy pulse, the synchronization signal pulse complementing unit 12 outputs the first synchronization signal pulse SP as the second synchronization signal pulse SP ′. In addition, the synchronization signal data complementing unit 11 is instructed to hold the first synchronization signal data SD and use it as the second synchronization signal data SD ′ (Load). Further, a reset signal is output to the reference timing signal generator 6 to reset the counter 6b (CNT) Rst).

  On the other hand, when the dummy pulse is received prior to the first synchronization signal pulse SP, the dummy pulse is output as the second synchronization signal pulse SP '. Further, the synchronization signal data complementing unit 11 is instructed to increment the value of the synchronization signal data held in the synchronization signal data complementing unit 11 by 1 and use it as the second synchronization signal data SD ′ (Inc). ).

  Next, the operation of the slave device 3 in the synchronization system 1 will be described with reference to FIGS.

Here, FIG. 3 is a flowchart showing a procedure of synchronization signal data and pulse complementation processing, and FIG. 4 is a diagram when returning from the free-running mode (with complement) to the Sync mode (without complement) after execution of the complement processing. It is a flowchart which shows the procedure of. FIG. 5 is a timing diagram showing the operation of the complementary circuit 7 in time series, and FIG. 6 is a diagram showing the operation transition of the complementary circuit 7. Note that “N ₀ ” to “N ₅ ” in FIG. 5 indicate the values of the synchronization signal data.

  First, synchronization signal data and pulse complementing processing will be described with reference to FIGS. 3 and 5.

  In complementing the synchronization signal data and the like, first, a reset signal is output from the synchronization signal pulse complementing unit 12 to the reference timing signal generating unit 6 to reset the counter 6b (step S1 in FIG. 3). This process is for aligning the rising timing of the dummy pulse generated by the reference timing signal generation unit 6 with the rising timing of the first synchronization signal pulse SP generated by the SpaceWire decoder 5. This is performed in response to the signal pulse SP being input to the synchronization signal pulse complementing unit 12.

Thereafter, the Timecode packet is correctly transmitted from the master device 2 to the slave device 3, and the synchronization signal pulse complementing unit 12 applies the first synchronization signal pulse SP before the dummy pulse rises (before the counter 6b times up). When received (YES in step 2 in FIG. 3: timings t1 and t2 in FIGS. 5A and 5B), the counter 6b is reset (step 3 in FIG. 3: FIGS. 5A and 5B). ) "CNT Rst ”), make sure that the dummy pulse does not rise.

  Further, the synchronization signal pulse complementing unit 12 instructs the synchronization signal data complementing unit 11 to use the first synchronization signal data SD as the second synchronization signal data SD ′ (step S4 in FIG. 3: FIG. 5). (A), (b) “Load”, “first synchronization signal data” and “second synchronization signal data”), the synchronization signal data received from the SpaceWire decoder 5 is output to the processing circuit 8. At the same time, the synchronization signal pulse complementing unit 12 uses the first synchronization signal pulse SP as the second synchronization signal pulse SP ′ (step S5 in FIG. 3: “first synchronization signal pulse” and “first synchronization signal pulse” in FIG. 5). 2 sync signal pulses ”), which is output to the processing circuit 8.

  On the other hand, the Timecode packet is not correctly transmitted from the master device 2 to the slave device 3, and the dummy pulse rises before the first synchronization signal pulse SP is received in the synchronization signal pulse complementing unit 12 (counter 6b). In the case where the time is up) (NO in step S2 in FIG. 3: timing t3 in FIGS. 5A and 5B), the synchronization signal data complementing unit 11 holds the synchronization held by the synchronization signal data complementing unit 11 Instruct to increment the value of the signal data and complement the synchronization signal data (step S6 in FIG. 3: “Inc”, “first synchronization signal data” and “first synchronization signal data” in FIGS. 5A and 5B) 2 synchronization signal data "). The synchronization signal data complementing unit 11 outputs the incremented synchronization signal data to the processing circuit 8 as the second synchronization signal data SD '.

Further, the synchronization signal pulse complementing unit 12 uses the dummy pulse as the second synchronization signal pulse SP ′ to complement the synchronization signal pulse (step S7 in FIG. 3: “Dummy” in FIGS. 5A and 5B). pulse "and" second sync signal pulse ").

  Next, the return process from the self-running mode to the Sync mode will be described with reference to FIGS. 4 and 5.

  When returning from the free-running mode to the Sync mode, the synchronization signal pulse complementing unit 12 resets the counter 6b in response to receiving the first synchronization signal pulse SP after the dummy pulse rises (FIG. 4). Steps S11 and S12: timing t4 in FIG. 5A, timing t4 ″ in FIG. 5B).

  Next, in the synchronization signal pulse complementing unit 12, the value of the first synchronization signal data SD (Data 1) output from the SpaceWire decoder 5 and the second synchronization signal data SD ′ ( Data2) is compared with each other to determine whether or not they match (step S13 in FIG. 4).

  At this time, as shown in FIG. 5A, when the values of the first and second synchronization signal data SD and SD ′ do not match (NO in step S13 in FIG. 4) at the timing t4 in FIG. In the “first synchronization signal data” and “second synchronization signal data”), the first synchronization signal data SD is used as the second synchronization signal data SD ′ for the synchronization signal data complementing unit 11. (Step S14 in FIG. 4: “Load” at timing t4 in FIG. 5A). Further, the synchronization signal pulse complementing unit 12 uses the first synchronization signal pulse SP received from the SpaceWire decoder 5 as the second synchronization signal pulse SP ′ (step S15 in FIG. 4: timing t4 in FIG. 5A). "First sync signal pulse" and "second sync signal pulse").

  On the other hand, as shown in FIG. 5B, when the values of the first and second synchronization signal data SD and SD ′ match (YES in step S13 in FIG. 4: timing t4 in FIG. 5B). "First synchronization signal data" and "second synchronization signal data"), the first synchronization signal pulse SP received from the SpaceWire decoder 5 is ignored (step S16 in FIG. 4: FIG. 5B). ) "First synchronization signal pulse" and "second synchronization signal pulse" at timing t4 ". Thereafter, when the next first synchronization signal data SD is input (timing t5 in FIG. 5B), the second synchronization signal data SD ′ and the synchronization signal pulse SP ′ are output (step of FIG. 3). S2-S5).

  Note that the first and second synchronization signal data SD and SD ′ are compared in synchronization with the input of the first synchronization signal pulse SP, and when the values match, the received first synchronization signal pulse SP. The operation is performed so that the second synchronization signal pulse SP ′ rises twice in a short period and causes the processing circuit 8 to malfunction.

  That is, due to individual differences of the oscillator 6a of the slave device 3 and accuracy differences between the oscillator 6a and the oscillator of the master device 2, the dummy pulse period (T in FIG. 5B) is the transmission of the Timecode packet. In this case, although the Timecode packet is correctly transmitted, the dummy pulse rises before the first synchronization signal pulse SP, and the second synchronization signal pulse is generated by the dummy pulse. SP ′ is complemented (timing t4 ′ in FIG. 5B). At this time, if the second synchronization signal pulse SP ′ is output in response to the first synchronization signal pulse SP (timing t ″ 4 in FIG. 5B) received slightly after the dummy pulse, As a result, since the second synchronization signal pulse SP ′ rises twice, in order to avoid this, the first received pulse is preferentially used and the delayed pulse is ignored. .

  As described above, according to the present embodiment, a dummy pulse that rises at the same cycle as the transmission cycle of the Timecode packet is generated inside the slave device 3 and precedes the reception of the first synchronization signal pulse SP. Since the second synchronization signal pulse SP ′ is generated by using the dummy pulse when the dummy pulse rises, the synchronization signal pulse can be complemented immediately at the time of transmission failure of the Timecoed packet. Complementary processing can be performed while maintaining the state in which the device 2 and the slave device 3 are synchronized.

  In addition, when the second synchronization signal pulse SP ′ is generated using the dummy pulse, the first synchronization signal data SD held by the synchronization signal data complementing unit 11 is incremented, and the slave device 3 spontaneously Since the value of the synchronization signal data is advanced, the synchronization signal data can be complemented simultaneously with the complement of the synchronization signal pulse.

  Next, a second embodiment of the space equipment synchronization system according to the present invention will be described with reference to FIG. In FIG. 7, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  In the synchronization system 20 according to the present embodiment, a period setting register 21 that sets the rising period of the dummy pulse is provided in the preceding stage of the reference timing signal generation unit 6. This cycle setting register 21 is for setting the maximum count value (time up time) of the counter 6b, and by changing the value of the cycle setting data, the rising cycle of the dummy pulse can be expanded and contracted.

  According to the present embodiment, the rising period of the dummy pulse can be freely changed, and even when the transmission period of the Timecode packet is changed on the main device 2 side, it is possible to flexibly cope with it.

DESCRIPTION OF SYMBOLS 1 Space device synchronization system 2 Master device 3 Slave device 4 SpaceWire network 5 SpaceWire decoder 6 Reference timing signal generator 6a Oscillator 6b Counter 7 Complement circuit 8 Processing circuit 11 Sync signal data complement unit 12 Sync signal pulse complement unit 20 Space equipment synchronization system 21 period setting register SD first synchronization signal data SD ′ second synchronization signal data SP first synchronization signal pulse SP ′ second synchronization signal pulse

Claims (3)

A space device synchronization system in which a master device and a plurality of slave devices are connected by the SpaceWire standard, and the slave devices are operated in synchronization with the master device,
The slave device is
A SpaceWire decoder that decodes a Timecode packet periodically output from the main device and generates a first synchronization signal pulse and first synchronization signal data;
A reference timing signal generator that generates a dummy pulse that rises in the same cycle as the Timecode packet;
A synchronization signal pulse complementing unit that inputs the first synchronization signal pulse and the dummy pulse and outputs a second synchronization signal pulse;
A synchronization signal data complementing unit that inputs the first synchronization signal data and the instruction signal from the synchronization signal pulse complementing unit and outputs the second synchronization signal data;
The synchronization signal pulse complementing unit
When the dummy pulse rises before receiving the first synchronization signal pulse, the synchronization signal pulse is complemented using the dummy pulse, and the complemented synchronization signal pulse is output as the second synchronization signal pulse. And instructing the synchronization signal data complementing unit to increment the value of the first synchronization signal data received immediately before, and outputting the incremented synchronization signal data as the second synchronization signal data. then,
The first synchronization signal data output from the SpaceWire decoder when the first synchronization signal pulse is received from the SpaceWire decoder after the complemented synchronization signal pulse is output as the second synchronization signal pulse. Is compared with the value of the second synchronization signal data output from the synchronization signal data complementing unit, and if they match, the first synchronization signal pulse from the SpaceWire decoder is ignored. A synchronization system for space equipment. 2. The space device synchronization system according to claim 1, further comprising a period setting register for setting a rising period of the dummy pulse, wherein the rising period of the dummy pulse is configured to be extendable. A space device that is connected to a main device according to the SpaceWire standard and operates in synchronization with the main device,
A SpaceWire decoder that decodes a Timecode packet periodically output from the main device and generates a first synchronization signal pulse and first synchronization signal data;
A reference timing signal generator that generates a dummy pulse that rises in the same cycle as the Timecode packet;
A synchronization signal pulse complementing unit that inputs the first synchronization signal pulse and the dummy pulse and outputs a second synchronization signal pulse;
A synchronization signal data complementing unit that inputs the first synchronization signal data and the instruction signal from the synchronization signal pulse complementing unit and outputs the second synchronization signal data;
The synchronization signal pulse complementing unit
When the dummy pulse rises before receiving the first synchronization signal pulse, the synchronization signal pulse is complemented using the dummy pulse, and the complemented synchronization signal pulse is output as the second synchronization signal pulse. And instructing the synchronization signal data complementing unit to increment the value of the first synchronization signal data received immediately before, and outputting the incremented synchronization signal data as the second synchronization signal data. then,
The first synchronization signal data output from the SpaceWire decoder when the first synchronization signal pulse is received from the SpaceWire decoder after the complemented synchronization signal pulse is output as the second synchronization signal pulse. Is compared with the value of the second synchronization signal data output from the synchronization signal data complementing unit, and if they match, the first synchronization signal pulse from the SpaceWire decoder is ignored. Space equipment characterized by doing.

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