JP5238980B2 - Synchronous oscillator that can establish and maintain synchronization instantaneously - Google Patents

Description

The present invention relates to a synchronous oscillator that can establish synchronization instantaneously and can maintain or maintain synchronization for a relatively long time.

Conventionally, synchronous oscillators that can establish and maintain synchronization have been proposed. (For example, see Patent Documents 1 to 3)
JP 2008-278479 A JP 2009-100061 JP 2009-210372 A

FIG. 7 shows an example of a conventional “digital synthesizer” disclosed in Patent Document 1. In FIG. 7, 10 is a digital synthesizer, 11 is a digital phase comparator, 12 is a numerically controlled oscillator (NCO), 13 is a frequency divider, 14 is an input terminal, and 15 is an output terminal.
The numerically controlled oscillator 12 changes its oscillation frequency according to the control signal output from the digital phase comparator 11, and the synchronous output signal is divided by N by the frequency divider 13 and input to one terminal of the phase comparator 11. Is done.

  When a synchronization input signal from the outside is applied to the input terminal 14, the phase comparator 11 compares the phase with the output signal of the frequency divider 13, and the control signal changes in accordance with the phase difference between the two. The oscillation frequency of the numerically controlled oscillator 12 is controlled according to the signal.

  When the oscillation frequency of the numerically controlled oscillator 12 is higher than the frequency of the synchronous input signal, the numerically controlled oscillator 12 functions to lower the oscillation frequency, and vice versa. When the oscillation frequency of the controlled oscillator 12 is equal to the frequency of the synchronization input signal, synchronization is established, the control signal is held to maintain synchronization, and the synchronization output signal output from the numerically controlled oscillator 12 is connected It is output to the outside through the terminal 14.

  In the conventional technique, since the phase is compared by the phase comparator 11, it takes time to establish synchronization, and the synchronization output signal output from the numerically controlled oscillator 12 at the time when synchronization is established. There is a problem that there is a residual phase error or synchronization establishment error between the signal and the synchronization input signal, and the residual phase error becomes unstable.

  In the conventional “ubiquitous mobile network having a relative distance measurement function” described in Patent Document 2, it is described in (Claim 1) that a “synchronous oscillator” is provided. There is a problem that has not been.

In the conventional “distance measuring device” described in Patent Document 3, the “digital synthesizer” described in Patent Document 1 is applied, and there is a problem similar to that of Patent Document 1.

The present invention has been made to solve the problem that the conventional phase-locked oscillator (PLL) or injection-locked oscillator cannot maintain synchronization when there is a period in which the input of the synchronous input signal is paused or stopped. Therefore, an object of the present invention is to provide a synchronous oscillator that can establish synchronization with a synchronization input signal instantaneously and can maintain synchronization with high accuracy and stability even when the synchronization input signal is paused or stopped.

  In the “synchronous oscillator capable of instantaneously establishing and maintaining synchronization” according to the present invention, the synchronous input signal is demodulated by the receiver 7 and unnecessary noise is removed by the band-pass filter 25 as shown in FIG. And converted to a digital signal by the zero crossing detector 26. On the other hand, the clock signal generated by the reference oscillator 21 having high frequency stability is directly used as a sampling signal or converted to a sampling signal having a high frequency by the phase-locked oscillator 23, and the digital signal is sampled using the sampling signal. Then, the timing of the rising point, falling point, or zero crossing of the synchronous input signal is detected.

At the detected timing, the output signal of the reference oscillator 21 is directly or frequency-converted into a clock signal, or converted to a high frequency by a phase-locked oscillator or multiplier to be a clock signal, and driven by the clock signal. By setting or resetting the counter 22 with set or reset, the counter with set or reset establishes synchronization with the synchronization input signal instantaneously, and after the synchronization input signal pauses or stops. Since the highly accurate synchronization can be maintained or maintained for a relatively long time, the synchronous oscillator can be realized at low cost. In addition, as shown in FIG. 1, it is not indispensable to connect by a wireless line, and the same effect is acquired even if it connects by a wired line.

  In a conventional synchronous oscillator that can maintain synchronization, a digitized phase comparator is adopted, but its output signal is an analog signal, and the analog signal is converted into a digital signal by an analog-to-digital converter. Since the frequency is controlled by adding or subtracting the set value of the register of the numerically controlled oscillator (NCO) by the control signal, it is difficult to establish synchronization in a short time and the synchronization establishment accuracy is low. Therefore, there is a problem that it is difficult to maintain the synchronization state stably and with high accuracy when the synchronization input signal is paused or stopped.

On the other hand, in the synchronous oscillator of the present invention, the set or reset counter is set or reset at the rising point, falling point, or zero crossing timing of the synchronous input signal. The counter can establish synchronization instantaneously, and even when the synchronization input signal is paused or stopped, the synchronization state can be maintained stably and with high accuracy, and the circuit can be configured in an integrated circuit at low cost. can get.

  The synchronous oscillator according to the present invention, as shown in FIG. 1 and claim 1 of the first embodiment of the present invention, instantaneously establishes synchronization with a synchronous input signal transmitted through a wireless line or a wired line, and In the synchronous oscillator 10 for maintaining synchronization for a relatively long time, the synchronous oscillator 10 converts at least the reference oscillator 21 whose oscillation frequency is highly stable and the output signal of the reference oscillator 21 directly or the frequency. The sampling signal is used as a sampling signal, and the synchronization detection means 24 for detecting the timing of the rising point, falling point, or zero crossing of the synchronizing input signal, and the output signal of the reference oscillator 21 are directly or frequency converted into a clock signal. And a counter or numerically controlled oscillator 22 with a set or reset driven by the clock signal. ,

  At the timing detected by the synchronization detection means 24, the counter or numerically controlled oscillator is set or reset to establish synchronization instantaneously, and the counter or numerically controlled oscillator with set or reset is connected to the synchronization input signal. It is possible to maintain or maintain the synchronization for a relatively long period of time with high accuracy even during the pause or stop.

  Further, as shown in FIG. 3 and claim 2, in order to add a synchronization establishment error function to the synchronization input signal, to detect the timing of the rising point, falling point, or zero crossing point of the synchronization input signal The phase of the sampling signal to be used is shifted to a different phase by providing a plurality of sets of phase shift means 52 a to 52 n, and the plurality of sets of sampling signals whose phases are shifted are sequentially or periodically by the switching control means 53. Switch to output.

  According to another aspect of the present invention, in order to give a synchronization establishment error function to the synchronization input signal, the phase of the synchronization input signal is shifted to a different phase by providing a plurality of sets of phase shift means 52a to 52n. Then, a plurality of sets of synchronous input signals whose phases are shifted are sequentially or periodically switched and output by the switching control means 53.

  Further, as shown in FIGS. 4 and 4, in order to give a synchronization establishment error function to the synchronization input signal, the synchronization input signal generator 1 side and the synchronization oscillator 10 side are connected by a wireless line, and the synchronization A plurality of antennas or transducers 6a and 6b are provided on the input signal generator 1 side, the synchronous oscillator 10 side, or both, and the antenna switch 61 sequentially or periodically switches the output.

  Further, as shown in FIG. 5 and claim 5, in correspondence with the provision of the synchronization establishment error function, a plurality of sets or counters with resets or numerically controlled oscillators 72 a to 72 n are provided, and the synchronization input signal is During the input, the plural sets of counters or numerically controlled oscillators 72a to 72n are switched in accordance with the timing of switching the switching control means 53 or the antenna switch 61 on the side to which the synchronization establishment error function is applied, and the plural sets The counters or numerically controlled oscillators are sequentially or periodically set or reset to establish synchronization instantaneously, and the plurality of sets of counters or numerically controlled oscillators remain while the synchronous input signal is paused or stopped. The operations of 72a to 72n are continued to maintain or maintain synchronization for a relatively long time, Sequentially or periodically switched to output the output signal of the counter 72A～72n.

According to a sixth aspect of the present invention, the sum of the phase shifts is not less than the length of one cycle of the sampling signal.
According to another aspect of the present invention, a synchronous input signal input to the synchronous oscillator 10, a synchronous output signal output from the synchronous oscillator 10, or both of them are transmitted as a transmission phase error, a center frequency deviation, a group delay. Jitter noise included in the synchronous output signal is reduced by passing through a band-pass filter that can be finely adjusted with little or a small amount of distortion or a combination thereof.

In addition, as described in claim 8, even when the synchronization input signal is transmitted continuously instead of intermittently, by providing a synchronization establishment error function directly or indirectly to the synchronization input signal, instantaneous interruption Alternatively, it can be applied to a wired line or a wireless line where multiple propagation occurs.
In addition, as shown in claim 9, the output signal of the reference oscillator is converted to a frequency of 10 times or more of the synchronous input signal using a phase synchronous oscillator or a multiplier, and the clock signal, sampling signal, or Used as both of these.

(Embodiment 1)
FIG. 1 is a configuration diagram of a synchronous oscillator according to a first embodiment of the present invention. In FIG. 1, 1 is a synchronous input signal generator, 2 is a reference oscillator, 3 is a synchronous input signal generating means, 4 is a transmitter, 5 and 6 are antennas or transducers, 7 is a receiver, 10 is a synchronous oscillator, Reference numeral 14 is a synchronization input terminal, 15 is a synchronization output terminal, 21 is a reference oscillator, 22 is a counter with set or reset, 23 is a phase synchronization oscillator, 24 is synchronization detection means, 25 is a band pass filter, and 26 is a zero crossing detector. Or it is a comparator.

  The antenna or transmitter / receiver 5 connected to the transmitter 4 and the antenna or transmitter / receiver 6 connected to the receiver 7 are installed at a location away from each other, and are connected by a wireless line. In the synchronous input signal generation means 3, a synchronous input signal that is synchronized with or orthogonal to the clock signal supplied from the reference oscillator 2 is generated, modulated and amplified by the transmitter 4, via the antenna or the transducer 5, It is intermittently transmitted to the space as a burst radio signal.

  The radio signal intermittently transmitted to the space is received by the antenna or the wave transmitter / receiver 6, and the synchronization input signal demodulated by the receiver 7 is converted to unnecessary harmonics by the band-pass filter 25 via the synchronization input terminal 14. After the noise is removed, it is converted to a digital signal by the zero-crossing detector 26, while the clock signal generated by the reference oscillator 21 is converted to a high frequency sampling signal either directly or by a phase-locked oscillator or multiplier 23. The sampling signal is supplied to the synchronization detector 24, the output signal of the zero crossing detector 26 is sampled, and the timing of the rising point, falling point, or zero crossing point of the synchronous input signal is detected.

At the detected timing, by setting or resetting the counter 22 with set or reset a plurality of times, for example, about three times, synchronization is established instantaneously, for example, in 3 microseconds, and the synchronization input signal is paused. However, even when stopped or removed, the synchronization state can be maintained or maintained with high accuracy and high stability for a relatively long time.
The set or reset counter 22 converts the output signal of the reference oscillator 21 into a clock signal directly or by using a phase-locked oscillator or a multiplier 23 to generate a clock signal, and is driven by the clock signal. It shall be.

In addition, the oscillation frequency of the reference oscillator 21 must be an integral multiple of the frequency of the synchronous input signal, and the frequency deviation between the two is within ± 1 ppm, and should be as small as possible. Is desirable.
Further, when the frequency of the synchronization input signal is 1 MHz, synchronization can be reliably established within 3 microseconds by continuing the set or reset three times.

FIG. 2 is a diagram for explaining the operation of the synchronous oscillator according to the first embodiment of the present invention. In FIG. 2, 31 is a synchronous input signal, 32 is a zero-crossing signal of the synchronous input signal, 33 is a sampling signal, 34a and 34b are set or reset signals, 35a to 35d are synchronous output signals output from the synchronous oscillator, 36a, 36b is the synchronization establishment error, 37 is the time axis of the synchronization input signal, 38 is the time axis of the zero crossing signal, 39 is the time axis of the sampling signal, 40 is the time axis of the set or reset signal, 41 is the time axis of the synchronization output signal It is.
Since the set or reset signals 34a and 34b are assigned several bits, the time required for establishing synchronization is proportional to the number of bits.

  Here, before synchronization is established, a synchronization error 36a exists between the phase of the zero-crossing signal 32 and the phase of the sampling signal 33, whereas the rising point, falling point, Alternatively, when the timing of the zero crossing point is detected and the counter is reset at the detected timing, a synchronization detection error 36b corresponding to the pulse interval of the sampling signal 33 is generated at the maximum. Therefore, synchronization is established for the pulse interval of the sampling signal 33. An error 36b occurs. When the pulse interval of the sampling signal 33 is Δt, the fluctuation range of the synchronization establishment error is represented by ± Δt / 2.

  In order to establish a technique for establishing synchronization with high accuracy and in a short time, and maintaining or maintaining synchronization for a relatively long time, (1) rising point, falling point, or zero of the synchronization input signal 31 It is possible to detect an intersection with high accuracy, (2) to be able to instantaneously establish synchronization with the synchronous oscillator at the detected timing, and (3) to be able to stably synchronize the synchronous oscillator even after the synchronous input signal 31 is paused or stopped. It is an essential condition to be able to hold or maintain

  For (1), in order to detect the rising, falling, or zero crossing of the synchronization input signal 31, the frequency of the sampling signal 33 is set to a frequency that is 10 times higher than the frequency of the synchronization input signal 31. There is a need. For example, when the frequency of the sampling signal is 256 MHz, the fluctuation range of the detection error of the rising or falling edge of the synchronous input signal is ± 2 nanoseconds.

  (2) can be realized by setting or resetting a counter with set or reset a plurality of times at the timing when the rising point, falling point, or zero crossing point of the synchronization input signal 31 is detected. The counter with set or reset uses the output signal of the highly stable crystal oscillator 21 as a clock signal directly or the output signal of the phase-synchronized oscillator or multiplier 23, counts down the clock signal 33, and outputs the synchronous input signal 31. Synchronized output signals 35a to 35d that are synchronized with or orthogonal to the.

For (3), if a counter with a set or reset is adopted, the synchronous oscillation continues even after the reset signal pauses or stops, and the frequency of the synchronous input signal 31 and the oscillation of the reference oscillator 21 are continued. Synchronization can be maintained or maintained within a frequency deviation between frequencies.

In order to give a synchronization establishment error function to the synchronization input signal 31, the synchronization input signal, a sampling signal for detecting a rising point, a falling point, or a zero crossing point of the synchronization input signal, or both of them. The synchronization establishment error can be reduced by providing a plurality of sets of phase shift means for the phase of the signal and selecting and outputting them sequentially by the switching control means.
In addition, even when the synchronization input signal is transmitted continuously instead of intermittent transmission, by providing a synchronization establishment error function directly or indirectly to the synchronization input signal, a wire that causes instantaneous interruption or multiple propagation is generated. It can be applied to a line or a wireless line at a low cost.

(Embodiment 2)
FIG. 6 is a block diagram of a synchronous oscillator according to the second embodiment of the present invention. In FIG. 6, 22 is a numerically controlled oscillator with set or reset, 81 is an adder, 82 is a look-up table, 83 is a digital-to-analog converter, 84 is a band pass filter, 85 is a zero crossing detector, and 74 is a clock signal. , 76 is a set or reset terminal, and 75 is an output terminal.

  The numerically controlled oscillator 22 is an alternative to the counter 22 with the set or reset of the synchronous oscillator 10, and the register of the adder 81 sets the frequency of the synchronous output signal synchronized with or orthogonal to the synchronous input signal. It is programmed so as to be generated, and the addition is sequentially repeated by the clock signal input to the input terminal 74, and is replaced with the change in amplitude or phase conversion by the look-up table 82, and is converted into an analog signal by the digital / analog converter 83. After being converted, unnecessary frequency components are removed by the band pass filter 84, converted into a digital signal by the comparator 85, and output as a digital signal from the output terminal 75.

When a set or reset signal is input to the set or reset terminal 76, the numerically controlled oscillator 22 outputs a neutral point (zero crossing point). When the set or reset signal is removed, the synchronous input A synchronous output signal synchronized with the rising, falling, or zero crossing of the signal is output from the output terminal 75.

FIG. 3 is a block diagram of the synchronization establishment error function generation means of the present invention. In FIG. 3, 21 is a reference oscillator, 23 is a phase-locked oscillator, 27 is a synchronization establishment error function generating means, 51 is a plurality of stages of phase shifting means, 52a to 52n are switching taps of the phase shifting means 51, and 53 is a switching control means. , 54 are sampling signal input terminals, 55 is a clock signal input terminal, and 56 is a sampling signal output terminal.
The synchronization establishment error function generation means 27 includes at least a phase shift means 51, switching tabs 52a to 52n, and a switching control means 53.

  The sampling signal output from the phase-synchronized oscillator 23 has a frequency that is sufficiently higher than the frequency of the synchronous input signal, for example, a frequency of 256 MHz or more, and is connected to the phase shift means 51. . The phase shift means 51 is constituted by a plurality of stages of shift registers, a plurality of stages of delay elements, or a plurality of stages of delay circuits, and the signal output of each stage is drawn out by switching taps 52a to 52n. The signals are sequentially selected and output from the sampling signal output terminal 56 to the outside.

  The amount of phase shift at each stage of the phase shift means 51 is desirably as small as possible, and the total of the phase shift amounts needs to be not less than the pulse interval Δt of the sampling signal. For example, if the frequency of the sampling signal is 256 MHz, the phase shift amount of each stage of the phase shift means 51 is 4 nanoseconds or less, and the total of the phase shift amounts needs to be 4 nanoseconds or more. . Here, assuming that the number of switching taps is 16 and the length of the burst signal is 0.5 ms, the switching control means 53 switches the taps at a speed of 32 μs per step.

Therefore, it is necessary to establish the synchronization in 1/10 of the switching time per step of 32 μs, that is, about 3 μs.
The synchronization establishment error function generation means 27 may be connected to the output terminal of the synchronization input signal generation means 3 or the output terminal of the zero crossing detector 26 when applied to a certain type of system. Effects can be obtained.

Further, if the total synchronization establishment error generated for each of the plurality of stages of taps 52a to 52n of the phase shift means 51 is expressed as a synchronization establishment error function, the synchronization establishment error function can be represented by a polynomial, and the polynomial is 0 or It is desirable to converge to a constant value.

FIG. 4 is another configuration diagram of the synchronization establishment error function generation means of the present invention. In FIG. 4, 27 is a synchronization establishment error function generating means, 25 is a receiver, 6a and 6b are a plurality of antennas or transducers, 61 is an antenna switch, and 14 is an output terminal of the receiver.
The plurality of antennas or transducers 6a and 6b are installed apart from each other by a quarter of a wavelength, and receive and receive radio signals while switching them sequentially or periodically using the antenna switch 61. When the synchronization input signal is demodulated by the machine 25, the phase of the synchronization input signal demodulated between the two is different due to the difference in propagation path length generated in the wireless section or multiple propagation, and the correlation between the two is small. I know.

Therefore, the same effect as that of the synchronization establishment error function generation means 27 shown in FIG. 3 can be obtained by switching the antenna switch 61 sequentially or periodically during reception as the burst signal.
Note that the greater the number of antennas or transducers, the greater the effect of providing a synchronization error function due to multiple propagation that occurs in the radio section.

FIG. 5 is another configuration diagram of the synchronization establishment error function generation means of the present invention. In FIG. 5, 22 is a counter with reset, 71 and 73 are switching control means, 72a to 72n are a plurality of counters or numerically controlled oscillators, 74 is a set or reset signal connection terminal, 75 is an output terminal, and 76 is a clock signal input. Terminal.
At the input terminal 74 of the counter or numerically controlled oscillator 22 or the reset signal, while the synchronization input signal is received as a burst signal, the synchronization detection means 24 causes the synchronization input signal to rise, fall, or zero crossing point. Is detected and input as a timing signal.

  Therefore, the switching control means 71 of FIG. 5 is switched sequentially or periodically in synchronization with the timing of switching the switching control means 53 or the antenna switch 61 on the side that gives the synchronization establishment error function in FIGS. During the period when the synchronization input signal is paused or stopped, or during a necessary period, the switching control means 71 is opened to maintain or maintain the synchronization, and the switching control means 73 sequentially or periodically. The synchronous output signal is output from the output terminal 75.

On the other hand, since the clock signal is directly or frequency-converted from the reference oscillator 21 to the clock signal input terminal 76 of the counter or numerically controlled oscillator 22, it is synchronized with the timing of the set or reset signal. Normally, a countdown is started to a lower frequency and synchronization is established.
Further, the switching of the switching control means 73 or the antenna switch 61 is performed by determining the order, performing it periodically, performing it periodically, performing it randomly, or selecting any method.

  Here, the reference oscillator 2 of the synchronous input generator 1 and the reference oscillator 21 of the synchronous oscillator 10 have an oscillation frequency deviation within ± 1 ppm. Therefore, there is a problem that the timing of the set or reset signal detected by the synchronization detecting means 24 is also kept constant, and therefore the synchronization establishment error is kept constant.

Therefore, when the synchronization establishment error function is added, the synchronization establishment error is converted into jitter noise. Therefore, the synchronization establishment error can be reduced by leveling by some method. As a method of leveling, the synchronization input signal inputted to the synchronous oscillator 10, synchronous output signal output from the synchronous oscillator 10, or both of these, the transfer phase error, the center frequency deviation, see group delay distortion, or If these combinations are few , or at least leveled through a band-pass filter that can be finely adjusted, the jitter noise can be reduced, so that the synchronization establishment error can be reduced. Since the leveled synchronous output signal is an analog signal, it can be converted to a digital signal using a zero-crossing detector.

In the above description, the case where a counter with a set or reset or a numerically controlled oscillator is used has been described. However, the synchronous oscillator can be easily configured by using an oscillator having a similar function.
The synchronization input signal may include a signal transmitted via a wired line, a signal obtained by demodulating a radio signal, a continuous signal, or any kind of synchronization input signal having a single frequency.
Also, depending on the use of the synchronous oscillator, the same effect can be obtained by providing the phase shift means on the side of generating the synchronous input signal and applying a plurality of sets of phase shifts.

Further, as another method of providing a synchronization establishment error function, when the synchronization input signal generator and the synchronization oscillator side are connected by a wireless line, the synchronization input signal generator side, the synchronization oscillator side, or Both of them are provided with a plurality of antennas or transducers and antenna switchers, and the plurality of antennas or transducers are periodically arranged in accordance with the switching timing of the switching control means provided in the counter of the synchronous oscillator. It is effective to switch.
In addition, an ultrasonic signal, a high-frequency signal, or an optical signal is used as a radio signal, and the ultrasonic signal and the optical signal are transmitted and received using a transducer.

  Since the present invention is configured as described above, the synchronization between the synchronization input signal and the synchronization output signal, which have the same frequency and the same phase in the communication system, or both of them are essential, Even if the sync input signal is established instantly with high accuracy within a few microseconds, and the sync input signal pauses, stops, disappears, or is removed, the sync output signal holds the sync status with high accuracy or It relates to the fundamental technology that can be widely used in the fields that need to be maintained.

Specifically, in the field of measuring the distance between wireless devices of the time-division simultaneous transmission / reception method, a device that measures the distance, a device that measures the distance, and a wireless device other than the two devices. From a device that relays signals, or a combination of these, the synchronization input signal that is transmitted or received included in the radio signal and the synchronization output signal that is output synchronously are instantly established with high accuracy. It can also be used to maintain synchronization for a relatively long time.
Further, when it is necessary to instantly configure an ad hoc network among a plurality of wireless devices, it can be used to instantaneously measure the distance between each other.

1 is a configuration diagram of a synchronous oscillator according to a first embodiment of the present invention. Operational explanatory diagram of the synchronous oscillator according to the first embodiment of the present invention Configuration diagram of synchronization establishment error function generation means of the present invention Another configuration diagram of synchronization establishment error function generation means of the present invention Another configuration diagram of synchronization establishment error function generation means of the present invention Configuration diagram of a synchronous oscillator according to a second embodiment of the present invention Configuration diagram showing a conventional example

DESCRIPTION OF SYMBOLS 1 Synchronous input signal generator 2 Reference oscillator 3 Synchronous input signal generation means 4 Transmitter 5, 6, 6a, 6b Antenna or transmitter / receiver 7 Receiver 10 Synchronous oscillator 21 Reference oscillator 22 Counter with set or reset 23 Phase synchronous oscillator 24 Phase synchronization detection means 25 Band-pass filter 26 Zero-crossing detector or comparator 27 Synchronization establishment error function generation means

Claims (8)

In a synchronous oscillator for establishing synchronization instantaneously with a synchronous input signal transmitted through a wireless line or a wired line and maintaining the synchronization for a relatively long time, at least the oscillation frequency is highly stable. A reference oscillator, a synchronization detection means for detecting a timing of a rising point, a falling point, or a zero crossing point of a synchronous input signal, directly or by converting the output signal of the reference oscillator into a sampling signal, and the reference An oscillator output signal is directly or frequency converted into a clock signal, a counter or numerically controlled oscillator with a set or reset driven by the clock signal, and a synchronization establishment error function adding means for adding a synchronization establishment error function And consists of
At the detected timing, the synchronization detection means sets the counter or numerically controlled oscillator with the synchronization establishment error function, and sets or resets to instantaneously establish synchronization, and the counter with the set or reset Alternatively, a numerically controlled oscillator can establish and maintain synchronization instantaneously, characterized in that it can maintain or maintain synchronization with high accuracy for a relatively long time while the synchronization input signal is paused or stopped. Synchronous oscillator.
The synchronization establishment error function providing means uses a plurality of sets of phase shift means to provide different phases for the phase of the sampling signal used to detect the timing of the rising point, falling point, or zero crossing of the synchronous input signal. 2. The synchronization is instantaneously established and maintained according to claim 1, wherein a plurality of sets of sampling signals shifted to the above-mentioned phase are shifted sequentially or periodically by the switching control means. Synchronous oscillator that can.
The synchronization establishment error function providing means shifts the phase of the synchronization input signal to a different phase by providing a plurality of sets of phase shift means, and switches the plurality of sets of synchronization input signals to which the phase has been shifted. 2. A synchronous oscillator capable of establishing and maintaining synchronization instantaneously according to claim 1, wherein switching is performed sequentially or periodically.
The synchronization establishment error function providing means connects the synchronization input signal generator side and the synchronization oscillator side by a wireless line, and provides a plurality of antennas on the synchronization input signal generator side, the synchronization oscillator side, or both 2. A synchronous oscillator capable of establishing and maintaining synchronization instantaneously according to claim 1, wherein switching is performed sequentially or periodically by an antenna switch.
The synchronization establishment error function providing means is provided with a plurality of sets or counters with resets or numerically controlled oscillators, and while the synchronization input signal is being input, the switching control means on the side that provides the synchronization establishment error function or According to the timing of switching the antenna switch, the plurality of sets of counters or numerically controlled oscillators are switched, and the plurality of sets of counters or numerically controlled oscillators are sequentially or periodically provided with the synchronization establishment error function, Set or reset to establish synchronization instantaneously, and while the synchronization input signal is paused or stopped, keep the operation of the multiple sets of counters to maintain or maintain synchronization for a relatively long time The output signals of the plurality of sets of counters or numerically controlled oscillators are switched sequentially or periodically and output. Instantly establishes synchronization and holding it locked oscillator which corresponds to one of the first claims, wherein up to fourth term.
The synchronous input signal input to the synchronous oscillator, the synchronous output signal output from the synchronous oscillator, or both of them are small in transmission phase error, center frequency deviation, delay distortion, or a combination thereof, or at least slight. 6. An adjustable band-pass filter is used to reduce noise contained in the synchronous output signal and, if necessary, converted to a digital signal by a zero-crossing detector. A synchronous oscillator that can establish and maintain synchronization instantaneously corresponding to any of the above .
Even when the synchronization input signal is transmitted continuously instead of intermittently, a wire connection or wireless that causes instantaneous interruption or multiple propagation by adding a synchronization establishment error function directly or indirectly to the synchronization input signal 7. A synchronous oscillator capable of establishing and maintaining synchronization instantaneously corresponding to any one of claims 1 to 6, characterized by being applicable to a line .
When the synchronization establishment error function providing means is connected between the synchronous input signal generator and the synchronous oscillator side by a wireless line, the synchronous input signal generator side, the synchronous oscillator side, or both, A plurality of antennas or transducers and an antenna switch are provided, and the plurality of antennas or transducers are switched sequentially or periodically in accordance with the switching timing of the switching control means provided in the synchronous oscillator. A synchronous oscillator capable of establishing and maintaining synchronization instantaneously corresponding to any one of claims 1 to 7 .

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