JP5238461B2 - Predistorter - Google Patents

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JP5238461B2
JP5238461B2 JP2008295454A JP2008295454A JP5238461B2 JP 5238461 B2 JP5238461 B2 JP 5238461B2 JP 2008295454 A JP2008295454 A JP 2008295454A JP 2008295454 A JP2008295454 A JP 2008295454A JP 5238461 B2 JP5238461 B2 JP 5238461B2
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distortion compensation
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polynomial
distortion
coefficient
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JP2010124190A (en
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孝基 柴田
孝義 佐々木
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Japan Radio Co Ltd
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Description

本発明は、信号増幅器などの被補償回路のメモリ効果による歪を補償するプリディストータに関するものである。   The present invention relates to a predistorter that compensates for distortion due to a memory effect of a compensated circuit such as a signal amplifier.

従来のプリディストータは、歪補償増幅装置の従来技術としては、単一のルックアップテーブル(LUT)を用いる方法(例えば、特許文献1を参照。)、やLUTを求めた後に歪補償多項式を用いて再び生成した単一のLUTを用いる方法(例えば、特許文献2を参照。)が知られている。また、メモリ効果対策を施した従来のプリディストータは、メモリ多項式を基本とした方法(例えば、特許文献3を参照。)、およびボルテラ(Volterra)級数を基本とした方法(例えば、特許文献4、5を参照。)が知られている。
特許第3560398号 特開2006−093947号公報 特開2004―320329号公報 特開2004―320598号公報 特開2007―282066号公報
In the conventional predistorter, as a conventional technique of the distortion compensation amplifying apparatus, a method using a single look-up table (LUT) (see, for example, Patent Document 1), or a distortion compensation polynomial is obtained after obtaining the LUT. There is known a method using a single LUT generated again using the same (for example, see Patent Document 2). In addition, conventional predistorters with memory effect countermeasures include a method based on a memory polynomial (for example, see Patent Document 3) and a method based on a Volterra series (for example, Patent Document 4). 5) is known.
Japanese Patent No. 3560398 JP 2006-093947 A JP 2004-320329 A JP 2004-320598 A JP 2007-282066 A

特にメモリ効果対策を施した歪補償増幅装置の従来技術では、メモリ多項式を基本とした方法やボルテラ級数を基本とした方法のいずれにしても、精度を高めるため、歪補償多項式の項(またはLUT)の数を多くすれば、歪補償多項式の係数を求める計算量が多くなり、計算時間がかかり結果として更新時間が長くなり、収束速度が遅くなるという課題があった。   In particular, in the prior art of the distortion compensation amplifying apparatus with a memory effect countermeasure, the distortion compensation polynomial term (or LUT) is used in order to improve accuracy in either the method based on the memory polynomial or the method based on the Volterra series. If the number of () is increased, the amount of calculation for obtaining the coefficient of the distortion compensation polynomial increases, and it takes a long time to calculate. As a result, the update time becomes long and the convergence speed becomes slow.

そこで、本発明は、上記課題を解決するためになされたもので、追従速度、および収束速度を速くすることもでき、十分な歪補償精度を得ることもできるプリディストータを提供することを目的とする。   Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a predistorter that can increase the follow-up speed and the convergence speed, and can obtain sufficient distortion compensation accuracy. And

前記目的を達成するために、本発明に係るプリディストータは、更新を始めた初期の段階では、歪補償多項式の一部の項の係数のみを更新するようにして計算量を減らして1回の更新に必要な時間を減少させ、段階的に算出する項の係数を増やしていき、歪補償値が規定値に収束する時間の減少と、歪補償精度を両立させることとした。   In order to achieve the above object, the predistorter according to the present invention reduces the amount of calculation once by updating only the coefficients of some terms of the distortion compensation polynomial at the initial stage of updating. The time required for the update is reduced, the coefficient of the term to be calculated in stages is increased, and both the reduction of the time for the distortion compensation value to converge to the specified value and the distortion compensation accuracy are made compatible.

具体的には、本発明に係るプリディストータは、入力信号から予歪補償信号を生成する歪補償多項式を有し、前記歪補償多項式で生成した前記予歪補償信号を被補償回路へ出力する歪補償部と、前記入力信号及び前記被補償回路の出力信号が入力され、前記歪補償多項式に前記入力信号を代入して生成した信号と前記歪補償多項式に前記出力信号を代入して生成した信号との差分が小さくなるように前記歪補償多項式の係数を計算し、前記歪補償部に対して前記歪補償多項式の係数を更新させる制御部と、を備える。前記歪補償部が有する前記歪補償多項式は、互いに異なる時刻で前記入力信号を取り込んだ複数のサンプリング信号のそれぞれから複数の歪補償値を算出し、前記歪補償値のそれぞれを前記サンプリング信号のいずれかに乗じて歪信号を算出し、全ての前記歪信号を合成して前記予歪補償信号を生成し、前記制御部は、前記歪補償部に対して更新させる前記歪補償多項式の係数の数を段階的に増加していくことを特徴とする。   Specifically, a predistorter according to the present invention has a distortion compensation polynomial that generates a predistortion compensation signal from an input signal, and outputs the predistortion compensation signal generated by the distortion compensation polynomial to a compensated circuit. The distortion compensation unit, the input signal and the output signal of the compensated circuit are input, and the signal generated by substituting the input signal into the distortion compensation polynomial and the output signal into the distortion compensation polynomial A control unit that calculates a coefficient of the distortion compensation polynomial so that a difference from the signal becomes small, and causes the distortion compensation unit to update the coefficient of the distortion compensation polynomial. The distortion compensation polynomial included in the distortion compensation unit calculates a plurality of distortion compensation values from each of a plurality of sampling signals that have captured the input signal at different times, and each of the distortion compensation values is calculated as any one of the sampling signals. The distortion signal is calculated by multiplying, all the distortion signals are combined to generate the predistortion compensation signal, and the control unit updates the distortion compensation polynomial coefficient number to be updated by the distortion compensation unit It is characterized by increasing step by step.

また、本発明に係る他のプリディストータは、入力信号から予歪補償信号を生成する歪補償多項式を有し、前記歪補償多項式で生成した前記予歪補償信号を被補償回路へ出力する歪補償部と、前記予歪補償信号及び前記被補償回路の出力信号が入力され、前記予歪補償信号と前記歪補償多項式に前記出力信号を代入して生成した信号との差分が小さくなるように前記歪補償多項式の係数を計算し、前記歪補償部に対して前記歪補償多項式の係数を更新させる制御部と、を備える。前記歪補償部が有する前記歪補償多項式は、互いに異なる時刻で前記入力信号を取り込んだ複数のサンプリング信号のそれぞれから複数の歪補償値を算出し、前記歪補償値のそれぞれを前記サンプリング信号のいずれかに乗じて歪信号を算出し、全ての前記歪信号を合成して前記予歪補償信号を生成し、前記制御部は、前記歪補償部に対して更新させる前記歪補償多項式の係数の数を段階的に増加していくことを特徴とする。   Another predistorter according to the present invention includes a distortion compensation polynomial that generates a predistortion compensation signal from an input signal, and outputs the predistortion compensation signal generated by the distortion compensation polynomial to a compensated circuit. The difference between the compensation unit, the predistortion compensation signal, and the output signal of the compensated circuit is input, and the difference between the predistortion compensation signal and the signal generated by substituting the output signal into the distortion compensation polynomial is reduced. A control unit that calculates the coefficient of the distortion compensation polynomial and causes the distortion compensation unit to update the coefficient of the distortion compensation polynomial. The distortion compensation polynomial included in the distortion compensation unit calculates a plurality of distortion compensation values from each of a plurality of sampling signals that have captured the input signal at different times, and each of the distortion compensation values is calculated as any one of the sampling signals. The distortion signal is calculated by multiplying, all the distortion signals are combined to generate the predistortion compensation signal, and the control unit updates the distortion compensation polynomial coefficient number to be updated by the distortion compensation unit It is characterized by increasing step by step.

歪補償開始時には歪補償多項式の一部の項の係数だけ更新し、更新が進むにつれて係数を更新する項数を増やしていく。歪補償多項式の更新においては、係数を更新する項数を減らすと計算量が少なくなるので更新時間が短くなり、収束速度が速くなる。しかし、一方で更新する係数の項数を減らすと歪補償精度が劣化するので、更新する係数の項数を段階的に増やして歪補償精度も確保する。このように歪補償多項式の係数を更新すると、動作開始から1回目の更新までにかかる時間が減少するので、従来技術に比べて収束速度が速くなり、かつ最終的な歪補償精度も従来技術と同じになる。   At the start of distortion compensation, only the coefficients of some terms of the distortion compensation polynomial are updated, and the number of terms for updating the coefficients is increased as the update proceeds. In updating the distortion compensation polynomial, if the number of terms for updating the coefficient is reduced, the amount of calculation is reduced, so the update time is shortened and the convergence speed is increased. However, if the number of coefficient terms to be updated is reduced, the distortion compensation accuracy deteriorates. Therefore, the number of coefficient terms to be updated is increased stepwise to ensure distortion compensation accuracy. When the coefficients of the distortion compensation polynomial are updated in this way, the time taken from the start of operation to the first update is reduced, so the convergence speed is faster than the conventional technology, and the final distortion compensation accuracy is also the same as the conventional technology. Be the same.

従って、本発明に係るプリディストータは、更新を始めた初期の段階で追従速度、および収束速度を速くすることができ、最終的には十分な歪補償精度を得ることができる。   Therefore, the predistorter according to the present invention can increase the follow-up speed and the convergence speed at the initial stage when the update is started, and finally can obtain sufficient distortion compensation accuracy.

本発明に係るプリディストータの前記制御部は、前記歪補償多項式の係数を更新した回数に基づいて前記歪補償部に対して更新させる前記歪補償多項式の係数の数を決定することができる。   The control unit of the predistorter according to the present invention can determine the number of coefficients of the distortion compensation polynomial to be updated by the distortion compensation unit based on the number of times of updating the coefficient of the distortion compensation polynomial.

本発明に係るプリディストータの前記制御部は、前記入力信号と前記被補償回路の出力信号との差分に基づいて前記歪補償部に対して更新させる前記歪補償多項式の係数の数を決定してもよい。   The control unit of the predistorter according to the present invention determines the number of coefficients of the distortion compensation polynomial to be updated by the distortion compensation unit based on a difference between the input signal and the output signal of the compensated circuit. May be.

本発明は、追従速度、および収束速度を速くすることもでき、十分な歪補償精度を得ることもできるプリディストータを提供することができる。   The present invention can provide a predistorter that can increase the follow-up speed and the convergence speed and can obtain sufficient distortion compensation accuracy.

添付の図面を参照して本発明の実施の形態を説明する。以下に説明する実施の形態は本発明の構成の例であり、本発明は、以下の実施の形態に制限されるものではない。なお、本明細書及び図面において符号が同じ構成要素は、相互に同一のものを示すものとする。また、枝番号を付さない符号での説明は該符号に枝番号を付した構成要素や信号全てに共通する説明である。   Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment. In the present specification and drawings, the same reference numerals denote the same components. In addition, the description with the reference numerals without the branch numbers is the description common to all the components and signals with the reference numerals assigned with the branch numbers.

図1は、本実施例のプリディストータ301の構成を説明するブロック図である。プリディストータ301は、入力信号Xから予歪補償信号Aを生成する歪補償多項式を有し、歪補償多項式で生成した予歪補償信号Aを被補償回路401へ出力する歪補償部11と、入力信号X及び被補償回路401の出力信号Yが入力され、歪補償多項式に入力信号Xを代入して生成した信号と歪補償多項式に出力信号Yを代入して生成した信号との差分が小さくなるように歪補償多項式の係数を計算し、歪補償部11に対して歪補償多項式の係数を更新させる制御部13と、を備える。   FIG. 1 is a block diagram illustrating the configuration of the predistorter 301 of this embodiment. The predistorter 301 has a distortion compensation polynomial that generates the predistortion compensation signal A from the input signal X, and outputs the predistortion compensation signal A generated by the distortion compensation polynomial to the compensated circuit 401. Input signal X and output signal Y of compensated circuit 401 are input, and the difference between the signal generated by substituting input signal X into the distortion compensation polynomial and the signal generated by substituting output signal Y into the distortion compensation polynomial is small. And a control unit 13 that calculates the coefficient of the distortion compensation polynomial so that the distortion compensation unit 11 updates the coefficient of the distortion compensation polynomial.

図2は、本実施例のプリディストータ302の構成を説明するブロック図である。プリディストータ302は、入力信号Xから予歪補償信号Aを生成する歪補償多項式を有し、歪補償多項式で生成した予歪補償信号Aを被補償回路401へ出力する歪補償部11と、予歪補償信号A及び被補償回路401の出力信号Yが入力され、予歪補償信号Aと歪補償多項式に出力信号Yを代入して生成した信号との差分が小さくなるように歪補償多項式の係数を計算し、歪補償部11に対して歪補償多項式の係数を更新させる制御部13と、を備える。   FIG. 2 is a block diagram illustrating the configuration of the predistorter 302 of this embodiment. The predistorter 302 has a distortion compensation polynomial that generates the predistortion compensation signal A from the input signal X, and outputs the predistortion compensation signal A generated by the distortion compensation polynomial to the compensated circuit 401; The predistortion signal A and the output signal Y of the compensated circuit 401 are input, and the distortion compensation polynomial A and the signal generated by substituting the output signal Y into the distortion compensation polynomial are reduced. And a control unit 13 that calculates the coefficient and causes the distortion compensation unit 11 to update the coefficient of the distortion compensation polynomial.

例えば、被補償回路401は増幅器である。以下の説明は、被補償回路401が増幅器として説明する。   For example, the compensated circuit 401 is an amplifier. In the following description, the compensated circuit 401 is described as an amplifier.

図3は、プリディストータ301及びプリディストータ302の歪補償部11を説明するブロック図である。歪補償部11は、後述する数式11又は数式21で表される歪補償多項式を有しており、入力信号Xから予歪補償信号を生成して被補償回路401へ出力する。歪補償多項式は、互いに異なる時刻で入力信号Xを取り込んだ複数のサンプリング信号のそれぞれから複数の歪補償値を算出し、歪補償値のそれぞれをサンプリング信号のいずれかに乗じて歪信号を算出し、全ての歪信号を合成して予歪補償信号Aを生成する。予歪補償信号Aは、被補償回路401の歪特性の逆歪特性(歪補償特性)が加えられているので、被補償回路401の出力信号Yの歪を小さくすることができる。   FIG. 3 is a block diagram illustrating the distortion compensator 11 of the predistorter 301 and the predistorter 302. The distortion compensation unit 11 has a distortion compensation polynomial expressed by Equation 11 or Equation 21 described later, and generates a predistortion compensation signal from the input signal X and outputs it to the compensated circuit 401. A distortion compensation polynomial calculates a distortion signal by calculating a plurality of distortion compensation values from each of a plurality of sampling signals that have captured the input signal X at different times, and multiplying each of the distortion compensation values by one of the sampling signals. The predistortion compensation signal A is generated by synthesizing all the distortion signals. Since the predistortion compensation signal A is added with the inverse distortion characteristic (distortion compensation characteristic) of the distortion characteristic of the compensated circuit 401, the distortion of the output signal Y of the compensated circuit 401 can be reduced.

制御部13は、歪補償多項式に入力信号Xを代入して生成した信号又は予歪補償信号Aと歪補償多項式に出力信号Yを代入して生成した信号との差分が0に近づくように歪補償多項式の係数を計算する。さらに、制御部13は、計算した係数を歪補償部11の歪補償多項式に適用させる。制御部13の働きによりプリディストータ301及びプリディストータ302は被補償回路401で生ずる歪の変動に追従できる。さらに、制御部13は、計算の際、更新を始めた初期の段階では、歪補償多項式の項のうち一部の係数だけを計算して歪補償多項式に適用し、更新が進むに連れて計算する歪補償多項式の係数の数を段階的に増やして歪補償多項式に適用する。制御部13がこのように歪補償多項式の係数を計算し、歪補償多項式に適用することで、動作開始から1回目の更新までにかかる時間が減少するので、従来技術に比べて収束速度が速くなり、かつ最終的な歪補償精度も従来技術と同じになる。   The control unit 13 performs distortion so that the difference between the signal generated by substituting the input signal X for the distortion compensation polynomial or the signal generated by substituting the output signal Y for the distortion compensation polynomial and the predistortion compensation signal A approaches zero. Calculate the coefficient of the compensation polynomial. Further, the control unit 13 applies the calculated coefficient to the distortion compensation polynomial of the distortion compensation unit 11. The predistorter 301 and the predistorter 302 can follow the distortion variation generated in the compensated circuit 401 by the operation of the control unit 13. Further, in the initial stage of the update, the control unit 13 calculates only some of the distortion compensation polynomial terms and applies them to the distortion compensation polynomial, and calculates as the update progresses. The number of coefficients of the distortion compensation polynomial to be applied is increased stepwise and applied to the distortion compensation polynomial. Since the control unit 13 calculates the coefficient of the distortion compensation polynomial and applies it to the distortion compensation polynomial in this way, the time required from the start of operation to the first update is reduced, so that the convergence speed is faster than the conventional technique. And the final distortion compensation accuracy is the same as that of the prior art.

(更新量の算出の説明)
複数の増幅器で構成された増幅器は、図4のようにモデル化できる。入力信号Xを周期Tでサンプリングした離散時間信号をx(nT)とし、出力信号Yを周期Tでサンプリングした離散時間信号をy(nT)とし、表記を簡単にするためにそれぞれをx(n),y(n)で表すこととする。また、x(n)及びy(n)は実数成分と虚数成分を持つ複素数信号であり、x(n)及びy(n)に対する乗算及び加算は、それぞれ複素乗算及び複素加算を示すものとする。すなわち、先に説明した図1および図2においては歪補償部11と被補償回路401との間には図示しない直交変調器、D/A変換器、およびアップコンバータがあり、被補償回路401と制御部の間には図示しないダウンコンバータ、A/D変換器、および直交復調器がある。このとき、増幅器を構成する要素増幅器513の歪特性を表す歪特性多項式をそれぞれ

Figure 0005238461
とおく。ここで、jは要素増幅器513の番号であり、Jは要素増幅器513の個数である。また、dは入力信号の正規化先行時間、または正規化遅延時間を表し、D1はj番目の要素増幅器の最大正規化先行時間、D2はj番目の要素増幅器の最大正規化遅延時間、kは次数であり、Kはj番目の要素増幅器の歪成分の最大次数を表す。 (Description of calculation of update amount)
An amplifier composed of a plurality of amplifiers can be modeled as shown in FIG. A discrete time signal obtained by sampling the input signal X with a period T s is represented by x (nT s ), and a discrete time signal obtained by sampling the output signal Y with a period T s is represented by y (nT s ). X (n), y (n). Also, x (n) and y (n) are complex signals having a real component and an imaginary component, and multiplication and addition for x (n) and y (n) indicate complex multiplication and complex addition, respectively. . That is, in FIG. 1 and FIG. 2 described above, there are a quadrature modulator, a D / A converter, and an upconverter (not shown) between the distortion compensator 11 and the compensated circuit 401. There are a down converter, an A / D converter, and a quadrature demodulator (not shown) between the control units. At this time, each of the distortion characteristic polynomials representing the distortion characteristics of the element amplifier 513 constituting the amplifier is
Figure 0005238461
far. Here, j is the number of the element amplifier 513, and J is the number of the element amplifiers 513. Also, d represents the normalization lead time of the input signal, or the normalization delay time, D1 j is the maximum normalization lead time of the jth element amplifier, D2 j is the maximum normalization delay time of the jth element amplifier, k is the order, and K j represents the maximum order of the distortion component of the j-th element amplifier.

また、要素増幅器513を合成する比率を入力信号Xの振幅値の関数(合成多項式)を

Figure 0005238461
とおく。ここで、rは入力信号の正規化先行時間、または正規化遅延時間を表し、R1はj番目の要素増幅器に対する合成する比率において関係する入力信号の最大正規化先行時間、R2はj番目の要素増幅器に対する合成する比率において関係する入力信号の最大正規化遅延時間、lは次数であり、Lはj番目の要素増幅器に対する合成する比率において関係する入力信号の最大次数から1次高い次数を表す。このとき、増幅器の出力は
Figure 0005238461
Further, the ratio of combining the element amplifiers 513 is expressed as a function (combining polynomial) of the amplitude value of the input signal X
Figure 0005238461
far. Here, r represents the normalization leading time of the input signal, or the normalization delay time, R1 j is the maximum normalization leading time of the input signal related in the combining ratio with respect to the jth element amplifier, and R2 j is the jth The maximum normalized delay time of the input signal related in the combining ratio with respect to the element amplifier of L, l is the order, and L j is the first order higher than the maximum order of the input signal related in the ratio of combining with the j-th element amplifier. Represents. At this time, the output of the amplifier is
Figure 0005238461

ここで、数式3を整理する。まず、異なる増幅器(異なるj)の同じ項をまとめると

Figure 0005238461
である。ここで、max(c,c,…,c)はc,c,…,cの最大値を表す。 Here, Formula 3 is arranged. First, the same terms for different amplifiers (different j)
Figure 0005238461
It is. Here, max (c 1, c 2 , ..., c J) are c 1, c 2, ..., representing the maximum value of c J.

次に、数式4のr=dの項をまとめると

Figure 0005238461
である。 Next, if the term of r = d of Formula 4 is put together,
Figure 0005238461
It is.

また、数式5は、

Figure 0005238461
Equation 5 is
Figure 0005238461

更に、

Figure 0005238461
Furthermore,
Figure 0005238461

すなわち、図4のようにモデル化できる増幅器の歪特性を推定するには、複素数係数h’d,k、係数h’r,d,l、および係数h’r,d,l,kを算出すれば良い。係数h’d,k、係数h’r,d,l、および係数h’r,d,l,kを算出するには入力信号Xおよび出力信号Yを数式7のモデルに適用して最小二乗法を用いればよい。 That is, in order to estimate the distortion characteristics of an amplifier that can be modeled as shown in FIG. 4, complex coefficients h ′ d, k , coefficients h ′ r, d, l , and coefficients h ′ r, d, l, k are calculated. Just do it. In order to calculate the coefficient h ′ d, k , the coefficient h ′ r, d, l , and the coefficient h ′ r, d, l, k , the input signal X and the output signal Y are applied to the model of Equation 7 and the minimum two Multiplication may be used.

(歪補償方法)
次に、図4のモデルに基づいた増幅装置の歪補償方法について説明する。増幅装置全体の入出力信号の関係は

Figure 0005238461
となり、線形であるのが理想的である。但し、Gは増幅装置の利得を表す実数定数である。ここでは、以降の議論を簡単にする目的で、G=1とおくこととする。 (Distortion compensation method)
Next, a distortion compensation method for the amplification device based on the model of FIG. 4 will be described. The relationship between the input and output signals of the entire amplifier is
Figure 0005238461
Ideally, it should be linear. Here, G is a real constant representing the gain of the amplifier. Here, G = 1 is set for the purpose of simplifying the following discussion.

しかし、実際の増幅装置では、入力信号の振幅(もしくは電力)が大きくなると入出力信号の関係は線形ではなく数式3または数式7で表現されるように非線形となる。一方、数式3又は数式7において入力信号と出力信号の関係が理想的になるときy(n)=x(n)の関係が成立する。従って、図4のモデルに基づいた増幅回路を歪補償するには、図4のモデルを数式で表現した歪特性多項式である数式3または数式7において入力信号Xと出力信号Yを入れ替えた歪補償多項式

Figure 0005238461
However, in an actual amplifying apparatus, when the amplitude (or power) of the input signal increases, the relationship between the input and output signals is not linear but nonlinear as expressed by Equation 3 or Equation 7. On the other hand, when the relationship between the input signal and the output signal is ideal in Equation 3 or Equation 7, the relationship y (n) = x (n) is established. Therefore, in order to perform distortion compensation for the amplifier circuit based on the model of FIG. 4, distortion compensation is performed by replacing the input signal X and the output signal Y in Equation 3 or Equation 7 which is a distortion characteristic polynomial expressing the model of FIG. Polynomial
Figure 0005238461

数式3から数式7に整理したのと同様に、数式9を整理すると、

Figure 0005238461
Similar to the arrangement from Equation 3 to Equation 7,
Figure 0005238461

この数式10の複素数係数w’d,k、w’r,d,l、及びw’r,d,l,kを最小二乗法を用いて推定し、入力信号Xを歪補償多項式に従って補償すればよい。最小二乗法により複素数係数w’d,k、w’r,d,l、及びw’r,d,l,kを算出するに際しては、複素数係数w’d,k、w’r,d,l、及びw’r,d,l,kの総数よりも多くの入力信号X及び出力信号Yをサンプリングしたx(n)とy(n)の組を用いる。 The complex coefficients w ′ d, k , w ′ r, d, l , and w ′ r, d, l, k of Equation 10 are estimated using the least square method, and the input signal X is compensated according to the distortion compensation polynomial. That's fine. In calculating the complex coefficients w ′ d, k , w ′ r, d, l and w ′ r, d, l, k by the least square method, the complex coefficients w ′ d, k , w ′ r, d, l, and w 'r, d, l, than the total number of k by sampling the many input signals X and output signal Y x (n) and using a set of y (n).

すなわち、最小2乗法を用いて得られた数式10の係数を用いて増幅装置の入出力関係を線形にする目的で、増幅装置の前段に設けてある増幅装置の非線形な歪特性(歪値)に対する逆歪特性(歪補償値)を生成するプリディストータ301、あるいは302において、入力信号Xに歪補償値を予め与えた予歪補償信号Aを生成して増幅装置に入力する。このとき、増幅装置の出力信号Yがy(n)=x(n)となる予歪補償信号Aを得るために、プリディストータ301、あるいは302は、数式11で表される歪補償多項式で入力信号Xに歪補償値を予め与えて予歪補償信号Aを生成して増幅装置に入力する。

Figure 0005238461
That is, for the purpose of linearizing the input / output relationship of the amplifying apparatus using the coefficient of Equation 10 obtained using the least square method, the nonlinear distortion characteristic (distortion value) of the amplifying apparatus provided in the preceding stage of the amplifying apparatus. In a predistorter 301 or 302 that generates a reverse distortion characteristic (distortion compensation value) for the input signal X, a predistortion compensation signal A in which a distortion compensation value is given in advance to the input signal X is generated and input to the amplifying apparatus. At this time, in order to obtain the predistortion compensation signal A in which the output signal Y of the amplifier is y (n) = x (n), the predistorter 301 or 302 is a distortion compensation polynomial expressed by Equation 11. A distortion compensation value is given in advance to the input signal X to generate a predistortion compensation signal A, which is input to the amplifier.
Figure 0005238461

図4のモデルを数式で表現した歪特性多項式である数式3または数式7で与えられる非線形な歪を補償する逆歪特性(歪補償特性)を与える予歪補償信号A、すなわち数式11のa(n)を得るには、数式3または数式7においてx(n)とy(n)を入れ替えた数式9または数式10の関係を満たす係数w’j,r,d,l,k、または、係数w’d,k、w’r,d,l、及びw’r,d,l,kを得ればよい。 A predistortion compensation signal A that gives an inverse distortion characteristic (distortion compensation characteristic) that compensates for the non-linear distortion given by the mathematical expression 3 or 7, which is a distortion characteristic polynomial expressing the model of FIG. In order to obtain n), a coefficient w ′ j, r, d, l, k that satisfies the relationship of Expression 9 or Expression 10 in which x (n) and y (n) are replaced in Expression 3 or 7 or coefficient What is necessary is to obtain w ′ d, k , w ′ r, d, l , and w ′ r, d, l, k .

(歪補償多項式の係数の算出方法)
ここで、数式10を利用して歪補償多項式の係数を求める方法について説明する。但し、ここでは、表現の簡単のためにDa=0、R1=0、D1=0とおく。複素数係数w’d,k、w’r,d,l、及びw’r,d,l,kをすべて並べた係数のベクトルを

Figure 0005238461
とおく。ここで、Tは行列の転置を表す。 (Calculation method of distortion compensation polynomial coefficients)
Here, a method for obtaining the coefficient of the distortion compensation polynomial using Expression 10 will be described. However, here, for simplicity of expression, Da = 0, R1 = 0, and D1 = 0. A vector of coefficients in which complex coefficients w ′ d, k , w ′ r, d, l , and w ′ r, d, l, k are all arranged
Figure 0005238461
far. Here, T represents transposition of the matrix.

次に、w、w、・・・、wを求める方法について説明する。数式12の歪補償多項式の係数w0,w1,・・・,wを求めるには、異なるnにおけるQ+1個以上の数式10が必要である。ここで、数式10を行列表現すると数式13となる。

Figure 0005238461
但し、
Figure 0005238461
歪補償多項式の係数を推定する際に使用する異なるnに対する数式10の個数はN(N≧Q+1)であり、数式10をN個まとめると数式13は数式15の連立方程式となる。
Figure 0005238461
Figure 0005238461
Next, a method for obtaining w 0 , w 1 ,..., W Q will be described. In order to obtain the coefficients w 0 , w 1 ,..., W Q of the distortion compensation polynomial in Expression 12, Q + 1 or more Expressions 10 in different n are required. Here, when Expression 10 is expressed as a matrix, Expression 13 is obtained.
Figure 0005238461
However,
Figure 0005238461
The number of Equations 10 for different n used to estimate the coefficient of the distortion compensation polynomial is N (N ≧ Q + 1). When N of Equations 10 are combined, Equation 13 becomes the simultaneous equations of Equation 15.
Figure 0005238461
Figure 0005238461

数式15又は数式17の連立方程式を解くことで、係数w,w,・・・,wが求まる。数式15又は数式17の連立方程式を解くには掃き出し法を用いても良いし、最小二乗法を用いて数式18としても良い。

Figure 0005238461
Figure 0005238461
但し、Hは行列の複素共役転置を表す。このようにして得られた係数w,w,・・・,wをa(n)に適用し、x(n)に応じた歪補償値を算出すれば歪補償ができる。 The coefficients w 0 , w 1 ,..., W Q are obtained by solving the simultaneous equations of Expression 15 or Expression 17. In order to solve the simultaneous equations of Formula 15 or Formula 17, the sweep-out method may be used, or Formula 18 may be used by using the least square method.
Figure 0005238461
Figure 0005238461
Where H represents the complex conjugate transpose of the matrix. Distortion compensation can be performed by applying the coefficients w 0 , w 1 ,..., W Q thus obtained to a (n) and calculating a distortion compensation value corresponding to x (n).

歪補償部11は、制御部13が算出した係数を受け取り、歪補償多項式に適用する。プリディストータ301は、この係数を適用した歪補償多項式で入力信号Xから予歪補償信号Aを生成する。歪補償部11が記憶する歪補償多項式は被補償回路401を適切にモデル化し、そのモデルの歪特性から得られたものであるため、プリディストータ301は少ない計算量で歪補償値を算出でき、歪補償の精度を高くすることができる。但し、プリディストータ301の係数である数式12の初期値は、

Figure 0005238461
である。 The distortion compensation unit 11 receives the coefficient calculated by the control unit 13 and applies it to the distortion compensation polynomial. The predistorter 301 generates a predistortion compensation signal A from the input signal X using a distortion compensation polynomial to which this coefficient is applied. Since the distortion compensation polynomial stored in the distortion compensation unit 11 is obtained by appropriately modeling the compensated circuit 401 and obtained from the distortion characteristics of the model, the predistorter 301 can calculate the distortion compensation value with a small amount of calculation. The accuracy of distortion compensation can be increased. However, the initial value of Equation 12, which is the coefficient of the predistorter 301, is
Figure 0005238461
It is.

(更新アルゴリズム)
歪補償多項式の係数を1回で正確に求めるには、想定している入力信号の振幅(または電力)の全てを網羅するような信号を実際に増幅装置に入力した際の入力信号と、入力信号に対応する出力信号の組を用いて歪補償多項式の係数を最小二乗法を用いて算出する必要があり、計算量が膨大なものとなる問題がある。すなわち、歪補償多項式の係数を正確に算出するには、サンプリングした入力信号と出力信号を非常に多く用いる必要がある。
(Update algorithm)
In order to accurately obtain the coefficient of the distortion compensation polynomial at one time, the input signal when the signal that covers all the amplitude (or power) of the assumed input signal is actually input to the amplifying device, and the input It is necessary to calculate the coefficient of the distortion compensation polynomial using the least square method using a set of output signals corresponding to the signal, and there is a problem that the amount of calculation becomes enormous. That is, in order to accurately calculate the coefficient of the distortion compensation polynomial, it is necessary to use a very large number of sampled input signals and output signals.

また、温度、および湿度、並びに経年変化により増幅装置の歪補償多項式の係数も変化する問題がある。さらに、増幅装置の歪補償をしながら歪補償多項式の係数を時刻の経過とともに更新していく必要がある。そこで、歪補償多項式の係数を時刻の経過とともに更新する更新アルゴリズムをここで示す。   Further, there is a problem that the coefficient of the distortion compensation polynomial of the amplifying device also changes due to temperature, humidity, and aging. Furthermore, it is necessary to update the coefficient of the distortion compensation polynomial with the passage of time while performing distortion compensation of the amplifier. An update algorithm for updating the coefficient of the distortion compensation polynomial with the passage of time is shown here.

増幅装置の歪補償をしながら歪補償多項式の係数を更新する場合、増幅装置への入力信号はx(n)ではなく、増幅装置の出力信号Yであるy(n)をx(n)に近づけるように歪補償した数式11の予歪補償信号Aが入力信号になっている。   When updating the coefficient of the distortion compensation polynomial while compensating for distortion of the amplification device, the input signal to the amplification device is not x (n), but y (n), which is the output signal Y of the amplification device, is changed to x (n). The predistortion compensation signal A of Formula 11 that has been subjected to distortion compensation so as to be close to each other is an input signal.

このとき、正確に増幅装置の歪補償がなされていれば、y(n)=x(n)が成立するので、数式11において

Figure 0005238461
も成立する。ここで、
Figure 0005238461
とおく。但し、w’d,k(i)、w’r,d,l(i)、およびw’r,d,l,k(i)はi回目の更新で得られた係数w’d,k、w’r,d,l、およびw’r,d,l,kをそれぞれ表す。 At this time, if distortion compensation of the amplifying apparatus is accurately performed, y (n) = x (n) is established.
Figure 0005238461
Also holds. here,
Figure 0005238461
far. However, w ′ d, k (i), w ′ r, d, l (i) and w ′ r, d, l, k (i) are the coefficients w ′ d, k obtained in the i-th update. , W ′ r, d, l and w ′ r, d, l, k respectively.

もし、増幅装置の歪補償が十分でなければ、y(n)=x(n)とはならず、

Figure 0005238461
とおくと、誤差
Figure 0005238461
が得られる。この誤差e(n)が零になるように歪補償多項式の係数を更新する。 If the distortion compensation of the amplifying device is not sufficient, y (n) = x (n) does not hold,
Figure 0005238461
Error
Figure 0005238461
Is obtained. The coefficient of the distortion compensation polynomial is updated so that this error e (n) becomes zero.

すなわち、増幅装置全体の入出力関係を線形とする条件y(n)=x(n)を満たす係数w’d,k(i)、w’r,d,l(i)、およびw’r,d,l,k(i)は数式10を満たす。ここで、係数w’d,k、w’r,d,l、およびw’r,d,l,kを全て並べた係数は数式12によりw、w、・・・、wで表されるので、i回目の更新で得られた係数w、w、・・・、wをそれぞれw(i)、w(i)、・・・、w(i)とおくと、増幅回路全体の入出力関係を線形とする条件y(n)=x(n)を満たす係数w(i)、w(i)、・・・、w(i)は数式10を満たす。従って、a’(n)とa”(n)が一致するように、w(i)、w(i)、・・・、w(i)を求めればよい。 That is, the coefficients w ′ d, k (i), w ′ r, d, l (i), and w ′ r satisfying the condition y (n) = x (n) that makes the input / output relationship of the entire amplification device linear. , D, l, k (i) satisfies Equation (10). Here, the coefficients w ′ d, k , w ′ r, d, l , and w ′ r, d, l, k are all arranged as w 0 , w 1 ,. because represented, i-th coefficient w 0 obtained updates, w 1, ···, w Q each w 0 (i), w 1 (i), ···, w Q (i) and In other words, the coefficients w 0 (i), w 1 (i),..., W Q (i) satisfying the condition y (n) = x (n) that makes the input / output relationship of the entire amplifier circuit linear are mathematical expressions. 10 is satisfied. Accordingly, w 0 (i), w 1 (i),..., W Q (i) may be obtained so that a ′ (n) and a ″ (n) match.

ここで、w,w,・・・wの更新について説明する。

Figure 0005238461
とおく。但し、i≧0である。なお、数式24の係数w(i)の初期値としては、w(0)=(1,0,・・・,0)を用いるか、同じ被補償部に対して十分な取り込み点数Nのときに数式15、数式17または数式18を用いて予め求めておいた係数wをw(0)=wとして用いるか、同じ被補償部に対して十分に更新回数を確保して予め求めておいた係数の行列w(∞)をw(0)=w(∞)として用いればよい。 Here, the update of w 0 , w 1 ,... W Q will be described.
Figure 0005238461
far. However, i ≧ 0. As an initial value of the coefficient w (i) in Expression 24, w (0) = (1, 0,..., 0) T is used, or a sufficient number N of acquisition points for the same compensated portion is used. Sometimes the coefficient w obtained in advance using Expression 15, Expression 17 or Expression 18 is used as w (0) = w, or it is obtained in advance by ensuring a sufficient number of updates for the same compensated portion. The matrix w (∞) of the coefficients may be used as w (0) = w (∞).

ここでは、表現の簡単のためにDa=0、R1=0、D1=0とおいた場合、w(i),w(i),・・・,w(i)に対応した入力信号X及び出力信号Yの行列は、それぞれ数式25及び数式29とおくことができる。

Figure 0005238461
である。
また、行x(i)を構成するベクトルx1(i)、x2(i)およびx3(i)はそれぞれ数式26、数式27及び数式28で表せる。
Figure 0005238461
Figure 0005238461
Figure 0005238461
Figure 0005238461
Figure 0005238461
である。
また、行y(i)を構成するベクトルy1(i)、y2(i)およびy3(i)はそれぞれ数式30、数式31及び数式32で表せる。
Figure 0005238461
Figure 0005238461
Figure 0005238461
Figure 0005238461
但し、Nは歪補償値を推定する際に使用する入出力信号の取り込み点数、Mは次の多項式係数の更新時に用いる入出力信号の取り込み開始までのサンプリング間隔数である。 Here, in order to simplify the expression, when Da = 0, R1 = 0, and D1 = 0, input signals corresponding to w 0 (i), w 1 (i),..., W Q (i) The matrixes of X and output signal Y can be expressed as Equation 25 and Equation 29, respectively.
Figure 0005238461
It is.
Further, the vectors x1 n (i), x2 n (i), and x3 n (i) constituting the row x n (i) can be expressed by Expression 26, Expression 27, and Expression 28, respectively.
Figure 0005238461
Figure 0005238461
Figure 0005238461
Figure 0005238461
Figure 0005238461
It is.
Further, the vectors y1 n (i), y2 n (i), and y3 n (i) constituting the row y n (i) can be expressed by Expression 30, Expression 31, and Expression 32, respectively.
Figure 0005238461
Figure 0005238461
Figure 0005238461
Figure 0005238461
Here, N is the number of input / output signal capture points used when estimating the distortion compensation value, and M is the number of sampling intervals until the start of input / output signal capture used when updating the next polynomial coefficient.

また、

Figure 0005238461
Figure 0005238461
Figure 0005238461
とおくと、連立方程式
Figure 0005238461
によりw(i)を更新すればよい。但し、μは0<μ≦1.0を満たす。 Also,
Figure 0005238461
Figure 0005238461
Figure 0005238461
Then, simultaneous equations
Figure 0005238461
The w (i) may be updated by However, μ satisfies 0 <μ ≦ 1.0.

本発明では歪補償多項式を複数のグループに分割し、更新を開始した初期の時点では歪補償多項式の係数の一部のみを計算して適用し、更新が進むにつれて計算して適用する歪補償多項式の係数の個数を段階的に増やしていく。例えば、数式21の歪補償多項式a’(n)を

Figure 0005238461
と分割する。図5のように、更新を開始した初期の時点では歪補償多項式a’(n)の一部b(n)の係数のみを計算して更新し、歪補償値に反映させる。更新が進むにつれてb(n)、b(n)の順(もしくはb(n)、b(n)の順)に追加して求める係数の個数を増やしていく。 In the present invention, the distortion compensation polynomial is divided into a plurality of groups, and only a part of the coefficient of the distortion compensation polynomial is calculated and applied at the initial time when the update is started, and the distortion compensation polynomial is calculated and applied as the update proceeds. Increase the number of coefficients in steps. For example, the distortion compensation polynomial a ′ (n) of Equation 21 is
Figure 0005238461
And split. As shown in FIG. 5, at the initial time when updating is started, only the coefficients of part b 0 (n) of the distortion compensation polynomial a ′ (n) are calculated and updated and reflected in the distortion compensation value. As the update progresses, the number of coefficients to be obtained is increased in the order of b 1 (n) and b 2 (n) (or in the order of b 2 (n) and b 1 (n)).

また、b(n)、b(n)およびb(n)をそれぞれ

Figure 0005238461
である。 B 0 (n), b 1 (n) and b 2 (n) are
Figure 0005238461
It is.

このように歪補償多項式a’(n)を分割した場合、図6のように歪補償多項式の係数の更新を開始した初期の段階では、c0,0(n)の係数のみを算出、更新し、歪補償に反映させ、更新が進むに連れて

Figure 0005238461
のような順番で、求める歪補償多項式の係数の数を増やしていく。 When the distortion compensation polynomial a ′ (n) is divided in this way, only the coefficient of c 0,0 (n) is calculated and updated at the initial stage where the update of the coefficient of the distortion compensation polynomial is started as shown in FIG. And reflected in distortion compensation, as the update progresses
Figure 0005238461
In this order, the number of distortion compensation polynomial coefficients to be obtained is increased.

更に、c0,d(n)、c1,d(n)およびc2,d(n)は、

Figure 0005238461
である。このとき、
Figure 0005238461
のような順番で、求める歪補償多項式の係数を増やしていく。 Furthermore, c 0, d (n), c 1, d (n) and c 2, d (n) are
Figure 0005238461
It is. At this time,
Figure 0005238461
In this order, the coefficients of the distortion compensation polynomial to be obtained are increased.

以上のような歪補償多項式の分割は、最終的には多項式の最小単位である単項式にまで分割可能である。分割して得られた多項式は例えば図5及び図6のように順番付けできる。但し、図5及び図6の順番付けはあくまでも一例であり、この順番に限定されるものではない。   The division of the distortion compensation polynomial as described above can be finally divided into monomials which are the minimum units of the polynomial. The polynomials obtained by the division can be ordered as shown in FIGS. 5 and 6, for example. However, the ordering of FIGS. 5 and 6 is merely an example, and is not limited to this order.

図5及び図6に示したように歪補償多項式の項の係数を計算して適用することで、更新の初期の段階では、更新して歪補償に用いる多項式の項数が少ないので、係数を算出する計算量が減少し、1回の更新に必要な時間も減少するので歪補償量が規定値に収束するまでの時間が減少する。また更新が進むに連れて歪補償に使用する多項式の項数が段階的に増えるので、最終的な歪補償精度が高くなる。従って、歪補償値が規定値に収束する時間の減少と、歪補償精度を両立させることができる。   As shown in FIGS. 5 and 6, by calculating and applying the coefficients of the distortion compensation polynomial terms, the number of polynomial terms to be updated and used for distortion compensation is small at the initial stage of updating. Since the calculation amount to be calculated is reduced and the time required for one update is also reduced, the time until the distortion compensation amount converges to the specified value is reduced. Further, as the update progresses, the number of polynomial terms used for distortion compensation increases stepwise, so that the final distortion compensation accuracy increases. Therefore, it is possible to achieve both a reduction in time for the distortion compensation value to converge to the specified value and distortion compensation accuracy.

本発明に係るプリディストータは、移動体通信基地局などに用いられる無線送信機の電力増幅器に適用することができる。   The predistorter according to the present invention can be applied to a power amplifier of a radio transmitter used in a mobile communication base station or the like.

本発明に係るプリディストータの構成を説明するブロック図である。It is a block diagram explaining the structure of the predistorter which concerns on this invention. 本発明に係るプリディストータの構成を説明するブロック図である。It is a block diagram explaining the structure of the predistorter which concerns on this invention. 本発明に係るプリディストータの歪補償回路を説明するブロック図である。It is a block diagram explaining the distortion compensation circuit of the predistorter concerning the present invention. 複数の増幅器で構成された増幅回路をモデル化した図である。It is the figure which modeled the amplifier circuit comprised with the some amplifier. 本発明に係るプリディストータの更新時の動作を説明する図である。It is a figure explaining the operation | movement at the time of the update of the predistorter which concerns on this invention. 本発明に係るプリディストータの更新時の動作を説明する図である。It is a figure explaining the operation | movement at the time of the update of the predistorter which concerns on this invention.

符号の説明Explanation of symbols

301、302:プリディストータ
11:歪補償部
13:制御部
22:強度算出部
23:ルックアップテーブル
24:複素乗算器
401:被補償回路
511:遅延素子
512−j:振幅値関数(jは自然数)
513:要素増幅器
514:複素乗算器
515:積算器
X:入力信号
Y:出力信号
A:予歪補償信号
301, 302: Predistorter 11: Distortion compensation unit 13: Control unit 22: Intensity calculation unit 23: Look-up table 24: Complex multiplier 401: Compensated circuit 511: Delay element 512-j: Amplitude value function (j is Natural number)
513: Element amplifier 514: Complex multiplier 515: Integrator X: Input signal Y: Output signal A: Predistortion compensation signal

Claims (4)

入力信号から予歪補償信号を生成する歪補償多項式を有し、前記歪補償多項式で生成した前記予歪補償信号を被補償回路へ出力する歪補償部と、
前記入力信号及び前記被補償回路の出力信号が入力され、前記歪補償多項式に前記入力信号を代入して生成した信号と前記歪補償多項式に前記出力信号を代入して生成した信号との差分が小さくなるように前記歪補償多項式の係数を計算し、前記歪補償部に対して前記歪補償多項式の係数を更新させる制御部と、
を備えるプリディストータであって、
前記歪補償部は、
互いに異なる時刻で前記入力信号を取り込んだ複数のサンプリング信号を生成し、
1の前記サンプリング信号に、少なくとも該1の前記サンプリング信号に基づく値又は他の前記サンプリング信号に基づく値を乗じた算出結果を取得し、前記算出結果を全て合算する前記歪補償多項式を用いて前記予歪補償信号を生成し、
前記制御部は、前記歪補償部に対して更新させる前記歪補償多項式の係数の数を段階的に増加していくことを特徴とするプリディストータ。
A distortion compensation unit that generates a predistortion compensation signal from an input signal, and outputs the predistortion compensation signal generated by the distortion compensation polynomial to a compensated circuit;
The input signal and the output signal of the compensated circuit are input, and a difference between a signal generated by substituting the input signal into the distortion compensation polynomial and a signal generated by substituting the output signal into the distortion compensation polynomial is A controller that calculates the coefficient of the distortion compensation polynomial so as to be reduced, and causes the distortion compensation unit to update the coefficient of the distortion compensation polynomial;
A predistorter comprising:
The distortion compensation unit
Generate a plurality of sampling signals that take in the input signal at different times,
A calculation result obtained by multiplying one sampling signal by at least a value based on the one sampling signal or a value based on another sampling signal is acquired, and the distortion compensation polynomial that adds all the calculation results is used to obtain the calculation result. Generate a predistortion signal,
The predistorter, wherein the control unit gradually increases the number of coefficients of the distortion compensation polynomial to be updated by the distortion compensation unit.
入力信号から予歪補償信号を生成する歪補償多項式を有し、前記歪補償多項式で生成した前記予歪補償信号を被補償回路へ出力する歪補償部と、
前記予歪補償信号及び前記被補償回路の出力信号が入力され、前記予歪補償信号と前記歪補償多項式に前記出力信号を代入して生成した信号との差分が小さくなるように前記歪補償多項式の係数を計算し、前記歪補償部に対して前記歪補償多項式の係数を更新させる制御部と、
を備えるプリディストータであって、
前記歪補償部は、
互いに異なる時刻で前記入力信号を取り込んだ複数のサンプリング信号を生成し、
1の前記サンプリング信号に、少なくとも該1の前記サンプリング信号に基づく値又は他の前記サンプリング信号に基づく値を乗じた算出結果を取得し、前記算出結果を全て合算する前記歪補償多項式を用いて前記予歪補償信号を生成し、
前記制御部は、前記歪補償部に対して更新させる前記歪補償多項式の係数の数を段階的に増加していくことを特徴とするプリディストータ。
A distortion compensation unit that generates a predistortion compensation signal from an input signal, and outputs the predistortion compensation signal generated by the distortion compensation polynomial to a compensated circuit;
The distortion compensation polynomial is inputted so that a difference between the predistortion compensation signal and a signal generated by substituting the output signal into the distortion compensation polynomial is reduced. A control unit that updates the coefficient of the distortion compensation polynomial to the distortion compensation unit;
A predistorter comprising:
The distortion compensation unit
Generate a plurality of sampling signals that take in the input signal at different times,
A calculation result obtained by multiplying one sampling signal by at least a value based on the one sampling signal or a value based on another sampling signal is acquired, and the distortion compensation polynomial that adds all the calculation results is used to obtain the calculation result. Generate a predistortion signal,
The predistorter, wherein the control unit gradually increases the number of coefficients of the distortion compensation polynomial to be updated by the distortion compensation unit.
前記制御部は、前記歪補償多項式の係数を更新した回数に基づいて前記歪補償部に対して更新させる前記歪補償多項式の係数の数を決定することを特徴とする請求項1又は2に記載のプリディストータ。   The said control part determines the number of the coefficient of the said distortion compensation polynomial made to update with respect to the said distortion compensation part based on the frequency | count that the coefficient of the said distortion compensation polynomial was updated. Predistorter. 前記制御部は、前記入力信号と前記被補償回路の出力信号との差分に基づいて前記歪補償部に対して更新させる前記歪補償多項式の係数の数を決定することを特徴とする請求項1又は2に記載のプリディストータ。   The control unit determines the number of coefficients of the distortion compensation polynomial to be updated by the distortion compensation unit based on a difference between the input signal and an output signal of the compensated circuit. Or the predistorter of 2.
JP2008295454A 2008-11-19 2008-11-19 Predistorter Expired - Fee Related JP5238461B2 (en)

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