JP5237628B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor element.

  In a light emitting diode (LED) in which an n-type layer and a p-type layer are formed on a semiconductor substrate, ohmic electrodes are formed on the n-type layer and the p-type layer, and light is emitted by flowing a forward current. The holes supplied from the p-type layer and the electrons supplied from the n-type layer undergo luminescent recombination to generate light having a predetermined wavelength. Luminescence goes in all directions.

  Since the ohmic electrode is usually formed by performing an alloying treatment by heating, the ohmic electrode generally has a low reflectance. In order to supply current uniformly over a wide area and suppress light absorption by the ohmic electrode, the ohmic electrode on the light extraction surface side is often patterned. When the output light is extracted from the front side, the light emitted toward the back side is often not effectively used. In order to improve the external luminous efficiency, a reflective structure is formed.

  4 (A) and 4 (B) show two types of reflecting structures disclosed in the prior art of JP-A-7-273368.

  In FIG. 4A, a transparent insulating film 109 such as silicon oxide is formed on the back surface of the semiconductor substrate 102 on which the LED is formed, and is patterned to leave, for example, a matrix-distributed region. The ohmic electrode 107 is formed on the front surface side, and the ohmic electrode 108 is formed so as to cover the transparent insulating film 109 on the back surface side. Even if the ohmic electrodes 107 and 108 are alloyed, the interface between the ohmic electrode 108 and the transparent insulating film 109 and the interface between the transparent insulating film 109 and the semiconductor substrate 102 are not disturbed, and a reflective surface is formed.

  In FIG. 4B, the ohmic electrode is alloyed in a state where the ohmic electrode 107 is formed on the front surface side and the pattern of the ohmic electrode 108 is formed on the back surface side. Thereafter, a reflective metal layer 110 such as Ag having high reflectivity is formed on the back surface of the semiconductor substrate so as to cover the pattern of the ohmic electrode 108. After the reflective metal layer 110 is formed, heat treatment is avoided so as to protect the interface between the reflective metal layer 110 and the semiconductor substrate 102. The interface between the reflective metal layer 110 and the semiconductor substrate 102 provides a highly reflective reflective surface.

  When mounting an LED on a package or submount, there is a junction-down structure in which the LED is mounted on the package or submount with the light emitting layer side down. It becomes easy to improve the heat dissipation efficiency of the heat generated from the light emitting layer. In this case, when a reflective structure is to be formed, a reflective structure and an ohmic electrode are formed on the light emitting layer side, and a bonding layer such as solder or a eutectic alloy is formed thereon. When the LED is mounted on a package or a submount, the bonding layer is heated and melted. At this time, the constituent elements of the bonding layer are diffused, causing a problem of deteriorating the performance of the LED. In order to prevent diffusion, a barrier metal layer is used.

  FIG. 5 shows a configuration of a junction down type light emitting diode disclosed in Japanese Patent Application Laid-Open No. 2007-317771. A light emitting layer 112 is formed on the surface (lower surface in the figure) of the semiconductor substrate 111. The semiconductor substrate 111 is formed of a light-transmitting semiconductor so that light emitted from the light emitting layer 112 is transmitted. An insulating film 113 that is transparent at the emission wavelength is formed on the surface (lower surface) of the light emitting layer 112, and is patterned to enable electrode formation. A p-side ohmic electrode 114 is formed on the light emitting layer 112 via the patterned insulating film 113. On the p-side ohmic electrode 114, a barrier metal layer 115, an adhesion layer 115a, and a bonding layer 117 are stacked. In addition, an n-side ohmic electrode 116 is formed on the back surface (upper surface) of the semiconductor substrate 111.

The insulating film 113 is made of SiO ₂ , Si ₃ N _4, or the like, and is formed to a thickness (for example, about 100 nm in the case of SiO ₂ ) that maximizes the reflectance. The insulating film 113 is partially removed by patterning so as to enable ohmic contact between the light emitting layer 112 and the p-type electrode 114. In the region where the insulating film 113 is present, light traveling downward from the light emitting layer 112 is reflected by the insulating film 113 and the p-side ohmic electrode 114 which is not alloyed, and is efficiently extracted upward.

  The p-side ohmic electrode 114 is formed of, for example, an AuZn film having a thickness of 100 to 400 nm, and is in ohmic contact with the lower surface of the light emitting layer 112 in a region where the insulating film 113 is not formed. The n-side ohmic electrode 116 is formed of an Au—Ge—Ni film.

  The barrier metal layer 115 is formed of, for example, a composite barrier metal layer having a TaN / Ta periodic structure by electron beam (EB) vapor deposition, sputtering, or the like. The barrier metal layer 115 forms a barrier that prevents diffusion between the p-side ohmic electrode 114 and the bonding layer 117. The adhesion layer 115 a improves the adhesion between the barrier metal layer 115 and the bonding layer 117.

  The p-side ohmic electrode 114 is formed for each chip in a region inside the boundary line that should become the outer periphery of the chip after chip separation. The barrier metal layer 115, the adhesion layer 115a, and the bonding layer 117 are patterned slightly smaller in shape than the p-type electrode 114. By removing the metal layer of the dicing street, clogging of the dicing blade can be reduced.

JP 7-273368 A JP 2007-317771 A

  There are some problems in the manufacturing process of the semiconductor having the junction down structure described above.

  For example, an ohmic electrode and a barrier metal layer are stacked on a semiconductor substrate on which a reflective insulating film pattern is formed and a resist mask is formed on a dicing street line, and an ohmic contact is made with the metal layer on the resist mask being lifted off. When the heat treatment is performed, the thermal expansion coefficient and Young's modulus of the insulating layer and the barrier metal layer are greatly different, so that floating (cavity) is generated at the interface between the insulating layer and the ohmic electrode, and the reflectance is lowered. There is.

  In order to avoid such problems, after the ohmic electrode layer is deposited, the wafer is once taken out from the furnace, the resist is removed, the ohmic electrode is heat-treated, and after further forming a resist mask as necessary, There is a method of depositing a barrier metal layer. However, this method has another problem that the adhesion strength at the interface between the ohmic electrode layer and the barrier metal layer is weakened.

  The objective of this invention is providing the manufacturing method of the semiconductor element which improved the adhesive strength of an ohmic electrode and a barrier metal layer.

  An object of the present invention is to provide a semiconductor element having improved adhesion strength between an ohmic electrode and a barrier metal layer.

According to an aspect of the present invention, a method for manufacturing a semiconductor device includes: (a1) a step of preparing a semiconductor multilayer structure; and (a2) forming a resist pattern on the semiconductor multilayer structure after the step (a1). And (b1) a step of forming an ohmic electrode layer containing Au on the semiconductor multilayer structure; and (b2) a step of removing the resist pattern together with the ohmic electrode layer thereon after the step (b1). If, after the (c1) the step (b2), a step of forming an adhesive layer containing Au on said ohmic electrode layer, a barrier metal layer without air release from (d1) said step (c1) forming Forming a film.

  According to the present invention, the adhesion strength between the ohmic electrode and the barrier metal layer can be improved.

  1A to 1G and FIGS. 2A to 2F are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device 100 according to an embodiment of the present invention.

The semiconductor substrate 1s is an AlGaAs substrate having an AlAs mixing ratio of 0.2 or more, and a light emitting layer 2 having an Al _0.02 GaAs active layer having a double hetero (DH) structure is formed on the semiconductor substrate 1s. Yes. As shown in FIG. 1A, the surface close to the light emitting layer 2 of the main surface of the semiconductor multilayer structure 1 including the semiconductor substrate 1s and the light emitting layer 2 (in this embodiment, the p-type layer side, hereinafter referred to as the semiconductor multilayer structure) 1 is called a p-type layer side surface 1p), and an insulating film 3 made of SiO ₂ is deposited to a thickness of 1000 mm. By providing the insulating film 3, light emitted from the light emitting layer 2 can be reflected to the semiconductor substrate 1s side and efficiently extracted from the semiconductor substrate 1s side.

  Next, a resist film is applied on the insulating film 3, a resist pattern is formed by exposure and development, and wet etching is performed by immersing in buffered hydrofluoric acid (BHF) for 2 minutes, as shown in FIG. In addition, a part of the insulating film 3 is removed so that the surface of the semiconductor multilayer structure 1 and the p-type ohmic electrode 5 to be formed later can be electrically connected.

  Subsequently, in order to prevent metal deposition on a portion that becomes a dicing street, as shown in FIG. 1C, a resist film is applied, exposed, and developed to form a resist pattern 4a. For example, AZ5214 manufactured by Electronic Materials can be used as the resist.

  Next, it is immersed in BHF for a moment, and the oxide film on the surface of the semiconductor multilayer structure 1 is removed, and as shown in FIG. 1C, AuZn (Zn content: 5 wt%) is vacuumed to a thickness of 3000 mm by sputtering or the like. The p-type ohmic electrode layer 5 is formed by vapor deposition. In addition, the Zn content of AnZn constituting the ohmic electrode layer 5 is set to a content capable of forming a high reflectance and sufficient ohmic contact.

  Thereafter, a lift-off tape is applied to the p-type layer side surface 1p of the semiconductor multilayer structure 1 and removed to remove most of the resist pattern 4a and the p-type ohmic electrode layer 5 thereon. Subsequently, by performing ultrasonic cleaning with acetone three times for 3 minutes, the resist pattern 4a is completely removed as shown in FIG.

  Next, as shown in FIG. 1E, wet etching is performed by immersing a portion of the insulating film 3 serving as a dicing street in BHF for 2 minutes, and then removed.

  Next, a resist pattern film is formed on the surface of the main surface of the semiconductor multilayer structure 1 far from the light emitting layer 2 (in this embodiment, the n-type layer side, hereinafter referred to as the n-type layer side surface 1n of the semiconductor multilayer structure 1). Is applied, and is baked at 90 ° C., and then exposed using an electrode mask. Further, a reverse bake at 110 ° C., entire exposure, and a developer diluted with pure water at a 1: 1 ratio with an AZ developer is 70. Patterning is performed by dipping for 2 seconds to form a resist pattern 4b shown in FIG. For example, AZ5214 manufactured by Electronic Materials can be used as the resist.

  Thereafter, wet etching is performed by immersing in BHF for 30 seconds, and after removing the oxide film on the n-type layer side surface 1n of the semiconductor multilayer structure 1, AuGeNi is deposited on the n-type layer side surface 1n of the semiconductor multilayer structure 1, As shown in FIG. 1G, an n-type ohmic electrode layer 6 is formed.

  Next, a lift-off tape is applied to the n-type layer side surface 1n of the semiconductor multilayer structure 1 and peeled off to remove most of the resist pattern 4b and the n-type ohmic electrode layer 6 thereon. Subsequently, by performing ultrasonic cleaning with acetone three times for 3 minutes, the resist pattern 4b is completely removed to obtain the state shown in FIG. In order to form ohmic contact between the p-type and n-type ohmic electrodes 5 and 6, heat treatment is performed. In this heat treatment, the wafer (semiconductor laminated structure 1) in the state shown in FIG. 2A is heated to 400 ° C. in an alloy furnace in a nitrogen atmosphere to alloy the ohmic electrode with the underlying semiconductor and cooled to 100 ° C. And after removing from the alloy furnace.

  Next, a resist film is applied to the p-type layer side surface 1p of the semiconductor multilayer structure 1 and baked at 100 ° C., then exposed using an electrode mask, and further subjected to inversion baking at 120 ° C., overall exposure, Patterning is performed by immersing in a developing solution (for example, AZ-300MIF) for 150 seconds to form a resist pattern 4c for preventing metal deposition on a portion that becomes a dicing street shown in FIG. For example, AZ5200 manufactured by Electronic Materials can be used as the resist.

  As shown in FIG. 2C, AuZn (Zn content: 5 wt%) is vacuum-deposited on the surface of the p-type ohmic electrode 5 by sputtering or the like to a thickness of 1000 mm to form the adhesive layer 10. Subsequently, without removing the semiconductor multilayer structure 1 from the sputtering apparatus or the like, the composite barrier metal layer 7 is sequentially vacuum-deposited on the surface of the adhesive layer 10 at a thickness of 2000 mm, Ta is 1000 mm, and TaN is 2000 mm by sputtering or the like. Form. By providing the composite barrier metal layer 7, it is possible to prevent thermal diffusion of the elements of the eutectic layer 9 to the ohmic electrode. The nitriding rate of TaN is set so as to have a barrier property and to obtain high adhesion with a layer containing Au. Thereafter, AZ remover ultrasonic cleaning is performed until the resist pattern 4c can be completely removed, resulting in a state shown in FIG.

  As shown in FIG. 2E, a resist pattern 4d (such as AZ5200 manufactured by Electronic Materials) is formed again. Thereafter, an adhesion improving layer 8 made of a laminate of Al, Ta, and Au is vapor-deposited, and then a eutectic material made of AuSn is vapor-deposited to form a eutectic layer 9. The eutectic layer 9 is preferably used for mounting a semiconductor light emitting element on a wiring board or the like. Finally, AZ remover ultrasonic cleaning is performed until the resist pattern 4d and the adhesion improving layer 8 and the eutectic layer 9 thereon can be completely removed to obtain the state shown in FIG.

  FIG. 3 is a table showing a comparison result of yield and die shear strength between the semiconductor device 100 according to the embodiment of the present invention and the semiconductor device according to the comparative example.

  Unlike the semiconductor element 100 according to the embodiment of the present invention, the semiconductor element according to the comparative example is a p-type ohmic electrode 5 made of AuZn having a thickness of 3000 mm without forming the adhesive layer 10 in the state shown in FIG. Of TaN (nitridation rate 0.7, where the nitridation rate indicates the ratio of the number of metal atoms and nitrogen atoms) is 2000 mm, Ta is 1000 mm, and TaN (nitridation rate 0.7) is 2000 mm in thickness. The composite barrier metal layer 7 is formed by vacuum deposition. Other than that, it was fabricated using the same materials and conditions as those of the semiconductor device 100 according to the example of the present invention.

  FIG. 3A is a table showing the results of measuring the yield of the semiconductor device 100 according to the example of the present invention and the semiconductor device according to the comparative example.

  In this table, the wafer attached to the blue sheet is separated into chips by a dicing process, and when the separated chip is peeled off the blue sheet, the sample in which the metal remains on the blue sheet is regarded as defective, and the yield is measured. .

  The semiconductor device according to the comparative example has a yield of 10% or less, whereas the semiconductor device 100 according to the present embodiment has a yield of 100%, which shows a dramatic improvement.

  Moreover, in order to evaluate the adhesiveness of an electrode interface, each die shear strength of the semiconductor element 100 by an Example and the semiconductor element by a comparative example was measured. FIG. 3B is a table showing the results.

  Note that the die shear strength is a strength required to peel the bonded semiconductor element by pressing the needle from the side surface in a state where the semiconductor element is mounted on a mounting surface such as a package or a wiring board. If the adhesion of the multilayer electrode structure and the strength of the eutectic bonding portion are sufficient, the strength until the device breaks down is measured.

  In the semiconductor element according to the comparative example, the peeling interface was limited to the ohmic electrode and the barrier metal interface, whereas in the semiconductor element 100 according to the example, it was found that element destruction occurred. For these reasons, in the semiconductor element 100 according to the example, the adhesion strength at the interface between the ohmic electrode (p-type ohmic electrode 5) and the barrier metal electrode (composite barrier metal layer 7) is sufficient, and compared with the comparative example. It can be seen that it has improved dramatically.

  When secondary ion mass spectrometry (SIMS) was performed on each of the semiconductor element 100 according to the example and the semiconductor element according to the comparative example, the barrier metal layer (composite barrier metal layer 7 of the example) in the semiconductor element according to the comparative example was obtained. And an ohmic electrode (corresponding to the p-type ohmic electrode 5 of the example) and a layer containing more carbon. In contrast, in the semiconductor device 100 according to the example, it was found that there is a layer containing more carbon at the interface between the p-type ohmic electrode (AuZn layer) 5 and the adhesive layer (AuZn layer) 10.

  As described above, according to the embodiment of the present invention, after the resist removing step after the formation of the ohmic electrode film (p-type ohmic electrode 5), the adhesive layer 10 is deposited on the ohmic electrode film (p-type ohmic electrode 5) in the vapor deposition apparatus. By forming the composite barrier metal layer 7 without taking out from the vapor deposition apparatus, the adhesion strength between the ohmic electrode 5 and the barrier metal layer 7 can be dramatically improved.

  In addition, according to the embodiment of the present invention, after the heat treatment after the formation of the ohmic electrode film (p-type ohmic electrode 5), the adhesive layer 10 is formed on the ohmic electrode film (p-type ohmic electrode 5) in the vapor deposition apparatus. By forming and forming the composite barrier metal layer 7 without taking out from the vapor deposition apparatus, the adhesion strength between the ohmic electrode 5 and the barrier metal layer 7 can be remarkably improved, and the insulating film 3 and the ohmic electrode 5 can be prevented from floating.

  That is, according to the embodiment of the present invention, even when the ohmic electrode film 5 is formed and released into the atmosphere and subjected to a photolithography process and an alloying process, the adhesive layer 10 made of a metal containing Au is formed, and then By forming the barrier metal layer 7 without exposing to the atmosphere, the adhesion strength between the ohmic electrode 5 and the barrier metal layer 7 can be dramatically improved via the adhesive layer 10.

  In the above-described embodiment, the conductivity type on the mounting surface side is p-type and the p-type ohmic electrode 5 is formed of AuZn. However, the p-type ohmic electrode 5 is formed of AuBe or the p-type ohmic electrode on the mounting surface side. Instead of the electrode 5, an n-type electrode may be formed of AuGe, AuSn, or the like. That is, the ohmic electrode 5 on the mounting surface side is formed of a material containing Au, and the adhesive layer 10 formed thereon is also formed of a material containing Au. By forming both the ohmic electrode 5 and the adhesive layer 10 with a material containing Au, the familiarity is improved and the adhesion is improved. If both the ohmic electrode 5 and the adhesive layer 10 are made of a material containing Au, the material may not be the same, but the adhesion is further improved by forming with the same material as in this embodiment.

In addition, since the embodiment of the present invention aims at improving the adhesion between the ohmic electrode and the barrier metal, the insulating film 3 is not limited to SiO ₂ but may be SiN _X or may be omitted. When the insulating film 3 is omitted, the insulating film 3 forming step described with reference to FIGS. 1A and 1B and the insulating film in the dicing street portion described with reference to FIG. A removal process becomes unnecessary.

In the above-described embodiment, the composite barrier metal layer 7 is formed of a TaN / Ta / TaN laminate, but may be formed of a nitride such as TiN or TiWN that can prevent the eutectic material from diffusing. Good. The barrier metal layer 7 may be a stacked layer of the above nitrides or a single layer.
Further, another layer may be sandwiched between the adhesive layer 10 and the barrier metal layer 7, but even in that case, the process from the formation of the adhesive layer 10 to the formation of the barrier metal layer 7 is not open to the atmosphere. Assumed to be performed.

  In addition, the adhesive layer 10 and the barrier metal layer 7 may be formed by different vapor deposition apparatuses, but in this case, the process from the formation of the adhesive layer 10 to the formation of the barrier metal layer 7 is not released to the atmosphere. Assumed to be performed.

  The material of the light emitting layer 2 is not limited to AlGaAs, but may be, for example, AlGaInP, GaN, etc. However, an AlGaAs-based semiconductor or an AlGaInP-based semiconductor requires an alloying step when forming an ohmic contact with the electrode. Therefore, the present invention can be preferably used. Further, the adhesion improving layer 8 can be omitted or constituted by other materials. Further, the eutectic material may not be part of the semiconductor element 100 as the eutectic layer 9 but may be replenished to the bottom surface when the semiconductor element 100 is attached.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

FIG. 5 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device 100 according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device 100 according to an embodiment of the present invention. 6 is a table showing a comparison result of yield and die shear strength of a semiconductor device 100 according to an embodiment of the present invention and a semiconductor device according to a comparative example. It is a schematic sectional drawing which shows the structure of the conventional semiconductor element. It is a schematic sectional drawing which shows the structure of the conventional semiconductor element.

Explanation of symbols

1 ... semiconductor multilayer structure, 2 ... light-emitting layer, 3: insulating film _(SiO 2), 4 ... resist, 5 ... p-type ohmic electrode (AuZn), 6 ... n-type ohmic electrode (AuGeNi), 7 ... composite barrier metal layer (TaN / Ta / TaN), 8 ... adhesion improving layer, 9 ... eutectic layer, 10 ... adhesive layer (AuZn), 100 ... semiconductor element

Claims (5)

(A1) preparing a semiconductor multilayer structure;
(A2) after the step (a1), forming a resist pattern on the semiconductor multilayer structure;
(B1) forming an ohmic electrode layer containing Au on the semiconductor multilayer structure;
(B2) After the step (b1), removing the resist pattern together with the ohmic electrode layer thereon;
(C1) After the step (b2) , forming a bonding layer containing Au on the ohmic electrode layer;
(D1) A method of manufacturing a semiconductor device, including the step of forming a barrier metal layer without releasing the air from the step (c1). Furthermore, (b3) between the step (b1) and the step (c1), heat-treating said ohmic electrode layer and the semiconductor laminated structure, No mounting Claim 1 Symbol and forming an ohmic contact A method for manufacturing a semiconductor device. Said step (c1) and (d1), the manufacturing method of a semiconductor device according to claim 1 or performed by vapor deposition. The method according to any one of claims 1 to 3, wherein the barrier metal layer is made of a metal nitride. The method of manufacturing a semiconductor element according to claim 1, wherein the ohmic electrode layer and the adhesive layer have the same composition.

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