JP5236054B2 - Optical link and manufacturing method thereof (available for redundant memory in which a loop is formed between two X-type couplers) - Google Patents

Description

  The present invention relates to a connection method using an optical link from a host or the like to a plurality of storage devices, and more specifically, an optical connection method that realizes multiplexing / redundancy using the branching of the optical link and its unidirectionality or The present invention relates to an optical wiring system.

  Currently, a method using an optical link is attracting attention as a method for connecting a CPU such as a host and a storage device such as a memory, and research is being conducted. System reliability (RAS) is important for servers (even recently, personal computers), and the system configuration as a storage device such as memory is based on error correction code (ECC), mirroring ( A plurality of storage devices such as a memory are prepared by other RAID such as RAID 1), and a multiplexed configuration or a redundant configuration is supported over them.

  A CPU such as a host provides a data read command and a data write command to a storage device such as a memory. In executing processing according to these commands, the memory In general, an input / output (IO or I / O) controller incorporated in a storage device such as a memory or externally attached to a storage device such as a memory is used. That is, this IO controller plays a role of how to interpret a command supplied from a host or the like to operate a storage device such as a memory.

  Fault tolerance that is multiplexed / redundant in the event of any fault (usually unexpectedly) in any location of multiple storage devices such as memory By using, the recovery operation is performed. Also for this recovery operation, the IO controller usually plays the role. In the case of RAID, this role is played by a part called a RAID controller, and may be called data rebuilding for the purpose of recovery operation. Therefore, it is conceivable to enhance the functions of this IO controller, but in a situation where a plurality of storage devices such as memories are connected, as long as electrical wiring and electrical links are followed, There is also a limit on recovery time.

  Patent Document 1 changes the copy speed for a copy operation between memory elements in a memory mirroring configuration, but assumes electrical connection and complicates the burden on the memory control device or the mirroring control device. End up.

  Patent Document 2 describes a branching device for an input optical signal. This document shows the general state of the art for light branching.

  Patent Document 3 is a manufacturing method of an optical fiber coupler (2 × 2 type optical fiber coupler), and shows a general technical level that such manufacturing is possible, and optical communication using the same. Describes the system. However, a terminal portion at one end of the 2 × 2 type optical fiber coupler is an unnecessary port, and the unnecessary port is not utilized. This 2 × 2 type optical fiber coupler is sometimes called an X type coupler because of its appearance characteristics.

JP 2008-217727 A JP 2001-166177 A Japanese Patent Laid-Open No. 11-6936

  It is desirable to shorten the recovery time in the event of a failure of a plurality of memories having a multiplexed configuration / redundant configuration and to make the functions of the IO controller simpler.

  When optically connecting a host or the like and a storage device such as a plurality of memories via two or more optical couplers, the branching of the optical coupler and its unidirectionality are used to connect between the two optical couplers. An optical link that can be used in a configuration in which a loop is provided and a method for manufacturing the same are provided.

  Here, a configuration is adopted in which the IO controller selects a plurality of operation modes.

  The recovery time at the time of failure of a plurality of memories having a multiplexed configuration / redundant configuration can be shortened, and the function of the IO controller can be made simpler.

FIG. 1 is a diagram showing a configuration of a memory unit used in the present invention. FIG. 2 is a diagram showing a connection example between a plurality of memory units and a host according to the present invention. FIG. 3 is a schematic diagram showing three types of states (operation modes) and transitions between these states according to the present invention. FIG. 4 is a diagram showing a timing chart of a memory recovery operation in a state where the host and two memory units are electrically connected as a conventional technique. FIG. 5 is a diagram showing a timing chart of a memory recovery operation in a state where the host and two memory units are optically connected (through a “loop” without returning to the host) according to the present invention. is there. FIG. 6 is a diagram showing an optical link creation method according to the present invention. In this example, the optical link is employed as the optical interconnect in FIG. 2, and the same reference numerals as those in FIG. 2 are given. FIG. 7 is a diagram showing a connection example further developed according to the present invention. FIG. 8 is a diagram showing a method of creating an optical link that realizes the connection of the advanced configuration of FIG. 7 according to the present invention.

  FIG. 1 is a diagram showing a configuration of a memory unit used in the present invention. A memory unit (hereinafter also expressed as an abbreviation called Unit) 100 includes an IO controller (hereinafter also expressed as an abbreviation called Ctrl.) 10 and a memory device (hereinafter also expressed as an abbreviation called Dev.) 20. Are included in the main components. The IO controller 10 performs control of designating data in the memory device 20 and an address where the data is stored through the input 22 of the memory device 20. Further, the IO controller 10 performs control to take out data in the memory device 20 through the output 24 of the memory device 20.

  The IO controller 10 controls not only the memory device 20 but also the optical interconnect. In the present invention, a plurality of operation modes can be set in the memory unit 100. It can be physically controlled by the mode switch 16 of the memory unit 100 main body, or can be controlled by a network connection such as that performed through the network interface 18 or by an optical link itself.

An important configuration in the present invention is that at least three types of operation modes can be set in the IO controller 10. Specifically, according to a read command (also expressed by an abbreviation Cmd) or a write command provided by the host (the transmission end),
(1) A state in which data is read from the memory in response to a read command, and data is written to the memory in response to a write command (Active Mode).
(2) A state that does not respond to a read command but only executes data writing to a memory in response to a write command (Snoop Mode), and
(3) A state in which data is written to the memory in response to the write command, and the read command is converted to the write command and the data is written to the memory (Recovery Mode).
About (at least) three types of states
Selective transition between the state of (1) and (2) and between the state of (2) and (3) is possible.
That is the point.

  Such at least three types of operation modes and selective transitions between them can be realized as functions of the IO controller 10 itself, but the IO controller 10 is built in the memory unit 100 as shown in FIG. Alternatively, the corresponding function as the IO controller 10 can be implemented as an externally attached memory unit 100 (not shown in this case).

  The receiving end (Rx) 12 can receive a read command or a write command through the receiving end 12. The receiving end (Rx) 12 can receive data, receive information such as an address, write data to any address in the memory device 20, and write data from any address in the memory device 20. The memory device 20 is operated for reading. Due to the unidirectional nature of the light, the receiving end (Rx) may be referred to as the write port or the input channel (In).

  At the transmission end (Tx) 14, data is output from the memory device through the transmission end 14 in accordance with a read command. Due to the unidirectional nature of the light, the output channel (Tx) 14 may be called a read port or an output channel (Out).

  FIG. 2 is a diagram showing a connection example between a plurality of memory units and a host according to the present invention. The memory unit 200 and the memory unit 400 have the same configuration as the memory unit 100 in FIG. What is illustrated as the host 50 only conceptually shows a function corresponding to a CPU for providing a command to a plurality of memory units (portion in which the memory unit 200 exists). What is necessary is just to construct | assemble as the relationship which can transmit / receive a command by the some optical interconnect between the units 400. FIG. Hereinafter, such a concept is also expressed by the notation “Host”.

  Write from the host 50 is simultaneously distributed to the receiving end (Rx) 212 of the memory unit 200 and the receiving end (Rx) 412 of the memory unit 400 via the coupler 30. As for reading from the memory, only the memory unit in the Active Mode state ((1) state) outputs data to the host 50 from the transmission end (Tx). In the case of this figure, only the memory unit 200 is in the Active Mode state, and the memory unit 400 is in the Snoop Mode state ((2) state), so only the transmission end (Tx) 214 of the memory unit 200 is present. Is not output from the transmitting end (Tx) 414 of the memory unit 400 (the fact that no data is output is schematically shown using a dotted line).

  In this figure, a plurality of optical interconnects are formed via two couplers 30 and 40. Each coupler is an X-type coupler, includes both ends (one end, the other end), can transmit light in one direction from one end side to the other end side, and both end sides In which two or more branches of the optical interconnect are included.

  From such a property and the connection relation of the optical interconnect, any X-type coupler has the property as an optical X-type coupler derived from the unidirectionality of light, and one coupler 30 of the two optical couplers is It serves as a splitter, and the other coupler 40 of the two optical couplers serves as a combiner.

  The coupler 30 serving as a splitter includes both ends (one end and the other end), includes a first branch 31 and a second branch 34 at one end, and a third branch 32 at the other end. And a fourth branch 33.

  The coupler 40, which serves as a combiner, includes both ends (one end and the other end), includes a first branch 41 and a second branch 43 at one end, and a third branch 44 at the other end. And a fourth branch 42.

  What should be noted here is that from the fourth branch 42 of the coupler 40, which serves as a combiner, to the second branch 34 of the coupler 30, which serves as a splitter. The point is that a “loop” is formed that connects (connects).

  Data read from the transmission end (Tx) 214 is interconnected so as to be fed back to the reception end (Rx) 212 and the reception end (Rx) 412.

  That is, thanks to the existence of this “loop”, the data read from the memory device is interconnected so as to be fed back to the input channels (Rx) of the IO controllers 210 and 410, and the newly added memory unit. By writing to, the memory can be copied (copied).

  In other words, information that has been discarded in the fourth branch 42 of the coupler 40 in the prior art is reclaimed by a loop. Furthermore, it can be said that such a characteristic interconnect wiring pattern itself takes over the function of the IO controller.

FIG. 3 is a schematic diagram showing three types of states (operation modes) and transitions between these states according to the present invention. Specifically, according to the read command or write command that comes from the host (the sending end),
(1) A state in which data is read from the memory in response to a read command, and data is written to the memory in response to a write command (Active Mode).
(2) A state that does not respond to a read command but only executes data writing to a memory in response to a write command (Snoop Mode), and
(3) A state in which data is written to the memory in response to the write command, and the read command is converted to the write command and the data is written to the memory (Recovery Mode).
About (at least) three types of states
Selective transition is possible between the state of (1) and (2) and between the state of (2) and (3).

  In FIG. 3, since the state (1) responds to both the read command and the write command, the initial is expressed as (R / W). . Since the state of (2) does not respond to the read command, the non-response is expressed in the form of (− / W) using the symbol (−). The state (3) is expressed in the form of (W / W) because the read command is converted into the write command.

  The selective transition between the state (1) and the state (2) can be realized through the mode switch 16 and the network interface 18 shown in FIG.

  A selective transition between the state (2) and the state (3) can also be realized through the mode changeover switch 16 and the like in FIG. For example, the state of (3) also transitions to the state of (3) (by controlling on / off of the mode changeover switch 16 etc. in FIG. 1) as a derivative form of the same Snoop Mode as the state of (2). By doing so, it is possible to realize an ON state in which Recovery is possible.

  In FIG. 3, as an additional state, (4) a state of initializing (POR: PowerOn Reset) and (5) an inactive state are also written. Usually, it is not enough to wire the host etc. to the memory unit, but it is possible to initialize and decide the address space or set the initial state of each memory unit on the assumption of the connection relationship This is to be done. However, this additional state (4) is not an essential configuration in the technical idea of the present invention, and the entire operation from the point when at least three states (operation modes) are set through initialization. Is feasible. Next, when a failure occurs during operation in each of the states (1), (2), and (3), the memory unit enters the state (5). When the memory unit is restored, after going through the state (4), the state (2) is reached after synchronizing with the memory unit operating in the state (1) in (3). When a failure occurs in the memory unit in the state (1), the memory unit in the state (2) immediately transitions to the state (1).

  FIG. 4 is a diagram showing a timing chart of a memory recovery operation in a state where the host and two memory units are electrically connected as a conventional technique. If a “loop” is not formed as in the prior art, the data read by the read command will once return to the host, and after that process, the write command is issued from the host again. It goes through the process. This is called RMW (Read-Modify-Write). The clock (Clock) controls the timing of a command and data read in response to the command. In the process of transmitting from the host to the IO controller to the memory device, at least one clock is required. However, this timing chart does not function (cannot be operated), and is merely an example. .

  FIG. 5 is a diagram showing a timing chart of a memory recovery operation in a state where the host and two memory units are optically connected (through a “loop” without returning to the host) according to the present invention. is there. Since the “loop” of the present invention is formed, a read command can be simultaneously transmitted to two IO controllers without returning to the host, and the read data can be transmitted at a faster timing (there is no need to return to the host). ) Can be sent to the other IO controller. In other words, writing to the new memory becomes possible during the Read cycle by the read command, and as a result, the Write cycle (separate time for issuing the write command) by the IO controller is unnecessary. Therefore, even if roughly estimated, the recovery time can be halved.

  FIG. 6 is a diagram showing an optical link creation method according to the present invention. In this example, the optical link is employed as the optical interconnect in FIG. 2, and the same reference numerals as those in FIG. 2 are given. Host Out is connected to the transmission end of the host. As can be easily imagined from the final form created from Step 1 to Step 2, Host In is connected to the receiving end (Rx) of the host. OAM 0 In is connected to the receiving end (Rx) 212 of the memory unit 200. OAM0 Out is connected to the transmission end (Tx) 214 of the memory unit 200. OAM1 In is connected to the receiving end (Rx) 412 of the memory unit 400. OAM1 Out is connected to the transmission end (Tx) 414 of the memory unit 400. OAM is an abbreviation for Optical Attachment to Memory (Unit).

  The delay timing of the optical link can be made uniform by aligning the lengths of the three fibers, the length to the fusion point, and the like. In Step 1 (Step 1), the three fibers are placed at two locations (a first location at a first distance from one end of the fiber, and a second location (which is different from the first location)). The optical link is completed only by fusing at a second fusing point. Patent Document 3 shows a general technical level for realizing the fusion. In actual application to the present invention, as shown in Step 2 (Step 2), a “loop” formed from the fourth branch 42 of the coupler 40 to the second branch 34 of the coupler 30 is mainly used. It can be applied to the connection relationship corresponding to the optical interconnect in FIG. It should be noted that Patent Document 3 does not disclose that the three fibers are bundled by shifting the positions where the fibers are fused in this way.

  FIG. 7 is a diagram showing a connection example further developed according to the present invention. First, compared with FIG. 2, the connection relationship is configured in a layered manner. In addition, as host, PHY (physical layer layer, first layer) on the host side is duplicated with Master (abbreviation of M or 0) and Slave (abbreviation of S or 1) to increase redundancy. Yes. The loop is configured as a memory-side coupler. Here, an example of one-stage drop is shown, but it is also possible to adapt to multiple stages. In this wiring example, the memory capacity is doubled by using two memory units by dropping.

  FIG. 8 is a diagram showing a method of creating an optical link that realizes the connection of the advanced configuration of FIG. 7 according to the present invention. The creation of the optical link described in FIG. 6 may be developed.

10, 210, 410 IO controller 12, 212, 412 Reception end (write port)
14, 214, 414 Transmission end (readout port)
16 mode selector switch 18 network interface 20, 220, 420 memory device 22 input 24 output 30 coupler (splitter) second coupler 31 (one end) first branch 32 (other end) third branch 33 (others) Fourth branch 34 (at one end) Second branch 40 (at one end) Coupler (combiner) First coupler 41 (at one end) First branch 42 (at the other end) Fourth branch 43 (at one end) 2 branch 44 (at the other end) 3rd branch 50 Host 100, 200, 400 Memory unit

Claims (2)

An optical link manufacturing method comprising:
Providing a first fiber, a second fiber, and a third fiber of the same length;
The first part located at a first distance from one end of the first fiber and the first part located at a first distance from one end of the second fiber are fused together as parts having the same length. (30) steps;
A second location that is different from the first location of the second fiber and is at a second distance from one end of the second fiber and a second distance from one end of the third fiber; (40) the step of fusing the second part in the part as a part having the same length;
Aligning one end (31) of the first fiber and one end (44) opposite the one end of the third fiber as the end of HostOut and the end of HostIn;
Aligning one end (32) opposite the one end of the first fiber and one end (41) of the second fiber as the end of OAM0In and the end of OAM0Out;
Aligning one end (33) opposite the one end of the second fiber and one end (43) of the third fiber as the end of OAM1In and the end of OAM1Out;
Having
Said method. Each includes both ends, can transmit light in one direction from one end side to the other end side, and includes two branches of the optical interconnect on one end side, and the other end side A first coupler (40) and a second coupler (30) comprising two branches of an optical interconnect at
In the first coupler (40), the second fiber and the third fiber are connected in an X shape,
In the second coupler (30), the first fiber and the second fiber are connected in an X shape,
The fourth branch (42) at the other end of the first coupler (40) is connected as a second fiber to the second branch (34) at one end of the second coupler (30), and
One end (31) of the first fiber and one end (44) opposite to one end of the third fiber are aligned as the end of HostOut and the end of HostIn,
One end (32) opposite to one end of the first fiber and one end (41) of the second fiber are aligned as the end of OAM0In and the end of OAM0Out,
One end (33) opposite to one end of the second fiber and one end (43) of the third fiber are aligned as the end of OAM1In and the end of OAM1Out,
Optical link.

Images