JP5228816B2 - Data relay device and data processing system - Google Patents

Description

  The present invention relates to a data relay device that relays data between two control devices, and relates to a data relay device that provides data received from one control device to the other control device.

  The in-vehicle laser sensor scans the area around the vehicle and scans the laser beam, and the complex matrix based on the distance data obtained from the time difference between the peak of the irradiated laser beam and the peak of the reflected light of the laser beam By performing calculations and the like, the position and shape of objects around the host vehicle are detected. In order to precisely detect the position and shape of objects around the vehicle with this in-vehicle laser sensor, the laser beam is scanned at short intervals, and a complex matrix calculation based on a large amount of distance data obtained by the scan Etc., and the processing load for performing such an operation is very large. Therefore, a CPU (hereinafter also referred to as a master CPU) that performs overall control of the on-board laser sensor and a high-speed dedicated CPU (hereinafter also referred to as a slave CPU) that perform the above-described calculation are provided, and a plurality of CPUs are mounted on the vehicle. The structure of controlling the laser sensor for the vehicle can be considered.

  In addition, when such a configuration is provided, for example, a dedicated IC for generating the distance data provides a large amount of distance data to the slave CPU, and a large amount of calculation results generated by the slave CPU. Data needs to be transmitted from the slave CPU to the master CPU. Therefore, for example, an FPGA (Field Programmable Gate Array) having a DPRAM (Dual Port Ram) is provided as a data relay device, and by performing DMA transfer via the DPRAM, distance data is provided to the slave CPU, and the slave CPU The calculation result data may be transmitted from to the master CPU.

By the way, a slave CPU that performs a matrix operation or the like having a very large processing load in this manner often uses a CPU that generates a larger amount of heat than the master CPU, and the slave CPU runs away due to heat generation compared to the master CPU. There is a high risk that In particular, the temperature inside the vehicle may become severe, and there is a risk that thermal runaway may be promoted. Therefore, it is necessary to monitor the operation of the slave CPU. Here, Patent Document 1 describes a device that detects an abnormality of an in-vehicle unit. This device transmits test data to the in-vehicle unit, receives a response to the test data from the in-vehicle unit, and performs an abnormality determination for the in-vehicle unit based on the received response.
Japanese Patent Laid-Open No. 2005-199951

  The invention described in Patent Document 1 is applied to the in-vehicle laser sensor having the master CPU and the slave CPU described above. The master CPU transmits test data to the slave CPU, and the slave CPU responds to the test data. Based on the above, the abnormality determination of the slave CPU may be performed. However, having such a configuration increases the processing load on the master CPU.

  The present invention has been made in view of the above problems. For example, the present invention provides and provides data to a predetermined control device such as a CPU such as the data relay device mounted on the above-described on-board laser sensor. It is invention regarding the apparatus etc. which transfer the production | generation data produced | generated in the said control apparatus based on the performed data to another control apparatus. An object of the present invention is to provide a data relay device or the like that can perform an abnormality determination on the operation of a predetermined control device while suppressing an increase in the processing load of these control devices.

The data relay device according to claim 1, which has been made to solve the above problem, provides processing data used for predetermined processing by the first control device to the first control device, and The generated data generated by the predetermined process is received from the first control device, and the received generated data is provided to the second control device. The control device may be, for example, a CPU or a control circuit having a CPU, or may be a dedicated circuit for performing predetermined processing without using the CPU. The data relay device receives processing data from the first control device and processing data providing means for providing processing data to the first control device, and receives the generated data from the first control device. Transfer means for providing to the apparatus, and first test data providing means for providing the first test data to the first control apparatus as the processing data. In addition, when the transfer unit receives from the first control device, the data relay device receives the generated data generated by the predetermined processing performed using the first test data provided as the processing data. A first determination unit that performs an abnormality determination on the first control device based on the received generated data; and a first test data storage unit that stores the first test data. .
The processing data providing means has a first dual port RAM in which one port is connected to the first control device, and the processing data stored in the first dual port RAM. By reading from the first control device, processing data is provided to the first control device.
The transfer means includes a second dual port RAM in which one port is connected to the first control device and the other port is connected to the second control device. The generated data is written to the second dual-port RAM by writing the generated data to the second dual-port RAM by the first control device and the generated data written to the second dual-port RAM by the first control device. The generation data is provided to the second control device by reading from the second control device.
The first test data providing means replaces the processing data stored in the first dual-port RAM of the processing data providing means with respect to the first control device, instead of the first test data providing means. By reading the first test data stored in the data storage means, the first test data is provided as processing data to the first control device.

  In other words, the data relay device provides the first test data as processing data to the first control device. In the first control device that has received the first test data as processing data, a predetermined process based on the first test data is performed to generate generation data. Then, the data relay device receives the generated data generated by the predetermined process based on the first test data from the first control device, and determines the abnormality for the first control device based on the received generated data. I do. At this time, the data relay device stores, for example, the abnormality determination data in advance, and compares the abnormality determination data with the generated data generated based on the first test data. You may perform abnormality determination about a control apparatus.

  By having such a configuration, the first control device and the second control device can perform abnormality determination for the first control device without newly providing dedicated processing for abnormality determination. . Further, the abnormality determination for the first control device can be performed without executing the abnormality determination process for the first control device by the second control device. Therefore, the data relay device according to claim 1 can perform abnormality determination for the first control device while suppressing an increase in processing load of the first control device and the second control device as much as possible.

In addition, the data relay device makes an abnormality determination based on the generated data generated based on the first test data as described above, and simultaneously with the abnormality determination for the first control device, It is also possible to perform an abnormality determination on the communication state with one control device.
In the data relay device according to the first aspect, the dual port RAM is used to provide data to the first control device and transfer data from the first control device to the second control device.
For this reason, the data relay device provides a large amount of processing data to the first control device in a short time or generates a large amount of generated data generated by the first control device in a short time. It can be transferred to the control device.
Note that the first control device may read the processing data stored in the first dual-port RAM or write the generated data to the second dual-port RAM by performing DMA transfer. good. Further, the second control device may read the generated data written in the second dual port RAM by performing DMA transfer.
According to a second aspect of the present invention, the data relay device receives processing data from the first control device and processing data providing means for providing processing data to the first control device. Transfer means for providing the first control data to the second control device, and first test data providing means for providing the first test data as processing data to the first control device. Further, when the transfer means receives from the first control device the generated data generated by the predetermined processing performed using the first test data provided as the processing data, the received generated data Based on the first determination means for determining the abnormality of the first control device, and the second test data, which is data used for the abnormality determination of the data relay device by the second control device, transfer means Includes second test data providing means for providing the second control device with the generated data received from the first control device.
Even with such a configuration, it is possible to make an abnormality determination for the first control device while suppressing an increase in the processing load of the first control device and the second control device as much as possible. Abnormality determination regarding the communication state between the device and the first control device can also be performed.
In addition, the second control device can perform an abnormality determination on the communication state between the data relay device and the second control device, for example. The second control device stores, for example, abnormality determination data in advance in a ROM or the like connected to the second control device, and compares the abnormality determination data with the second test data. Accordingly, the abnormality determination for the data relay device may be performed.
According to a third aspect of the present invention, the data relay device stores the second test data that is data used for abnormality determination regarding the data relay device by the second control device. The test data storage means may be further provided. In addition, the data relay device stores the second test data stored in the second test data storage unit in place of the generated data stored in the second dual port RAM of the transfer unit. Second test data providing means for providing the second test data to the second control device as generated data received by the transfer means from the first control device by reading the second test data. May be further provided.
Even if it has such a structure, the 2nd control apparatus can perform abnormality determination about the communication state between a data relay apparatus and a 2nd control apparatus, for example.

  The data relay device may provide the first test data to the first control device at the following timing.

That is, as described in claim 6 , the data relay device performs the first control with the first test data as processing data to the first test data providing means at regular timing. In addition, the first test data providing unit receives the provision instruction from the instruction unit, and receives the first test data as the processing data. You may provide to one control apparatus.

  By doing so, the data relay device can make an abnormality determination for the first control device at a predetermined cycle. For this reason, after an abnormality occurs in the first control device, it is possible to reliably detect the abnormality in the first control device within the predetermined period at the longest.

According to a seventh aspect of the present invention, the instruction means sends the first test data to the first test data providing means in response to an instruction from the second control device. A provision instruction which is an instruction to provide to the first control device may be performed.

  By doing so, the second control device can make an abnormality determination for the first control device at an optimum timing.

According to an eighth aspect of the present invention, the instruction means sends the first test data as processing data to the first test data providing means in response to an instruction from the user. You may perform the provision instruction | indication which is an instruction | indication of providing to a control apparatus.

  By doing so, for example, when the user feels an abnormality related to the operation of the second control device, it is possible to make an abnormality determination for the second control device. Therefore, the convenience of the data relay device can be improved.

Further, as described in claim 1 or the like, when the processing data is provided to the first control device by the first dual port RAM, some abnormality occurs in the first control device. There is a possibility that the processing data may not be read from the first dual port RAM. However, the data relay device described in claim 1 and the like cannot detect such an abnormality.

Therefore, the data relay device described in claim 4 is configured so that the first control device first stores the first processing data after the new processing data is stored in the first dual port RAM included in the processing data providing means. The apparatus further includes second determination means for determining abnormality of the first control device based on the time until the processing data stored in the dual port RAM is read.

  By doing so, the data relay device regards that the first control device has failed when the processing data stored in the first dual port RAM is not read by the first control device. be able to.

In addition, as described in claim 1 or the like, when the generated data is received from the first control device by the second dual port RAM, some abnormality occurs in the first control device, and the second dual port RAM There is a possibility that the generated data is not written to the port RAM. However, the data relay device described in claim 1 and the like cannot detect such an abnormality.

Therefore, in the data relay device described in claim 5, after the processing data stored in the first dual port RAM of the processing data providing means is read by the first control device, , Based on the time until the generated data generated in the predetermined processing performed using the processing data by the first control device is written in the second dual-port RAM of the transfer means. The apparatus further includes third determination means for performing abnormality determination on one control device.

  By doing so, the data relay device can be regarded as having an abnormality in the first control device when the generated data is not written to the second dual port RAM by the first control device.

  Further, the data relay device may notify the second control device of the abnormality determination result for the first control device.

That is, as described in claim 9 , the determination means may notify the second control device of the result of the abnormality determination for the first control device.

  By so doing, the second control device can detect an abnormality that has occurred in the first control device.

  In addition, the data relay device may have the following configuration.

That is, as described in claim 10 , the data relay device may be configured by a dedicated circuit realized by an FPGA.

  By having such a configuration, the circuit configuration of the data relay device can be easily changed, and the data relay device can be efficiently developed.

Further, a data relay device according to claim 1 to claim 10, the first control device according to any one of claims 1 to 10, any one of claims 1 to 10 It may be distributed in the market as a data processing system having the second control device described in 1). Even when the data relay device, the first control device, and the second control device are configured as such a data processing system, the above-described effects can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments of the present invention are not limited to the following embodiments, and various forms can be adopted as long as they belong to the technical scope of the present invention.

[About operation overview]
First, the outline | summary of operation | movement of the vehicle-mounted laser sensor in this embodiment is demonstrated using the explanatory drawing described in FIG.

  FIG. 1A shows an explanatory diagram of the laser irradiation direction by the in-vehicle laser sensor. As shown in FIG. 1A, the in-vehicle laser sensor has a right limit direction 110 that is a direction diagonally forward to the right of the host vehicle from a left limit direction 100 that is the diagonally forward direction of the host vehicle. Then, the laser beam is irradiated while shifting the direction at a predetermined angle. When the laser irradiation direction reaches the right limit direction 110, the irradiation direction is returned to the left limit direction 100, and the laser beam is irradiated again in the right limit direction 110.

  Further, when the on-vehicle laser sensor sets the direction of the laser light, the intensity of the laser light peaks at a predetermined timing. Based on the peak time difference between the timing when the intensity of the irradiated laser beam reaches its peak and the timing when the intensity of the reflected light of the laser beam peaks, the distance between the host vehicle and the object ahead of the host vehicle is detected. To do. FIG. 1B shows an explanatory diagram regarding this peak time difference.

  When an object is present in front of the host vehicle, the laser beam is reflected by the vehicle laser sensor and is reflected by the object, and the reflected light is detected by the light receiving circuit of the vehicle laser sensor. The light receiving circuit converts the detected reflected light into an electrical signal corresponding to the intensity and outputs the electrical signal. The electric signal output from the light receiving circuit is the light receiving signal in the explanatory diagram of FIG. 1B, and a reflection peak appears at a timing corresponding to the distance between the host vehicle and the reflecting object. . Then, based on the time difference between the timing of the reflection peak and the timing of the peak of the irradiated laser beam, the distance to the object is calculated.

  Since laser light is a kind of light, if the speed of light is C, the distance from the vehicle-mounted laser sensor to the reflective object is calculated as distance = C × peak time difference / 2 (the peak time difference is the round trip time). So, one-way distance is divided by 2). The measurement of the peak time difference and the calculation of the distance are executed by a distance measurement processing unit in the FPGA. Since the laser beam travels back and forth at a distance of about 15 cm in a time of 1 ns, it is required to measure the peak time difference with a time resolution shorter than 1 ns in order to obtain a vehicle-mounted laser sensor having a distance measurement resolution of 15 cm or more. The For this reason, the peak time difference is measured by a dedicated IC such as an FPGA.

  In addition to the method described above, there is a method for measuring the distance using the phase difference between the irradiated laser beam and the reflected light, but this method can measure only a distance of about several meters. However, an in-vehicle laser sensor is required to detect an object at a distance of 50 m or more. For this reason, the in-vehicle laser sensor according to the present embodiment employs a method of calculating the distance based on the peak time difference.

[Description of configuration]
(1) Configuration of In-Vehicle Laser Sensor FIG. 2 is a block diagram showing the configuration of the in-vehicle laser sensor 1. The in-vehicle laser sensor 1 includes an FPGA 10, a master control unit 20, a light emitting circuit 30, a light emitting scanner 40, a light receiving circuit 50, an AD converter 60, and a slave control unit 70. The FPGA 10, the master control unit 20, the light emitting circuit 30, the light emitting scanner 40, the light receiving circuit 50, and the AD converter 60 are mounted on the same substrate. The slave control unit 70 is mounted on a base different from the FPGA 10 or the like, and the slave control unit 70 and the FPGA 10 are connected by a cable.

  The FPGA 10 is a part that generates distance data based on the above-described peak time difference and provides the generated distance data and the like to the slave control unit 70. Further, the FPGA 10 is a part that transfers the calculation data generated based on the distance data by the slave control unit 70 to the master control unit 20. The FPGA 10 is connected to the master control unit 20 and the AD converter 60.

  The master control unit 20 is a part that controls the entire vehicle-mounted laser sensor 1. Specifically, the master control unit 20 controls the light emitting circuit 30 and the light emitting scanner 40 and the light receiving circuit 50. Further, the calculation data generated by the slave control unit 70 is acquired via the FPGA 10, and information based on the acquired calculation data is output to the outside.

  The light emitting circuit 30 is a part that is irradiated with laser light by a laser oscillator (not shown).

  The light emitting scanner 40 controls the irradiation direction and intensity of the laser light from the light emitting circuit 30, and scans the laser light in the range from the left limit direction 100 to the right limit direction 110 in the explanatory diagram shown in FIG. It is a part to perform. Specifically, the light emitting scanner 40 causes the light emitting circuit 30 to emit laser light while shifting the direction at a predetermined angle from the left limit direction 100 to the right limit direction 110. When the laser irradiation direction reaches the right limit direction 110, the irradiation direction is returned to the left limit direction 100, and the laser beam is irradiated again in the right limit direction 110. The light-emitting scanner 40 scans from the left limit direction 100 to the right limit direction 110 as one cycle, and repeats the cycle while the host vehicle is operating.

  The light receiving circuit 50 is a part that receives the reflected light of the laser light and generates a received light signal that is an analog electric signal based on the reflected light. The light receiving circuit 50 generates a light receiving signal having a voltage corresponding to the intensity of the received reflected light and outputs the light receiving signal to the AD converter 60.

  The AD converter 60 is a part that acquires a light reception signal from the light reception circuit 50 and performs AD conversion on the acquired light reception signal. The AD converter 60 outputs the digital data of the received light signal generated by AD conversion to the FPGA 10.

  The slave control unit 70 is a part that performs calculations for specifying the position and shape of an object ahead of the host vehicle based on the distance data acquired from the FPGA 10. Note that the processing load for performing these operations is very large, and the slave controller 70 operates with a clock faster than the master controller 20 in order to speed up the processing. The slave control unit 70 transfers the calculation data generated by the calculation to the master control unit 20 via the FPGA 10.

(2) Configuration of FPGA 10 Next, the configuration of the FPGA 10 will be described with reference to the block diagram shown in FIG. The FPGA 10 includes a distance measurement processing unit 11, a master reception control unit 12, a first DPRAM 13a, a second DPRAM 13b, a time check unit 14, a slave transmission control unit 15a, a slave test data storage unit 15b, a slave reception control unit 16a, It has a slave determination data storage unit 16b, an abnormality determination instruction unit 17, a master transmission control unit 18a, and a master test data storage unit 18b. The master reception control unit 12, the master transmission control unit 18 a, the master CPU 21 of the master control unit 20, the RAM 22, and the DMA control unit 23 are connected to the master control unit bus line 24. In addition, the time check unit 14, the slave transmission control unit 15a, the slave reception control unit 16a, the slave CPU 71 of the slave control unit 70, the first RAM 72, the DMA control unit 73, and the second RAM 74 are connected to the slave control unit bus line 75. It is connected.

  The distance measurement processing unit 11 is a part that acquires digital data of a light reception signal from the AD converter 60, generates distance data based on the digital data, and writes the distance data to the first DPRAM 13a.

  The master reception control unit 12 is a part that controls the writing of data to the first DPRAM 13a. The master reception control unit 12 writes the distance data received from the distance measurement processing unit 11 into the first DPRAM 13a, and the calculation parameter received from the master control unit 20 via the master control unit bus line 24. Write to.

  The first DPRAM 13a is a well-known dual-port RAM having two ports, a first port 13a-1 and a second port 13a-2, and capable of writing and reading data from each port. The first port 13a-1 of the first DPRAM 13a is connected to the master reception control unit 12, and the second port 13a-2 is connected to the slave transmission control unit 15a.

  The second DPRAM 13b is a well-known dual-port RAM having two ports, a first port 13b-1 and a second port 13b-2, in which data can be written and read from each port. The first port 13b-1 of the second DPRAM 13b is connected to the master transmission control unit 18a, and the second port 13b-2 is connected to the slave reception control unit 16a.

  The time check unit 14 is a part for determining whether or not the access to the DPRAM is normally performed by the slave control unit 70. Based on the data transmission preparation completion notification signal from the master reception control unit 12, the time check unit 14 specifies the timing when the writing of the distance data or the like to the first DPRAM 13a is completed. Further, based on the signal from the slave control unit bus line 75, the access to the DPRAM by the slave control unit 70 is detected.

  The slave transmission control unit 15a is a part that controls the reading of data from the first DPRAM 13a.

  The slave test data storage unit 15b is a part that stores slave test data.

  The slave reception control unit 16a is a part that controls the writing of data to the second DPRAM 13b.

  The slave determination data storage unit 16b is a part that stores slave determination data.

  The abnormality determination instruction unit 17 is a part that instructs the slave transmission control unit 15a, the slave reception control unit 16a, and the master transmission control unit 18a to perform abnormality determination on the slave control unit 70 at a predetermined timing. . The abnormality determination instruction unit 17 may, for example, give an instruction to make an abnormality determination every time a predetermined time elapses, or give an instruction to make an abnormality determination in response to an instruction from the master control unit 20. You can go. Further, for example, the abnormality determination instruction unit 17 may issue an instruction to perform abnormality determination when it is detected that a predetermined operation has been performed on the in-vehicle laser sensor 1 from the user.

  The master transmission control unit 18a is a part that controls the reading of data from the second DPRAM 13b.

  The master test data storage unit 18b is a part that stores master test data.

(3) Configuration of Master Control Unit 20 Next, the configuration of the master control unit 20 will be described with reference to the block diagram shown in FIG. The master control unit 20 includes a master CPU 21, a RAM 22, and a DMA control unit 23. These parts are connected to the master reception control unit 12 and the master transmission control unit 18a of the FPGA 10 by the master control unit bus line 24.

  The master CPU 21 is a part that performs control of the master control unit 20 and various calculations in accordance with a program loaded in a ROM (not shown) or RAM 22.

  The RAM 22 is a storage device used as a main memory or the like that is directly accessed from the CPU 21. The RAM 22 is loaded with programs such as the OS and various applications, and the results of various calculations by the CPU 21 are also stored in the RAM 22.

  The DMA control unit 23 is a part that performs DMA transfer between the RAM 22 and the first DPRAM 13 a and the second DPRAM 13 b of the FPGA 10.

(4) Configuration of Slave Control Unit 70 Next, the configuration of the slave control unit 70 will be described with reference to the block diagram shown in FIG. The slave control unit 70 includes a slave CPU 71, a first RAM 72, a DMA control unit 73, and a second RAM 74. These parts are connected to the time check unit 14, the slave transmission control unit 15a, the slave reception control unit 16a, and the slave control unit bus line 75 of the FPGA 10.

  The slave CPU 71 is a part that performs control of the slave control unit 70 and various calculations in accordance with a program loaded in a ROM (not shown), the first RAM 72, and the second RAM 74.

  The first RAM 72 and the second RAM 74 are storage devices used as a main memory or the like accessed directly from the CPU 71. Programs such as the OS and various applications are read into these RAMs, and the results of various calculations by the CPU 71 are also stored in these RAMs.

  The DMA control unit 73 is a part that performs DMA transfer between the first RAM 72 and the second RAM 74 and the first DPRAM 13 a and the second DPRAM 13 b of the FPGA 10.

[Description of operation]
Next, the operation of the in-vehicle laser sensor 1 will be described. As already described, the in-vehicle laser sensor 1 scans the laser beam forward of the host vehicle after the start of operation of the host vehicle, and detects the position, shape, etc. of an object existing in front of the host vehicle based on reflected light To do. This process is generally performed in the following steps.
(A) The master control unit 20 scans the laser beam, and the received light signal of the reflected light is input to the FPGA 10.
(B) The FPGA 10 generates distance data based on the peak of the received light signal of the reflected light, and provides the generated distance data and the like to the slave controller 70. Here, the FPGA 10 provides slave test data instead of distance data or the like at a predetermined timing.
(C) The slave control unit 70 performs a calculation for specifying the position, shape, and the like of an object existing in front of the host vehicle based on the distance data and the like, and provides calculation data generated by the calculation to the FPGA 10. The FPGA 10 that has received the calculation data provides the calculation data to the master control unit 20. Here, when the FPGA 10 receives the calculation data based on the slave test data, the FPGA 10 performs an abnormality determination on the slave control unit 70 based on the data, and further performs master control on the master test data instead of the calculation data. Provided to part 20.

  Here, each of the processes executed by the master control unit 20, the slave control unit 70, and the FPGA 10 in order to realize the above process will be described.

  In the present embodiment, an in-vehicle laser sensor is taken as an example, and a process for performing abnormality determination on a control device such as the slave control unit 70 will be described. However, it should be noted that the present invention is not applicable only to an in-vehicle laser sensor.

(1) Processing executed by the master control unit 20 The master control unit 20 performs laser control processing, DMA interrupt processing, and timeout interrupt processing in order to realize the above-described processing (a) to (c). The

(1-1) Laser Control Processing and DMA Interrupt Processing First, laser control processing will be described using the flowchart shown in FIG. This process is started when the driving of the host vehicle is started. Moreover, this process is complete | finished when the driving | operation of the own vehicle is complete | finished.

  In S <b> 205, the master control unit 20 causes the light emitting scanner 40 and the light emitting circuit 30 to scan one cycle of the laser light and causes the light receiving circuit 50 to receive the reflected light of each irradiated laser light. The light receiving circuit 50 that receives the reflected light outputs a light reception signal to the AD converter 60, and the AD converter 60 converts the light reception signal into digital data and outputs the digital data to the distance measurement processing unit 11 in the FPGA 10. . The distance measurement processing unit 11 generates distance data based on the digital data, and writes the generated distance data from the first port 13a-1 to the first DPRAM 13a via the master reception control unit 12. When the writing of all the distance data generated by the one-cycle scan is completed, the distance measurement processing unit 11 notifies the master control unit 20 of the completion of the writing of the distance data by a distance data writing end notification signal.

  Subsequently, in S <b> 210, the master control unit 20 determines whether or not a distance data write end notification has been received from the distance measurement processing unit 11. If the write end notification is received (S210: Yes), the master control unit 20 proceeds to S215. If the write end notification is not received (S210: No), the process of S210 is executed again. To do.

  In S215, the master control unit 20 causes the DMA control unit 23 to start DMA transfer to the first DPRAM 13a for the operation parameters stored in the RAM 22. Specifically, the DMA control unit 23 accesses the first DPRAM 13a from the first port 13a-1 via the master reception control unit 12, and the calculation parameters stored in the RAM 22 are transferred to the first DPRAM 13a. Perform DMA transfer. Then, the process proceeds to S220.

  In S220, the master control unit 20 determines whether or not the DMA transfer is completed based on the state of the DMA transfer end flag (details will be described later). When the DMA transfer is completed (S220: Yes), the master control unit 20 clears the DMA transfer end flag and shifts the process to S225. If the DMA transfer has not ended (S220: No), the master control unit 20 executes the process of S220 again.

  In S225, the master control unit 20 waits until the calculation based on the distance data or the like by the slave control unit 70 ends and the calculation data is written in the second DPRAM 13b. Specifically, when the status of the read request notification signal that is a 2-bit signal is other than “11” (S225: No), the master control unit 20 finishes writing the operation data to the second DPRAM 13b. The process proceeds to S230.

  In S230, the master control unit 20 causes the DMA control unit 23 to start DMA transfer to the RAM 22 for the operation data stored in the second DPRAM 13b. Specifically, the DMA control unit 23 accesses the second DPRAM 13b from the first port 13b-1 via the master transmission control unit 18a, and performs DMA transfer of the operation data stored in the second DPRAM 13b. .

  Subsequently, in S235, the master control unit 20 determines whether the DMA transfer is completed based on the state of the DMA transfer end flag. When the DMA transfer is completed (S235: Yes), the master control unit 20 clears the DMA transfer end flag and shifts the process to S240. If the DMA transfer has not ended (S235: No), the master control unit 20 executes the process of S235 again.

  In S240, the master control unit 20 checks the state of the read request notification signal, and when this signal is “00” (when the abnormality determination for the slave control unit 70 is not performed) (S240: Yes). , The process proceeds to S245. When this signal is other than “00” (S240: No), the master control unit 20 shifts the process to S250.

  In S245, the master control unit 20 performs processing such as notifying the user of an object existing ahead of the host vehicle based on the calculation data. Then, the process proceeds to S205 in order to scan the laser beam and receive the reflected beam again.

  In S250, where the state of the read request notification signal is other than “00”, the master control unit 20 checks the state of the read request notification signal again. When this signal is “01” (when the abnormality determination for the slave control unit 70 is performed and the slave control unit 70 is determined to be normal) (S250: Yes), the master control unit 20 performs the process in S255. Transition. Further, when this signal is other than “01” (when an abnormality determination is made for the slave control unit 70 and the slave control unit 70 is determined to be abnormal) (S250: No), the master control unit 20 The process proceeds to S265.

  In S255, the master control unit 20 checks whether or not the determination data stored in the ROM (not shown) matches the master test data transferred to the RAM 22. If these data match, it is determined that the communication state between the master control unit 20 and the FPGA 10 is normal (S260: Yes), and the process proceeds to S280. If these data do not match (S260: No), the process proceeds to S265.

  In S <b> 265, the master control unit 20 updates the number of occurrences of abnormality in the operation of the slave control unit 70 and the communication state between the slave control unit 70, the FPGA 10, and the master control unit 20. In addition, the master control unit 20 specifies the current time by a clock function or the like, and executes the specification of the current temperature by a temperature sensor (not shown), and the current time, the current temperature, etc. As shown in FIG.

  In S270, the master control unit 20 determines whether or not the stop condition of the own device is satisfied based on the number of occurrences of abnormality. Specifically, for example, when an abnormality is detected a predetermined number of times continuously, or when abnormality determination is performed continuously over a plurality of cycles, an abnormality is detected a predetermined number of times, or within a certain time For example, when the abnormality detected in the above reaches a predetermined number of times, it may be considered that the stop condition is satisfied. When the stop condition is satisfied (S270: Yes), the master control unit 20 shifts the process to S275. When the stop condition is not satisfied (S270: No), the master control unit 20 shifts the process to S280.

  In S275, the master control unit 20 notifies the user of the occurrence of abnormality via a voice output unit (not shown), etc., and the vehicle-mounted laser sensor 1 is stopped and the process is terminated. After the vehicle-mounted laser sensor 1 is in a stopped state, for example, when the device is reset by turning on the power of the device or operating a restart switch (not shown), the front side of the vehicle The processing for detecting the position, shape, etc. of the object existing in the object may be resumed.

  In S280 that is shifted when the result of the abnormality determination is normal or when the stop condition is not satisfied, the master control unit 20 performs an alternative process when the abnormality determination is performed. Specifically, for example, processing such as notifying the user of an object existing ahead of the host vehicle may be performed based on the calculation data in the previous cycle. Then, the process proceeds to S205 in order to scan the laser beam and receive the reflected beam again.

  The master control unit 20 and the FPGA 10 are mounted on the same board, and it is considered that there is a low possibility that an abnormality will occur in communication between the master control unit 20 and the FPGA 10. For this reason, the master control unit 20 does not necessarily need to execute the abnormality determination based on the master test data acquired from the FPGA 10, that is, the processes of S255 and S260.

(1-2) DMA Interrupt Processing Next, DMA interrupt processing will be described using the flowchart shown in FIG. This process is started when the DMA transfer by the DMA control unit 23 is completed. When this process is started, the master control unit 20 sets a DMA transfer end flag (S305) and ends this process.

(1-3) Time-out interrupt process Next, the time-out interrupt process will be described with reference to the flowchart shown in FIG. This process is started when the slave controller 70 does not access the first DPRAM 13a or the second DPRAM 13b of the FPGA 10. Specifically, this is a process called as an interrupt process when the state of the timeout notification signal from the time check unit 14 of the FPGA 10 becomes “1”. When this process is activated, the master control unit 20 notifies the user of the occurrence of an abnormality via a voice output unit (not shown) and the vehicle-mounted laser sensor 1 is stopped (S405), and the process ends.

(2) Processing performed in slave control unit 70 In the slave control unit 70, arithmetic processing and DMA interrupt processing are executed in order to realize the above-described processing (a) to (c).

(2-1) Calculation Processing First, calculation processing will be described using the flowchart shown in FIG. This process is started when the driving of the host vehicle is started. Moreover, this process is complete | finished when the driving | operation of the own vehicle is complete | finished.

  In S505, the slave control unit 70 determines whether or not the writing of the distance data and calculation parameters to the first DPRAM 13a has been completed. Specifically, the above determination is made based on the state of the data transmission preparation end notification signal from the master reception control unit 12 of the FPGA 10, and when the state of this signal is “1”, the writing of the distance data or the like is completed. The process proceeds to S510. When the data transmission preparation end notification signal is “0”, the slave control unit 70 executes the process of S505 again.

  In S510, the slave control unit 70 causes the DMA control unit 73 to start DMA transfer to the second RAM 74 for the distance data and calculation parameters stored in the first DPRAM 13a. Specifically, the DMA control unit 73 accesses the first DPRAM 13a from the second port 13a-2 via the slave transmission control unit 15a, and performs DMA transfer such as distance data stored in the first DPRAM 13a. Do.

  Subsequently, in S515, the slave control unit 70 determines whether the DMA transfer is completed based on the state of the DMA transfer end flag (details will be described later). When the DMA transfer is completed (S515: Yes), the slave control unit 70 clears the DMA transfer end flag, and the process proceeds to S520. When the DMA transfer has not ended (S515: No), the master control unit 20 executes the process of S515 again.

  In S520, the slave control unit 70 performs a calculation for specifying the position, shape, and the like of an object ahead of the host vehicle based on the distance data written in the second RAM 74 and the calculation parameter. The calculation data generated by this calculation is stored in the first RAM 72.

  When the calculation is completed, the slave control unit 70 causes the DMA control unit 73 to start DMA transfer of the calculation data stored in the first RAM 72 to the second DPRAM 13b (S525). Specifically, the DMA control unit 73 accesses the second DPRAM 13b from the second port 13b-2 via the slave reception control unit 16a, and performs DMA transfer of the operation data stored in the first RAM 72. .

  Subsequently, in S530, the slave control unit 70 determines whether the DMA transfer is completed based on the state of the DMA transfer end flag. When the DMA transfer ends (S530: Yes), the slave control unit 70 clears the DMA transfer end flag, and proceeds to S505. When the DMA transfer has not ended (S530: No), the master control unit 20 executes the process of S530 again.

(2-2) DMA Interrupt Process The DMA interrupt process similar to that of the master control unit 20 is also executed in the slave control unit 70. This process is started when the DMA transfer by the DMA control unit 73 is completed. When this process is started, the slave control unit 70 sets a DMA transfer end flag and ends this process.

(3) Processing Performed in FPGA 10 Next, operations performed in the FPGA 10 for realizing the above-described processing (a) to (c) will be described with reference to the block diagram shown in FIG. The operation described below is an operation corresponding to any step in the laser control process by the master control unit 20 or the calculation process by the slave control unit 70.

(3-1) About the operation of writing distance data or the like to the first DPRAM 13a In S205 in the laser control processing by the master control unit 20, one cycle of laser light scanning is performed, but the distance measurement processing unit 11 of the FPGA 10 Each time the reflected light of the irradiated laser beam is received, digital data of the received light signal of this reflected light is input. And the distance measurement process part 11 pinpoints the timing when reflected light becomes a peak based on the digital data of a received light signal, and produces | generates distance data based on this timing. Then, the distance measurement processing unit 11 writes the generated distance data from the first port 13a-1 to the first DPRAM 13a via the master reception control unit 12.

  When the generation of distance data for one cycle of scanning is completed, the distance measurement processing unit 11 sets the distance data write completion notification signal to “1”, thereby completing the generation of distance data for the master control unit 20. Notify that it has been done. Receiving this notification, the master control unit 20 performs DMA transfer of calculation parameters to the first DPRAM 13a via the master reception control unit 12. When the DMA transfer of the calculation parameter is completed, the master reception control unit 12 sets the data transmission preparation completion notification signal to “1”, thereby indicating that the DMA transfer of the calculation parameter is completed, and the time check unit 14 and the slave control unit 70. And notify. The distance data write completion notification signal and the data transmission preparation completion notification signal are returned to “0” after a predetermined time has elapsed.

(3-2) Operation for Providing Distance Data etc. to Slave Control Unit 70 In S510 in the arithmetic processing by the slave control unit 70, DMA to the second RAM 74 for the distance data etc. stored in the first DPRAM 13a. Transfer starts. The DMA controller 73 of the slave controller 70 accesses the first DPRAM 13a from the second port 13a-2 via the slave transmission controller 15a, and performs DMA transfer such as distance data stored in the first DPRAM 13a. Do.

  Here, when the slave transmission control unit 15a receives an instruction from the abnormality determination instruction unit 17 to perform abnormality determination on the slave control unit 70, the slave transmission control unit 15a replaces the first DPRAM 13a with the DMA control unit 73. The slave test data storage unit 15b is accessed to execute DMA transfer of the slave test data.

(3-3) Operation for Acquiring Calculation Data from Slave Control Unit 70 In S525 in the calculation processing by the slave control unit 70, the second DPRAM 13b for the calculation data stored in the first RAM 72 of the slave control unit 70 is obtained. DMA transfer to is started. The DMA control unit 73 of the slave control unit 70 accesses the second DPRAM 13b from the second port 13b-2 via the slave reception control unit 16a, and performs DMA transfer of the operation data stored in the first RAM 72. .

  Here, when the slave reception control unit 16a receives an instruction from the abnormality determination instruction unit 17 to perform abnormality determination on the slave control unit 70, the slave reception control unit 16a performs abnormality determination based on the DMA-transferred calculation data. Specifically, the slave reception control unit 16a determines whether the operation data written to the second DPRAM 13b by the DMA transfer matches the slave determination data stored in the slave determination data storage unit 16b. To do. Each time operation data is written to the second DPRAM 13b by the DMA control unit 73, the slave reception control unit 16a sequentially compares the written operation data with the corresponding slave determination data. If all of these data match, it is determined that the slave control unit 70 is normal, and otherwise, it is determined that the slave control unit 70 is abnormal.

Further, the slave reception control unit 16a uses a 2-bit signal to the master transmission control unit 18a or the master control unit 20 when the DMA transfer of the operation data or the abnormality determination for the slave control unit 70 is completed. A certain read request notification signal is set from “11” (no read request) to another value. Specifically, this signal is set as follows according to the presence / absence of abnormality determination and the result of abnormality determination.
“00”: When no abnormality determination is made for the slave control unit 70 • “01”: When an abnormality determination is made for the slave control unit 70 and the determination result is normal • “10”: Abnormality for the slave control unit 70 When the determination is made and the determination result is abnormal. Note that when a predetermined time elapses after the read request notification signal is set, the read request notification signal is set to “11” again.

(3-4) Operation for Providing Calculation Data to Master Control Unit 20 In S230 in the laser control process by the master control unit 20, the calculation data stored in the second DPRAM 13b is transferred to the RAM 22 of the master control unit 20. DMA transfer is started. The DMA control unit 23 of the master control unit 20 accesses the second DPRAM 13b from the first port 13b-1 via the master transmission control unit 18a, and performs DMA transfer of operation data stored in the second DPRAM 13b. .

  Here, the master transmission control unit 18a receives an instruction from the abnormality determination instruction unit 17 to perform the abnormality determination for the slave control unit 70, and if the read request signal is “01”, the master transmission control unit 18a Master test data is provided. At this time, the master transmission control unit 18a causes the DMA control unit 23 to access the master test data storage unit 18b instead of the second DPRAM 13b and execute DMA transfer of the master test data.

  The master test data may be the same data as the slave determination data, for example. In such a case, the FPGA 10 may not include the master test data storage unit 18b, and the master transmission control unit 18a is stored in the slave determination data storage unit 16b with respect to the DMA control unit 23. DMA transfer of slave determination data may be executed.

(3-5) Monitoring of access from the slave control unit 70 to the DPRAM Next, an operation for monitoring the access to the first DPRAM 13a and the second DPRAM 13b by the slave control unit 70 will be described.

  When the writing to the first DPRAM 13a is completed for the distance data and the calculation parameters based on the laser beam scan performed in S205 in the laser control processing by the master control unit 20, the master reception control unit 12 notifies the completion of data transmission preparation. The signal is set to “1”, and the time check unit 14 and the slave control unit 70 are notified that the DMA transfer of the operation parameter has been completed. Upon receipt of this notification, the time check unit 14 starts a timer, and after the writing of the distance data or the like to the first DPRAM 13a is completed, the slave control unit 70 performs DMA such as the distance data stored in the first DPRAM 13a. Measure the time until transfer starts. If the DMA transfer is not started even after a predetermined time has elapsed, it is considered that an abnormality has occurred in the slave control unit 70, and the timeout notification signal to the master control unit 20 is set to “1”.

  In S510 in the arithmetic processing by the slave control unit 70, the DMA transfer to the second RAM 74 for the distance data stored in the first DPRAM 13a is started. When this DMA transfer is started, The time check unit 14 starts a timer. Then, the slave controller 70 measures the time until the DMA transfer of the operation data to the second DPRAM 13b is started. If the DMA transfer of the operation data to the second DPRAM 13b is not started even after the predetermined time has elapsed, the time check unit 14 considers that an abnormality has occurred in the slave control unit 70, and the master control unit 20 Set the timeout notification signal to “1”.

  When the time-out notification signal is set to “1”, the master control unit 20 executes time-out interrupt processing, and the in-vehicle laser sensor 1 is stopped.

[effect]
The in-vehicle laser sensor 1 in the present embodiment includes a master control unit 20 that controls the entire apparatus and a slave control unit 70 that performs calculations based on distance data and the like. The provision of distance data and the like to the slave control unit 70 and the transfer of calculation data from the slave control unit 70 to the master control unit 20 are performed via the DPRAM included in the FPGA 10. Therefore, even when the master control unit bus line 24 and the slave control unit bus line 75 have different formats or different bus clocks, a large amount of data can be exchanged in a short time.

  The master controller 20 and the FPGA 10 are mounted on the same board, but the FPGA 10 and the slave controller 70 are mounted on different boards, and the FPGA 10 and the slave controller 70 are connected by a cable. Has been. For this reason, it is considered that the communication between the FPGA 10 and the slave control unit 70 is more susceptible to noise than the communication between the FPGA 10 and the master control unit 20. Here, as a method for checking the communication state between the FPGA 10 and the slave control unit 70, a method using a parity bit or a checksum can be considered. However, in such a method, only the communication state can be checked. .

  In addition, the slave control unit 70 operates with a clock faster than the master control unit 20, and has a higher risk of runaway due to heat generation than the master control unit 20, and monitors the operation of the slave control unit 70. Need to do.

  Therefore, the FPGA 10 provides slave test data to the slave control unit 70 instead of distance data or the like at regular timing. The slave control unit 70 that has received the test data for slave performs the same processing as when the distance data or the like is received, and writes the operation data into the second DPRAM 13b. Then, the FPGA 10 performs an abnormality determination on the slave control unit 70 based on the calculation data generated based on the slave test data by the slave control unit 70.

  By doing so, the master controller 20 and the slave controller 70 can perform abnormality determination on the slave controller 70 without newly providing dedicated processing for abnormality determination. Further, the master control unit 20 can perform the abnormality determination for the slave control unit 70 without performing the abnormality determination process for the slave control unit 70. Therefore, according to the vehicle-mounted laser sensor 1 of the present embodiment, it is possible to perform abnormality determination on the slave control unit 70 while suppressing an increase in processing load on the master control unit 20 and the slave control unit 70 as much as possible. Further, the FPGA 10 performs an abnormality determination based on the calculation data generated based on the slave test data, so that not only an abnormality determination regarding the slave control unit 70 but also a communication state between the FPGA 10 and the slave control unit 70 is obtained. Abnormality determination can also be performed.

  Here, the calculation data generated by the slave control unit 70 at the time of abnormality determination is not generated based on the distance data generated by the distance measurement processing unit 11, and the calculation data is not stored in the master control unit 20. It is unnecessary. Therefore, the FPGA 10 provides master test data to the master control unit 20 in place of the calculation data when the result of the abnormality determination for the slave control unit 70 is normal. Then, the master control unit 20 performs abnormality determination on the communication state between the master control unit 20 and the FPGA 10 by comparing the received master test data with the determination data. By doing so, the master control unit 20 can detect an abnormality in communication with the FPGA 10.

  Further, it is assumed that the slave controller 70 does not access the DPRAM of the FPGA 10 due to some abnormality. However, even if such an abnormality occurs, it cannot be detected by the above-described method.

  Therefore, the FPGA 10 measures the time from when the writing of the distance data or the like to the first DPRAM 13a is completed until the DMA transfer of the distance data or the like stored in the first DPRAM 13a by the slave control unit 70 is started. . Also, the time from the start of DMA transfer of distance data or the like stored in the first DPRAM 13a from the slave controller 70 to the start of DMA transfer of operation data to the second DPRAM 13b is set. measure. If these times exceed a predetermined time, it is determined that an abnormality has occurred in the slave controller 70.

  By doing so, it is possible to detect an abnormality in which the slave controller 70 does not access the DPRAM of the FPGA 10.

[Other Embodiments]
(1) The in-vehicle laser sensor 1 according to the present embodiment provides distance data and the like to the slave control unit 70 and calculation data from the slave control unit 70 to the master control unit 20 by the FPGA 10 whose circuit configuration can be changed. We are transferring. However, a gate array or the like whose circuit configuration cannot be changed may be provided with the same configuration as the FPGA 10 in the present embodiment, and the gate array may be mounted on the in-vehicle laser sensor 1 instead of the FPGA 10. Even in the case of such a configuration, it is possible to perform abnormality determination on the slave control unit 70 while suppressing an increase in processing load on the master control unit 20 and the slave control unit 70.

  (2) In the present embodiment, distance data and the like are provided to the slave control unit 70 and data are transferred from the slave control unit 70 to the master control unit 20 via the DPRAM included in the FPGA 10. However, the FPGA 10 may provide distance data to the slave control unit 70 or transfer data from the slave control unit 70 to the master control unit 20 by, for example, serial communication. Even when data is provided by serial communication or the like, the slave controller 70 has the same configuration as that of the present embodiment, thereby suppressing an increase in processing load on the master controller 20 and the slave controller 70. An abnormality determination can be made.

  (3) In the slave control unit 70 in the present embodiment, the slave CPU 71 executes a calculation for specifying the position, shape, and the like of an object existing ahead of the host vehicle based on distance data or the like. However, the slave control unit 70 may have a configuration in which the above calculation is executed by a dedicated circuit. Even in such a case, the same effect can be obtained.

[Correspondence with Claims]
The correspondence between the terms used in the description of the above embodiment and the terms used in the description of the claims is shown.

  The FPGA 10 corresponds to the data relay device, the slave control unit 70 corresponds to the first control device, and the master control unit 20 corresponds to the second control device. The on-vehicle laser sensor 1 corresponds to a data processing system. Also, the calculation process is a predetermined process, the distance data and calculation parameters are the processing data, the calculation data is the generated data, the slave test data is the first test data, and the master test data is the second test. It corresponds to each data.

  The first DPRAM 13a and the slave transmission control unit 15a correspond to processing data providing means, and the first DPRAM 13a corresponds to the first dual port RAM. The second DPRAM 13b, the slave reception control unit 16a, and the master transmission control unit 18a correspond to transfer means, and the second DPRAM 13b corresponds to a second dual port RAM.

  The slave transmission control unit 15a is the first test data providing unit, the slave test data storage unit 15b is the first test data storage unit, and the master transmission control unit 18a is the second test data providing unit. The master test data storage unit 18b corresponds to a second test data storage unit. The slave reception control unit 16a corresponds to a first determination unit, and the time check unit 14 corresponds to a second determination unit and a third determination unit. Further, the abnormality determination instruction unit 17 corresponds to an instruction unit, and the instruction given by the abnormality determination instruction unit 17 corresponds to a provision instruction.

It is explanatory drawing for demonstrating the irradiation direction and peak time difference of a laser. It is a block diagram about the structure of the vehicle-mounted laser sensor. It is a block diagram about structures, such as FPGA. It is a flowchart about a laser control process. It is a flowchart about a DMA interruption process and a timeout interruption process. It is a flowchart about a calculation process.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Vehicle-mounted laser sensor, 10 ... FPGA, 11 ... Distance measurement process part, 12 ... Master reception control part, 13a ... 1st DPRAM, 13a-1 ... 1st port, 13a-2 ... 2nd port, 13b ... Second DPRAM, 13b-1 ... first port, 13b-2 ... second port, 14 ... time check unit, 15a ... slave transmission control unit, 15b ... slave test data storage unit, 16a ... slave reception control unit, 16b ... Slave determination data storage unit, 17 ... Abnormality determination instruction unit, 18a ... Master transmission control unit, 18b ... Master test data storage unit, 20 ... Master control unit, 21 ... Master CPU, 22 ... RAM, 23 ... DMA Control unit 24 ... Master control unit bus line 30 ... Light emitting circuit 40 ... Light emitting scanner 50 ... Light receiving circuit 60 ... AD converter 70 ... Slave control unit 71 ... slave CPU, 72 ... first RAM, 73 ... DMA controller, 74 ... second RAM, 75 ... slave controller bus line.

Claims (11)

Provide the processing data used for the predetermined process by the first control device to the first control device, and receive the generated data generated by the predetermined process from the first control device, A data relay device that provides the received generated data to a second control device;
The data relay device
Processing data providing means for providing the processing data to the first control device;
Transfer means for receiving the generated data from the first controller and providing the received generated data to the second controller;
First test data providing means for providing first test data to the first control device as the processing data;
When the transfer means receives from the first control device the generated data generated by the predetermined processing performed using the first test data provided as the processing data, First determination means for performing abnormality determination on the first control device based on the generated data;
First test data storage means for storing the first test data;
With
The processing data providing means includes a first dual port RAM having one port connected to the first control device, and the processing data stored in the first dual port RAM. The data is read from the first control device to provide the processing data to the first control device,
The transfer means includes a second dual port RAM in which one port is connected to the first control device and the other port is connected to the second control device. The generated data is written to the second dual port RAM by the control device, thereby receiving the generated data from the first control device and the second dual port by the first control device. The generated data written in the RAM is read from the second control device to provide the generated data to the second control device,
The first test data providing means replaces the processing data stored in the first dual port RAM included in the processing data providing means with respect to the first control device. Providing the first control data as the processing data to the first control device by causing the first test data stored in one test data storage means to be read.
A data relay device. Provide the processing data used for the predetermined process by the first control device to the first control device, and receive the generated data generated by the predetermined process from the first control device, A data relay device that provides the received generated data to a second control device;
The data relay device
Processing data providing means for providing the processing data to the first control device;
Transfer means for receiving the generated data from the first controller and providing the received generated data to the second controller;
First test data providing means for providing first test data to the first control device as the processing data;
When the transfer means receives from the first control device the generated data generated by the predetermined processing performed using the first test data provided as the processing data, First determination means for performing abnormality determination on the first control device based on the generated data;
Second test data, which is data used for abnormality determination related to the data relay device by the second control device, is used as the generated data received by the transfer unit from the first control device. Second test data providing means to be provided to the control device;
A data relay device comprising: The data relay device according to claim 1 ,
The data relay device
Second test data storage means for storing second test data which is data used for abnormality determination related to the data relay device by the second control device;
The second control device stores the second data stored in the second test data storage means instead of the generated data stored in the second dual-port RAM of the transfer means. By reading the test data, the second test data is provided to the second control device as the generated data received by the transfer means from the first control device. Data providing means,
Further comprising
A data relay device. In the data relay device according to claim 1 or 3 ,
The data relay device stores the new processing data in the first dual port RAM included in the processing data providing means, and then stores the data in the first dual port RAM by the first control device. Further comprising second determination means for performing an abnormality determination on the first control device based on a time until the stored processing data is read.
A data relay device. In the data processing device according to any one of claims 1, 3 , or 4 ,
The data relay device is configured to read the processing data stored in the first dual port RAM included in the processing data providing unit by the first control device, and then Based on the time until the generated data generated in the predetermined processing performed using the processing data by the control device is written in the second dual-port RAM of the transfer unit, Further comprising third determination means for performing abnormality determination on the first control device;
A data relay device. In the data relay device according to any one of claims 1 to 5 ,
The data relay device instructs the first test data providing means to provide the first test data to the first control device as the processing data at a regular timing. An instruction means for giving a provision instruction;
The first test data providing unit, when receiving the provision instruction from the instruction unit, provides the first test data to the first control device as the processing data;
A data relay device. In the data relay device according to any one of claims 1 to 5 ,
In response to an instruction from the second control device, the data relay device uses the first test data as the processing data to the first test data providing unit. Further comprising an instruction means for giving a provision instruction that is an instruction to provide to
The first test data providing unit, when receiving the provision instruction from the instruction unit, provides the first test data to the first control device as the processing data;
A data relay device. In the data relay device according to any one of claims 1 to 5 ,
The data relay device provides the first test data to the first control device as the processing data to the first test data providing means in response to an instruction from a user. An instruction means for giving a provision instruction that is an instruction;
The first test data providing unit, when receiving the provision instruction from the instruction unit, provides the first test data to the first control device as the processing data;
A data relay device. In the data relay device according to any one of claims 1 to 8 ,
The determination means notifies the second control device of a result of abnormality determination for the first control device;
A data relay device. In the data relay device according to any one of claims 1 to 9 ,
The data relay device is constituted by a dedicated circuit realized by an FPGA;
A data relay device. A data relay apparatus according to any one of claims 1 to 10, a first control device according to any one of claims 1 to 10, according to one of claims 1 to 10, wherein And a second control device.

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